From 826783ab79a2f125b90eb03c76ff24a430f338d6 Mon Sep 17 00:00:00 2001 From: Philip Smart Date: Tue, 14 Feb 2023 09:16:03 +0000 Subject: [PATCH] MZ80A Virtual RFS Driver added --- .gitignore | 29 +- .gitmodules | 3 + CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qsf | 4 +- CPLD/v1.0/MZ80A/tzpuFusionX.vhd | 30 +- CPLD/v1.0/MZ80A/tzpuFusionX_Toplevel.vhd | 4 +- CPLD/v1.0/MZ80A/tzpuFusionX_pkg.vhd | 4 +- software/FusionX/src/driver/MZ80A/optparse.h | 403 +++ software/FusionX/src/driver/MZ80A/z80ctrl.c | 973 +++++++ software/FusionX/src/driver/MZ80A/z80driver.c | 1922 +++++++++++++ software/FusionX/src/driver/MZ80A/z80driver.h | 439 +++ software/FusionX/src/driver/MZ80A/z80io.c | 452 +++ software/FusionX/src/driver/MZ80A/z80io.h | 507 ++++ .../FusionX/src/driver/MZ80A/z80io_test.c | 541 ++++ software/FusionX/src/driver/MZ80A/z80menu.c | 57 + software/FusionX/src/driver/MZ80A/z80menu.h | 44 + .../FusionX/src/driver/MZ80A/z80vhw_rfs.c | 714 +++++ .../FusionX/src/driver/MZ80A/z80vhw_tzpu.c | 91 + software/FusionX/src/driver/Makefile | 4 +- software/linux/boot/include/ms_version.h | 4 +- .../kernel/arch/arm/boot/dts/aks-cdu.dts | 119 - .../boot/dts/alphascale-asm9260-devkit.dts | 13 - .../arch/arm/boot/dts/alphascale-asm9260.dtsi | 63 - .../kernel/arch/arm/boot/dts/alpine-db.dts | 35 - .../kernel/arch/arm/boot/dts/alpine.dtsi | 170 -- .../arm/boot/dts/am335x-baltos-ir2110.dts | 71 - .../arm/boot/dts/am335x-baltos-ir3220.dts | 119 - .../arm/boot/dts/am335x-baltos-ir5221.dts | 144 - .../arch/arm/boot/dts/am335x-baltos.dtsi | 408 --- .../arch/arm/boot/dts/am335x-base0033.dts | 95 - .../arch/arm/boot/dts/am335x-bone-common.dtsi | 395 --- .../kernel/arch/arm/boot/dts/am335x-bone.dts | 26 - .../arch/arm/boot/dts/am335x-boneblack.dts | 159 -- .../arch/arm/boot/dts/am335x-bonegreen.dts | 53 - .../arch/arm/boot/dts/am335x-chiliboard.dts | 187 -- .../arch/arm/boot/dts/am335x-chilisom.dtsi | 178 -- .../arch/arm/boot/dts/am335x-cm-t335.dts | 569 ---- .../kernel/arch/arm/boot/dts/am335x-evm.dts | 785 ------ .../kernel/arch/arm/boot/dts/am335x-evmsk.dts | 718 ----- .../kernel/arch/arm/boot/dts/am335x-icev2.dts | 322 --- .../arch/arm/boot/dts/am335x-igep0033.dtsi | 323 --- .../kernel/arch/arm/boot/dts/am335x-lxm.dts | 366 --- .../kernel/arch/arm/boot/dts/am335x-nano.dts | 440 --- .../arch/arm/boot/dts/am335x-pepper.dts | 656 ----- .../arch/arm/boot/dts/am335x-phycore-som.dtsi | 373 --- .../arch/arm/boot/dts/am335x-sbc-t335.dts | 219 -- .../kernel/arch/arm/boot/dts/am335x-shc.dts | 577 ---- .../kernel/arch/arm/boot/dts/am335x-sl50.dts | 507 ---- .../arch/arm/boot/dts/am335x-wega-rdk.dts | 22 - .../kernel/arch/arm/boot/dts/am335x-wega.dtsi | 224 -- .../arch/arm/boot/dts/am33xx-clocks.dtsi | 646 ----- .../kernel/arch/arm/boot/dts/am33xx.dtsi | 945 ------- .../arch/arm/boot/dts/am3517-craneboard.dts | 174 -- .../kernel/arch/arm/boot/dts/am3517-evm.dts | 61 - .../kernel/arch/arm/boot/dts/am3517.dtsi | 94 - .../arch/arm/boot/dts/am3517_mt_ventoux.dts | 27 - .../arch/arm/boot/dts/am35xx-clocks.dtsi | 128 - .../kernel/arch/arm/boot/dts/am4372.dtsi | 1177 -------- .../arch/arm/boot/dts/am437x-cm-t43.dts | 415 --- .../arch/arm/boot/dts/am437x-gp-evm.dts | 988 ------- .../arch/arm/boot/dts/am437x-idk-evm.dts | 416 --- .../arch/arm/boot/dts/am437x-sbc-t43.dts | 180 -- .../arch/arm/boot/dts/am437x-sk-evm.dts | 761 ------ .../arch/arm/boot/dts/am43x-epos-evm.dts | 795 ------ .../arch/arm/boot/dts/am43xx-clocks.dtsi | 836 ------ .../kernel/arch/arm/boot/dts/am572x-idk.dts | 85 - .../boot/dts/am57xx-beagle-x15-common.dtsi | 596 ---- .../arm/boot/dts/am57xx-beagle-x15-revb1.dts | 24 - .../arch/arm/boot/dts/am57xx-beagle-x15.dts | 24 - .../arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 617 ----- .../arm/boot/dts/am57xx-commercial-grade.dtsi | 23 - .../arch/arm/boot/dts/am57xx-idk-common.dtsi | 355 --- .../arm/boot/dts/am57xx-industrial-grade.dtsi | 23 - .../arch/arm/boot/dts/am57xx-sbc-am57x.dts | 179 -- .../kernel/arch/arm/boot/dts/animeo_ip.dts | 166 -- .../arm-realview-eb-11mp-bbrevd-ctrevb.dts | 32 - .../boot/dts/arm-realview-eb-11mp-bbrevd.dts | 28 - .../boot/dts/arm-realview-eb-11mp-ctrevb.dts | 93 - .../arm/boot/dts/arm-realview-eb-11mp.dts | 74 - .../boot/dts/arm-realview-eb-a9mp-bbrevd.dts | 28 - .../arm/boot/dts/arm-realview-eb-a9mp.dts | 70 - .../arm/boot/dts/arm-realview-eb-bbrevd.dts | 29 - .../arm/boot/dts/arm-realview-eb-bbrevd.dtsi | 45 - .../arch/arm/boot/dts/arm-realview-eb-mp.dtsi | 220 -- .../arch/arm/boot/dts/arm-realview-eb.dts | 166 -- .../arch/arm/boot/dts/arm-realview-eb.dtsi | 444 --- .../arch/arm/boot/dts/arm-realview-pb1176.dts | 570 ---- .../arch/arm/boot/dts/arm-realview-pb11mp.dts | 682 ----- .../arch/arm/boot/dts/arm-realview-pba8.dts | 178 -- .../arch/arm/boot/dts/arm-realview-pbx-a9.dts | 228 -- .../arch/arm/boot/dts/arm-realview-pbx.dtsi | 542 ---- .../arch/arm/boot/dts/armada-370-db.dts | 277 -- .../arm/boot/dts/armada-370-dlink-dns327l.dts | 358 --- .../arch/arm/boot/dts/armada-370-mirabox.dts | 211 -- .../arm/boot/dts/armada-370-netgear-rn102.dts | 300 -- .../arm/boot/dts/armada-370-netgear-rn104.dts | 312 --- .../arch/arm/boot/dts/armada-370-rd.dts | 250 -- .../boot/dts/armada-370-seagate-nas-2bay.dts | 36 - .../boot/dts/armada-370-seagate-nas-4bay.dts | 133 - .../boot/dts/armada-370-seagate-nas-xbay.dtsi | 231 -- ...armada-370-seagate-personal-cloud-2bay.dts | 51 - .../dts/armada-370-seagate-personal-cloud.dts | 37 - .../armada-370-seagate-personal-cloud.dtsi | 178 -- .../boot/dts/armada-370-synology-ds213j.dts | 349 --- .../arch/arm/boot/dts/armada-370-xp.dtsi | 349 --- .../kernel/arch/arm/boot/dts/armada-370.dtsi | 447 --- .../arch/arm/boot/dts/armada-375-db.dts | 206 -- .../kernel/arch/arm/boot/dts/armada-375.dtsi | 656 ----- .../kernel/arch/arm/boot/dts/armada-380.dtsi | 152 -- .../arch/arm/boot/dts/armada-385-db-ap.dts | 265 -- .../boot/dts/armada-385-linksys-caiman.dts | 114 - .../arm/boot/dts/armada-385-linksys-cobra.dts | 114 - .../arch/arm/boot/dts/armada-385-linksys.dtsi | 333 --- .../kernel/arch/arm/boot/dts/armada-385.dtsi | 184 -- .../arch/arm/boot/dts/armada-388-clearfog.dts | 446 --- .../arch/arm/boot/dts/armada-388-db.dts | 204 -- .../arch/arm/boot/dts/armada-388-gp.dts | 435 --- .../arch/arm/boot/dts/armada-388-rd.dts | 145 - .../kernel/arch/arm/boot/dts/armada-388.dtsi | 70 - .../dts/armada-38x-solidrun-microsom.dtsi | 128 - .../kernel/arch/arm/boot/dts/armada-38x.dtsi | 678 ----- .../arch/arm/boot/dts/armada-390-db.dts | 175 -- .../kernel/arch/arm/boot/dts/armada-390.dtsi | 60 - .../arch/arm/boot/dts/armada-395-gp.dts | 163 -- .../kernel/arch/arm/boot/dts/armada-395.dtsi | 76 - .../arch/arm/boot/dts/armada-398-db.dts | 161 -- .../kernel/arch/arm/boot/dts/armada-398.dtsi | 68 - .../kernel/arch/arm/boot/dts/armada-39x.dtsi | 590 ---- .../arch/arm/boot/dts/armada-xp-axpwifiap.dts | 181 -- .../kernel/arch/arm/boot/dts/armada-xp-db.dts | 279 -- .../kernel/arch/arm/boot/dts/armada-xp-gp.dts | 264 -- .../boot/dts/armada-xp-lenovo-ix4-300d.dts | 328 --- .../arm/boot/dts/armada-xp-linksys-mamba.dts | 400 --- .../arch/arm/boot/dts/armada-xp-matrix.dts | 116 - .../arch/arm/boot/dts/armada-xp-mv78230.dtsi | 231 -- .../arch/arm/boot/dts/armada-xp-mv78260.dtsi | 333 --- .../arch/arm/boot/dts/armada-xp-mv78460.dtsi | 371 --- .../arm/boot/dts/armada-xp-netgear-rn2120.dts | 378 --- .../boot/dts/armada-xp-openblocks-ax3-4.dts | 248 -- .../arm/boot/dts/armada-xp-synology-ds414.dts | 364 --- .../kernel/arch/arm/boot/dts/armada-xp.dtsi | 379 --- .../kernel/arch/arm/boot/dts/armv7-m.dtsi | 22 - .../arch/arm/boot/dts/artpec6-devboard.dts | 64 - .../kernel/arch/arm/boot/dts/artpec6.dtsi | 220 -- .../arch/arm/boot/dts/aspeed-ast2500-evb.dts | 25 - .../arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 25 - .../kernel/arch/arm/boot/dts/aspeed-g4.dtsi | 161 -- .../kernel/arch/arm/boot/dts/aspeed-g5.dtsi | 170 -- .../kernel/arch/arm/boot/dts/at91-ariag25.dts | 178 -- .../arch/arm/boot/dts/at91-ariettag25.dts | 79 - .../kernel/arch/arm/boot/dts/at91-cosino.dtsi | 120 - .../arm/boot/dts/at91-cosino_mega2560.dts | 78 - .../kernel/arch/arm/boot/dts/at91-foxg20.dts | 156 -- .../kernel/arch/arm/boot/dts/at91-kizbox.dts | 150 - .../kernel/arch/arm/boot/dts/at91-kizbox2.dts | 216 -- .../arch/arm/boot/dts/at91-kizboxmini.dts | 129 - .../arch/arm/boot/dts/at91-qil_a9260.dts | 184 -- .../arch/arm/boot/dts/at91-sam9_l9260.dts | 121 - .../arm/boot/dts/at91-sama5d2_xplained.dts | 507 ---- .../arm/boot/dts/at91-sama5d3_xplained.dts | 336 --- .../arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi | 130 - .../arm/boot/dts/at91-sama5d4_ma5d4evk.dts | 170 -- .../arm/boot/dts/at91-sama5d4_xplained.dts | 275 -- .../arch/arm/boot/dts/at91-sama5d4ek.dts | 329 --- .../kernel/arch/arm/boot/dts/at91-vinco.dts | 256 -- .../kernel/arch/arm/boot/dts/at91rm9200.dtsi | 965 ------- .../arch/arm/boot/dts/at91rm9200_pqfp.dtsi | 17 - .../kernel/arch/arm/boot/dts/at91rm9200ek.dts | 136 - .../kernel/arch/arm/boot/dts/at91sam9260.dtsi | 1030 ------- .../arch/arm/boot/dts/at91sam9260ek.dts | 211 -- .../kernel/arch/arm/boot/dts/at91sam9261.dtsi | 876 ------ .../arch/arm/boot/dts/at91sam9261ek.dts | 211 -- .../kernel/arch/arm/boot/dts/at91sam9263.dtsi | 1034 ------- .../arch/arm/boot/dts/at91sam9263ek.dts | 227 -- .../kernel/arch/arm/boot/dts/at91sam9g15.dtsi | 29 - .../arch/arm/boot/dts/at91sam9g15ek.dts | 41 - .../kernel/arch/arm/boot/dts/at91sam9g20.dtsi | 68 - .../arch/arm/boot/dts/at91sam9g20ek.dts | 29 - .../arch/arm/boot/dts/at91sam9g20ek_2mmc.dts | 55 - .../arm/boot/dts/at91sam9g20ek_common.dtsi | 225 -- .../kernel/arch/arm/boot/dts/at91sam9g25.dtsi | 31 - .../arch/arm/boot/dts/at91sam9g25ek.dts | 69 - .../kernel/arch/arm/boot/dts/at91sam9g35.dtsi | 30 - .../arch/arm/boot/dts/at91sam9g35ek.dts | 46 - .../kernel/arch/arm/boot/dts/at91sam9g45.dtsi | 1331 --------- .../arch/arm/boot/dts/at91sam9m10g45ek.dts | 357 --- .../kernel/arch/arm/boot/dts/at91sam9n12.dtsi | 1045 ------- .../arch/arm/boot/dts/at91sam9n12ek.dts | 262 -- .../kernel/arch/arm/boot/dts/at91sam9rl.dtsi | 1119 -------- .../kernel/arch/arm/boot/dts/at91sam9rlek.dts | 237 -- .../kernel/arch/arm/boot/dts/at91sam9x25.dtsi | 32 - .../arch/arm/boot/dts/at91sam9x25ek.dts | 30 - .../kernel/arch/arm/boot/dts/at91sam9x35.dtsi | 31 - .../arch/arm/boot/dts/at91sam9x35ek.dts | 45 - .../kernel/arch/arm/boot/dts/at91sam9x5.dtsi | 1285 --------- .../arch/arm/boot/dts/at91sam9x5_can.dtsi | 71 - .../arch/arm/boot/dts/at91sam9x5_isi.dtsi | 72 - .../arch/arm/boot/dts/at91sam9x5_lcd.dtsi | 165 -- .../arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 67 - .../arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 55 - .../arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 69 - .../arch/arm/boot/dts/at91sam9x5cm.dtsi | 100 - .../arch/arm/boot/dts/at91sam9x5dm.dtsi | 101 - .../arch/arm/boot/dts/at91sam9x5ek.dtsi | 165 -- .../kernel/arch/arm/boot/dts/at91sam9xe.dtsi | 60 - .../kernel/arch/arm/boot/dts/atlas6-evb.dts | 78 - .../kernel/arch/arm/boot/dts/atlas6.dtsi | 802 ------ .../kernel/arch/arm/boot/dts/atlas7-evb.dts | 128 - .../kernel/arch/arm/boot/dts/atlas7.dtsi | 1957 ------------- .../arch/arm/boot/dts/axm5516-amarillo.dts | 51 - .../arch/arm/boot/dts/axm5516-cpus.dtsi | 204 -- .../kernel/arch/arm/boot/dts/axm55xx.dtsi | 204 -- .../kernel/arch/arm/boot/dts/axp152.dtsi | 49 - .../kernel/arch/arm/boot/dts/axp209.dtsi | 104 - .../kernel/arch/arm/boot/dts/axp22x.dtsi | 155 -- .../kernel/arch/arm/boot/dts/axp809.dtsi | 53 - .../arch/arm/boot/dts/bcm-cygnus-clock.dtsi | 133 - .../kernel/arch/arm/boot/dts/bcm-cygnus.dtsi | 381 --- .../kernel/arch/arm/boot/dts/bcm-nsp.dtsi | 479 ---- .../kernel/arch/arm/boot/dts/bcm11351.dtsi | 424 --- .../arch/arm/boot/dts/bcm21664-garnet.dts | 56 - .../kernel/arch/arm/boot/dts/bcm21664.dtsi | 357 --- .../arch/arm/boot/dts/bcm23550-sparrow.dts | 80 - .../kernel/arch/arm/boot/dts/bcm23550.dtsi | 415 --- .../kernel/arch/arm/boot/dts/bcm28155-ap.dts | 121 - .../arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 36 - .../arch/arm/boot/dts/bcm2835-rpi-a.dts | 29 - .../arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 37 - .../arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 30 - .../arch/arm/boot/dts/bcm2835-rpi-b.dts | 24 - .../arch/arm/boot/dts/bcm2835-rpi-zero.dts | 40 - .../kernel/arch/arm/boot/dts/bcm2835-rpi.dtsi | 86 - .../kernel/arch/arm/boot/dts/bcm2835.dtsi | 25 - .../arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 41 - .../kernel/arch/arm/boot/dts/bcm2836.dtsi | 78 - .../arm/boot/dts/bcm283x-rpi-smsc9512.dtsi | 19 - .../arm/boot/dts/bcm283x-rpi-smsc9514.dtsi | 19 - .../arm/boot/dts/bcm283x-rpi-usb-host.dtsi | 3 - .../kernel/arch/arm/boot/dts/bcm283x.dtsi | 330 --- .../arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 97 - .../arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 84 - .../boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 153 -- .../arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 65 - .../arm/boot/dts/bcm4708-netgear-r6250.dts | 96 - .../arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 88 - .../arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 168 -- .../kernel/arch/arm/boot/dts/bcm4708.dtsi | 36 - .../arm/boot/dts/bcm47081-asus-rt-n18u.dts | 78 - .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 128 - .../boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 38 - .../kernel/arch/arm/boot/dts/bcm47081.dtsi | 26 - .../arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 66 - .../boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 137 - .../arm/boot/dts/bcm4709-netgear-r7000.dts | 106 - .../arm/boot/dts/bcm4709-netgear-r8000.dts | 116 - .../arm/boot/dts/bcm47094-dlink-dir-885l.dts | 119 - .../arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi | 15 - .../arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi | 18 - .../arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi | 18 - .../kernel/arch/arm/boot/dts/bcm5301x.dtsi | 332 --- .../kernel/arch/arm/boot/dts/bcm59056.dtsi | 95 - .../kernel/arch/arm/boot/dts/bcm63138.dtsi | 198 -- .../arm/boot/dts/bcm7445-bcm97445svmb.dts | 37 - .../kernel/arch/arm/boot/dts/bcm7445.dtsi | 316 --- .../arch/arm/boot/dts/bcm911360_entphn.dts | 78 - .../kernel/arch/arm/boot/dts/bcm911360k.dts | 52 - .../kernel/arch/arm/boot/dts/bcm94708.dts | 56 - .../kernel/arch/arm/boot/dts/bcm94709.dts | 56 - .../kernel/arch/arm/boot/dts/bcm953012er.dts | 104 - .../kernel/arch/arm/boot/dts/bcm953012k.dts | 63 - .../kernel/arch/arm/boot/dts/bcm958300k.dts | 77 - .../kernel/arch/arm/boot/dts/bcm958305k.dts | 85 - .../kernel/arch/arm/boot/dts/bcm958522er.dts | 131 - .../kernel/arch/arm/boot/dts/bcm958525er.dts | 143 - .../kernel/arch/arm/boot/dts/bcm958525xmc.dts | 152 -- .../kernel/arch/arm/boot/dts/bcm958622hr.dts | 171 -- .../kernel/arch/arm/boot/dts/bcm958623hr.dts | 179 -- .../kernel/arch/arm/boot/dts/bcm958625hr.dts | 181 -- .../kernel/arch/arm/boot/dts/bcm958625k.dts | 141 - .../kernel/arch/arm/boot/dts/bcm963138dvt.dts | 42 - .../kernel/arch/arm/boot/dts/bcm988312hr.dts | 183 -- .../kernel/arch/arm/boot/dts/bcm9hmidc.dtsi | 42 - .../arm/boot/dts/berlin2-sony-nsz-gs7.dts | 74 - .../kernel/arch/arm/boot/dts/berlin2.dtsi | 561 ---- .../boot/dts/berlin2cd-google-chromecast.dts | 88 - .../kernel/arch/arm/boot/dts/berlin2cd.dtsi | 494 ---- .../arm/boot/dts/berlin2q-marvell-dmp.dts | 175 -- .../kernel/arch/arm/boot/dts/berlin2q.dtsi | 658 ----- .../arch/arm/boot/dts/compulab-sb-som.dtsi | 49 - .../arm/boot/dts/cros-adc-thermistors.dtsi | 44 - .../arch/arm/boot/dts/cros-ec-keyboard.dtsi | 110 - .../kernel/arch/arm/boot/dts/cros-ec-sbs.dtsi | 52 - .../kernel/arch/arm/boot/dts/cx92755.dtsi | 144 - .../arch/arm/boot/dts/cx92755_equinox.dts | 86 - .../arch/arm/boot/dts/da850-enbw-cmc.dts | 44 - .../kernel/arch/arm/boot/dts/da850-evm.dts | 292 -- .../kernel/arch/arm/boot/dts/da850-lcdk.dts | 221 -- .../linux/kernel/arch/arm/boot/dts/da850.dtsi | 413 --- .../kernel/arch/arm/boot/dts/dm8148-evm.dts | 149 - .../kernel/arch/arm/boot/dts/dm8148-t410.dts | 107 - .../arch/arm/boot/dts/dm814x-clocks.dtsi | 339 --- .../kernel/arch/arm/boot/dts/dm814x.dtsi | 578 ---- .../kernel/arch/arm/boot/dts/dm8168-evm.dts | 175 -- .../arch/arm/boot/dts/dm816x-clocks.dtsi | 250 -- .../kernel/arch/arm/boot/dts/dm816x.dtsi | 516 ---- .../arch/arm/boot/dts/dove-cm-a510.dtsi | 195 -- .../arch/arm/boot/dts/dove-cubox-es.dts | 12 - .../kernel/arch/arm/boot/dts/dove-cubox.dts | 142 - .../kernel/arch/arm/boot/dts/dove-d2plug.dts | 69 - .../kernel/arch/arm/boot/dts/dove-d3plug.dts | 103 - .../kernel/arch/arm/boot/dts/dove-dove-db.dts | 38 - .../arch/arm/boot/dts/dove-sbc-a510.dts | 182 -- .../linux/kernel/arch/arm/boot/dts/dove.dtsi | 803 ------ .../arch/arm/boot/dts/dra62x-clocks.dtsi | 49 - .../arch/arm/boot/dts/dra62x-j5eco-evm.dts | 138 - .../kernel/arch/arm/boot/dts/dra62x.dtsi | 23 - .../arm/boot/dts/dra7-dspeve-thermal.dtsi | 27 - .../kernel/arch/arm/boot/dts/dra7-evm.dts | 939 ------- .../arch/arm/boot/dts/dra7-iva-thermal.dtsi | 27 - .../linux/kernel/arch/arm/boot/dts/dra7.dtsi | 1989 -------------- .../arch/arm/boot/dts/dra72-evm-common.dtsi | 817 ------ .../arch/arm/boot/dts/dra72-evm-revc.dts | 73 - .../kernel/arch/arm/boot/dts/dra72-evm.dts | 45 - .../kernel/arch/arm/boot/dts/dra72x.dtsi | 52 - .../kernel/arch/arm/boot/dts/dra74x.dtsi | 121 - .../arch/arm/boot/dts/dra7xx-clocks.dtsi | 2196 --------------- .../kernel/arch/arm/boot/dts/ecx-2000.dts | 114 - .../kernel/arch/arm/boot/dts/ecx-common.dtsi | 241 -- .../arch/arm/boot/dts/efm32gg-dk3750.dts | 87 - .../kernel/arch/arm/boot/dts/efm32gg.dtsi | 176 -- .../arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 - .../kernel/arch/arm/boot/dts/emev2-kzm9d.dts | 121 - .../linux/kernel/arch/arm/boot/dts/emev2.dtsi | 286 -- .../kernel/arch/arm/boot/dts/ep7209.dtsi | 191 -- .../arch/arm/boot/dts/ep7211-edb7211.dts | 100 - .../kernel/arch/arm/boot/dts/ep7211.dtsi | 12 - .../kernel/arch/arm/boot/dts/ethernut5.dts | 94 - .../kernel/arch/arm/boot/dts/evk-pro3.dts | 59 - .../boot/dts/exynos-mfc-reserved-memory.dtsi | 35 - .../arm/boot/dts/exynos-syscon-restart.dtsi | 27 - .../arm/boot/dts/exynos3250-artik5-eval.dts | 43 - .../arch/arm/boot/dts/exynos3250-artik5.dtsi | 335 --- .../arch/arm/boot/dts/exynos3250-monk.dts | 635 ----- .../arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 559 ---- .../arch/arm/boot/dts/exynos3250-rinato.dts | 906 ------ .../kernel/arch/arm/boot/dts/exynos3250.dtsi | 900 ------ .../arm/boot/dts/exynos4-cpu-thermal.dtsi | 52 - .../kernel/arch/arm/boot/dts/exynos4.dtsi | 998 ------- .../arch/arm/boot/dts/exynos4210-origen.dts | 334 --- .../arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 856 ------ .../arch/arm/boot/dts/exynos4210-smdkv310.dts | 203 -- .../arch/arm/boot/dts/exynos4210-trats.dts | 493 ---- .../boot/dts/exynos4210-universal_c210.dts | 584 ---- .../kernel/arch/arm/boot/dts/exynos4210.dtsi | 452 --- .../kernel/arch/arm/boot/dts/exynos4212.dtsi | 133 - .../boot/dts/exynos4412-odroid-common.dtsi | 565 ---- .../arch/arm/boot/dts/exynos4412-odroidu3.dts | 133 - .../arch/arm/boot/dts/exynos4412-odroidx.dts | 97 - .../arch/arm/boot/dts/exynos4412-odroidx2.dts | 49 - .../arch/arm/boot/dts/exynos4412-origen.dts | 547 ---- .../arm/boot/dts/exynos4412-ppmu-common.dtsi | 50 - .../arch/arm/boot/dts/exynos4412-prime.dtsi | 41 - .../arch/arm/boot/dts/exynos4412-smdk4412.dts | 154 -- .../arch/arm/boot/dts/exynos4412-tiny4412.dts | 99 - .../boot/dts/exynos4412-tmu-sensor-conf.dtsi | 24 - .../arch/arm/boot/dts/exynos4412-trats2.dts | 1297 --------- .../kernel/arch/arm/boot/dts/exynos4412.dtsi | 156 -- .../arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 575 ---- .../kernel/arch/arm/boot/dts/exynos4415.dtsi | 650 ----- .../arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 972 ------- .../kernel/arch/arm/boot/dts/exynos4x12.dtsi | 578 ---- .../kernel/arch/arm/boot/dts/exynos5.dtsi | 180 -- .../arch/arm/boot/dts/exynos5250-arndale.dts | 561 ---- .../arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 818 ------ .../arch/arm/boot/dts/exynos5250-smdk5250.dts | 424 --- .../arm/boot/dts/exynos5250-snow-common.dtsi | 688 ----- .../arm/boot/dts/exynos5250-snow-rev5.dts | 47 - .../arch/arm/boot/dts/exynos5250-snow.dts | 43 - .../arch/arm/boot/dts/exynos5250-spring.dts | 558 ---- .../kernel/arch/arm/boot/dts/exynos5250.dtsi | 1063 -------- .../arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 572 ---- .../arm/boot/dts/exynos5260-xyref5260.dts | 96 - .../kernel/arch/arm/boot/dts/exynos5260.dtsi | 313 --- .../arch/arm/boot/dts/exynos5410-odroidxu.dts | 578 ---- .../arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 618 ----- .../arch/arm/boot/dts/exynos5410-smdk5410.dts | 116 - .../kernel/arch/arm/boot/dts/exynos5410.dtsi | 363 --- .../arm/boot/dts/exynos5420-arndale-octa.dts | 405 --- .../arch/arm/boot/dts/exynos5420-cpus.dtsi | 126 - .../arm/boot/dts/exynos5420-peach-pit.dts | 1093 -------- .../arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 723 ----- .../arch/arm/boot/dts/exynos5420-smdk5420.dts | 422 --- .../arm/boot/dts/exynos5420-trip-points.dtsi | 35 - .../kernel/arch/arm/boot/dts/exynos5420.dtsi | 1480 ---------- .../arch/arm/boot/dts/exynos5422-cpus.dtsi | 125 - .../boot/dts/exynos5422-odroidxu3-audio.dtsi | 61 - .../boot/dts/exynos5422-odroidxu3-common.dtsi | 614 ----- .../boot/dts/exynos5422-odroidxu3-lite.dts | 38 - .../arm/boot/dts/exynos5422-odroidxu3.dts | 69 - .../arm/boot/dts/exynos5422-odroidxu4.dts | 48 - .../arch/arm/boot/dts/exynos5440-sd5v1.dts | 45 - .../arch/arm/boot/dts/exynos5440-ssdk5440.dts | 84 - .../boot/dts/exynos5440-tmu-sensor-conf.dtsi | 24 - .../arm/boot/dts/exynos5440-trip-points.dtsi | 25 - .../kernel/arch/arm/boot/dts/exynos5440.dtsi | 324 --- .../boot/dts/exynos54xx-odroidxu-leds.dtsi | 50 - .../kernel/arch/arm/boot/dts/exynos54xx.dtsi | 198 -- .../arch/arm/boot/dts/exynos5800-peach-pi.dts | 1062 -------- .../kernel/arch/arm/boot/dts/exynos5800.dtsi | 136 - ...nfinity2m-spinand-ssc011a-s01a-fusionx.dts | 0 .../kernel/arch/arm/boot/dts/ge863-pro3.dtsi | 47 - .../kernel/arch/arm/boot/dts/hi3519-demb.dts | 42 - .../kernel/arch/arm/boot/dts/hi3519.dtsi | 187 -- .../arch/arm/boot/dts/hi3620-hi4511.dts | 650 ----- .../kernel/arch/arm/boot/dts/hi3620.dtsi | 566 ---- .../kernel/arch/arm/boot/dts/highbank.dts | 142 - .../kernel/arch/arm/boot/dts/hip01-ca9x2.dts | 51 - .../linux/kernel/arch/arm/boot/dts/hip01.dtsi | 110 - .../kernel/arch/arm/boot/dts/hip04-d01.dts | 32 - .../linux/kernel/arch/arm/boot/dts/hip04.dtsi | 983 ------- .../arch/arm/boot/dts/hisi-x5hd2-dkb.dts | 86 - .../kernel/arch/arm/boot/dts/hisi-x5hd2.dtsi | 556 ---- .../kernel/arch/arm/boot/dts/imx1-ads.dts | 152 -- .../kernel/arch/arm/boot/dts/imx1-apf9328.dts | 129 - .../kernel/arch/arm/boot/dts/imx1-pinfunc.h | 302 -- .../linux/kernel/arch/arm/boot/dts/imx1.dtsi | 266 -- .../kernel/arch/arm/boot/dts/imx23-evk.dts | 159 -- .../arch/arm/boot/dts/imx23-olinuxino.dts | 136 - .../kernel/arch/arm/boot/dts/imx23-pinfunc.h | 333 --- .../kernel/arch/arm/boot/dts/imx23-sansa.dts | 207 -- .../arch/arm/boot/dts/imx23-stmp378x_devb.dts | 81 - .../kernel/arch/arm/boot/dts/imx23-xfi3.dts | 179 -- .../linux/kernel/arch/arm/boot/dts/imx23.dtsi | 624 ----- .../arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | 73 - ...25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 73 - ...25-eukrea-mbimxsd25-baseboard-dvi-svga.dts | 45 - ...x25-eukrea-mbimxsd25-baseboard-dvi-vga.dts | 45 - .../dts/imx25-eukrea-mbimxsd25-baseboard.dts | 186 -- .../arch/arm/boot/dts/imx25-karo-tx25.dts | 113 - .../kernel/arch/arm/boot/dts/imx25-pdk.dts | 316 --- .../kernel/arch/arm/boot/dts/imx25-pinfunc.h | 605 ---- .../linux/kernel/arch/arm/boot/dts/imx25.dtsi | 606 ----- .../kernel/arch/arm/boot/dts/imx27-apf27.dts | 124 - .../arch/arm/boot/dts/imx27-apf27dev.dts | 264 -- .../arm/boot/dts/imx27-eukrea-cpuimx27.dtsi | 296 -- .../dts/imx27-eukrea-mbimxsd27-baseboard.dts | 273 -- .../kernel/arch/arm/boot/dts/imx27-pdk.dts | 197 -- .../boot/dts/imx27-phytec-phycard-s-rdk.dts | 168 -- .../boot/dts/imx27-phytec-phycard-s-som.dtsi | 103 - .../arm/boot/dts/imx27-phytec-phycore-rdk.dts | 324 --- .../boot/dts/imx27-phytec-phycore-som.dtsi | 349 --- .../kernel/arch/arm/boot/dts/imx27-pinfunc.h | 480 ---- .../linux/kernel/arch/arm/boot/dts/imx27.dtsi | 594 ---- .../kernel/arch/arm/boot/dts/imx28-apf28.dts | 85 - .../arch/arm/boot/dts/imx28-apf28dev.dts | 231 -- .../arch/arm/boot/dts/imx28-apx4devkit.dts | 226 -- .../arch/arm/boot/dts/imx28-cfa10036.dts | 144 - .../arch/arm/boot/dts/imx28-cfa10037.dts | 89 - .../arch/arm/boot/dts/imx28-cfa10049.dts | 436 --- .../arch/arm/boot/dts/imx28-cfa10055.dts | 167 -- .../arch/arm/boot/dts/imx28-cfa10056.dts | 119 - .../arch/arm/boot/dts/imx28-cfa10057.dts | 177 -- .../arch/arm/boot/dts/imx28-cfa10058.dts | 144 - .../arch/arm/boot/dts/imx28-duckbill.dts | 121 - .../arm/boot/dts/imx28-eukrea-mbmx283lc.dts | 71 - .../arm/boot/dts/imx28-eukrea-mbmx287lc.dts | 50 - .../arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi | 330 --- .../kernel/arch/arm/boot/dts/imx28-evk.dts | 378 --- .../kernel/arch/arm/boot/dts/imx28-m28.dtsi | 61 - .../kernel/arch/arm/boot/dts/imx28-m28cu3.dts | 271 -- .../kernel/arch/arm/boot/dts/imx28-m28evk.dts | 275 -- .../kernel/arch/arm/boot/dts/imx28-pinfunc.h | 506 ---- .../kernel/arch/arm/boot/dts/imx28-sps1.dts | 171 -- .../kernel/arch/arm/boot/dts/imx28-tx28.dts | 723 ----- .../linux/kernel/arch/arm/boot/dts/imx28.dtsi | 1294 --------- .../kernel/arch/arm/boot/dts/imx31-bug.dts | 27 - .../linux/kernel/arch/arm/boot/dts/imx31.dtsi | 146 - .../arm/boot/dts/imx35-eukrea-cpuimx35.dtsi | 96 - .../dts/imx35-eukrea-mbimxsd35-baseboard.dts | 164 -- .../kernel/arch/arm/boot/dts/imx35-pdk.dts | 68 - .../kernel/arch/arm/boot/dts/imx35-pinfunc.h | 970 ------- .../linux/kernel/arch/arm/boot/dts/imx35.dtsi | 401 --- .../kernel/arch/arm/boot/dts/imx50-evk.dts | 119 - .../kernel/arch/arm/boot/dts/imx50-pinfunc.h | 923 ------- .../linux/kernel/arch/arm/boot/dts/imx50.dtsi | 502 ---- .../kernel/arch/arm/boot/dts/imx51-apf51.dts | 89 - .../arch/arm/boot/dts/imx51-apf51dev.dts | 225 -- .../arch/arm/boot/dts/imx51-babbage.dts | 655 ----- .../boot/dts/imx51-digi-connectcore-jsk.dts | 108 - .../boot/dts/imx51-digi-connectcore-som.dtsi | 377 --- .../arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | 104 - .../dts/imx51-eukrea-mbimxsd51-baseboard.dts | 294 -- .../kernel/arch/arm/boot/dts/imx51-pinfunc.h | 772 ------ .../kernel/arch/arm/boot/dts/imx51-ts4800.dts | 329 --- .../linux/kernel/arch/arm/boot/dts/imx51.dtsi | 592 ---- .../kernel/arch/arm/boot/dts/imx53-ard.dts | 183 -- .../kernel/arch/arm/boot/dts/imx53-m53.dtsi | 140 - .../kernel/arch/arm/boot/dts/imx53-m53evk.dts | 375 --- .../kernel/arch/arm/boot/dts/imx53-mba53.dts | 255 -- .../kernel/arch/arm/boot/dts/imx53-pinfunc.h | 1189 -------- .../arch/arm/boot/dts/imx53-qsb-common.dtsi | 368 --- .../kernel/arch/arm/boot/dts/imx53-qsb.dts | 115 - .../kernel/arch/arm/boot/dts/imx53-qsrb.dts | 154 -- .../kernel/arch/arm/boot/dts/imx53-smd.dts | 279 -- .../arch/arm/boot/dts/imx53-tqma53.dtsi | 288 -- .../arch/arm/boot/dts/imx53-tx53-x03x.dts | 325 --- .../arch/arm/boot/dts/imx53-tx53-x13x.dts | 261 -- .../kernel/arch/arm/boot/dts/imx53-tx53.dtsi | 549 ---- .../arch/arm/boot/dts/imx53-usbarmory.dts | 224 -- .../arch/arm/boot/dts/imx53-voipac-bsb.dts | 158 -- .../arm/boot/dts/imx53-voipac-dmm-668.dtsi | 277 -- .../linux/kernel/arch/arm/boot/dts/imx53.dtsi | 812 ------ .../arch/arm/boot/dts/imx6dl-apf6dev.dts | 60 - .../arm/boot/dts/imx6dl-aristainetos2_4.dts | 159 -- .../arm/boot/dts/imx6dl-aristainetos2_7.dts | 97 - .../arm/boot/dts/imx6dl-aristainetos_4.dts | 89 - .../arm/boot/dts/imx6dl-aristainetos_7.dts | 78 - .../arch/arm/boot/dts/imx6dl-cubox-i.dts | 49 - .../arm/boot/dts/imx6dl-dfi-fs700-m60.dts | 23 - .../arch/arm/boot/dts/imx6dl-gw51xx.dts | 19 - .../arch/arm/boot/dts/imx6dl-gw52xx.dts | 19 - .../arch/arm/boot/dts/imx6dl-gw53xx.dts | 19 - .../arch/arm/boot/dts/imx6dl-gw54xx.dts | 19 - .../arch/arm/boot/dts/imx6dl-gw551x.dts | 55 - .../arch/arm/boot/dts/imx6dl-gw552x.dts | 20 - .../arch/arm/boot/dts/imx6dl-gw553x.dts | 55 - .../arch/arm/boot/dts/imx6dl-hummingboard.dts | 50 - .../arch/arm/boot/dts/imx6dl-nit6xlite.dts | 49 - .../arch/arm/boot/dts/imx6dl-nitrogen6x.dts | 51 - .../arm/boot/dts/imx6dl-phytec-pbab01.dts | 19 - .../arm/boot/dts/imx6dl-phytec-pfla02.dtsi | 22 - .../kernel/arch/arm/boot/dts/imx6dl-pinfunc.h | 1091 -------- .../arch/arm/boot/dts/imx6dl-rex-basic.dts | 30 - .../arch/arm/boot/dts/imx6dl-riotboard.dts | 539 ---- .../arch/arm/boot/dts/imx6dl-sabreauto.dts | 17 - .../arch/arm/boot/dts/imx6dl-sabrelite.dts | 50 - .../arch/arm/boot/dts/imx6dl-sabresd.dts | 17 - .../arch/arm/boot/dts/imx6dl-ts4900.dts | 49 - .../arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts | 133 - .../arch/arm/boot/dts/imx6dl-tx6s-8034.dts | 237 -- .../arch/arm/boot/dts/imx6dl-tx6s-8035.dts | 253 -- .../arch/arm/boot/dts/imx6dl-tx6u-801x.dts | 207 -- .../arch/arm/boot/dts/imx6dl-tx6u-8033.dts | 248 -- .../arch/arm/boot/dts/imx6dl-tx6u-811x.dts | 178 -- .../arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts | 255 -- .../kernel/arch/arm/boot/dts/imx6dl-udoo.dts | 18 - .../arm/boot/dts/imx6dl-wandboard-revb1.dts | 22 - .../arch/arm/boot/dts/imx6dl-wandboard.dts | 22 - .../kernel/arch/arm/boot/dts/imx6dl.dtsi | 186 -- .../arch/arm/boot/dts/imx6q-apalis-ixora.dts | 318 --- .../arch/arm/boot/dts/imx6q-apf6dev.dts | 64 - .../kernel/arch/arm/boot/dts/imx6q-arm2.dts | 230 -- .../kernel/arch/arm/boot/dts/imx6q-b450v3.dts | 107 - .../kernel/arch/arm/boot/dts/imx6q-b650v3.dts | 100 - .../kernel/arch/arm/boot/dts/imx6q-b850v3.dts | 144 - .../kernel/arch/arm/boot/dts/imx6q-ba16.dtsi | 634 ----- .../arch/arm/boot/dts/imx6q-bx50v3.dtsi | 301 -- .../kernel/arch/arm/boot/dts/imx6q-cm-fx6.dts | 281 -- .../arch/arm/boot/dts/imx6q-cubox-i.dts | 57 - .../arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts | 23 - .../arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 487 ---- .../kernel/arch/arm/boot/dts/imx6q-evi.dts | 506 ---- .../kernel/arch/arm/boot/dts/imx6q-gk802.dts | 177 -- .../kernel/arch/arm/boot/dts/imx6q-gw51xx.dts | 19 - .../kernel/arch/arm/boot/dts/imx6q-gw52xx.dts | 23 - .../kernel/arch/arm/boot/dts/imx6q-gw53xx.dts | 23 - .../arch/arm/boot/dts/imx6q-gw5400-a.dts | 524 ---- .../kernel/arch/arm/boot/dts/imx6q-gw54xx.dts | 23 - .../kernel/arch/arm/boot/dts/imx6q-gw551x.dts | 55 - .../kernel/arch/arm/boot/dts/imx6q-gw552x.dts | 24 - .../kernel/arch/arm/boot/dts/imx6q-gw553x.dts | 55 - .../kernel/arch/arm/boot/dts/imx6q-h100.dts | 395 --- .../arch/arm/boot/dts/imx6q-hummingboard.dts | 58 - .../arch/arm/boot/dts/imx6q-icore-rqs.dts | 78 - .../arch/arm/boot/dts/imx6q-marsboard.dts | 403 --- .../arch/arm/boot/dts/imx6q-nitrogen6_max.dts | 53 - .../arch/arm/boot/dts/imx6q-nitrogen6x.dts | 55 - .../kernel/arch/arm/boot/dts/imx6q-novena.dts | 785 ------ .../arch/arm/boot/dts/imx6q-phytec-pbab01.dts | 27 - .../arm/boot/dts/imx6q-phytec-pfla02.dtsi | 22 - .../kernel/arch/arm/boot/dts/imx6q-pinfunc.h | 1047 ------- .../arch/arm/boot/dts/imx6q-rex-pro.dts | 34 - .../arch/arm/boot/dts/imx6q-sabreauto.dts | 25 - .../arch/arm/boot/dts/imx6q-sabrelite.dts | 54 - .../arch/arm/boot/dts/imx6q-sabresd.dts | 25 - .../kernel/arch/arm/boot/dts/imx6q-sbc6x.dts | 94 - .../arch/arm/boot/dts/imx6q-tbs2910.dts | 430 --- .../kernel/arch/arm/boot/dts/imx6q-ts4900.dts | 53 - .../arm/boot/dts/imx6q-tx6q-1010-comtft.dts | 133 - .../arch/arm/boot/dts/imx6q-tx6q-1010.dts | 207 -- .../arm/boot/dts/imx6q-tx6q-1020-comtft.dts | 164 -- .../arch/arm/boot/dts/imx6q-tx6q-1020.dts | 238 -- .../arch/arm/boot/dts/imx6q-tx6q-1036.dts | 252 -- .../arch/arm/boot/dts/imx6q-tx6q-1110.dts | 182 -- .../arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts | 264 -- .../kernel/arch/arm/boot/dts/imx6q-udoo.dts | 22 - .../arch/arm/boot/dts/imx6q-utilite-pro.dts | 197 -- .../arm/boot/dts/imx6q-wandboard-revb1.dts | 26 - .../arch/arm/boot/dts/imx6q-wandboard.dts | 26 - .../linux/kernel/arch/arm/boot/dts/imx6q.dtsi | 337 --- .../arch/arm/boot/dts/imx6qdl-apalis.dtsi | 984 ------- .../arch/arm/boot/dts/imx6qdl-apf6.dtsi | 158 -- .../arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 479 ---- .../arm/boot/dts/imx6qdl-aristainetos.dtsi | 418 --- .../arm/boot/dts/imx6qdl-aristainetos2.dtsi | 633 ----- .../arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 263 -- .../arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 201 -- .../arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 380 --- .../arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 568 ---- .../arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 558 ---- .../arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 678 ----- .../arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 349 --- .../arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 302 -- .../arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 433 --- .../arm/boot/dts/imx6qdl-hummingboard.dtsi | 304 --- .../arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 411 --- .../arm/boot/dts/imx6qdl-microsom-ar8035.dtsi | 99 - .../arch/arm/boot/dts/imx6qdl-microsom.dtsi | 161 -- .../arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 631 ----- .../arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 874 ------ .../arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 682 ----- .../arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 181 -- .../arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 436 --- .../kernel/arch/arm/boot/dts/imx6qdl-rex.dtsi | 354 --- .../arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 630 ----- .../arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 607 ----- .../arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 615 ----- .../arch/arm/boot/dts/imx6qdl-ts4900.dtsi | 481 ---- .../kernel/arch/arm/boot/dts/imx6qdl-tx6.dtsi | 744 ----- .../arch/arm/boot/dts/imx6qdl-udoo.dtsi | 287 -- .../arm/boot/dts/imx6qdl-wandboard-revb1.dtsi | 42 - .../arm/boot/dts/imx6qdl-wandboard-revc1.dtsi | 41 - .../arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 265 -- .../kernel/arch/arm/boot/dts/imx6qdl.dtsi | 1281 --------- .../arm/boot/dts/imx6qp-nitrogen6_max.dts | 59 - .../arch/arm/boot/dts/imx6qp-sabreauto.dts | 93 - .../arch/arm/boot/dts/imx6qp-sabresd.dts | 93 - .../kernel/arch/arm/boot/dts/imx6qp.dtsi | 89 - .../kernel/arch/arm/boot/dts/imx6sl-evk.dts | 642 ----- .../kernel/arch/arm/boot/dts/imx6sl-pinfunc.h | 1077 -------- .../kernel/arch/arm/boot/dts/imx6sl-warp.dts | 233 -- .../kernel/arch/arm/boot/dts/imx6sl.dtsi | 913 ------- .../arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 709 ----- .../kernel/arch/arm/boot/dts/imx6sx-pinfunc.h | 1558 ----------- .../arch/arm/boot/dts/imx6sx-sabreauto.dts | 146 - .../arch/arm/boot/dts/imx6sx-sdb-reva.dts | 143 - .../arch/arm/boot/dts/imx6sx-sdb-sai.dts | 67 - .../kernel/arch/arm/boot/dts/imx6sx-sdb.dts | 130 - .../kernel/arch/arm/boot/dts/imx6sx-sdb.dtsi | 604 ---- .../kernel/arch/arm/boot/dts/imx6sx.dtsi | 1298 --------- .../arch/arm/boot/dts/imx6ul-14x14-evk.dts | 499 ---- .../arch/arm/boot/dts/imx6ul-geam-kit.dts | 101 - .../kernel/arch/arm/boot/dts/imx6ul-geam.dtsi | 361 --- .../arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 549 ---- .../kernel/arch/arm/boot/dts/imx6ul-pinfunc.h | 938 ------- .../arch/arm/boot/dts/imx6ul-tx6ul-0010.dts | 53 - .../arch/arm/boot/dts/imx6ul-tx6ul-0011.dts | 68 - .../arm/boot/dts/imx6ul-tx6ul-mainboard.dts | 271 -- .../arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 973 ------- .../kernel/arch/arm/boot/dts/imx6ul.dtsi | 942 ------- .../arm/boot/dts/imx7-colibri-eval-v3.dtsi | 144 - .../arch/arm/boot/dts/imx7-colibri.dtsi | 624 ----- .../arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 285 -- .../arm/boot/dts/imx7d-colibri-eval-v3.dts | 66 - .../arch/arm/boot/dts/imx7d-colibri.dtsi | 54 - .../arch/arm/boot/dts/imx7d-nitrogen7.dts | 744 ----- .../kernel/arch/arm/boot/dts/imx7d-pinfunc.h | 1154 -------- .../arch/arm/boot/dts/imx7d-sbc-imx7.dts | 42 - .../kernel/arch/arm/boot/dts/imx7d-sdb.dts | 645 ----- .../linux/kernel/arch/arm/boot/dts/imx7d.dtsi | 140 - .../arm/boot/dts/imx7s-colibri-eval-v3.dts | 51 - .../arch/arm/boot/dts/imx7s-colibri.dtsi | 50 - .../kernel/arch/arm/boot/dts/imx7s-warp.dts | 446 --- .../linux/kernel/arch/arm/boot/dts/imx7s.dtsi | 991 ------- .../arch/arm/boot/dts/infinity2m-BGA128M.dts | 71 - .../arm/boot/dts/infinity2m-clks_simple.dtsi | 834 ------ .../arm/boot/dts/infinity2m-doublenet.dtsi | 4 - .../arch/arm/boot/dts/infinity2m-fpga.dts | 79 - .../arch/arm/boot/dts/infinity2m-fpga.dtsi | 523 ---- .../arch/arm/boot/dts/infinity2m-fusionx.dtsi | 25 +- .../arch/arm/boot/dts/infinity2m-gates.dtsi | 174 -- .../dts/infinity2m-ssc011a-s01a-fusionx.dtsi | 25 +- ...nfinity2m-ssc011a-s01a-padmux-fusionx.dtsi | 10 +- .../kernel/arch/arm/boot/dts/infinity2m.dtsi | 581 ---- .../kernel/arch/arm/boot/dts/integrator.dtsi | 133 - .../kernel/arch/arm/boot/dts/integratorap.dts | 202 -- .../kernel/arch/arm/boot/dts/integratorcp.dts | 267 -- .../arch/arm/boot/dts/keystone-clocks.dtsi | 414 --- .../arm/boot/dts/keystone-k2e-clocks.dtsi | 77 - .../arch/arm/boot/dts/keystone-k2e-evm.dts | 162 -- .../arch/arm/boot/dts/keystone-k2e-netcp.dtsi | 229 -- .../arch/arm/boot/dts/keystone-k2e.dtsi | 153 -- .../arch/arm/boot/dts/keystone-k2g-evm.dts | 43 - .../arch/arm/boot/dts/keystone-k2g.dtsi | 129 - .../arm/boot/dts/keystone-k2hk-clocks.dtsi | 425 --- .../arch/arm/boot/dts/keystone-k2hk-evm.dts | 186 -- .../arm/boot/dts/keystone-k2hk-netcp.dtsi | 232 -- .../arch/arm/boot/dts/keystone-k2hk.dtsi | 117 - .../arm/boot/dts/keystone-k2l-clocks.dtsi | 266 -- .../arch/arm/boot/dts/keystone-k2l-evm.dts | 135 - .../arch/arm/boot/dts/keystone-k2l-netcp.dtsi | 212 -- .../arch/arm/boot/dts/keystone-k2l.dtsi | 260 -- .../kernel/arch/arm/boot/dts/keystone.dtsi | 339 --- .../arch/arm/boot/dts/kirkwood-6192.dtsi | 86 - .../arch/arm/boot/dts/kirkwood-6281.dtsi | 88 - .../arch/arm/boot/dts/kirkwood-6282.dtsi | 138 - .../arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 51 - .../kernel/arch/arm/boot/dts/kirkwood-b3.dts | 198 -- .../boot/dts/kirkwood-blackarmor-nas220.dts | 173 -- .../arch/arm/boot/dts/kirkwood-cloudbox.dts | 102 - .../arch/arm/boot/dts/kirkwood-d2net.dts | 47 - .../arch/arm/boot/dts/kirkwood-db-88f6281.dts | 28 - .../arch/arm/boot/dts/kirkwood-db-88f6282.dts | 32 - .../kernel/arch/arm/boot/dts/kirkwood-db.dtsi | 92 - .../arch/arm/boot/dts/kirkwood-dir665.dts | 276 -- .../arch/arm/boot/dts/kirkwood-dns320.dts | 58 - .../arch/arm/boot/dts/kirkwood-dns325.dts | 62 - .../arch/arm/boot/dts/kirkwood-dnskw.dtsi | 234 -- .../arch/arm/boot/dts/kirkwood-dockstar.dts | 109 - .../arch/arm/boot/dts/kirkwood-dreamplug.dts | 126 - .../arch/arm/boot/dts/kirkwood-ds109.dts | 42 - .../arch/arm/boot/dts/kirkwood-ds110jv10.dts | 42 - .../arch/arm/boot/dts/kirkwood-ds111.dts | 45 - .../arch/arm/boot/dts/kirkwood-ds112.dts | 53 - .../arch/arm/boot/dts/kirkwood-ds209.dts | 45 - .../arch/arm/boot/dts/kirkwood-ds210.dts | 47 - .../arch/arm/boot/dts/kirkwood-ds212.dts | 48 - .../arch/arm/boot/dts/kirkwood-ds212j.dts | 42 - .../arch/arm/boot/dts/kirkwood-ds409.dts | 49 - .../arch/arm/boot/dts/kirkwood-ds409slim.dts | 41 - .../arch/arm/boot/dts/kirkwood-ds411.dts | 57 - .../arch/arm/boot/dts/kirkwood-ds411j.dts | 49 - .../arch/arm/boot/dts/kirkwood-ds411slim.dts | 49 - .../arch/arm/boot/dts/kirkwood-goflexnet.dts | 189 -- .../dts/kirkwood-guruplug-server-plus.dts | 132 - .../arch/arm/boot/dts/kirkwood-ib62x0.dts | 145 - .../arch/arm/boot/dts/kirkwood-iconnect.dts | 194 -- .../arm/boot/dts/kirkwood-iomega_ix2_200.dts | 225 -- .../kernel/arch/arm/boot/dts/kirkwood-is2.dts | 39 - .../arch/arm/boot/dts/kirkwood-km_common.dtsi | 46 - .../arm/boot/dts/kirkwood-km_fixedeth.dts | 23 - .../arm/boot/dts/kirkwood-km_kirkwood.dts | 30 - .../arch/arm/boot/dts/kirkwood-laplug.dts | 170 -- .../boot/dts/kirkwood-linkstation-6282.dtsi | 192 -- .../dts/kirkwood-linkstation-duo-6281.dtsi | 186 -- .../boot/dts/kirkwood-linkstation-lsqvl.dts | 135 - .../boot/dts/kirkwood-linkstation-lsvl.dts | 57 - .../boot/dts/kirkwood-linkstation-lswsxl.dts | 57 - .../boot/dts/kirkwood-linkstation-lswvl.dts | 112 - .../boot/dts/kirkwood-linkstation-lswxl.dts | 116 - .../arm/boot/dts/kirkwood-linkstation.dtsi | 201 -- .../arm/boot/dts/kirkwood-linksys-viper.dts | 240 -- .../arch/arm/boot/dts/kirkwood-lschlv2.dts | 19 - .../arch/arm/boot/dts/kirkwood-lsxhl.dts | 19 - .../arch/arm/boot/dts/kirkwood-lsxl.dtsi | 236 -- .../arch/arm/boot/dts/kirkwood-mplcec4.dts | 215 -- .../arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 179 -- .../arch/arm/boot/dts/kirkwood-nas2big.dts | 141 - .../arch/arm/boot/dts/kirkwood-net2big.dts | 65 - .../arch/arm/boot/dts/kirkwood-net5big.dts | 171 -- .../dts/kirkwood-netgear_readynas_duo_v2.dts | 251 -- .../dts/kirkwood-netgear_readynas_nv+_v2.dts | 264 -- .../arch/arm/boot/dts/kirkwood-netxbig.dtsi | 234 -- .../arm/boot/dts/kirkwood-ns2-common.dtsi | 96 - .../kernel/arch/arm/boot/dts/kirkwood-ns2.dts | 39 - .../arch/arm/boot/dts/kirkwood-ns2lite.dts | 34 - .../arch/arm/boot/dts/kirkwood-ns2max.dts | 58 - .../arch/arm/boot/dts/kirkwood-ns2mini.dts | 59 - .../arch/arm/boot/dts/kirkwood-nsa310.dts | 138 - .../arch/arm/boot/dts/kirkwood-nsa310a.dts | 114 - .../arch/arm/boot/dts/kirkwood-nsa320.dts | 222 -- .../arch/arm/boot/dts/kirkwood-nsa325.dts | 235 -- .../arm/boot/dts/kirkwood-nsa3x0-common.dtsi | 157 -- .../arm/boot/dts/kirkwood-openblocks_a6.dts | 183 -- .../arm/boot/dts/kirkwood-openblocks_a7.dts | 211 -- .../arm/boot/dts/kirkwood-openrd-base.dts | 42 - .../arm/boot/dts/kirkwood-openrd-client.dts | 77 - .../arm/boot/dts/kirkwood-openrd-ultimate.dts | 58 - .../arch/arm/boot/dts/kirkwood-openrd.dtsi | 125 - .../arch/arm/boot/dts/kirkwood-pogo_e02.dts | 134 - .../boot/dts/kirkwood-pogoplug-series-4.dts | 179 -- .../arch/arm/boot/dts/kirkwood-rd88f6192.dts | 109 - .../arm/boot/dts/kirkwood-rd88f6281-a.dts | 43 - .../arm/boot/dts/kirkwood-rd88f6281-z0.dts | 35 - .../arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 134 - .../arch/arm/boot/dts/kirkwood-rs212.dts | 53 - .../arch/arm/boot/dts/kirkwood-rs409.dts | 45 - .../arch/arm/boot/dts/kirkwood-rs411.dts | 45 - .../boot/dts/kirkwood-sheevaplug-common.dtsi | 105 - .../boot/dts/kirkwood-sheevaplug-esata.dts | 43 - .../arch/arm/boot/dts/kirkwood-sheevaplug.dts | 43 - .../arch/arm/boot/dts/kirkwood-synology.dtsi | 857 ------ .../arch/arm/boot/dts/kirkwood-t5325.dts | 229 -- .../arch/arm/boot/dts/kirkwood-topkick.dts | 215 -- .../arch/arm/boot/dts/kirkwood-ts219-6281.dts | 55 - .../arch/arm/boot/dts/kirkwood-ts219-6282.dts | 57 - .../arch/arm/boot/dts/kirkwood-ts219.dtsi | 105 - .../arch/arm/boot/dts/kirkwood-ts419-6281.dts | 20 - .../arch/arm/boot/dts/kirkwood-ts419-6282.dts | 23 - .../arch/arm/boot/dts/kirkwood-ts419.dtsi | 75 - .../kernel/arch/arm/boot/dts/kirkwood.dtsi | 392 --- .../boot/dts/logicpd-som-lv-37xx-devkit.dts | 264 -- .../arch/arm/boot/dts/logicpd-som-lv.dtsi | 275 -- .../boot/dts/logicpd-torpedo-37xx-devkit.dts | 404 --- .../arm/boot/dts/logicpd-torpedo-som.dtsi | 244 -- .../kernel/arch/arm/boot/dts/lpc18xx.dtsi | 538 ---- .../arch/arm/boot/dts/lpc3250-ea3250.dts | 272 -- .../arch/arm/boot/dts/lpc3250-phy3250.dts | 226 -- .../kernel/arch/arm/boot/dts/lpc32xx.dtsi | 502 ---- .../kernel/arch/arm/boot/dts/lpc4337-ciaa.dts | 221 -- .../arch/arm/boot/dts/lpc4350-hitex-eval.dts | 483 ---- .../kernel/arch/arm/boot/dts/lpc4350.dtsi | 39 - .../arm/boot/dts/lpc4357-ea4357-devkit.dts | 625 ----- .../kernel/arch/arm/boot/dts/lpc4357.dtsi | 43 - .../kernel/arch/arm/boot/dts/ls1021a-qds.dts | 333 --- .../kernel/arch/arm/boot/dts/ls1021a-twr.dts | 245 -- .../kernel/arch/arm/boot/dts/ls1021a.dtsi | 678 ----- .../linux/kernel/arch/arm/boot/dts/meson.dtsi | 175 -- .../arch/arm/boot/dts/meson6-atv1200.dts | 70 - .../kernel/arch/arm/boot/dts/meson6.dtsi | 80 - .../arch/arm/boot/dts/meson8-minix-neo-x8.dts | 129 - .../kernel/arch/arm/boot/dts/meson8.dtsi | 167 -- .../kernel/arch/arm/boot/dts/meson8b-mxq.dts | 67 - .../arch/arm/boot/dts/meson8b-odroidc1.dts | 78 - .../kernel/arch/arm/boot/dts/meson8b.dtsi | 228 -- .../arch/arm/boot/dts/mmp2-brownstone.dts | 196 -- .../linux/kernel/arch/arm/boot/dts/mmp2.dtsi | 254 -- .../arch/arm/boot/dts/moxart-uc7112lx.dts | 117 - .../kernel/arch/arm/boot/dts/moxart.dtsi | 148 - .../kernel/arch/arm/boot/dts/mpa1600.dts | 68 - .../kernel/arch/arm/boot/dts/mps2-an385.dts | 92 - .../kernel/arch/arm/boot/dts/mps2-an399.dts | 92 - .../linux/kernel/arch/arm/boot/dts/mps2.dtsi | 242 -- .../kernel/arch/arm/boot/dts/mt2701-evb.dts | 29 - .../kernel/arch/arm/boot/dts/mt2701-pinfunc.h | 735 ----- .../kernel/arch/arm/boot/dts/mt2701.dtsi | 215 -- .../kernel/arch/arm/boot/dts/mt6580-evbp1.dts | 38 - .../kernel/arch/arm/boot/dts/mt6580.dtsi | 116 - .../arch/arm/boot/dts/mt6589-aquaris5.dts | 40 - .../kernel/arch/arm/boot/dts/mt6589.dtsi | 147 - .../kernel/arch/arm/boot/dts/mt6592-evb.dts | 26 - .../kernel/arch/arm/boot/dts/mt6592.dtsi | 143 - .../kernel/arch/arm/boot/dts/mt7623-evb.dts | 33 - .../kernel/arch/arm/boot/dts/mt7623.dtsi | 147 - .../kernel/arch/arm/boot/dts/mt8127-moose.dts | 29 - .../kernel/arch/arm/boot/dts/mt8127.dtsi | 169 -- .../kernel/arch/arm/boot/dts/mt8135-evbp1.dts | 199 -- .../kernel/arch/arm/boot/dts/mt8135-pinfunc.h | 1302 --------- .../kernel/arch/arm/boot/dts/mt8135.dtsi | 266 -- .../arm/boot/dts/mvebu-linkstation-fan.dtsi | 72 - .../dts/mvebu-linkstation-gpio-simple.dtsi | 105 - .../kernel/arch/arm/boot/dts/mxs-pinfunc.h | 31 - .../arch/arm/boot/dts/nspire-classic.dtsi | 79 - .../kernel/arch/arm/boot/dts/nspire-clp.dts | 45 - .../kernel/arch/arm/boot/dts/nspire-cx.dts | 116 - .../kernel/arch/arm/boot/dts/nspire-tp.dts | 44 - .../kernel/arch/arm/boot/dts/nspire.dtsi | 196 -- .../arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi | 54 - .../arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi | 58 - .../arch/arm/boot/dts/omap-zoom-common.dtsi | 91 - .../linux/kernel/arch/arm/boot/dts/omap2.dtsi | 299 -- .../arch/arm/boot/dts/omap2420-clocks.dtsi | 270 -- .../kernel/arch/arm/boot/dts/omap2420-h4.dts | 66 - .../arch/arm/boot/dts/omap2420-n800.dts | 8 - .../arch/arm/boot/dts/omap2420-n810-wimax.dts | 8 - .../arch/arm/boot/dts/omap2420-n810.dts | 15 - .../arm/boot/dts/omap2420-n8x0-common.dtsi | 105 - .../kernel/arch/arm/boot/dts/omap2420.dtsi | 220 -- .../arch/arm/boot/dts/omap2430-clocks.dtsi | 344 --- .../kernel/arch/arm/boot/dts/omap2430-sdp.dts | 73 - .../kernel/arch/arm/boot/dts/omap2430.dtsi | 319 --- .../arch/arm/boot/dts/omap24xx-clocks.dtsi | 1244 --------- .../arch/arm/boot/dts/omap3-beagle-xm-ab.dts | 16 - .../arch/arm/boot/dts/omap3-beagle-xm.dts | 392 --- .../kernel/arch/arm/boot/dts/omap3-beagle.dts | 435 --- .../arch/arm/boot/dts/omap3-cm-t3517.dts | 157 -- .../arch/arm/boot/dts/omap3-cm-t3530.dts | 59 - .../arch/arm/boot/dts/omap3-cm-t3730.dts | 97 - .../arch/arm/boot/dts/omap3-cm-t3x.dtsi | 323 --- .../arch/arm/boot/dts/omap3-cm-t3x30.dtsi | 130 - .../arm/boot/dts/omap3-devkit8000-common.dtsi | 373 --- .../boot/dts/omap3-devkit8000-lcd-common.dtsi | 73 - .../arm/boot/dts/omap3-devkit8000-lcd43.dts | 37 - .../arm/boot/dts/omap3-devkit8000-lcd70.dts | 37 - .../arch/arm/boot/dts/omap3-devkit8000.dts | 19 - .../arch/arm/boot/dts/omap3-evm-37xx.dts | 215 -- .../arch/arm/boot/dts/omap3-evm-common.dtsi | 161 -- .../kernel/arch/arm/boot/dts/omap3-evm.dts | 21 - .../kernel/arch/arm/boot/dts/omap3-gta04.dtsi | 620 ----- .../arch/arm/boot/dts/omap3-gta04a3.dts | 48 - .../arch/arm/boot/dts/omap3-gta04a4.dts | 13 - .../arch/arm/boot/dts/omap3-gta04a5.dts | 17 - .../arch/arm/boot/dts/omap3-ha-common.dtsi | 88 - .../kernel/arch/arm/boot/dts/omap3-ha-lcd.dts | 165 -- .../kernel/arch/arm/boot/dts/omap3-ha.dts | 28 - .../kernel/arch/arm/boot/dts/omap3-igep.dtsi | 219 -- .../arm/boot/dts/omap3-igep0020-common.dtsi | 263 -- .../arm/boot/dts/omap3-igep0020-rev-f.dts | 54 - .../arch/arm/boot/dts/omap3-igep0020.dts | 50 - .../arm/boot/dts/omap3-igep0030-common.dtsi | 105 - .../arm/boot/dts/omap3-igep0030-rev-g.dts | 76 - .../arch/arm/boot/dts/omap3-igep0030.dts | 62 - .../kernel/arch/arm/boot/dts/omap3-ldp.dts | 308 --- .../arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 462 ---- .../arch/arm/boot/dts/omap3-lilly-dbb056.dts | 170 -- .../kernel/arch/arm/boot/dts/omap3-n9.dts | 73 - .../kernel/arch/arm/boot/dts/omap3-n900.dts | 1029 ------- .../arch/arm/boot/dts/omap3-n950-n9.dtsi | 437 --- .../kernel/arch/arm/boot/dts/omap3-n950.dts | 187 -- .../boot/dts/omap3-overo-alto35-common.dtsi | 78 - .../arch/arm/boot/dts/omap3-overo-alto35.dts | 22 - .../arch/arm/boot/dts/omap3-overo-base.dtsi | 287 -- .../dts/omap3-overo-chestnut43-common.dtsi | 68 - .../arm/boot/dts/omap3-overo-chestnut43.dts | 38 - .../arm/boot/dts/omap3-overo-common-dvi.dtsi | 111 - .../boot/dts/omap3-overo-common-lcd35.dtsi | 166 -- .../boot/dts/omap3-overo-common-lcd43.dtsi | 178 -- .../dts/omap3-overo-common-peripherals.dtsi | 95 - .../boot/dts/omap3-overo-gallop43-common.dtsi | 58 - .../arm/boot/dts/omap3-overo-gallop43.dts | 38 - .../boot/dts/omap3-overo-palo35-common.dtsi | 53 - .../arch/arm/boot/dts/omap3-overo-palo35.dts | 37 - .../boot/dts/omap3-overo-palo43-common.dtsi | 54 - .../arch/arm/boot/dts/omap3-overo-palo43.dts | 38 - .../arm/boot/dts/omap3-overo-storm-alto35.dts | 21 - .../boot/dts/omap3-overo-storm-chestnut43.dts | 38 - .../boot/dts/omap3-overo-storm-gallop43.dts | 38 - .../arm/boot/dts/omap3-overo-storm-palo35.dts | 37 - .../arm/boot/dts/omap3-overo-storm-palo43.dts | 38 - .../arm/boot/dts/omap3-overo-storm-summit.dts | 30 - .../arm/boot/dts/omap3-overo-storm-tobi.dts | 22 - .../boot/dts/omap3-overo-storm-tobiduo.dts | 21 - .../arch/arm/boot/dts/omap3-overo-storm.dtsi | 35 - .../boot/dts/omap3-overo-summit-common.dtsi | 32 - .../arch/arm/boot/dts/omap3-overo-summit.dts | 30 - .../arm/boot/dts/omap3-overo-tobi-common.dtsi | 40 - .../arch/arm/boot/dts/omap3-overo-tobi.dts | 22 - .../boot/dts/omap3-overo-tobiduo-common.dtsi | 62 - .../arch/arm/boot/dts/omap3-overo-tobiduo.dts | 21 - .../kernel/arch/arm/boot/dts/omap3-overo.dtsi | 34 - .../arch/arm/boot/dts/omap3-pandora-1ghz.dts | 70 - .../arm/boot/dts/omap3-pandora-600mhz.dts | 65 - .../arm/boot/dts/omap3-pandora-common.dtsi | 690 ----- .../dts/omap3-panel-sharp-ls037v7dw01.dtsi | 71 - .../arch/arm/boot/dts/omap3-sb-t35.dtsi | 138 - .../arch/arm/boot/dts/omap3-sbc-t3517.dts | 75 - .../arch/arm/boot/dts/omap3-sbc-t3530.dts | 47 - .../arch/arm/boot/dts/omap3-sbc-t3730.dts | 43 - .../kernel/arch/arm/boot/dts/omap3-sniper.dts | 254 -- .../arch/arm/boot/dts/omap3-tao3530.dtsi | 349 --- .../arch/arm/boot/dts/omap3-thunder.dts | 129 - .../kernel/arch/arm/boot/dts/omap3-zoom3.dts | 234 -- .../linux/kernel/arch/arm/boot/dts/omap3.dtsi | 853 ------ .../kernel/arch/arm/boot/dts/omap3430-sdp.dts | 197 -- .../arch/arm/boot/dts/omap3430es1-clocks.dtsi | 208 -- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 268 -- .../kernel/arch/arm/boot/dts/omap34xx.dtsi | 79 - ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 242 -- .../arch/arm/boot/dts/omap36xx-clocks.dtsi | 110 - .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 198 -- .../kernel/arch/arm/boot/dts/omap36xx.dtsi | 118 - .../arch/arm/boot/dts/omap3xxx-clocks.dtsi | 1665 ------------ .../arch/arm/boot/dts/omap4-cpu-thermal.dtsi | 41 - .../arm/boot/dts/omap4-duovero-parlor.dts | 195 -- .../arch/arm/boot/dts/omap4-duovero.dtsi | 265 -- .../kernel/arch/arm/boot/dts/omap4-kc1.dts | 182 -- .../arch/arm/boot/dts/omap4-panda-a4.dts | 20 - .../arch/arm/boot/dts/omap4-panda-common.dtsi | 550 ---- .../arch/arm/boot/dts/omap4-panda-es.dts | 73 - .../kernel/arch/arm/boot/dts/omap4-panda.dts | 16 - .../arch/arm/boot/dts/omap4-sdp-es23plus.dts | 17 - .../kernel/arch/arm/boot/dts/omap4-sdp.dts | 704 ----- .../arch/arm/boot/dts/omap4-var-dvk-om44.dts | 71 - .../boot/dts/omap4-var-om44customboard.dtsi | 235 -- .../arm/boot/dts/omap4-var-som-om44-wlan.dtsi | 78 - .../arch/arm/boot/dts/omap4-var-som-om44.dtsi | 346 --- .../arch/arm/boot/dts/omap4-var-stk-om44.dts | 17 - .../linux/kernel/arch/arm/boot/dts/omap4.dtsi | 1026 ------- .../arch/arm/boot/dts/omap443x-clocks.dtsi | 18 - .../kernel/arch/arm/boot/dts/omap443x.dtsi | 74 - .../kernel/arch/arm/boot/dts/omap4460.dtsi | 93 - .../arch/arm/boot/dts/omap446x-clocks.dtsi | 27 - .../arch/arm/boot/dts/omap44xx-clocks.dtsi | 1643 ----------- .../arch/arm/boot/dts/omap5-board-common.dtsi | 749 ----- .../kernel/arch/arm/boot/dts/omap5-cm-t54.dts | 684 ----- .../arch/arm/boot/dts/omap5-core-thermal.dtsi | 28 - .../arch/arm/boot/dts/omap5-gpu-thermal.dtsi | 28 - .../arch/arm/boot/dts/omap5-igep0050.dts | 118 - .../arch/arm/boot/dts/omap5-sbc-t54.dts | 51 - .../kernel/arch/arm/boot/dts/omap5-uevm.dts | 98 - .../linux/kernel/arch/arm/boot/dts/omap5.dtsi | 1130 -------- .../arch/arm/boot/dts/omap54xx-clocks.dtsi | 1390 ---------- ...and-ssc011a-s01a-rgb565-rmii-doublenet.dts | 0 .../arch/arm/boot/dts/orion5x-kuroboxpro.dts | 127 - .../arm/boot/dts/orion5x-lacie-d2-network.dts | 236 -- .../orion5x-lacie-ethernet-disk-mini-v2.dts | 174 -- .../arm/boot/dts/orion5x-linkstation-lsgl.dts | 91 - .../boot/dts/orion5x-linkstation-lswtgl.dts | 151 - .../arm/boot/dts/orion5x-linkstation.dtsi | 180 -- .../arch/arm/boot/dts/orion5x-lswsgl.dts | 276 -- .../dts/orion5x-maxtor-shared-storage-2.dts | 178 -- .../arch/arm/boot/dts/orion5x-mv88f5181.dtsi | 49 - .../arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 45 - .../arm/boot/dts/orion5x-netgear-wnr854t.dts | 251 -- .../arm/boot/dts/orion5x-rd88f5182-nas.dts | 177 -- .../kernel/arch/arm/boot/dts/orion5x.dtsi | 241 -- .../kernel/arch/arm/boot/dts/ox810se.dtsi | 336 --- .../arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 249 -- .../arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 365 --- .../arm/boot/dts/picoxcell-pc7302-pc3x2.dts | 86 - .../arm/boot/dts/picoxcell-pc7302-pc3x3.dts | 92 - .../linux/kernel/arch/arm/boot/dts/pm9g45.dts | 164 -- .../kernel/arch/arm/boot/dts/prima2-evb.dts | 37 - .../kernel/arch/arm/boot/dts/prima2.dtsi | 840 ------ .../arch/arm/boot/dts/pxa168-aspenite.dts | 38 - .../kernel/arch/arm/boot/dts/pxa168.dtsi | 158 -- .../kernel/arch/arm/boot/dts/pxa27x.dtsi | 140 - .../kernel/arch/arm/boot/dts/pxa2xx.dtsi | 152 -- .../kernel/arch/arm/boot/dts/pxa3xx.dtsi | 254 -- .../kernel/arch/arm/boot/dts/pxa910-dkb.dts | 175 -- .../kernel/arch/arm/boot/dts/pxa910.dtsi | 175 -- .../arm/boot/dts/qcom-apq8060-dragonboard.dts | 665 ----- .../qcom-apq8064-arrow-sd-600eval-pins.dtsi | 52 - .../dts/qcom-apq8064-arrow-sd-600eval.dts | 351 --- .../boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 291 -- .../arm/boot/dts/qcom-apq8064-cm-qs600.dts | 250 -- .../arm/boot/dts/qcom-apq8064-ifc6410.dts | 333 --- .../arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 287 -- .../dts/qcom-apq8064-sony-xperia-yuga.dts | 394 --- .../arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 - .../arch/arm/boot/dts/qcom-apq8064.dtsi | 1100 -------- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 325 --- .../arm/boot/dts/qcom-apq8084-ifc6540.dts | 33 - .../arch/arm/boot/dts/qcom-apq8084-mtp.dts | 22 - .../arch/arm/boot/dts/qcom-apq8084.dtsi | 518 ---- .../boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 - .../arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 112 - .../arch/arm/boot/dts/qcom-ipq4019.dtsi | 273 -- .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 102 - .../arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 1 - .../arch/arm/boot/dts/qcom-ipq8064.dtsi | 346 --- .../arch/arm/boot/dts/qcom-msm8660-surf.dts | 77 - .../arch/arm/boot/dts/qcom-msm8660.dtsi | 416 --- .../arch/arm/boot/dts/qcom-msm8960-cdp.dts | 353 --- .../arch/arm/boot/dts/qcom-msm8960.dtsi | 324 --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 262 -- .../dts/qcom-msm8974-sony-xperia-honami.dts | 460 ---- .../arch/arm/boot/dts/qcom-msm8974.dtsi | 757 ------ .../kernel/arch/arm/boot/dts/qcom-pm8841.dtsi | 36 - .../kernel/arch/arm/boot/dts/qcom-pm8941.dtsi | 175 -- .../arch/arm/boot/dts/qcom-pma8084.dtsi | 118 - .../arch/arm/boot/dts/r7s72100-genmai.dts | 74 - .../arch/arm/boot/dts/r7s72100-rskrza1.dts | 61 - .../kernel/arch/arm/boot/dts/r7s72100.dtsi | 444 --- .../arch/arm/boot/dts/r8a73a4-ape6evm.dts | 251 -- .../kernel/arch/arm/boot/dts/r8a73a4.dtsi | 895 ------ .../arm/boot/dts/r8a7740-armadillo800eva.dts | 318 --- .../kernel/arch/arm/boot/dts/r8a7740.dtsi | 724 ----- .../arch/arm/boot/dts/r8a7778-bockw.dts | 233 -- .../kernel/arch/arm/boot/dts/r8a7778.dtsi | 629 ----- .../arch/arm/boot/dts/r8a7779-marzen.dts | 251 -- .../kernel/arch/arm/boot/dts/r8a7779.dtsi | 598 ---- .../arch/arm/boot/dts/r8a7790-lager.dts | 762 ------ .../kernel/arch/arm/boot/dts/r8a7790.dtsi | 1910 ------------- .../arch/arm/boot/dts/r8a7791-koelsch.dts | 711 ----- .../arch/arm/boot/dts/r8a7791-porter.dts | 457 ---- .../kernel/arch/arm/boot/dts/r8a7791.dtsi | 1891 ------------- .../arch/arm/boot/dts/r8a7792-blanche.dts | 330 --- .../arch/arm/boot/dts/r8a7792-wheat.dts | 199 -- .../kernel/arch/arm/boot/dts/r8a7792.dtsi | 929 ------- .../kernel/arch/arm/boot/dts/r8a7793-gose.dts | 560 ---- .../kernel/arch/arm/boot/dts/r8a7793.dtsi | 1504 ---------- .../kernel/arch/arm/boot/dts/r8a7794-alt.dts | 364 --- .../kernel/arch/arm/boot/dts/r8a7794-silk.dts | 464 ---- .../kernel/arch/arm/boot/dts/r8a7794.dtsi | 1615 ----------- .../arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi | 41 - .../arm/boot/dts/r8a77xx-aa121td01-panel.dtsi | 41 - .../kernel/arch/arm/boot/dts/rk3036-evb.dts | 83 - .../kernel/arch/arm/boot/dts/rk3036-kylin.dts | 434 --- .../kernel/arch/arm/boot/dts/rk3036.dtsi | 771 ------ .../arch/arm/boot/dts/rk3066a-bqcurie2.dts | 238 -- .../arch/arm/boot/dts/rk3066a-marsboard.dts | 243 -- .../arch/arm/boot/dts/rk3066a-rayeager.dts | 488 ---- .../kernel/arch/arm/boot/dts/rk3066a.dtsi | 696 ----- .../arch/arm/boot/dts/rk3188-radxarock.dts | 396 --- .../kernel/arch/arm/boot/dts/rk3188.dtsi | 623 ----- .../kernel/arch/arm/boot/dts/rk3228-evb.dts | 72 - .../kernel/arch/arm/boot/dts/rk3229-evb.dts | 90 - .../kernel/arch/arm/boot/dts/rk322x.dtsi | 705 ----- .../arch/arm/boot/dts/rk3288-evb-act8846.dts | 225 -- .../arch/arm/boot/dts/rk3288-evb-rk808.dts | 239 -- .../kernel/arch/arm/boot/dts/rk3288-evb.dtsi | 396 --- .../arch/arm/boot/dts/rk3288-fennec.dts | 382 --- .../arch/arm/boot/dts/rk3288-firefly-beta.dts | 71 - .../boot/dts/rk3288-firefly-reload-core.dtsi | 310 --- .../arm/boot/dts/rk3288-firefly-reload.dts | 403 --- .../arch/arm/boot/dts/rk3288-firefly.dts | 71 - .../arch/arm/boot/dts/rk3288-firefly.dtsi | 596 ---- .../kernel/arch/arm/boot/dts/rk3288-miqi.dts | 472 ---- .../arch/arm/boot/dts/rk3288-popmetal.dts | 535 ---- .../kernel/arch/arm/boot/dts/rk3288-r89.dts | 425 --- .../arch/arm/boot/dts/rk3288-rock2-som.dtsi | 303 --- .../arch/arm/boot/dts/rk3288-rock2-square.dts | 226 -- .../boot/dts/rk3288-veyron-analog-audio.dtsi | 101 - .../arch/arm/boot/dts/rk3288-veyron-brain.dts | 139 - .../boot/dts/rk3288-veyron-chromebook.dtsi | 333 --- .../arch/arm/boot/dts/rk3288-veyron-jaq.dts | 213 -- .../arch/arm/boot/dts/rk3288-veyron-jerry.dts | 206 -- .../arm/boot/dts/rk3288-veyron-mickey.dts | 250 -- .../arm/boot/dts/rk3288-veyron-minnie.dts | 290 -- .../arch/arm/boot/dts/rk3288-veyron-pinky.dts | 135 - .../arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 127 - .../arm/boot/dts/rk3288-veyron-speedy.dts | 179 -- .../arch/arm/boot/dts/rk3288-veyron.dtsi | 577 ---- .../kernel/arch/arm/boot/dts/rk3288.dtsi | 1691 ------------ .../kernel/arch/arm/boot/dts/rk3xxx.dtsi | 442 --- .../arch/arm/boot/dts/s3c2416-pinctrl.dtsi | 175 -- .../arch/arm/boot/dts/s3c2416-smdk2416.dts | 85 - .../kernel/arch/arm/boot/dts/s3c2416.dtsi | 125 - .../kernel/arch/arm/boot/dts/s3c24xx.dtsi | 95 - .../kernel/arch/arm/boot/dts/s3c6400.dtsi | 41 - .../arch/arm/boot/dts/s3c6410-mini6410.dts | 224 -- .../arch/arm/boot/dts/s3c6410-smdk6410.dts | 103 - .../kernel/arch/arm/boot/dts/s3c6410.dtsi | 57 - .../arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 685 ----- .../kernel/arch/arm/boot/dts/s3c64xx.dtsi | 202 -- .../arch/arm/boot/dts/s5pv210-aquila.dts | 393 --- .../kernel/arch/arm/boot/dts/s5pv210-goni.dts | 450 --- .../arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 841 ------ .../arch/arm/boot/dts/s5pv210-smdkc110.dts | 78 - .../arch/arm/boot/dts/s5pv210-smdkv210.dts | 239 -- .../arch/arm/boot/dts/s5pv210-torbreck.dts | 92 - .../kernel/arch/arm/boot/dts/s5pv210.dtsi | 636 ----- .../arch/arm/boot/dts/sama5d2-pinfunc.h | 880 ------ .../kernel/arch/arm/boot/dts/sama5d2.dtsi | 1285 --------- .../kernel/arch/arm/boot/dts/sama5d3.dtsi | 1496 ---------- .../kernel/arch/arm/boot/dts/sama5d31.dtsi | 16 - .../kernel/arch/arm/boot/dts/sama5d31ek.dts | 53 - .../kernel/arch/arm/boot/dts/sama5d33.dtsi | 14 - .../kernel/arch/arm/boot/dts/sama5d33ek.dts | 46 - .../kernel/arch/arm/boot/dts/sama5d34.dtsi | 16 - .../kernel/arch/arm/boot/dts/sama5d34ek.dts | 63 - .../kernel/arch/arm/boot/dts/sama5d35.dtsi | 18 - .../kernel/arch/arm/boot/dts/sama5d35ek.dts | 57 - .../kernel/arch/arm/boot/dts/sama5d36.dtsi | 20 - .../kernel/arch/arm/boot/dts/sama5d36ek.dts | 55 - .../kernel/arch/arm/boot/dts/sama5d3_can.dtsi | 74 - .../arch/arm/boot/dts/sama5d3_emac.dtsi | 55 - .../arch/arm/boot/dts/sama5d3_gmac.dtsi | 88 - .../kernel/arch/arm/boot/dts/sama5d3_lcd.dtsi | 215 -- .../arch/arm/boot/dts/sama5d3_mci2.dtsi | 59 - .../arch/arm/boot/dts/sama5d3_tcb1.dtsi | 39 - .../arch/arm/boot/dts/sama5d3_uart.dtsi | 79 - .../kernel/arch/arm/boot/dts/sama5d3xcm.dtsi | 89 - .../kernel/arch/arm/boot/dts/sama5d3xdm.dtsi | 41 - .../kernel/arch/arm/boot/dts/sama5d3xmb.dtsi | 209 -- .../arch/arm/boot/dts/sama5d3xmb_emac.dtsi | 26 - .../arch/arm/boot/dts/sama5d3xmb_gmac.dtsi | 48 - .../kernel/arch/arm/boot/dts/sama5d4.dtsi | 1899 ------------- .../arch/arm/boot/dts/samsung_k3pe0e000b.dtsi | 67 - .../kernel/arch/arm/boot/dts/sh73a0-kzm9g.dts | 409 --- .../kernel/arch/arm/boot/dts/sh73a0.dtsi | 938 ------- .../kernel/arch/arm/boot/dts/skeleton64.dtsi | 13 - .../kernel/arch/arm/boot/dts/socfpga.dtsi | 870 ------ .../arch/arm/boot/dts/socfpga_arria10.dtsi | 786 ------ .../arm/boot/dts/socfpga_arria10_socdk.dtsi | 107 - .../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 39 - .../arch/arm/boot/dts/socfpga_arria5.dtsi | 44 - .../arm/boot/dts/socfpga_arria5_socdk.dts | 87 - .../arch/arm/boot/dts/socfpga_cyclone5.dtsi | 49 - .../boot/dts/socfpga_cyclone5_de0_sockit.dts | 112 - .../arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 34 - .../arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 94 - .../arm/boot/dts/socfpga_cyclone5_socdk.dts | 92 - .../arm/boot/dts/socfpga_cyclone5_sockit.dts | 180 -- .../boot/dts/socfpga_cyclone5_socrates.dts | 82 - .../boot/dts/socfpga_cyclone5_vining_fpga.dts | 311 --- .../kernel/arch/arm/boot/dts/socfpga_vt.dts | 90 - .../arch/arm/boot/dts/spear1310-evb.dts | 427 --- .../kernel/arch/arm/boot/dts/spear1310.dtsi | 316 --- .../arch/arm/boot/dts/spear1340-evb.dts | 525 ---- .../kernel/arch/arm/boot/dts/spear1340.dtsi | 174 -- .../kernel/arch/arm/boot/dts/spear13xx.dtsi | 343 --- .../kernel/arch/arm/boot/dts/spear300-evb.dts | 255 -- .../kernel/arch/arm/boot/dts/spear300.dtsi | 89 - .../kernel/arch/arm/boot/dts/spear310-evb.dts | 208 -- .../kernel/arch/arm/boot/dts/spear310.dtsi | 118 - .../kernel/arch/arm/boot/dts/spear320-evb.dts | 207 -- .../kernel/arch/arm/boot/dts/spear320-hmi.dts | 305 --- .../kernel/arch/arm/boot/dts/spear320.dtsi | 147 - .../kernel/arch/arm/boot/dts/spear3xx.dtsi | 157 -- .../kernel/arch/arm/boot/dts/spear600-evb.dts | 116 - .../kernel/arch/arm/boot/dts/spear600.dtsi | 210 -- .../kernel/arch/arm/boot/dts/st-pincfg.h | 71 - .../arm/boot/dts/ste-ccu8540-pinctrl.dtsi | 196 -- .../kernel/arch/arm/boot/dts/ste-ccu8540.dts | 94 - .../kernel/arch/arm/boot/dts/ste-ccu9540.dts | 79 - .../kernel/arch/arm/boot/dts/ste-dbx5x0.dtsi | 1210 -------- .../arch/arm/boot/dts/ste-href-ab8500.dtsi | 428 --- .../arch/arm/boot/dts/ste-href-ab8505.dtsi | 240 -- .../arm/boot/dts/ste-href-family-pinctrl.dtsi | 745 ----- .../arch/arm/boot/dts/ste-href-stuib.dtsi | 194 -- .../arm/boot/dts/ste-href-tvk1281618.dtsi | 278 -- .../kernel/arch/arm/boot/dts/ste-href.dtsi | 282 -- .../arm/boot/dts/ste-hrefprev60-stuib.dts | 41 - .../arch/arm/boot/dts/ste-hrefprev60-tvk.dts | 26 - .../arch/arm/boot/dts/ste-hrefprev60.dtsi | 133 - .../arm/boot/dts/ste-hrefv60plus-stuib.dts | 43 - .../arch/arm/boot/dts/ste-hrefv60plus-tvk.dts | 28 - .../arch/arm/boot/dts/ste-hrefv60plus.dtsi | 341 --- .../arch/arm/boot/dts/ste-nomadik-nhk15.dts | 254 -- .../arm/boot/dts/ste-nomadik-pinctrl.dtsi | 175 -- .../arch/arm/boot/dts/ste-nomadik-s8815.dts | 171 -- .../arm/boot/dts/ste-nomadik-stn8815.dtsi | 884 ------ .../kernel/arch/arm/boot/dts/ste-snowball.dts | 671 ----- .../kernel/arch/arm/boot/dts/ste-u300.dts | 463 ---- .../arch/arm/boot/dts/stih407-b2120.dts | 31 - .../arch/arm/boot/dts/stih407-clock.dtsi | 326 --- .../arch/arm/boot/dts/stih407-family.dtsi | 1027 ------- .../arch/arm/boot/dts/stih407-pinctrl.dtsi | 1257 --------- .../kernel/arch/arm/boot/dts/stih407.dtsi | 147 - .../arch/arm/boot/dts/stih410-b2120.dts | 64 - .../arch/arm/boot/dts/stih410-b2260.dts | 194 -- .../arch/arm/boot/dts/stih410-clock.dtsi | 347 --- .../arch/arm/boot/dts/stih410-pinctrl.dtsi | 34 - .../kernel/arch/arm/boot/dts/stih410.dtsi | 264 -- .../arch/arm/boot/dts/stih415-b2000.dts | 15 - .../arch/arm/boot/dts/stih415-b2020.dts | 15 - .../arch/arm/boot/dts/stih415-clock.dtsi | 533 ---- .../arch/arm/boot/dts/stih415-pinctrl.dtsi | 545 ---- .../kernel/arch/arm/boot/dts/stih415.dtsi | 234 -- .../arch/arm/boot/dts/stih416-b2000.dts | 15 - .../arch/arm/boot/dts/stih416-b2020.dts | 37 - .../arch/arm/boot/dts/stih416-b2020e.dts | 65 - .../arch/arm/boot/dts/stih416-clock.dtsi | 756 ----- .../arch/arm/boot/dts/stih416-pinctrl.dtsi | 692 ----- .../kernel/arch/arm/boot/dts/stih416.dtsi | 517 ---- .../arch/arm/boot/dts/stih418-b2199.dts | 113 - .../arch/arm/boot/dts/stih418-clock.dtsi | 348 --- .../kernel/arch/arm/boot/dts/stih418.dtsi | 109 - .../arch/arm/boot/dts/stih41x-b2000.dtsi | 96 - .../arch/arm/boot/dts/stih41x-b2020.dtsi | 82 - .../arch/arm/boot/dts/stih41x-b2020x.dtsi | 32 - .../kernel/arch/arm/boot/dts/stih41x.dtsi | 47 - .../arch/arm/boot/dts/stihxxx-b2120.dtsi | 183 -- .../arch/arm/boot/dts/stm32429i-eval.dts | 125 - .../arch/arm/boot/dts/stm32f429-disco.dts | 88 - .../kernel/arch/arm/boot/dts/stm32f429.dtsi | 413 --- .../arch/arm/boot/dts/stm32f469-disco.dts | 75 - .../arch/arm/boot/dts/sun4i-a10-a1000.dts | 227 -- .../arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 164 -- .../boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 186 -- .../arm/boot/dts/sun4i-a10-cubieboard.dts | 246 -- .../boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 281 -- .../arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 210 -- .../arch/arm/boot/dts/sun4i-a10-hackberry.dts | 166 -- .../arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 142 - .../arch/arm/boot/dts/sun4i-a10-inet1.dts | 274 -- .../arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 230 -- .../arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 400 --- .../dts/sun4i-a10-itead-iteaduino-plus.dts | 120 - .../arm/boot/dts/sun4i-a10-jesurun-q5.dts | 209 -- .../arch/arm/boot/dts/sun4i-a10-marsboard.dts | 214 -- .../arm/boot/dts/sun4i-a10-mini-xplus.dts | 150 - .../arch/arm/boot/dts/sun4i-a10-mk802.dts | 149 - .../arch/arm/boot/dts/sun4i-a10-mk802ii.dts | 116 - .../arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 237 -- .../arch/arm/boot/dts/sun4i-a10-pcduino.dts | 239 -- .../arch/arm/boot/dts/sun4i-a10-pcduino2.dts | 78 - .../boot/dts/sun4i-a10-pov-protab2-ips9.dts | 260 -- .../kernel/arch/arm/boot/dts/sun4i-a10.dtsi | 1379 ---------- .../arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 159 -- .../arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 187 -- .../arch/arm/boot/dts/sun5i-a10s-mk802.dts | 160 -- .../boot/dts/sun5i-a10s-olinuxino-micro.dts | 292 -- .../arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 140 - .../arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 232 -- .../kernel/arch/arm/boot/dts/sun5i-a10s.dtsi | 267 -- .../boot/dts/sun5i-a13-difrnce-dit4350.dts | 50 - .../dts/sun5i-a13-empire-electronix-d709.dts | 226 -- .../dts/sun5i-a13-empire-electronix-m712.dts | 51 - .../arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 222 -- .../arm/boot/dts/sun5i-a13-inet-98v-rev2.dts | 50 - .../boot/dts/sun5i-a13-olinuxino-micro.dts | 191 -- .../arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 237 -- .../arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 86 - .../arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 145 - .../kernel/arch/arm/boot/dts/sun5i-a13.dtsi | 375 --- .../arch/arm/boot/dts/sun5i-gr8-evb.dts | 342 --- .../kernel/arch/arm/boot/dts/sun5i-gr8.dtsi | 1087 -------- .../arch/arm/boot/dts/sun5i-r8-chip.dts | 244 -- .../kernel/arch/arm/boot/dts/sun5i-r8.dtsi | 87 - .../dts/sun5i-reference-design-tablet.dtsi | 210 -- .../linux/kernel/arch/arm/boot/dts/sun5i.dtsi | 717 ----- .../arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 93 - .../arch/arm/boot/dts/sun6i-a31-colombus.dts | 169 -- .../arm/boot/dts/sun6i-a31-hummingbird.dts | 262 -- .../kernel/arch/arm/boot/dts/sun6i-a31-i7.dts | 149 - .../kernel/arch/arm/boot/dts/sun6i-a31-m9.dts | 241 -- .../boot/dts/sun6i-a31-mele-a1000g-quad.dts | 246 -- .../kernel/arch/arm/boot/dts/sun6i-a31.dtsi | 926 ------- .../boot/dts/sun6i-a31s-colorfly-e708-q1.dts | 72 - .../arch/arm/boot/dts/sun6i-a31s-cs908.dts | 103 - .../arm/boot/dts/sun6i-a31s-inet-q972.dts | 100 - .../arch/arm/boot/dts/sun6i-a31s-primo81.dts | 254 -- .../arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 142 - .../arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 153 -- .../boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 194 -- .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 203 -- .../kernel/arch/arm/boot/dts/sun6i-a31s.dtsi | 53 - .../dts/sun6i-reference-design-tablet.dtsi | 193 -- .../boot/dts/sun7i-a20-bananapi-m1-plus.dts | 234 -- .../arch/arm/boot/dts/sun7i-a20-bananapi.dts | 293 -- .../arch/arm/boot/dts/sun7i-a20-bananapro.dts | 269 -- .../arm/boot/dts/sun7i-a20-cubieboard2.dts | 234 -- .../arm/boot/dts/sun7i-a20-cubietruck.dts | 348 --- .../arm/boot/dts/sun7i-a20-hummingbird.dts | 282 -- .../arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 247 -- .../arm/boot/dts/sun7i-a20-icnova-swac.dts | 169 -- .../arm/boot/dts/sun7i-a20-itead-ibox.dts | 149 - .../arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 341 --- .../kernel/arch/arm/boot/dts/sun7i-a20-m3.dts | 173 -- .../arch/arm/boot/dts/sun7i-a20-mk808c.dts | 187 -- .../arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 307 --- .../arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 222 -- .../dts/sun7i-a20-olinuxino-lime2-emmc.dts | 82 - .../boot/dts/sun7i-a20-olinuxino-lime2.dts | 280 -- .../boot/dts/sun7i-a20-olinuxino-micro.dts | 320 --- .../arm/boot/dts/sun7i-a20-orangepi-mini.dts | 283 -- .../arch/arm/boot/dts/sun7i-a20-orangepi.dts | 257 -- .../arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 241 -- .../arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 263 -- .../arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 271 -- .../boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 238 -- .../kernel/arch/arm/boot/dts/sun7i-a20.dtsi | 1714 ------------ .../arch/arm/boot/dts/sun8i-a23-a33.dtsi | 616 ----- .../arch/arm/boot/dts/sun8i-a23-evb.dts | 134 - .../arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts | 76 - .../arch/arm/boot/dts/sun8i-a23-inet86dz.dts | 67 - .../arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 1 - .../arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 1 - .../dts/sun8i-a23-polaroid-mid2407pxe03.dts | 118 - .../dts/sun8i-a23-polaroid-mid2809pxe04.dts | 101 - .../arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 50 - .../kernel/arch/arm/boot/dts/sun8i-a23.dtsi | 72 - .../arm/boot/dts/sun8i-a33-et-q8-v1.6.dts | 1 - .../arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 95 - .../arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 108 - .../arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts | 1 - .../arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 226 -- .../arch/arm/boot/dts/sun8i-a33-q8-tablet.dts | 50 - .../arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 219 -- .../kernel/arch/arm/boot/dts/sun8i-a33.dtsi | 257 -- .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 64 - .../boot/dts/sun8i-a83t-cubietruck-plus.dts | 65 - .../kernel/arch/arm/boot/dts/sun8i-a83t.dtsi | 228 -- .../boot/dts/sun8i-h3-bananapi-m2-plus.dts | 195 -- .../arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 125 - .../arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 214 -- .../arm/boot/dts/sun8i-h3-orangepi-lite.dts | 178 -- .../arm/boot/dts/sun8i-h3-orangepi-one.dts | 163 -- .../boot/dts/sun8i-h3-orangepi-pc-plus.dts | 88 - .../arm/boot/dts/sun8i-h3-orangepi-pc.dts | 185 -- .../arm/boot/dts/sun8i-h3-orangepi-plus.dts | 95 - .../arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 53 - .../kernel/arch/arm/boot/dts/sun8i-h3.dtsi | 586 ---- .../arch/arm/boot/dts/sun8i-q8-common.dtsi | 100 - .../arch/arm/boot/dts/sun8i-r16-parrot.dts | 351 --- .../dts/sun8i-reference-design-tablet.dtsi | 242 -- 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CPLD/v1.0/MZ700/build/greybox_tmp @@ -58,8 +52,6 @@ CPLD/v1.0/MZ700/tranZPUterSW.vhd.clk CPLD/v1.0/MZ700/tranZPUterSW.vhd.presweep CPLD/v1.0/MZ700/working CPLD/v1.0/MZ700/working2 -CPLD/v1.0/MZ80A -CPLD/v1.0/MZ80A/build CPLD/v1.0/MZ80A/build/db/ CPLD/v1.0/MZ80A/build/emuMZ_ClockII.qip CPLD/v1.0/MZ80A/build/greybox_tmp @@ -341,7 +333,6 @@ software/FusionX/src/driver/Makefile3 software/FusionX/src/driver/MZ2000/old/ software/FusionX/src/driver/MZ700/old/ software/FusionX/src/driver/mz700.rom -software/FusionX/src/driver/MZ80A/ software/FusionX/src/driver/MZ80A/old/ software/FusionX/src/driver/test software/FusionX/src/driver/.tmp_versions @@ -1668,4 +1659,22 @@ software/linux/kernel/drivers/sstar/emac/modules.order software/linux/kernel/drivers/sstar/netphy/modules.builtin software/linux/kernel/drivers/sstar/netphy/modules.order software/linux/project/release/nvr/i2m/011A/glibc/8.2.1/bin/kernel/spinand/ - +README.md.last +software/CPM +software/FusionX/history +software/FusionX/src/driver.ng/ +software/FusionX/src/driver/Makefile.old +software/FusionX/src/driver/Z80.c.old2 +software/FusionX/src/driver/Zeta.test/ +software/FusionX/src/driver/sa1510.orig +software/linux/kernel/arch/arm/boot/dts/hold/ +software/linux/kernel/arch/arm/configs/infinity2m_spinand_fusionx_defconfig.hld2 +CPLD/v1.0/MZ80A.ng/ +software/FusionX/src/driver/MZ80A/emumz.c +software/FusionX/src/driver/MZ80A/sharpmz.c +software/FusionX/src/driver/MZ700/emumz.c +software/FusionX/src/driver/MZ700/sharpmz.c +software/FusionX/src/driver/MZ2000/emumz.c +software/FusionX/src/driver/MZ2000/sharpmz.c +software/FusionX/src/driver/MZ80A/z80driver.c.bad +software/FusionX/src/driver/MZ80A/z80vhw_rfs.c.bad diff --git a/.gitmodules b/.gitmodules index 1a740080c..0fe64a128 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,3 +4,6 @@ [submodule "software/FusionX/src/driver/Zeta"] path = software/FusionX/src/driver/Zeta url = https://github.com/redcode/Zeta.git +[submodule "software/FusionX/src/driver/6502"] + path = software/FusionX/src/driver/6502 + url = https://github.com/redcode/6502.git diff --git a/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qsf b/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qsf index 39de4a6f9..5090ce405 100644 --- a/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qsf +++ b/CPLD/v1.0/MZ80A/build/tzpuFusionX_MZ80A.qsf @@ -127,10 +127,10 @@ set_location_assignment PIN_21 -to VSOM_RSV[1] # SOM Control Signals # =================== set_location_assignment PIN_28 -to VSOM_READY -set_location_assignment PIN_18 -to VSOM_LTSTATE +set_location_assignment PIN_19 -to VSOM_LTSTATE set_location_assignment PIN_27 -to VSOM_BUSRQ set_location_assignment PIN_26 -to VSOM_BUSACK -set_location_assignment PIN_19 -to VSOM_INT +set_location_assignment PIN_18 -to VSOM_INT set_location_assignment PIN_22 -to VSOM_NMI set_location_assignment PIN_25 -to VSOM_WAIT set_location_assignment PIN_23 -to VSOM_RESET diff --git a/CPLD/v1.0/MZ80A/tzpuFusionX.vhd b/CPLD/v1.0/MZ80A/tzpuFusionX.vhd index 0b9d5c013..0b0875ef5 100644 --- a/CPLD/v1.0/MZ80A/tzpuFusionX.vhd +++ b/CPLD/v1.0/MZ80A/tzpuFusionX.vhd @@ -9,9 +9,12 @@ -- for the MZ-80A. -- -- Credits: --- Copyright: (c) 2018-22 Philip Smart +-- Copyright: (c) 2018-23 Philip Smart -- --- History: Nov 2022 - Initial write for the MZ-2000, adaption to MZ-80A underway. +-- History: Nov 2022 v1.0 - Initial write for the MZ-2000, adaption to the MZ-80A. +-- Feb 2023 v1.1 - Updates, after numerous tests to try and speed up the Z80 transaction +-- from SSD202 issuing a command to data being returned. Source now +-- different to the MZ-700/MZ-2000 so will need back porting. -- --------------------------------------------------------------------------------------------------------- -- This source file is free software: you can redistribute it and-or modify @@ -272,7 +275,7 @@ begin -- On the second edge, if occurring within 1 second of the first, the PM_RESET signal to the SOM is triggered, held low for 1 second, -- forcing the SOM to reboot. SYSRESET: process( Z80_CLKi, Z80_RESETn ) - variable timer1 : integer range 0 to 354000 := 0; + variable timer1 : integer range 0 to 200000 := 0; variable timer100 : integer range 0 to 10 := 0; variable timerPMReset : integer range 0 to 10 := 0; variable resetCount : integer range 0 to 3 := 0; @@ -308,7 +311,7 @@ begin end if; -- 100ms interval. - if(timer1 = 354000) then + if(timer1 = 200000) then timer100 := timer100 + 1; if(timer100 >= 10) then @@ -353,7 +356,7 @@ begin elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 3 and SPI_BIT_CNT = 0) then SPI_RX_DATA(23 downto 16) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; - elsif(SPI_SHIFT_EN = '1' and SPI_FRAME_CNT = 4 and SPI_BIT_CNT = 0) then + elsif(SPI_FRAME_CNT = 4 and SPI_BIT_CNT = 0) then SPI_RX_DATA(31 downto 24) <= SPI_RX_SREG(6 downto 0) & VSOM_SPI_MOSI; end if; end if; @@ -363,18 +366,22 @@ begin -- SPI Slave output. Return the current data set as selected by the input signals XACT. SPI_OUTPUT : process(VSOM_SPI_CLK,VSOM_SPI_CSn,SPI_TX_DATA) begin + -- Chip Select inactive, disable process and reset control flags. if(VSOM_SPI_CSn = '1') then SPI_SHIFT_EN <= '0'; - SPI_BIT_CNT <= 15; + SPI_BIT_CNT <= 7; -- SPI_CLK_POLARITY='0' => falling edge; SPI_CLK_POLARITY='1' => risinge edge elsif(VSOM_SPI_CLK'event and VSOM_SPI_CLK = not SPI_CLK_POLARITY) then + -- Each clock reset the shift enable and done flag in preparation for the next cycle. SPI_SHIFT_EN <= '1'; + -- Bit count decrements to detect when last bit of byte is sent. if(SPI_BIT_CNT > 0) then SPI_BIT_CNT <= SPI_BIT_CNT - 1; end if; + -- Shift out the next bit. VSOM_SPI_MISO <= SPI_TX_SREG(6); SPI_TX_SREG <= SPI_TX_SREG(5 downto 0) & '0'; @@ -429,6 +436,7 @@ begin -- for 8bit, 16bit and 32bit transmissions. -- The packet is formatted as follows: -- + -- < SPI_CPU_ADDR > < SPI_CPU_DATA >< SOM_CMD> -- < SPI_FRAME_CNT=4 >< SPI_FRAME=3 > < SPI_FRAME_CNT=2 >< SPI_FRAME_CNT=1> -- < 16bit Z80 Address > < Z80 Data > -- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -581,7 +589,7 @@ begin end if; -- Whenever we return to Idle or just prior to Refresh from a Fetch cycle set all control signals to default. - if(FSM_STATE = IdleCycle or FSM_STATE = RefreshCycle) then + if((FSM_STATE = IdleCycle or FSM_STATE = RefreshCycle) and Z80_CLK_TGL = '1') then CPU_DATA_EN <= '0'; Z80_MREQni <= '1'; Z80_IORQni <= '1'; @@ -598,6 +606,7 @@ begin AUTOREFRESH_CNT <= AUTOREFRESH_CNT - 1; if(AUTOREFRESH_CNT = 0) then FSM_STATE <= RefreshCycle_3; + FSM_STATUS<= '1'; end if; end if; end if; @@ -701,6 +710,7 @@ begin when IdleCycle => CPU_LAST_T_STATE <= '1'; + FSM_STATUS <= '0'; -- FSM_STATE <= IdleCycle; ----------------------------- @@ -733,12 +743,12 @@ begin when RefreshCycle => -- Latch data from mainboard. CPU_DATA_IN <= Z80_DATA; - FSM_STATUS <= '0'; Z80_RFSHni <= '0'; when RefreshCycle_11 => -- Falling edge of T3 activates the MREQ line. Z80_MREQni <= '0'; + FSM_STATUS <= '0'; when RefreshCycle_20 => @@ -978,5 +988,9 @@ begin -- DAC clocks. --VGA_PXL_CLK <= CLK_50M; MONO_PXL_CLK <= VGA_PXL_CLK; + + -- Currently unassigned. + VGA_COLR <= '0'; + MONO_RSV <= '0'; end architecture; diff --git a/CPLD/v1.0/MZ80A/tzpuFusionX_Toplevel.vhd b/CPLD/v1.0/MZ80A/tzpuFusionX_Toplevel.vhd index 5598e2619..961c46c9c 100644 --- a/CPLD/v1.0/MZ80A/tzpuFusionX_Toplevel.vhd +++ b/CPLD/v1.0/MZ80A/tzpuFusionX_Toplevel.vhd @@ -10,9 +10,9 @@ -- project which targets the MZ-80A host. -- -- Credits: --- Copyright: (c) 2018-22 Philip Smart +-- Copyright: (c) 2018-23 Philip Smart -- --- History: Nov 2022 - Snapshot taken from the MZ-2000 version of the tzpuFusionX source. +-- History: Nov 2022 v1.0 - Snapshot taken from the MZ-2000 version of the tzpuFusionX source. -- --------------------------------------------------------------------------------------------------------- -- This source file is free software: you can redistribute it and-or modify diff --git a/CPLD/v1.0/MZ80A/tzpuFusionX_pkg.vhd b/CPLD/v1.0/MZ80A/tzpuFusionX_pkg.vhd index e0b7c7f78..775553046 100644 --- a/CPLD/v1.0/MZ80A/tzpuFusionX_pkg.vhd +++ b/CPLD/v1.0/MZ80A/tzpuFusionX_pkg.vhd @@ -9,9 +9,9 @@ -- which targets the MZ-80A host. -- -- Credits: --- Copyright: (c) 2018-22 Philip Smart +-- Copyright: (c) 2018-23 Philip Smart -- --- History: Nov 2022 - Snapshot taken from the MZ-2000 version of the tzpuFusionX source. +-- History: Nov 2022 v1.0 - Snapshot taken from the MZ-2000 version of the tzpuFusionX source. -- --------------------------------------------------------------------------------------------------------- -- This source file is free software: you can redistribute it and-or modify diff --git a/software/FusionX/src/driver/MZ80A/optparse.h b/software/FusionX/src/driver/MZ80A/optparse.h new file mode 100644 index 000000000..f96184add --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/optparse.h @@ -0,0 +1,403 @@ +/* Optparse --- portable, reentrant, embeddable, getopt-like option parser + * + * This is free and unencumbered software released into the public domain. + * + * To get the implementation, define OPTPARSE_IMPLEMENTATION. + * Optionally define OPTPARSE_API to control the API's visibility + * and/or linkage (static, __attribute__, __declspec). + * + * The POSIX getopt() option parser has three fatal flaws. These flaws + * are solved by Optparse. + * + * 1) Parser state is stored entirely in global variables, some of + * which are static and inaccessible. This means only one thread can + * use getopt(). It also means it's not possible to recursively parse + * nested sub-arguments while in the middle of argument parsing. + * Optparse fixes this by storing all state on a local struct. + * + * 2) The POSIX standard provides no way to properly reset the parser. + * This means for portable code that getopt() is only good for one + * run, over one argv with one option string. It also means subcommand + * options cannot be processed with getopt(). Most implementations + * provide a method to reset the parser, but it's not portable. + * Optparse provides an optparse_arg() function for stepping over + * subcommands and continuing parsing of options with another option + * string. The Optparse struct itself can be passed around to + * subcommand handlers for additional subcommand option parsing. A + * full reset can be achieved by with an additional optparse_init(). + * + * 3) Error messages are printed to stderr. This can be disabled with + * opterr, but the messages themselves are still inaccessible. + * Optparse solves this by writing an error message in its errmsg + * field. The downside to Optparse is that this error message will + * always be in English rather than the current locale. + * + * Optparse should be familiar with anyone accustomed to getopt(), and + * it could be a nearly drop-in replacement. The option string is the + * same and the fields have the same names as the getopt() global + * variables (optarg, optind, optopt). + * + * Optparse also supports GNU-style long options with optparse_long(). + * The interface is slightly different and simpler than getopt_long(). + * + * By default, argv is permuted as it is parsed, moving non-option + * arguments to the end. This can be disabled by setting the `permute` + * field to 0 after initialization. + */ +#ifndef OPTPARSE_H +#define OPTPARSE_H + +#ifndef OPTPARSE_API +# define OPTPARSE_API +#endif + +struct optparse { + char **argv; + int permute; + int optind; + int optopt; + char *optarg; + char errmsg[64]; + int subopt; +}; + +enum optparse_argtype { + OPTPARSE_NONE, + OPTPARSE_REQUIRED, + OPTPARSE_OPTIONAL +}; + +struct optparse_long { + const char *longname; + int shortname; + enum optparse_argtype argtype; +}; + +/** + * Initializes the parser state. + */ +OPTPARSE_API +void optparse_init(struct optparse *options, char **argv); + +/** + * Read the next option in the argv array. + * @param optstring a getopt()-formatted option string. + * @return the next option character, -1 for done, or '?' for error + * + * Just like getopt(), a character followed by no colons means no + * argument. One colon means the option has a required argument. Two + * colons means the option takes an optional argument. + */ +OPTPARSE_API +int optparse(struct optparse *options, const char *optstring); + +/** + * Handles GNU-style long options in addition to getopt() options. + * This works a lot like GNU's getopt_long(). The last option in + * longopts must be all zeros, marking the end of the array. The + * longindex argument may be NULL. + */ +OPTPARSE_API +int optparse_long(struct optparse *options, + const struct optparse_long *longopts, + int *longindex); + +/** + * Used for stepping over non-option arguments. + * @return the next non-option argument, or NULL for no more arguments + * + * Argument parsing can continue with optparse() after using this + * function. That would be used to parse the options for the + * subcommand returned by optparse_arg(). This function allows you to + * ignore the value of optind. + */ +OPTPARSE_API +char *optparse_arg(struct optparse *options); + +/* Implementation */ +#ifdef OPTPARSE_IMPLEMENTATION + +#define OPTPARSE_MSG_INVALID "invalid option" +#define OPTPARSE_MSG_MISSING "option requires an argument" +#define OPTPARSE_MSG_TOOMANY "option takes no arguments" + +static int +optparse_error(struct optparse *options, const char *msg, const char *data) +{ + unsigned p = 0; + const char *sep = " -- '"; + while (*msg) + options->errmsg[p++] = *msg++; + while (*sep) + options->errmsg[p++] = *sep++; + while (p < sizeof(options->errmsg) - 2 && *data) + options->errmsg[p++] = *data++; + options->errmsg[p++] = '\''; + options->errmsg[p++] = '\0'; + return '?'; +} + +OPTPARSE_API +void +optparse_init(struct optparse *options, char **argv) +{ + options->argv = argv; + options->permute = 1; + options->optind = 1; + options->subopt = 0; + options->optarg = 0; + options->errmsg[0] = '\0'; +} + +static int +optparse_is_dashdash(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] == '-' && arg[2] == '\0'; +} + +static int +optparse_is_shortopt(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] != '-' && arg[1] != '\0'; +} + +static int +optparse_is_longopt(const char *arg) +{ + return arg != 0 && arg[0] == '-' && arg[1] == '-' && arg[2] != '\0'; +} + +static void +optparse_permute(struct optparse *options, int index) +{ + char *nonoption = options->argv[index]; + int i; + for (i = index; i < options->optind - 1; i++) + options->argv[i] = options->argv[i + 1]; + options->argv[options->optind - 1] = nonoption; +} + +static int +optparse_argtype(const char *optstring, char c) +{ + int count = OPTPARSE_NONE; + if (c == ':') + return -1; + for (; *optstring && c != *optstring; optstring++); + if (!*optstring) + return -1; + if (optstring[1] == ':') + count += optstring[2] == ':' ? 2 : 1; + return count; +} + +OPTPARSE_API +int +optparse(struct optparse *options, const char *optstring) +{ + int type; + char *next; + char *option = options->argv[options->optind]; + options->errmsg[0] = '\0'; + options->optopt = 0; + options->optarg = 0; + if (option == 0) { + return -1; + } else if (optparse_is_dashdash(option)) { + options->optind++; /* consume "--" */ + return -1; + } else if (!optparse_is_shortopt(option)) { + if (options->permute) { + int index = options->optind++; + int r = optparse(options, optstring); + optparse_permute(options, index); + options->optind--; + return r; + } else { + return -1; + } + } + option += options->subopt + 1; + options->optopt = option[0]; + type = optparse_argtype(optstring, option[0]); + next = options->argv[options->optind + 1]; + switch (type) { + case -1: { + char str[2] = {0, 0}; + str[0] = option[0]; + options->optind++; + return optparse_error(options, OPTPARSE_MSG_INVALID, str); + } + case OPTPARSE_NONE: + if (option[1]) { + options->subopt++; + } else { + options->subopt = 0; + options->optind++; + } + return option[0]; + case OPTPARSE_REQUIRED: + options->subopt = 0; + options->optind++; + if (option[1]) { + options->optarg = option + 1; + } else if (next != 0) { + options->optarg = next; + options->optind++; + } else { + char str[2] = {0, 0}; + str[0] = option[0]; + options->optarg = 0; + return optparse_error(options, OPTPARSE_MSG_MISSING, str); + } + return option[0]; + case OPTPARSE_OPTIONAL: + options->subopt = 0; + options->optind++; + if (option[1]) + options->optarg = option + 1; + else + options->optarg = 0; + return option[0]; + } + return 0; +} + +OPTPARSE_API +char * +optparse_arg(struct optparse *options) +{ + char *option = options->argv[options->optind]; + options->subopt = 0; + if (option != 0) + options->optind++; + return option; +} + +static int +optparse_longopts_end(const struct optparse_long *longopts, int i) +{ + return !longopts[i].longname && !longopts[i].shortname; +} + +static void +optparse_from_long(const struct optparse_long *longopts, char *optstring) +{ + char *p = optstring; + int i; + for (i = 0; !optparse_longopts_end(longopts, i); i++) { + if (longopts[i].shortname && longopts[i].shortname < 127) { + int a; + *p++ = longopts[i].shortname; + for (a = 0; a < (int)longopts[i].argtype; a++) + *p++ = ':'; + } + } + *p = '\0'; +} + +/* Unlike strcmp(), handles options containing "=". */ +static int +optparse_longopts_match(const char *longname, const char *option) +{ + const char *a = option, *n = longname; + if (longname == 0) + return 0; + for (; *a && *n && *a != '='; a++, n++) + if (*a != *n) + return 0; + return *n == '\0' && (*a == '\0' || *a == '='); +} + +/* Return the part after "=", or NULL. */ +static char * +optparse_longopts_arg(char *option) +{ + for (; *option && *option != '='; option++); + if (*option == '=') + return option + 1; + else + return 0; +} + +static int +optparse_long_fallback(struct optparse *options, + const struct optparse_long *longopts, + int *longindex) +{ + int result; + char optstring[96 * 3 + 1]; /* 96 ASCII printable characters */ + optparse_from_long(longopts, optstring); + result = optparse(options, optstring); + if (longindex != 0) { + *longindex = -1; + if (result != -1) { + int i; + for (i = 0; !optparse_longopts_end(longopts, i); i++) + if (longopts[i].shortname == options->optopt) + *longindex = i; + } + } + return result; +} + +OPTPARSE_API +int +optparse_long(struct optparse *options, + const struct optparse_long *longopts, + int *longindex) +{ + int i; + char *option = options->argv[options->optind]; + if (option == 0) { + return -1; + } else if (optparse_is_dashdash(option)) { + options->optind++; /* consume "--" */ + return -1; + } else if (optparse_is_shortopt(option)) { + return optparse_long_fallback(options, longopts, longindex); + } else if (!optparse_is_longopt(option)) { + if (options->permute) { + int index = options->optind++; + int r = optparse_long(options, longopts, longindex); + optparse_permute(options, index); + options->optind--; + return r; + } else { + return -1; + } + } + + /* Parse as long option. */ + options->errmsg[0] = '\0'; + options->optopt = 0; + options->optarg = 0; + option += 2; /* skip "--" */ + options->optind++; + for (i = 0; !optparse_longopts_end(longopts, i); i++) { + const char *name = longopts[i].longname; + if (optparse_longopts_match(name, option)) { + char *arg; + if (longindex) + *longindex = i; + options->optopt = longopts[i].shortname; + arg = optparse_longopts_arg(option); + if (longopts[i].argtype == OPTPARSE_NONE && arg != 0) { + return optparse_error(options, OPTPARSE_MSG_TOOMANY, name); + } if (arg != 0) { + options->optarg = arg; + } else if (longopts[i].argtype == OPTPARSE_REQUIRED) { + options->optarg = options->argv[options->optind]; + if (options->optarg == 0) + return optparse_error(options, OPTPARSE_MSG_MISSING, name); + else + options->optind++; + } + return options->optopt; + } + } + return optparse_error(options, OPTPARSE_MSG_INVALID, option); +} + +#endif /* OPTPARSE_IMPLEMENTATION */ +#endif /* OPTPARSE_H */ diff --git a/software/FusionX/src/driver/MZ80A/z80ctrl.c b/software/FusionX/src/driver/MZ80A/z80ctrl.c new file mode 100644 index 000000000..d360ab859 --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80ctrl.c @@ -0,0 +1,973 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80ctrl.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Control Interface +// This file contains a command line utility tool for controlling the z80drv device +// driver. The tool allows manipulation of the emulated Z80, inspection of its +// memory and data, transmission of adhoc commands to the underlying CPLD-Z80 +// gateway and loading/saving of programs and data to/from the Z80 virtual and +// host memory. +// +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of the Z80 device driver. +// Copyright: (c) 2019-2023 Philip Smart +// (c) 1999-2023 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 v1.0 - v1.Initial write of the z80 kernel driver software. +// Feb 2023 v1.1 - Extended to allow Rom upload for RFS and other drivers. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80driver.h" + +#define VERSION "1.1" +#define AUTHOR "P.D.Smart" +#define COPYRIGHT "(c) 2018-23" + +// Getopt_long is buggy so we use optparse. +#define OPTPARSE_IMPLEMENTATION +#define OPTPARSE_API static +#include "optparse.h" + +// Device driver name. +#define DEVICE_FILENAME "/dev/z80drv" + +// Constants for the Sharp MZ80A MZF file format. +#define MZF_HEADER_SIZE 128 // Size of the MZF header. +#define MZF_ATTRIBUTE 0x00 // Code Type, 01 = Machine Code. +#define MZF_FILENAME 0x01 // Title/Name (17 bytes). +#define MZF_FILENAME_LEN 17 // Length of the filename, it is not NULL terminated, generally a CR can be taken as terminator but not guaranteed. +#define MZF_FILESIZE 0x12 // Size of program. +#define MZF_LOADADDR 0x14 // Load address of program. +#define MZF_EXECADDR 0x16 // Exec address of program. +#define MZF_COMMENT 0x18 // Comment, used for details of the file or startup code. +#define MZF_COMMENT_LEN 104 // Length of the comment field. +#define CMT_TYPE_OBJCD 0x001 // MZF contains a binary object. +#define CMT_TYPE_BTX1CD 0x002 // MZF contains a BASIC program. +#define CMT_TYPE_BTX2CD 0x005 // MZF contains a BASIC program. +#define CMT_TYPE_TZOBJCD0 0x0F8 // MZF contains a TZFS binary object for page 0. +#define CMT_TYPE_TZOBJCD1 0x0F9 +#define CMT_TYPE_TZOBJCD2 0x0FA +#define CMT_TYPE_TZOBJCD3 0x0FB +#define CMT_TYPE_TZOBJCD4 0x0FC +#define CMT_TYPE_TZOBJCD5 0x0FD +#define CMT_TYPE_TZOBJCD6 0x0FE +#define CMT_TYPE_TZOBJCD7 0x0FF // MZF contains a TZFS binary object for page 7. +#define MZ_CMT_ADDR 0x10F0 + +// Structure to define a Sharp MZ80A MZF directory structure. This header appears at the beginning of every Sharp MZ80A tape (and more recently archived/emulator) images. +// +typedef struct __attribute__((__packed__)) { + uint8_t attr; // MZF attribute describing the file. + uint8_t fileName[MZF_FILENAME_LEN]; // Each directory entry is the size of an MZF filename. + uint16_t fileSize; // Size of file. + uint16_t loadAddr; // Load address for the file. + uint16_t execAddr; // Execution address where the Z80 starts processing. + uint8_t comment[MZF_COMMENT_LEN]; // Text comment field but often contains a startup machine code program. +} t_svcDirEnt; + +// Possible commands to be issued to the Z80 driver. +enum CTRL_COMMANDS { + Z80_CMD_STOP = 0, + Z80_CMD_START = 1, + Z80_CMD_PAUSE = 2, + Z80_CMD_CONTINUE = 3, + Z80_CMD_RESET = 4, + Z80_CMD_SPEED = 5, + Z80_CMD_HOST_RAM = 6, + Z80_CMD_VIRTUAL_RAM = 7, + Z80_CMD_DUMP_MEMORY = 8, + Z80_CMD_MEMORY_TEST = 9, + Z80_CMD_ADD_DEVICE = 10, + Z80_CMD_DEL_DEVICE = 11, + CPLD_CMD_SEND_CMD = 12, + CPLD_CMD_SPI_TEST = 13, + CPLD_CMD_PRL_TEST = 14 +}; + + +// Shared memory between this process and the Z80 driver. +static t_Z80Ctrl *Z80Ctrl = NULL; +static uint8_t *Z80RAM = NULL; +static uint8_t *Z80ROM = NULL; + +// Method to obtain and return the output screen width. +// +uint8_t getScreenWidth(void) +{ + return(MAX_SCREEN_WIDTH); +} + +struct termios orig_termios; + +void reset_terminal_mode() +{ + tcsetattr(0, TCSANOW, &orig_termios); +} + +void set_conio_terminal_mode() +{ + struct termios new_termios; + + /* take two copies - one for now, one for later */ + tcgetattr(0, &orig_termios); + memcpy(&new_termios, &orig_termios, sizeof(new_termios)); + + /* register cleanup handler, and set the new terminal mode */ + atexit(reset_terminal_mode); + cfmakeraw(&new_termios); + tcsetattr(0, TCSANOW, &new_termios); +} + +int kbhit() +{ + struct timeval tv = { 0L, 0L }; + fd_set fds; + FD_ZERO(&fds); + FD_SET(0, &fds); + return select(1, &fds, NULL, NULL, &tv) > 0; +} + +int getch(uint8_t wait) +{ + int r; + unsigned char c; + + if(wait != 0 || (wait == 0 && kbhit())) + { + if ((r = read(0, &c, sizeof(c))) < 0) { + return r; + } else { + return c; + } + } + return 0; +} + +void delay(int number_of_seconds) +{ + // Converting time into milli_seconds + int milli_seconds = 1000 * number_of_seconds; + + // Storing start time + clock_t start_time = clock(); + + // looping till required time is not achieved + while (clock() < start_time + milli_seconds); +} + +// Function to dump out a given section of memory via the UART. +// +int memoryDump(uint32_t memaddr, uint32_t memsize, uint8_t memoryType, uint32_t memwidth, uint32_t dispaddr, uint8_t dispwidth) +{ + uint8_t displayWidth = dispwidth;; + uint32_t pnt = memaddr; + uint32_t endAddr = memaddr + memsize; + uint32_t addr = dispaddr; + uint32_t i = 0; + //uint32_t data; + int8_t keyIn; + int result = -1; + char c = 0; + + // Sanity check. memoryType == 0 required kernel driver to dump so we exit as it cannot be performed here. + if(memoryType == 0) + return(-1); + + // Reconfigure terminal to allow non-blocking key input. + // + set_conio_terminal_mode(); + + // If not set, calculate output line width according to connected display width. + // + if(displayWidth == 0) + { + switch(getScreenWidth()) + { + case 40: + displayWidth = 8; + break; + case 80: + displayWidth = 16; + break; + default: + displayWidth = 32; + break; + } + } + + while (1) + { + printf("%08lX", addr); // print address + printf(": "); + + // print hexadecimal data + for (i=0; i < displayWidth; ) + { + switch(memwidth) + { + case 16: + if(pnt+i < endAddr) + printf("%04X", memoryType == 1 ? (uint16_t)Z80RAM[pnt+i] : memoryType == 2 ? (uint16_t)Z80ROM[pnt+i] : memoryType == 3 ? (uint16_t)Z80Ctrl->page[pnt+i] : (uint16_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + + case 32: + if(pnt+i < endAddr) + printf("%08lX", memoryType == 1 ? (uint32_t)Z80RAM[pnt+i] : memoryType == 2 ? (uint32_t)Z80ROM[pnt+i] : memoryType == 3 ? (uint32_t)Z80Ctrl->page[pnt+i] : (uint32_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + + case 8: + default: + if(pnt+i < endAddr) + printf("%02X", memoryType == 1 ? (uint8_t)Z80RAM[pnt+i] : memoryType == 2 ? (uint8_t)Z80ROM[pnt+i] : memoryType == 3 ? (uint8_t)Z80Ctrl->page[pnt+i] : (uint8_t)Z80Ctrl->iopage[pnt+i]); + else + printf(" "); + i++; + break; + } + fputc((char)' ', stdout); + } + + // print ascii data + printf(" |"); + + // print single ascii char + for (i=0; i < displayWidth; i++) + { + c = memoryType == 1 ? (char)Z80RAM[pnt+i] : memoryType == 2 ? (char)Z80ROM[pnt+i] : memoryType == 3 ? (char)Z80Ctrl->page[pnt+i] : (char)Z80Ctrl->iopage[pnt+i]; + if ((pnt+i < endAddr) && (c >= ' ') && (c <= '~')) + fputc((char)c, stdout); + else + fputc((char)' ', stdout); + } + + printf("|\r\n"); + fflush(stdout); + + // Move on one row. + pnt += displayWidth; + addr += displayWidth; + + // User abort (ESC), pause (Space) or all done? + // + keyIn = getch(0); + if(keyIn == ' ') + { + do { + keyIn = getch(0); + } while(keyIn != ' ' && keyIn != 0x1b); + } + // Escape key pressed, exit with 0 to indicate this to caller. + if (keyIn == 0x1b) + { + sleep(1); + result = 0; + goto memoryDumpExit; + } + + // End of buffer, exit the loop. + if(pnt >= (memaddr + memsize)) + { + break; + } + } + + // Normal exit, return -1 to show no key pressed. +memoryDumpExit: + reset_terminal_mode(); + return(result); +} + +// Method to load a program or data file into the Z80 memory. First load into Virtual memory and then trigger a sync to bring Host RAM in line. +// +int z80load(int fdZ80, char *fileName, uint32_t romLoadAddr, uint8_t useROM) +{ + // Locals. + struct ioctlCmd ioctlCmd; + int result = 0; + long fileSize; + t_svcDirEnt mzfHeader; + + // Open the file and read directly into the Virtual memory via the share. + FILE *ptr; + ptr = fopen(fileName, "rb"); + if(ptr) + { + // Get size of file for sanity checks. + fseek(ptr, 0, SEEK_END); + fileSize = ftell(ptr); + fseek(ptr, 0, SEEK_SET); + + // Sanity checks. + if(useROM) + { + if((romLoadAddr+fileSize) > Z80_VIRTUAL_ROM_SIZE) + { + printf("Error: Binary ROM file out of ROM bounds (Size=%ld, Load=%08x)\n", fileSize, romLoadAddr); + result = 1; + } + } else + { + // First the header. + fread((uint8_t *)&mzfHeader, MZF_HEADER_SIZE, 1, ptr); + if((mzfHeader.loadAddr + mzfHeader.fileSize) > Z80_VIRTUAL_RAM_SIZE) + { + printf("Error: MZF file out of RAM bounds (Size=%ld, Load=%08x)\n", fileSize, romLoadAddr); + result = 1; + } + } + } + else + { + printf("Couldnt open file:%s\n", fileName); + result = 1; + } + + // No file errors, read contents into Z80 memory. + if(result == 0) + { + // Pause the Z80. + // + ioctlCmd.cmd = IOCTL_CMD_Z80_PAUSE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + if(useROM) + { + // Now read in the data. + fread(&Z80ROM[romLoadAddr], fileSize, 1, ptr); + printf("Loaded %s, Size:%08x, Addr:%08x\n", fileName, fileSize, romLoadAddr); + } + else + { + #if(TARGET_HOST_MZ700 == 1 || TARGET_HOST_MZ80A) + if(mzfHeader.loadAddr > 0x1000) + { + #endif + // Copy in the header. + memcpy((uint8_t *)&Z80RAM[MZ_CMT_ADDR], (uint8_t *)&mzfHeader, MZF_HEADER_SIZE); + + // Now read in the data. + fread(&Z80RAM[mzfHeader.loadAddr], mzfHeader.fileSize, 1, ptr); + printf("Loaded %s, Size:%04x, Addr:%04x, Exec:%04x\n", fileName, mzfHeader.fileSize, mzfHeader.loadAddr, mzfHeader.execAddr); + #if(TARGET_HOST_MZ700 == 1 || TARGET_HOST_MZ80A) + } + #endif + + // Sync the loaded image from Virtual memory to hard memory. + ioctlCmd.cmd = IOCTL_CMD_SYNC_TO_HOST_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + + #if(TARGET_HOST_MZ2000 == 1) + // Set PC to 2 (NST) which switches to RUN mode and executes at 0000H + ioctlCmd.z80.pc = 2; + #endif + #if(TARGET_HOST_MZ700 == 1 || TARGET_HOST_MZ80A) + // MZ-700 or MZ-80A just use the MZF header exec address. + ioctlCmd.z80.pc = mzfHeader.execAddr; + #endif + + // Set PC to required setting ready for run. + ioctlCmd.cmd = IOCTL_CMD_SETPC; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + // Resume Z80 processing. + // + ioctlCmd.cmd = IOCTL_CMD_Z80_CONTINUE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + } + + return(result); +} + +// Method to save FusionX memory to a local file. +// +int z80save(int fdZ80, char *fileName, long addr, long size, long memoryType) +{ + // Locals. + struct ioctlCmd ioctlCmd; + int result = 0; + t_svcDirEnt mzfHeader; + + // Pause the Z80. + // + //ioctlCmd.cmd = IOCTL_CMD_Z80_PAUSE; + //ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + // Open the file and write directly into the file from the shared memory segment. + FILE *ptr; + ptr = fopen(fileName, "wb"); + if(ptr) + { + switch(memoryType) + { + case 0: + break; + + case 2: + fwrite(&Z80ROM[addr], size, 1, ptr); + + case 3: + fwrite(&Z80Ctrl->page[addr], size, 1, ptr); + break; + + case 4: + fwrite(&Z80Ctrl->iopage[addr], size, 1, ptr); + break; + + case 1: + default: + fwrite(&Z80RAM[addr], size, 1, ptr); + break; + } + } + fclose(ptr); + + return(result); +} + +// Method to request basic Z80 operations. +// +int ctrlCmd(int fdZ80, enum CTRL_COMMANDS cmd, long param1, long param2, long param3) +{ + // Locals. + struct ioctlCmd ioctlCmd; + uint32_t idx; + int result = 0; + + switch(cmd) + { + case Z80_CMD_STOP: + // Use IOCTL to request Z80 to Stop (power off) processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_START: + // Use IOCTL to request Z80 to Start (power on) processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_START; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_PAUSE: + // Use IOCTL to request Z80 to pause processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_PAUSE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_CONTINUE: + // Use IOCTL to request Z80 continue processing. + ioctlCmd.cmd = IOCTL_CMD_Z80_CONTINUE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_RESET: + // Use IOCTL to request Z80 reset. + ioctlCmd.cmd = IOCTL_CMD_Z80_RESET; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_SPEED: + // Check value is in range. + for(idx=1; idx < 256; idx+=idx) + { + if((uint32_t)param1 == idx) break; + } + if(idx == 256) + { + printf("Speed factor is illegal. It must be a multiple value of the original CPU clock, ie. 1x, 2x, 4x etc\n"); + result = -1; + } else + { + // Use IOCTL to request Z80 cpu freq change. + ioctlCmd.speed.speedMultiplier = (uint32_t)param1; + ioctlCmd.cmd = IOCTL_CMD_Z80_CPU_FREQ; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + break; + case Z80_CMD_ADD_DEVICE: + ioctlCmd.vdev.device = VIRTUAL_DEVICE_NONE; + if(strcasecmp((char *)param1, "RFS") == 0) + { + ioctlCmd.vdev.device = VIRTUAL_DEVICE_RFS; + } + else if(strcasecmp((char *)param1, "TZPU") == 0) + { + ioctlCmd.vdev.device = VIRTUAL_DEVICE_TZPU; + } + if(ioctlCmd.vdev.device != VIRTUAL_DEVICE_NONE) + { + ioctlCmd.cmd = IOCTL_CMD_ADD_DEVICE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + break; + case Z80_CMD_DEL_DEVICE: + ioctlCmd.vdev.device = VIRTUAL_DEVICE_NONE; + if(strcasecmp((char *)param1, "RFS") == 0) + { + ioctlCmd.vdev.device = VIRTUAL_DEVICE_RFS; + } + else if(strcasecmp((char *)param1, "TZPU") == 0) + { + ioctlCmd.vdev.device = VIRTUAL_DEVICE_TZPU; + } + if(ioctlCmd.vdev.device != VIRTUAL_DEVICE_NONE) + { + ioctlCmd.cmd = IOCTL_CMD_DEL_DEVICE; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + break; + case CPLD_CMD_SEND_CMD: + // Build up the IOCTL command to request the given data is sent to the CPLD. + ioctlCmd.cmd = IOCTL_CMD_CPLD_CMD; + ioctlCmd.cpld.cmd = (uint32_t)param1; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_DUMP_MEMORY: + // If virtual memory, we can dump it via the shared memory segment. + if((uint8_t)param1) + { + memoryDump((uint32_t)param2, (uint32_t)param3, (uint8_t)param1, (uint8_t)param1 == 3 || (uint8_t)param1 == 4 ? 32 : 8, (uint32_t)param2, 0); + } else + { + // Build an IOCTL command to get the driver to dump the memory. + ioctlCmd.cmd = IOCTL_CMD_DUMP_MEMORY; + ioctlCmd.addr.start = (uint32_t)param2; + ioctlCmd.addr.end = (uint32_t)param2+(uint32_t)param3; + ioctlCmd.addr.size = (uint32_t)param3; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + } + break; + case Z80_CMD_HOST_RAM: + // Use IOCTL to request change to host RAM. + ioctlCmd.cmd = IOCTL_CMD_USE_HOST_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_VIRTUAL_RAM: + // Use IOCTL to request change to host RAM. + ioctlCmd.cmd = IOCTL_CMD_USE_VIRTUAL_RAM; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case Z80_CMD_MEMORY_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_Z80_MEMTEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case CPLD_CMD_PRL_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_PRL_TEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + case CPLD_CMD_SPI_TEST: + // Send command to test the SPI. + ioctlCmd.cmd = IOCTL_CMD_SPI_TEST; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + break; + + default: + printf("Command not supported!\n"); + result = -1; + break; + } + + return(result); +} + +// Method to perform some simple tests on the Z80 emulator. +// +int z80test(int fdZ80) +{ + // Locals. + struct ioctlCmd ioctlCmd; + int result = 0; + + // Stop the Z80. + // +printf("Send STOP\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + FILE *ptr; + ptr = fopen("/customer/mz700.rom", "rb"); + if(ptr) + { + fread(&Z80RAM, 65536, 1, ptr); + } else printf("Couldnt open file\n"); + + // Configure the Z80. + // +printf("Send SETPC\n"); + ioctlCmd.z80.pc = 0; + ioctl(fdZ80, IOCTL_CMD_SETPC, &ioctlCmd); + + memoryDump(0 , 65536, 1, 8, 0, 0); + + // Start the Z80. + // +printf("Send START\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_START; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + delay(10); + +printf("Send STOP\n"); + ioctlCmd.cmd = IOCTL_CMD_Z80_STOP; + ioctl(fdZ80, IOCTL_CMD_SEND, &ioctlCmd); + + memoryDump(0, 65536, 1, 8, 0, 0); +out: + return(result); +} + +// Output usage screen. So mamy commands you do need to be prompted!! +void showArgs(char *progName, struct optparse *options) +{ + printf("%s %s %s %s\n\n", progName, VERSION, COPYRIGHT, AUTHOR); + printf("Synopsis:\n"); + printf("%s --help # This help screen.\n", progName); + printf(" --cmd = RESET # Reset the Z80\n"); + printf(" = STOP # Stop and power off the Z80\n"); + printf(" = START # Power on and start the Z80\n"); + printf(" = PAUSE # Pause running Z80\n"); + printf(" = CONTINUE # Continue Z80 execution\n"); + printf(" = HOSTRAM # Use HOST DRAM\n"); + printf(" = VIRTRAM # Use Virtual RAM\n"); + printf(" = ADDDEV --device # Add a virtual device into the Z80 configuration.\n"); + printf(" = DELDEV --device # Remove a virtual device from the Z80 configuration.\n"); + printf(" = SPEED --mult <1, 2, 4, 8, 16, 32, 64, 128> # In Virtual RAM mode, set CPU speed to base clock x factor.\n"); + printf(" = LOADMZF --file # Load MZF file into RAM.\n"); + printf(" = LOADROM --file --addr <24 bit addr> # Load contents of binary file into ROM at address. default = 0x000000.\n"); + printf(" = SAVE --file --addr <24bit addr> --end <24bit addr> [--size <24bit>] --type <0 - Host RAM, 1 = Virtual RAM, 2 = Virtual ROM, 3 = PageTable, 4 = IOPageTable>\n"); + printf(" = DUMP --addr <24bit addr> --end <24bit addr> [--size <24bit>] --type <0 - Host RAM, 1 = Virtual RAM, 2 = Virtual ROM, 3 = PageTable, 4 = IOPageTable>\n"); + printf(" = CPLDCMD --data <32bit command> # Send adhoc 32bit command to CPLD.\n"); + printf(" = Z80TEST # Perform various debugging tests\n"); + printf(" = SPITEST # Perform SPI testing\n"); + printf(" = PRLTEST # Perform Parallel Bus testing\n"); + printf(" = Z80MEMTEST # Perform HOST memory tests.\n"); + printf(" -- # Some commands can be abbreviated, ie. --start.\n"); + +} + +int main(int argc, char *argv[]) +{ + int fdZ80; + char buff[64]; + char cmd[64] = { 0 }; + char fileName[256] = { 0 }; + char devName[32] = { 0 }; + int opt; + uint32_t hexData = 0; + long speedMultiplier = 1; + long startAddr = 0x0000; + long endAddr = 0x1000; + int memoryType = 0; + int helpFlag = 0; + int verboseFlag = 0; + + // Define parameters to be processed. + struct optparse options; + static struct optparse_long long_options[] = + { + {"help", 'h', OPTPARSE_NONE}, + {"cmd", 'c', OPTPARSE_REQUIRED}, + {"file", 'f', OPTPARSE_REQUIRED}, + {"data", 'd', OPTPARSE_REQUIRED}, + {"mult", 'S', OPTPARSE_REQUIRED}, + {"type", 'T', OPTPARSE_REQUIRED}, + {"addr", 'a', OPTPARSE_REQUIRED}, + {"end", 'e', OPTPARSE_REQUIRED}, + {"size", 's', OPTPARSE_REQUIRED}, + {"device", 'D', OPTPARSE_REQUIRED}, + {"verbose", 'v', OPTPARSE_NONE}, + {"save", '0', OPTPARSE_NONE}, + {"dump", '1', OPTPARSE_NONE}, + {"loadmzf", '2', OPTPARSE_NONE}, + {"loadrom", '3', OPTPARSE_NONE}, + {"reset", '4', OPTPARSE_NONE}, + {"stop", '5', OPTPARSE_NONE}, + {"start", '6', OPTPARSE_NONE}, + {"pause", '7', OPTPARSE_NONE}, + {"continue", '8', OPTPARSE_NONE}, + {"speed", '9', OPTPARSE_NONE}, + {"cpldcmd", '+', OPTPARSE_NONE}, + {"adddev", '-', OPTPARSE_NONE}, + {"deldev", ':', OPTPARSE_NONE}, + {0} + }; + + // Parse the command line options. + // + optparse_init(&options, argv); + while((opt = optparse_long(&options, long_options, NULL)) != -1) + { + switch(opt) + { + // Hex data. + case 'd': + // hexData = (uint32_t)strtol(options.optarg, NULL, 0); + sscanf(options.optarg, "0x%08x", &hexData); + printf("Hex data:%08x\n", hexData); + break; + + // Start address for memory operations. + case 'a': + startAddr = strtol(options.optarg, NULL, 0); + //printf("Start Addr:%04x\n", startAddr); + break; + + // Speed multiplication factor for CPU governor when running in virtual memory. + case 'S': + speedMultiplier = strtol(options.optarg, NULL, 0); + //printf("Speed = base freq x %d\n", speedFactor); + break; + + // End address for memory operations. + case 'e': + endAddr = strtol(options.optarg, NULL, 0); + //printf("End Addr:%04x\n", endAddr); + break; + + // Size instead of end address for memory operations. + case 's': + endAddr = startAddr + strtol(options.optarg, NULL, 0); + //printf("End Addr:%04x\n", endAddr); + break; + + // Memory type flag, 0 = host, 1 = virtual RAM, 2 = virtual ROM, 3 = page table, 4 = iopage table. + case 'T': + memoryType = atoi(options.optarg); + break; + + // Filename. + case 'f': + strcpy(fileName, options.optarg); + break; + + // Device name. + case 'D': + strcpy(devName, options.optarg); + break; + + // Command to execute. + case 'c': + strcpy(cmd, options.optarg); + break; + + // Quick command flags. + case '0': + strcpy(cmd, "SAVE"); + break; + case '1': + strcpy(cmd, "DUMP"); + break; + case '2': + strcpy(cmd, "LOADMZF"); + break; + case '3': + strcpy(cmd, "LOADROM"); + break; + case '4': + strcpy(cmd, "RESET"); + break; + case '5': + strcpy(cmd, "STOP"); + break; + case '6': + strcpy(cmd, "START"); + break; + case '7': + strcpy(cmd, "PAUSE"); + break; + case '8': + strcpy(cmd, "CONTINUE"); + break; + case '9': + strcpy(cmd, "SPEED"); + break; + case '+': + strcpy(cmd, "CPLDCMD"); + break; + case '-': + strcpy(cmd, "ADDDEV"); + break; + case ':': + strcpy(cmd, "DELDEV"); + + // Verbose mode. + case 'v': + verboseFlag = 1; + break; + + // Command help needed. + case 'h': + helpFlag = 1; + break; + + // Unrecognised, show synopsis. + case '?': + showArgs(argv[0], &options); + printf("%s: %s\n", argv[0], options.errmsg); + return(1); + } + } + + // Open the z80drv driver and attach to its shared memory, basically the Z80 control structure which includes the virtual Z80 memory. + fdZ80 = open(DEVICE_FILENAME, O_RDWR|O_NDELAY); + if(fdZ80 >= 0) + { + Z80Ctrl = (t_Z80Ctrl *)mmap(0, sizeof(t_Z80Ctrl), PROT_READ | PROT_WRITE, MAP_SHARED, fdZ80, 0); + + if(Z80Ctrl == (void *)-1) + { + printf("Failed to attach to the Z80 Control structure, cannot continue, exiting....\n"); + close(fdZ80); + exit(1); + } + Z80RAM = (uint8_t *)mmap(0, Z80_VIRTUAL_RAM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fdZ80, 0); + if(Z80RAM == (void *)-1) + { + printf("Failed to attach to the Z80 RAM, cannot continue, exiting....\n"); + close(fdZ80); + exit(1); + } + Z80ROM = (uint8_t *)mmap(0, Z80_VIRTUAL_ROM_SIZE+0x1000, PROT_READ | PROT_WRITE, MAP_SHARED, fdZ80, 0); + if(Z80ROM == (void *)-1) + { + printf("Failed to attach to the Z80 ROM, cannot continue, exitting....\n"); + close(fdZ80); + exit(1); + } + } else + { + printf("Failed to open the Z80 Driver, exiting...\n"); + exit(1); + } + + // Basic string to method mapping. Started off with just 1 or two but has grown, may need a table! + if(strcasecmp(cmd, "LOADMZF") == 0) + { + z80load(fdZ80, fileName, 0, 0); + } else + if(strcasecmp(cmd, "LOADROM") == 0) + { + z80load(fdZ80, fileName, startAddr, 1); + } else + if(strcasecmp(cmd, "RESET") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_RESET, 0, 0, 0); + } else + if(strcasecmp(cmd, "STOP") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_STOP, 0, 0, 0); + } else + if(strcasecmp(cmd, "START") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_START, 0, 0, 0); + } else + if(strcasecmp(cmd, "PAUSE") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_PAUSE, 0, 0, 0); + } else + if(strcasecmp(cmd, "CONTINUE") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_CONTINUE, 0, 0, 0); + } else + if(strcasecmp(cmd, "SPEED") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_SPEED, speedMultiplier, 0, 0); + } else + if(strcasecmp(cmd, "DUMP") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_DUMP_MEMORY, memoryType, startAddr, (endAddr - startAddr)); + } else + if(strcasecmp(cmd, "SAVE") == 0) + { + z80save(fdZ80, fileName, startAddr, (endAddr - startAddr), memoryType); + } else + if(strcasecmp(cmd, "HOSTRAM") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_HOST_RAM, 0, 0, 0); + } else + if(strcasecmp(cmd, "VIRTRAM") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_VIRTUAL_RAM, 0, 0, 0); + } else + if(strcasecmp(cmd, "ADDDEV") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_ADD_DEVICE, (long)&devName, 0, 0); + } else + if(strcasecmp(cmd, "DELDEV") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_DEL_DEVICE, (long)&devName, 0, 0); + } else + if(strcasecmp(cmd, "CPLDCMD") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_SEND_CMD, hexData, 0, 0); + } else + + // Test methods, if the code is built-in to the driver. + if(strcasecmp(cmd, "Z80TEST") == 0) + { + z80test(fdZ80); + } else + if(strcasecmp(cmd, "SPITEST") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_SPI_TEST, 0, 0, 0); + } else + if(strcasecmp(cmd, "PRLTEST") == 0) + { + ctrlCmd(fdZ80, CPLD_CMD_PRL_TEST, 0, 0, 0); + } else + if(strcasecmp(cmd, "Z80MEMTEST") == 0) + { + ctrlCmd(fdZ80, Z80_CMD_MEMORY_TEST, 0, 0, 0); + } + else + { + showArgs(argv[0], &options); + if(helpFlag == 0) + printf("No command given, nothing done!\n"); + } + + // Unmap shared memory and close the device. + munmap(Z80Ctrl, sizeof(t_Z80Ctrl)); + close(fdZ80); + + return(0); +} diff --git a/software/FusionX/src/driver/MZ80A/z80driver.c b/software/FusionX/src/driver/MZ80A/z80driver.c new file mode 100644 index 000000000..0b20daff1 --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80driver.c @@ -0,0 +1,1922 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80driver.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Driver +// This file contains the methods used to create a linux device driver which provides +// the services of a Z80 CPU emulation and the control of an underlying Z80'less host +// system. In essence this driver is the host Z80 CPU. +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of this driver and in all ways, is compatible with +// the original Z80. +// Copyright: (c) 2019-2023 Philip Smart +// (c) 1999-2023 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 - v1.0 Initial write of the z80 kernel driver software. +// Jan 2023 - v1.1 Added MZ-2000/MZ-80A modes. There are serious limitations with the +// SSD202 I/O. The I/O Bus appears to run at 72MHz and the GPIO bits +// are split across 2x16 registers per bit. This limits 8bit read +// speed to < 2MB/s, write speed slower due to select signal. Thus it +// is not feasible to run a program in the host memory at full speed. +// Virtual (Kernel) memory is used for all programs and host is only +// accessed for specific reasons, such as the MZ-80A FDD Bios which +// changes according to state of READY signal. I/O operations have to +// use lookahead during fetch cycle to steal time in order to meet timings. +// If SigmaStar make a newer SSD or an alternative becomes available which +// has I/O bus running at 4x speed or has 32bit per cycle GPIO access then +// the design needs to be upgraded to fulfill the idea of running programs +// in host memory at full speed. +// Feb 2023 - v1.2 Added MZ-80A Rom Filing System device driver. This allows the FusionX +// hosted in an MZ-80A to run the original RFS Monitor and software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" +#include "z80menu.h" +#include "z80driver.h" + +#include +#include +#include + +/* Meta Information */ +MODULE_LICENSE(DRIVER_LICENSE); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESCRIPTION); +MODULE_VERSION(DRIVER_VERSION); +MODULE_INFO(versiondate, DRIVER_VERSION_DATE); +MODULE_INFO(copyright, DRIVER_COPYRIGHT); + +/* Global variables for the threads */ +static struct task_struct *kthread_z80; +static int threadId_z80 = 1; + +// Device class and major numbers. +static struct class *class; +static struct device *device; +static int major; + +// CPU Instance. +static Z80 Z80CPU; + +// Z80 Control data. +static t_Z80Ctrl *Z80Ctrl = NULL; + +// Runtime control of the CPU. As the CPU runs in a detached thread on core 1, the cpu needs to be suspended before any external +// operations can take place. This is achieved with the runtime mutex. +enum Z80_RUN_STATES Z80RunMode; +static struct mutex Z80RunModeMutex; +static DEFINE_MUTEX(Z80DRV_MUTEX); + +// Include the virtual hardware drivers. +#if(TARGET_HOST_MZ80A == 1) + #include "z80vhw_rfs.c" +#endif +#include "z80vhw_tzpu.c" + +//------------------------------------------------------------------------------------------------------------------------------- +// +// Host Memory and I/O Mapping and Execution Logic. +// +// Methods are all static and inline to maximise performance. +// +//------------------------------------------------------------------------------------------------------------------------------- + +// Method to decode an address and make any system memory map changes as required. +// +static inline void decodeMemoryMapSetup(zuint16 address, zuint8 data, uint8_t ioFlag, uint8_t readFlag) +{ + // Locals. + uint32_t idx; + + // If the RFS module is enabled, it must set the map otherwise use the default handler. + // + #if(TARGET_HOST_MZ80A == 1) + if(Z80Ctrl->virtualDeviceBitMap & VIRTUAL_DEVICE_RFS) + { + rfsDecodeMemoryMapSetup(address, data, ioFlag, readFlag); + } else + #endif + { + // Decoding memory address or I/O address? + if(ioFlag == 0) + { + // Certain machines have memory mapped I/O, these need to be handled in-situ as some reads may change the memory map. + // These updates are made whilst waiting for the CPLD to retrieve the requested byte. + // + // 0000 - 0FFF : MZ80K/A/700 = Monitor ROM or RAM (MZ80A rom swap) + // 1000 - CFFF : MZ80K/A/700 = RAM + // C000 - CFFF : MZ80A = Monitor ROM (MZ80A rom swap) + // D000 - D7FF : MZ80K/A/700 = VRAM + // D800 - DFFF : MZ700 = Colour VRAM (MZ700) + // E000 - E003 : MZ80K/A/700 = 8255 + // E004 - E007 : MZ80K/A/700 = 8254 + // E008 - E00B : MZ80K/A/700 = LS367 + // E00C - E00F : MZ80A = Memory Swap (MZ80A) + // E010 - E013 : MZ80A = Reset Memory Swap (MZ80A) + // E014 : MZ80A/700 = Normat CRT display + // E015 : MZ80A/700 = Reverse CRT display + // E200 - E2FF : MZ80A/700 = VRAM roll up/roll down. + // E800 - EFFF : MZ80K/A/700 = User ROM socket or DD Eprom (MZ700) + // F000 - F7FF : MZ80K/A/700 = Floppy Disk interface. + // F800 - FFFF : MZ80K/A/700 = Floppy Disk interface. + switch(address) + { + #if(TARGET_HOST_MZ700 == 1) + #endif + #if(TARGET_HOST_MZ2000 == 1) + #endif + + #if(TARGET_HOST_MZ80A == 1) + // Memory map switch. + case 0xE00C: case 0xE00D: case 0xE00E: case 0xE00F: + if(readFlag) + { + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, (0xC000+idx)); + setMemoryType((idx+0xC000)/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + } + Z80Ctrl->memSwitch = 1; + break; + + // Reset memory map switch. + case 0xE010: case 0xE011: case 0xE012: case 0xE013: + if(readFlag) + { + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + setMemoryType((idx+0xC000)/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, (idx+0xC000)); + } + } + Z80Ctrl->memSwitch = 0; + break; + #endif + + default: + break; + } + } else + { + // Determine if this is a memory management port and update the memory page if required. + switch(address & 0x00FF) + { + // MZ700 memory mode switch. + // + // MZ-700 + // |0000:0FFF|1000:CFFF|D000:FFFF + // ------------------------------ + // OUT 0xE0 = |DRAM | | + // OUT 0xE1 = | | |DRAM + // OUT 0xE2 = |MONITOR | | + // OUT 0xE3 = | | |Memory Mapped I/O + // OUT 0xE4 = |MONITOR |DRAM |Memory Mapped I/O + // OUT 0xE5 = | | |Inhibit + // OUT 0xE6 = | | | + // + // = Return to the state prior to the complimentary command being invoked. + #if(TARGET_HOST_MZ700 == 1) + // Enable lower 4K block as DRAM + case IO_ADDR_E0: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + break; + + // Enable upper 12K block, including Video/Memory Mapped peripherals area, as DRAM. + case IO_ADDR_E1: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + // MZ-700 mode we only work in first 64K block. + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + } + break; + + // Enable MOnitor ROM in lower 4K block + case IO_ADDR_E2: + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + break; + + // Enable Video RAM and Memory mapped peripherals in upper 12K block. + case IO_ADDR_E3: + if(!Z80Ctrl->inhibitMode) + { + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Reset to power on condition memory map. + case IO_ADDR_E4: + // Lower 4K set to Monitor ROM. + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + if(!Z80Ctrl->inhibitMode) + { + // Upper 12K to hardware. + for(idx=0xD000; idx < 0xE000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + for(idx=0xE000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + } + break; + + // Inhibit. Backup current page data in region 0xD000-0xFFFF and inhibit it. + case IO_ADDR_E5: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + backupMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_INHIBIT, idx); + } + Z80Ctrl->inhibitMode = 1; + break; + + // Restore D000-FFFF to its original state. + case IO_ADDR_E6: + for(idx=0xD000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + restoreMemoryType(idx/MEMORY_BLOCK_GRANULARITY); + } + Z80Ctrl->inhibitMode = 0; + break; + #endif + + #if(TARGET_HOST_MZ2000 == 1) + case IO_ADDR_E0: + break; + + case IO_ADDR_E1: + break; + + case IO_ADDR_E2: + break; + + case IO_ADDR_E3: + // Program control register. + if(value & 0x80) + { + } else + { + switch((value >> 1) & 0x07) + { + // NST toggle. + case 1: + // NST pages in all RAM and resets cpu. + if(value & 0x01) + { + Z80Ctrl->lowMemorySwap = 0; + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(Z80Ctrl->defaultPageMode == USE_PHYSICAL_RAM) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + } + z80_instant_reset(&Z80CPU); + } + break; + + default: + break; + } + } + break; + + case IO_ADDR_E8: + // NEED FLAG TO SET THIS WHEN CALLED WITH NON MEMORY SWITCH BYTE + if(isPhysical(0xD000) && (value & 0x80) == 0) + { + for(idx=0xC000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(Z80Ctrl->defaultPageMode == USE_PHYSICAL_RAM) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, (Z80Ctrl->lowMemorySwap ? idx - 0x8000 : idx)); + } + } + } else + if(value & 0x80) + { + if(value & 0x40) + { + setMemoryType(0xD000/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, 0xD000); + } else + { + for(idx=0xC000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + } + } + break; + #endif + + #if(TARGET_HOST_MZ80A == 1) + #endif + + // Port is not a memory management port. + default: + break; + } + } + } + + return; +} + +// Method to decode address and invoke virtual hardware to handle accordingly. +// +static inline zuint8 readVirtualHW(zuint16 address, uint8_t ioFlag) +{ + // Locals. + // + zuint8 data = 0xFF; + + // Invoke the specific hardware emulation. + // + #if(TARGET_HOST_MZ80A == 1) + // RFS only has memory mapped registers. + if((Z80Ctrl->virtualDeviceBitMap & VIRTUAL_DEVICE_RFS) && ioFlag == 0) + { + data = rfsRead(address); + } + #endif + if((Z80Ctrl->virtualDeviceBitMap & VIRTUAL_DEVICE_TZPU) && (ioFlag == 0 || isVirtualDevice(address, VIRTUAL_DEVICE_TZPU))) + { + data = tzpuRead(address); + } + + return(data); +} + +// Method to decode address and invoke virtual hardware to handle accordingly. +// +static inline void writeVirtualHW(zuint16 address, zuint8 data, uint8_t ioFlag) +{ + // Locals. + + // Invoke the specific hardware emulation. + // + #if(TARGET_HOST_MZ80A == 1) + // RFS only has memory mapped registers. + if((Z80Ctrl->virtualDeviceBitMap & VIRTUAL_DEVICE_RFS) && ioFlag == 0) + { + rfsWrite(address, data); + } + #endif + if((Z80Ctrl->virtualDeviceBitMap & VIRTUAL_DEVICE_TZPU) && (ioFlag == 0 || isVirtualDevice(address, VIRTUAL_DEVICE_TZPU))) + { + tzpuWrite(address, data); + } + + return; +} + +// The first design, using the SSD202 from SigmaStar suffers from very slow I/O, ie. reading an 8bit GPIO value, in a tight loop +// attains just short of 2MB/s as you need to read 8xindividual I/O bits and the I/O subsystem is running much slower than the CPU (~72MHz). +// Due to this, we use the SPI as it is quicker but we need to look ahead and send off requests to the CPLD ahead of time to minimise delay in +// time critical operations such as Floppy Disk read/write. +// +// This method attempts to decode the current opcode and if it is a hardware operation, make the request ahead of the Z80 emulator. +static inline void lookAhead(zuint16 address, zuint8 opcode, zuint8 opcode2) +{ + // Locals. + // + + // IN r,(C) INI, INIR, IND, INDR + if( (opcode == 0xED && (( (opcode2 & 0x78) != 0) || ((opcode2 & 0xBA) != 0)) && ((opcode2 & 0x01) == 0x00)) ) + { + SPI_SEND32( (Z80CPU.bc.uint16_value << 16) | CPLD_CMD_READIO_ADDR); + Z80Ctrl->ioReadAhead = 1; + } + // IN A, (N) + else if(opcode == 0xDB) + { + SPI_SEND32( ((Z80CPU.bc.uint16_value & 0xff00) | opcode2) << 16 | CPLD_CMD_READIO_ADDR); + Z80Ctrl->ioReadAhead = 1; + } + // OUT (C), r OTDR, OTIR, OUTD, OUTI + else if( (opcode == 0xED && (( (opcode2 & 0x79) != 0) || ((opcode2 & 0xBB) != 0)) && ((opcode2 & 0x01) == 0x01)) ) + { + SPI_SEND32( (Z80CPU.bc.uint16_value << 16) | ((opcode2 == 0x79 ? Z80CPU.af.uint8_values.at_1 : + opcode2 == 0x41 ? Z80CPU.bc.uint8_values.at_1 : + opcode2 == 0x49 ? Z80CPU.bc.uint8_values.at_0 : + opcode2 == 0x51 ? Z80CPU.de.uint8_values.at_1 : + opcode2 == 0x59 ? Z80CPU.de.uint8_values.at_0 : + opcode2 == 0x61 ? Z80CPU.hl.uint8_values.at_1 : + opcode2 == 0x69 ? Z80CPU.hl.uint8_values.at_0 : + isVirtualROM((Z80CPU.hl.uint16_value)) ? readVirtualROM((Z80CPU.hl.uint16_value)) : readVirtualRAM((Z80CPU.hl.uint16_value))) << 8) + | CPLD_CMD_WRITEIO_ADDR); + Z80Ctrl->ioWriteAhead = 1; + } + // OUT (N), A + else if(opcode == 0xD3) + { + SPI_SEND32( ((Z80CPU.bc.uint16_value & 0xff00) | opcode2) << 16 | (Z80CPU.af.uint8_values.at_1 << 8) | CPLD_CMD_WRITEIO_ADDR); + Z80Ctrl->ioWriteAhead = 1; + } +} + +//------------------------------------------------------------------------------------------------------------------------------- +// +// Z80 CPU Kernel Logic. +// +// THe Z80 CPU is initialised and set running, processing instructions either from the underlying host hardware or internal +// memory. The configuration and flow is controlled via the Z80Ctrl structure which is User Space accessible. +// +//------------------------------------------------------------------------------------------------------------------------------- + +// Method to read a byte from physical hardware or internal virtual memory/devices. +// The page table indicates the source and the read is processed accordingly. +static zuint8 z80_read(void *context, zuint16 address) +{ + // Locals. + // + zuint8 data; + Z_UNUSED(context) + + // Only read if the address is in physical RAM. + if(isPhysical(address)) + { + // Commence cycle to retrieve the data from Real RAM. + SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_READ_ADDR); + + // Decode address to action any host specific memory map changes. + decodeMemoryMapSetup(address, 0, 0, true); + + // Data arrived? + while(CPLD_READY() == 0); + data = z80io_PRL_Read(); + + // Pause until the Last T-State is detected. + //while(CPLD_LAST_TSTATE() == 0); + } + else if(isVirtualHW(address)) + { + // Decode the address and if virtual logic exists, invoke it. + data = readVirtualHW(address, 0); + } + else if(isVirtualMemory(address)) + { + // Retrieve data from virtual memory. + data = isVirtualROM(address) ? readVirtualROM(address) : readVirtualRAM(address); + } + + // Keyport data? Store. + if(isHW(address) && address == 0xE001 && (Z80Ctrl->keyportStrobe & 0x0f) == 8 && (data & 0x41) == 0) + { + Z80Ctrl->keyportShiftCtrl = 0x01; + } else + if(isHW(address) && address == 0xE001 && (Z80Ctrl->keyportStrobe & 0x0f) == 0 && (data & 0x80) == 0) + { + Z80Ctrl->keyportHotKey = 0x01; + } + + return(data); +} + +// Method to write a byte to physical hardware or internal virtual memory or devices. +// The page table indicates the target and the write is processed accordingly. +static void z80_write(void *context, zuint16 address, zuint8 data) +{ + // Locals. + Z_UNUSED(context) + + // To detect Hotkey presses, we need to store the keyboard strobe data and on keydata read. + if(isHW(address) && address == 0xE000) + { + Z80Ctrl->keyportStrobe = data; + } + + // Write to physical host? + if(isPhysical(address)) + { + // Commence cycle to write the data to real RAM. + SPI_SEND32((uint32_t)address << 16 | data << 8 | CPLD_CMD_WRITE_ADDR); + + // Write-thru to virtual memory if we update real memory. + if(isPhysicalRAM(address)) + writeVirtualRAM(address, data); + + // Decode address to action any host specific memory map changes. + decodeMemoryMapSetup(address, data, 0, false); + + // Pause until the Last T-State is detected. + //while(CPLD_LAST_TSTATE() == 0); + } + else if(isVirtualHW(address)) + { + // Decode the address and if virtual logic exists, invoke and write to it. + writeVirtualHW(address, data, 0); + } + else if(isVirtualRAM(address)) + { + // Update virtual memory. + writeVirtualRAM(address, data); + } + // Cannot write to virtual ROM so no logic. +} + +// Primary Opcode fetch method. This method is called each time a single or multi-byte opcode is +// encountered. Opcode data is retrieved via the z80_fetch method. +// +// Depending on the address and the configured page map, the opcode is fetched from hardware +// or internal virtual memory. As this method is the primary timing method for Z80 instructions +// (read/write methods dont affect the timing so much as long as they operate in less than the read/write +// cycle of an original Z80). +// +// Initially the timing on the virtual memory is set by a governor delay but this will be updated to a more +// precise M/T-State cycle per instruction type delay. +static zuint8 z80_fetch_opcode(void *context, zuint16 address) +{ + // Locals. + zuint8 opcode = 0x00; + volatile uint32_t idx; // Leave as volatile otherwise optimiser will optimise out the delay code. + Z_UNUSED(context) + + // Normally only opcode fetches occur in RAM but allow any physical address as it could be a Z80 programming trick. + #if(TARGET_HOST_MZ80A == 1) + // MZ-80A floppy disk controller uses address 0xF3FE/0xF7FE to direct program flow according to READY state of the + // MB8866 controller. + if(isPhysical(address) || address == 0xF3FE) + #else + if(isPhysical(address)) + #endif + { + // Commence cycle to fetch the opcode from potentially Real RAM albeit it could be any physical hardware. + SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_FETCH_ADDR); + while(CPLD_READY() == 0); + opcode = z80io_PRL_Read(); + + // Pause until the Last T-State is detected. + //while(CPLD_LAST_TSTATE() == 0); + } else + // Virtual fetches only occur in memory as we are not emulating original hardware. + if(isVirtualMemory(address)) + { + // Delay loop is to govern execution speed to the same as the original host. Timing is primarily based on the main opcode + // fetch so long as the additional opcode parameter and read/write take less time than original host. + if(isVirtualROM(address)) + { + opcode = readVirtualROM(address); + for(idx=0; idx < Z80Ctrl->cpuGovernorDelayROM; idx++); + } else + { + opcode = readVirtualRAM(address); + for(idx=0; idx < Z80Ctrl->cpuGovernorDelayRAM; idx++); + } + } +//if(address < 0x9e0 || address > 0xA00) +//if(address >= 0xE800 && address < 0xF000) +//pr_info("Fetch:%04x(%08x):%02x\n", address, getPageAddr(address, MEMORY_TYPE_VIRTUAL_MASK), opcode); + // Check if this operation is I/O or known memory I/O so we can look ahead to optimise sending request to CPLD. + lookAhead(address, opcode, isVirtualROM((address+1)) ? readVirtualROM((address+1)) : readVirtualRAM((address+1))); + + return(opcode); +} + +// Method similar to z80_read, kept seperate to avoid additional what-if logic and doesnt require virtual hardware logic. +// +static zuint8 z80_fetch(void *context, zuint16 address) +{ + // Locals. + // + zuint8 data = 0x00; + Z_UNUSED(context) + + // Normally only opcode fetches occur in RAM but allow any physical address as it could be a Z80 programming trick. + if(isPhysical(address)) + { + // Given the limitation of the SigmaStar I/O, it isnt possible to fetch all code from ROM real time, it is therefore cached + // and read from cache. + data = isPhysicalROM(address) ? readVirtualROM(address) : readVirtualRAM(address); + + // Commence cycle to retrieve the data from Real RAM. + //SPI_SEND32((uint32_t)address << 16 | CPLD_CMD_READ_ADDR); + + //while(CPLD_READY() == 0); + //data = READ_CPLD_DATA_IN(); + + // Pause until the Last T-State is detected. + //while(CPLD_LAST_TSTATE() == 0); + } else + if(isVirtualMemory(address)) + { + // Retrieve data from virtual memory. + data = isVirtualROM(address) ? readVirtualROM(address) : readVirtualRAM(address); + } + + // Check for interrupts. + if(CPLD_Z80_NMI() != 0) z80_nmi(&Z80CPU); + z80_int(&Z80CPU, CPLD_Z80_INT() != 0); +//if(CPLD_Z80_INT() != 0) pr_info("Interrupt High\n"); + return(data); +} + +// Method to perform a Z80 input operation. This normally goes to hardware and the CPLD executes the required cycle. +// Some ports are dedicated virtual ports providing virtual services to the host computer/application. These are intercepted +// and processed in this driver. +static zuint8 z80_in(void *context, zuint16 port) +{ + // Locals. + zuint8 value; + Z_UNUSED(context) + + // Physical port go direct to hardware to retrieve value. + if(isPhysicalIO(port)) + { + if(Z80Ctrl->ioReadAhead == 0) + { + // Commence cycle to retrieve the value from the I/O port. Port contains the 16bit BC value. + SPI_SEND32((uint32_t)port << 16 | CPLD_CMD_READIO_ADDR); + + // Whilst waiting for the CPLD, we now determine if this is a memory management port and update the memory page if required. + decodeMemoryMapSetup(port, 0, 1, true); + } + Z80Ctrl->ioReadAhead = 0; + + // Finally ensure the data from the port is ready and retrieve it. + while(CPLD_READY() == 0); + value = z80io_PRL_Read(); + } else + // Virtual I/O Port. + if(isVirtualIO(port)) + { + // Virtual I/O - call the handler. + value = readVirtualHW(port, 1); + } +//pr_info("z80_in:0x%x, 0x%x\n", port, value); + return(value); +} + +// Method to perform a Z80 output operation. This normally goes to hardware and the CPLD executes the required cycle. +// Some ports are dedicated virtual ports providing virtual services to the host computer/application. These are intercepted +// and processed in this driver. +// There are also ports which are both hardware and need mirroring in software. These ports, typically memory mapping ports. +// when activated in the hardware need to be mirrored in the page table so correct virtual memory is used when addressed. +static void z80_out(void *context, zuint16 port, zuint8 value) +{ + // Locals. + #if(TARGET_HOST_MZ2000 == 1) + uint32_t idx; + #endif + Z_UNUSED(context) + + // Physical port go direct to hardware to retrieve value. + if(isPhysicalIO(port)) + { + // If byte has already been written during the fetch phase, skip. + if(Z80Ctrl->ioWriteAhead == 0) + { + // Commence cycle to write the value to the I/O port. Port contains the 16bit BC value. + SPI_SEND32((uint32_t)port << 16 | value << 8 | CPLD_CMD_WRITEIO_ADDR); + } + Z80Ctrl->ioWriteAhead = 0; + + // Decode address to action any host specific memory map changes. + decodeMemoryMapSetup(port, value, 1, false); + } else + if(isVirtualIO(port)) + { + // Decode the address and if virtual logic exists, invoke and write to it. + writeVirtualHW(port, value, 1); + } +//pr_info("z80_out:0x%x, 0x%x\n", port, value); +} + +// NOP - No Operation method. This instruction is used for timing, padding out an application or during +// HALT cycles to ensure Refresh occurs. +// If the address is configured as hardware (via the page table) then a refresh cycle is requested otherwise +// nothing to be done. +static zuint8 z80_nop(void *context, zuint16 address) +{ + // Locals. + Z_UNUSED(context) + + if(isPhysical(address)) + { + // If autorefresh is not enabled, send a single refresh request. + if(Z80Ctrl->refreshDRAM == 0) + SPI_SEND8(CPLD_CMD_REFRESH); +pr_info("NOP"); + } + return 0x00; +} + +// HALT - CPU executes a HALT instruction which results in the HALT line going active low and then it enters +// a state executing NOP instructions to ensure DRAM refresh until a reset or INT event. +static void z80_halt(void *context, zboolean state) +{ + // Locals. + Z_UNUSED(context) Z_UNUSED(state) + + // Inform CPLD of halt state. + pr_info("z80_halt\n"); + SPI_SEND8(CPLD_CMD_HALT); + Z80CPU.cycles = Z80_MAXIMUM_CYCLES; +} + +// Methods below are not yet implemented, Work In Progress! +static zuint8 z80_context(void *context, zuint16 address) +{ + Z_UNUSED(context) + pr_info("z80_context\n"); + return 0x00; +} +static zuint8 z80_nmia(void *context, zuint16 address) +{ + Z_UNUSED(context) + pr_info("z80_nmia\n"); + return 0x00; +} +static zuint8 z80_inta(void *context, zuint16 address) +{ + Z_UNUSED(context) + //pr_info("z80_inta\n"); + return 0x00; +} +static zuint8 z80_intFetch(void *context, zuint16 address) +{ + Z_UNUSED(context) + pr_info("z80_int_fetch\n"); + return 0x00; +} +static void z80_ldia(void *context) +{ + Z_UNUSED(context) + pr_info("z80_ldia\n"); +} +static void z80_ldra(void *context) +{ + Z_UNUSED(context) + pr_info("z80_ldra\n"); +} +static void z80_reti(void *context) +{ + Z_UNUSED(context) + pr_info("z80_reti\n"); +} +static void z80_retn(void *context) +{ + Z_UNUSED(context) + pr_info("z80_retn\n"); +} +static zuint8 z80_illegal(void *context, zuint8 opcode) +{ + Z_UNUSED(context) + pr_info("z80_illegal\n"); + return 0x00; +} + +// Z80 CPU Emulation Thread +// ------------------------ +// This is a kernel thread, bound to CPU 1 with IRQ's disabled. +// The Z80 is controlled by a mutex protected variable to define run, stop, pause and terminate modes. +int thread_z80(void * thread_nr) +{ + // Locals. + uint8_t canRun = 0; + int t_nr = *(int *) thread_nr; + //struct sched_param param = {.sched_priority = 99}; + spinlock_t spinLock; + unsigned long flags; + + // Initialise spinlock and disable IRQ's. We should be the only process running on core 1. + spin_lock_init(&spinLock); + spin_lock_irqsave(&spinLock, flags); + + // Assign this emulation to high priority realtime scheduling. Also the task will be assigned to an isolated CPU. + //sched_setscheduler(current, SCHED_RR, ¶m); + + // Run the CPU forever or until a stop occurs. + while(!kthread_should_stop()) + { + // Run the Z80 emulation if enabled. + if(canRun) z80_run(&Z80CPU, 100); + + // Reset pressed? + if(CPLD_RESET()) + { + z80_instant_reset(&Z80CPU); + setupMemory(Z80Ctrl->defaultPageMode); + + // Wait for release before restarting CPU. + while(CPLD_RESET()); + } else + { + // Update state to indicate request has been actioned. + mutex_lock(&Z80RunModeMutex); + if(Z80RunMode == Z80_STOP) Z80RunMode = Z80_STOPPED; + if(Z80RunMode == Z80_PAUSE) Z80RunMode = Z80_PAUSED; + if(Z80RunMode == Z80_CONTINUE) Z80RunMode = Z80_RUNNING; + if(Z80RunMode == Z80_RUNNING) canRun=1; else canRun=0; + mutex_unlock(&Z80RunModeMutex); + + // Hotkey pressed? Bring up user menu. + if(Z80Ctrl->keyportShiftCtrl && Z80Ctrl->keyportHotKey) + { + z80menu(); + Z80Ctrl->keyportShiftCtrl = 0; + Z80Ctrl->keyportHotKey = 0; + } + } + } + + // Release spinlock as we are unloading driver. + spin_unlock_irqrestore(&spinLock, flags); + pr_info("kthread - Z80 Thread %d finished execution!\n", t_nr); + return 0; +} + + +//------------------------------------------------------------------------------------------------------------------------------- +// +// User space driver access. +// +//------------------------------------------------------------------------------------------------------------------------------- + + +// Device close. +// When a user space application terminates or closes the z80drv device driver, this function is called +// to close any open connections, memory and variables required to handle the user space application +// requests. +static int z80drv_release(struct inode *inodep, struct file *filep) +{ + // Locals. + + mutex_unlock(&Z80DRV_MUTEX); + //pr_info("z80drv: Device successfully closed\n"); + + return(0); +} + +// Device open. +// When a user space application open's the z80drv device driver, this function is called +// to initialise and allocate any required memory or devices prior to servicing requests from the +// user space application. +static int z80drv_open(struct inode *inodep, struct file *filep) +{ + // Locals. + int ret = 0; + + if(!mutex_trylock(&Z80DRV_MUTEX)) + { + pr_alert("z80drv: device busy!\n"); + ret = -EBUSY; + goto out; + } + + //pr_info("z80drv: Device opened\n"); + +out: + return(ret); +} + +// Map shared memory. +// The z80drv allocates on the stack a chunk of memory and control variables which is used to control the Z80 Emulation state +// and provide it with internal 'virtual memory'. This virtual memory is either used as the core Z80 memory or as banked extensions +// to the host DRAM. +// The user space application is able to bind with the shared memory to perform tasks such as load/save of applications. +static int z80drv_mmap(struct file *filp, struct vm_area_struct *vma) +{ + // Locals. + int ret = 0; + struct page *page = NULL; + unsigned long size = (unsigned long)(vma->vm_end - vma->vm_start); + + // Z80Ctrl? + if(size >= sizeof(t_Z80Ctrl) && size <= (sizeof(t_Z80Ctrl)+0x1000)) + { + // Map the memory and exit. + page = virt_to_page((unsigned long)Z80Ctrl + (vma->vm_pgoff << PAGE_SHIFT)); + ret = remap_pfn_range(vma, vma->vm_start, page_to_pfn(page), size, vma->vm_page_prot); + if (ret != 0) + { + goto out; + } + } + else if(size >= Z80_VIRTUAL_RAM_SIZE && size < (Z80_VIRTUAL_RAM_SIZE+0x1000)) + { + // Map the memory and exit. + page = virt_to_page((unsigned long)Z80Ctrl->ram + (vma->vm_pgoff << PAGE_SHIFT)); + ret = remap_pfn_range(vma, vma->vm_start, page_to_pfn(page), size, vma->vm_page_prot); + if (ret != 0) + { + goto out; + } + } + // To distinguish a ROM map request from a RAM request, the ROM size is 1 page greater than actual memory. + else if(size >= (Z80_VIRTUAL_ROM_SIZE+0x1000) && size < (Z80_VIRTUAL_ROM_SIZE+0x2000)) + { + // Map the memory and exit. + page = virt_to_page((unsigned long)Z80Ctrl->rom + (vma->vm_pgoff << PAGE_SHIFT)); + ret = remap_pfn_range(vma, vma->vm_start, page_to_pfn(page), size, vma->vm_page_prot); + if (ret != 0) + { + goto out; + } + } + else + { + ret = -EINVAL; + goto out; + } + +out: + return ret; +} + +// Device read. +// This method allows an application which opens the z80drv driver to read data in a stream. It is here for +// possible future use. +static ssize_t z80drv_read(struct file *filep, char *buffer, size_t len, loff_t *offset) +{ + // Locals. + int ret; + + if (len > Z80_VIRTUAL_RAM_SIZE) + { + pr_info("read overflow!\n"); + ret = -EFAULT; + goto out; + } + + if (copy_to_user(buffer, Z80Ctrl, len) == 0) + { + pr_info("z80drv: copy %u char to the user\n", len); + ret = len; + } else + { + ret = -EFAULT; + } + +out: + return ret; +} + +// Device write. +// This method allows an application which opens the z80drv driver to write stream data. It is here for +// possible future use. +static ssize_t z80drv_write(struct file *filep, const char *buffer, size_t len, loff_t *offset) +{ + // Locals. + int ret; + + if (copy_from_user(Z80Ctrl, buffer, len)) + { + pr_err("z80drv: write fault!\n"); + ret = -EFAULT; + goto out; + } + pr_info("z80drv: copy %d char from the user\n", len); + ret = len; + +out: + return ret; +} + +// Function to dump out a given section of the physical host memory. +// +int memoryDump(uint32_t memaddr, uint32_t memsize, uint32_t dispaddr, uint8_t dispwidth) +{ + uint8_t displayWidth = dispwidth; + uint32_t pnt = memaddr; + uint32_t endAddr = memaddr + memsize; + uint32_t addr = dispaddr; + uint8_t data; + uint32_t i = 0; + int result = -1; + char c = 0; + + // If not set, calculate output line width according to connected display width. + // + if(displayWidth == 0) + { + switch(MAX_SCREEN_WIDTH) + { + case 40: + displayWidth = 8; + break; + case 80: + displayWidth = 16; + break; + default: + displayWidth = 32; + break; + } + } + + while (1) + { + pr_info(KERN_INFO "%08X", addr); // print address + pr_info(KERN_CONT ": "); + + // print hexadecimal data + for (i=0; i < displayWidth; ) + { + if(pnt+i < endAddr) + { + SPI_SEND32((uint16_t)(pnt+i) << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + data = z80io_PRL_Read(); + pr_info(KERN_CONT "%02X", data); + } + else + pr_info(KERN_CONT " "); + i++; + + pr_info(KERN_CONT " "); + } + + // print ascii data + pr_info(KERN_CONT " |"); + + // print single ascii char + for (i=0; i < displayWidth; i++) + { + SPI_SEND32((uint16_t)(pnt+i) << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + c = (char)z80io_PRL_Read(); + if ((pnt+i < endAddr) && (c >= ' ') && (c <= '~')) + pr_info(KERN_CONT "%c", (char)c); + else + pr_info(KERN_CONT " "); + } + + pr_info(KERN_CONT "|\n"); + + // Move on one row. + pnt += displayWidth; + addr += displayWidth; + + // End of buffer, exit the loop. + if(pnt >= (memaddr + memsize)) + { + break; + } + } + + return(result); +} + +// Method to setup a default memory/IO profile. This profile will be changed by the host processing and also can be tweaked +// by the z80ctrl application. +// +void setupMemory(enum Z80_MEMORY_PROFILE mode) +{ + // Locals. + uint32_t idx; + + if(mode == USE_PHYSICAL_RAM) + { + #if(TARGET_HOST_MZ700 == 1) + #endif + #if(TARGET_HOST_MZ2000 == 1) + // Initialise the page pointers and memory to use physical RAM. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0 && idx < 0x8000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } + else //if(idx >= 0x8000 && idx < 0xD000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + + // Video RAM labelled as HW as we dont want to cache it. + //else if(idx >= 0xD000 && idx < 0xE000) + // { + // setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + //} else + // { + // setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + // } + } + #endif + #if(TARGET_HOST_MZ80A == 1) + // Initialise the page pointers and memory to use physical RAM. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0 && idx < 0x1000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } + else if(idx >= 0x1000 && idx < 0xD000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + else if(idx >= 0xD000 && idx < 0xE000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + else if(idx >= 0xE000 && idx < 0xE800) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + else if(idx >= 0xE800 && idx < 0x10000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_ROM, idx); + } else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_RAM, idx); + } + } + #endif + for(idx=0x0000; idx < 0x10000; idx++) + { + Z80Ctrl->iopage[idx] = idx | IO_TYPE_PHYSICAL_HW; + } + // Cancel refresh as using physical RAM for program automatically refreshes DRAM. + Z80Ctrl->refreshDRAM = 0; + } + else if(mode == USE_VIRTUAL_RAM) + { + #if(TARGET_HOST_MZ2000 == 1) + // Initialise the page pointers and memory to use virtual RAM. + // MZ-2000 comes up in IPL mode where lower 32K is ROM and upper 32K is RAM remapped from 0x0000. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0 && idx < 0x8000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, (Z80Ctrl->lowMemorySwap ? idx - 0x8000 : idx)); + } + } + for(idx=0x0000; idx < 0x10000; idx++) + { + Z80Ctrl->iopage[idx] = idx | IO_TYPE_PHYSICAL_HW; + } + // Enable refresh as using virtual RAM stops refresh of host DRAM. + Z80Ctrl->refreshDRAM = 1; + #endif + #if(TARGET_HOST_MZ80A == 1) + // Initialise the page pointers and memory to use virtual RAM. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0 && idx < 0x1000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + else if(idx >= 0xD000 && idx < 0xE000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_VRAM, idx); + } + else if(idx >= 0xE000 && idx < 0xE800) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_PHYSICAL_HW, idx); + } + else if(idx >= 0xE800 && idx < 0xF000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_HW, idx); + } + else if(idx >= 0xF000 && idx < 0x10000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, idx); + } + else + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, idx); + } + } + for(idx=0x0000; idx < 0x10000; idx++) + { + Z80Ctrl->iopage[idx] = idx | IO_TYPE_PHYSICAL_HW; + } + // Enable refresh as using virtual RAM stops refresh of host DRAM. + Z80Ctrl->refreshDRAM = 0; + #endif + } + + // Call driver specific methods to change default memory map per device requirements. + #if(TARGET_HOST_MZ80A == 1) + if(Z80Ctrl->virtualDeviceBitMap & VIRTUAL_DEVICE_RFS) + rfsSetupMemory(mode); + #endif + if(Z80Ctrl->virtualDeviceBitMap & VIRTUAL_DEVICE_TZPU) + tzpuSetupMemory(mode); + + // Enable autorefresh if refreshDRAM is set. + SPI_SEND8(Z80Ctrl->refreshDRAM == 1 ? CPLD_CMD_SET_AUTO_REFRESH : CPLD_CMD_CLEAR_AUTO_REFRESH); + + // Inhibit mode disabled. + Z80Ctrl->inhibitMode = 0; + return; +} + +// IOCTL Method +// This method allows User Space application to control the Z80 CPU and internal functionality of the +// device driver. This is the preferred control method along with the shared memory segment for the driver. +static long int z80drv_ioctl(struct file *file, unsigned cmd, unsigned long arg) +{ + // Locals. + struct ioctlCmd ioctlCmd; + uint16_t idx; + uint32_t tmp[2]; + enum Z80_RUN_STATES currentRunMode; + enum Z80_RUN_STATES nextRunMode; + + // Get current running mode so any operations on the Z80 return it to original mode unless action overrides it. + mutex_lock(&Z80RunModeMutex); currentRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + + switch(cmd) + { + // Basic commands. + case IOCTL_CMD_SEND: + if(copy_from_user(&ioctlCmd, (int32_t *)arg, sizeof(ioctlCmd))) + pr_info("IOCTL - Couldnt retrieve command!\n"); + else + { + //pr_info("IOCTL - Command (%08x)\n", ioctlCmd.cmd); + switch(ioctlCmd.cmd) + { + // Command to stop the Z80 CPU and power off. + case IOCTL_CMD_Z80_STOP: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + z80_power(&Z80CPU, FALSE); + Z80_PC(Z80CPU) = 0; + pr_info("Z80 stopped.\n"); + break; + + // Command to power on and start the Z80 CPU. + case IOCTL_CMD_Z80_START: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_RUNNING; mutex_unlock(&Z80RunModeMutex); + + z80_power(&Z80CPU, TRUE); + pr_info("Z80 started.\n"); + break; + + // Command to pause the Z80. + case IOCTL_CMD_Z80_PAUSE: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_PAUSE; mutex_unlock(&Z80RunModeMutex); + pr_info("Z80 paused.\n"); + break; + + // Command to release a paused Z80. + case IOCTL_CMD_Z80_CONTINUE: + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_CONTINUE; mutex_unlock(&Z80RunModeMutex); + pr_info("Z80 running.\n"); + break; + + // Command to perform a CPU reset. + case IOCTL_CMD_Z80_RESET: + // Stop the CPU prior to reset. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + z80_instant_reset(&Z80CPU); + setupMemory(Z80Ctrl->defaultPageMode); + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + pr_info("Z80 Reset.\n"); + break; + + // Command to setup the page table to use host memory and physical hardware. + case IOCTL_CMD_USE_HOST_RAM: + // Stop the CPU prior to memory reconfiguration. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80Ctrl->defaultPageMode = USE_PHYSICAL_RAM; + setupMemory(Z80Ctrl->defaultPageMode); + z80_instant_reset(&Z80CPU); + + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + pr_info("Z80 Set to use Host Memory.\n"); + break; + + // Command to setup the page table to use virtual memory, only physical hardware is accessed on the host. + case IOCTL_CMD_USE_VIRTUAL_RAM: + // Stop the CPU prior to memory reconfiguration. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80Ctrl->defaultPageMode = USE_VIRTUAL_RAM; + setupMemory(Z80Ctrl->defaultPageMode); + z80_instant_reset(&Z80CPU); + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + pr_info("Z80 Set to use Virtual Memory.\n"); + break; + + // Command to synchronise virtual memory to host DRAM. + case IOCTL_CMD_SYNC_TO_HOST_RAM: + // Stop the CPU prior to memory sync. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Copy virtual memory to host DRAM. + for(idx=0x1000; idx < 0xD000; idx++) + { + SPI_SEND32((uint32_t)idx << 16 | Z80Ctrl->ram[idx] << 8 | CPLD_CMD_WRITE_ADDR); + } + + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + pr_info("Z80 Host DRAM syncd with Virtual Memory.\n"); + break; + + // Command to dump out host memory. + case IOCTL_CMD_DUMP_MEMORY: + // Need to suspend the Z80 otherwise we will get memory clashes. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_PAUSE; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_PAUSE); + + // Dump out the physical memory address. + memoryDump(ioctlCmd.addr.start, ioctlCmd.addr.end - ioctlCmd.addr.start, ioctlCmd.addr.start, 0); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to set the governor delay to approximate real Z80 cpu frequencies when running in virtual memory. + case IOCTL_CMD_Z80_CPU_FREQ: + switch(ioctlCmd.speed.speedMultiplier) + { + case 2: + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_X2; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_X2; + break; + + case 4: + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_X4; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_X4; + break; + + case 8: + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_X8; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_X8; + break; + + case 16: + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_X16; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_X16; + break; + + case 32: + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_X32; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_X32; + break; + + case 64: + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_X64; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_X64; + break; + + case 128: + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_X128; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_X128; + break; + + case 1: + default: + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_NORMAL; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_NORMAL; + break; + } + break; + + // Command to set the Z80 CPU Program Counter value. + case IOCTL_CMD_SETPC: + // Stop the CPU prior to PC change. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + Z80_PC(Z80CPU) = ioctlCmd.z80.pc; + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + pr_info("PC set to %04x\n", ioctlCmd.z80.pc); + break; + + // Command to add a virtual device into the Z80 configuration. + case IOCTL_CMD_ADD_DEVICE: + // Check that there is space to add the device and that it doesnt already exist. + if(Z80Ctrl->virtualDeviceCnt == MAX_VIRTUAL_DEVICES) + { + pr_info("Virtual Device table full, cannot add new device.\n"); + break; + } + for(idx = 0; idx < Z80Ctrl->virtualDeviceCnt; idx++) + { + if(Z80Ctrl->virtualDevice[idx] == ioctlCmd.vdev.device) + { + pr_info("Virtual Device already installed.\n"); + break; + } + } + if(idx < Z80Ctrl->virtualDeviceCnt) + break; + #if(TARGET_HOST_MZ700 == 1 || TARGET_HOST_MZ2000 == 1) + pr_info("RFS Board currently supported on MZ-80A Host only.\n"); + break; + #endif + + // Stop the CPU prior to adding virtual device. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Add in device, setting up hooks etc as required. The devices are stored in an array for ease of reference and lookup + // in the driver and ctrl program, in actual use they are a bit map for performance as scanning an array is time consuming. + switch(ioctlCmd.vdev.device) + { + #if(TARGET_HOST_MZ80A == 1) + case VIRTUAL_DEVICE_RFS: + Z80Ctrl->virtualDevice[Z80Ctrl->virtualDeviceCnt++] = VIRTUAL_DEVICE_RFS; + Z80Ctrl->virtualDeviceBitMap |= VIRTUAL_DEVICE_RFS; + rfsInit(); + break; + #endif + + case VIRTUAL_DEVICE_TZPU: + Z80Ctrl->virtualDevice[Z80Ctrl->virtualDeviceCnt++] = VIRTUAL_DEVICE_TZPU; + Z80Ctrl->virtualDeviceBitMap |= VIRTUAL_DEVICE_TZPU; + tzpuInit(); + break; + + case VIRTUAL_DEVICE_NONE: + default: + break; + } + + // Re-initialise the memory map to reflect device removal. + setupMemory(Z80Ctrl->defaultPageMode); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + pr_info("Virtual device added.\n"); + break; + + // Command to remove a device from the Z80 configuration. + case IOCTL_CMD_DEL_DEVICE: + // Locate the device. + for(idx = 0; idx < Z80Ctrl->virtualDeviceCnt; idx++) + { + if(Z80Ctrl->virtualDevice[idx] == ioctlCmd.vdev.device) + break; + } + if(idx == Z80Ctrl->virtualDeviceCnt) + { + pr_info("Virtual Device not found.\n"); + break; + } + + // Stop the CPU prior to virtual device removal. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + while(idx < (Z80Ctrl->virtualDeviceCnt-1)) + { + Z80Ctrl->virtualDevice[idx] = Z80Ctrl->virtualDevice[idx+1]; + } + Z80Ctrl->virtualDeviceCnt--; + + // Delete the device, removing hooks etc as required. + switch(ioctlCmd.vdev.device) + { + case VIRTUAL_DEVICE_RFS: + Z80Ctrl->virtualDeviceBitMap &= ~VIRTUAL_DEVICE_RFS; + break; + + case VIRTUAL_DEVICE_TZPU: + Z80Ctrl->virtualDeviceBitMap &= ~VIRTUAL_DEVICE_TZPU; + break; + + case VIRTUAL_DEVICE_NONE: + default: + break; + } + + // Re-initialise the memory map to reflect device removal. + setupMemory(Z80Ctrl->defaultPageMode); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + pr_info("Device removed\n"); + break; + + // Method to send adhoc commands to the CPLD, ie for switching active display etc. + case IOCTL_CMD_CPLD_CMD: + // Stop the CPU prior to sending a direct command to the CPLD. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Send the command, small delay then send NOP to retrieve the response. + z80io_SPI_Send32(ioctlCmd.cpld.cmd, &tmp[0]); + udelay(50); + z80io_SPI_Send32(0x00000000, &tmp[0]); + z80io_SPI_Send32(0x00000000, &tmp[1]); + pr_info("CPLD TX:%08x, RX:%08x,%08x\n", ioctlCmd.cpld.cmd, tmp[0], tmp[1]); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of SOM to CPLD SPI tests. + case IOCTL_CMD_SPI_TEST: + // Stop the CPU prior to SPI testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform SPI Tests. + z80io_SPI_Test(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of SOM to CPLD Parallel Bus tests. + case IOCTL_CMD_PRL_TEST: + // Stop the CPU prior to SPI testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform Parallel Bus tests. + z80io_PRL_Test(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + // Command to run a series of Z80 host memory tests to assess the performance of the SOM->CPLD interface. + case IOCTL_CMD_Z80_MEMTEST: + // Stop the CPU prior to Host memory testing. + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + do { mutex_lock(&Z80RunModeMutex); nextRunMode = Z80RunMode ; mutex_unlock(&Z80RunModeMutex); + } while(nextRunMode == Z80_STOP); + + // Perform host memory tests. + z80io_Z80_TestMemory(); + + // Z80 can continue. + mutex_lock(&Z80RunModeMutex); Z80RunMode = currentRunMode; mutex_unlock(&Z80RunModeMutex); + break; + + default: + break; + } + } + break; + + default: + pr_info("IOCTL - Unhandled Command (%08x)\n", ioctlCmd.cmd); + break; + + } + return 0; +} + +// Structure to declare public API methods. +// Standard Linux device driver structure to declare accessible methods within the driver. +static const struct file_operations z80drv_fops = { + .open = z80drv_open, + .read = z80drv_read, + .write = z80drv_write, + .release = z80drv_release, + .mmap = z80drv_mmap, + .unlocked_ioctl = z80drv_ioctl, + .owner = THIS_MODULE, +}; + +// Initialisation. +// This is the entry point into the device driver when loaded into the kernel. +// The method intialises any required hardware (ie. GPIO's, SPI etc), memory and the Z80 +// Emulation. It also allocates the Major and Minor device numbers and sets up the +// device in /dev. +static int __init ModuleInit(void) +{ + // Locals. + int idx; + int ret = 0; + + // Setup the Z80 handlers. + Z80CPU.context = z80_context; + Z80CPU.fetch = z80_fetch; + Z80CPU.fetch_opcode = z80_fetch_opcode; + Z80CPU.read = z80_read; + Z80CPU.write = z80_write; + Z80CPU.nop = z80_nop; + Z80CPU.in = z80_in; + Z80CPU.out = z80_out; + Z80CPU.halt = z80_halt; + Z80CPU.nmia = z80_nmia; + Z80CPU.inta = z80_inta; + Z80CPU.int_fetch = z80_intFetch; + Z80CPU.ld_i_a = z80_ldia; + Z80CPU.ld_r_a = z80_ldra; + Z80CPU.reti = z80_reti; + Z80CPU.retn = z80_retn; + Z80CPU.illegal = z80_illegal; + + // Version information. + pr_info("%s\n%s %s %s\n", DRIVER_DESCRIPTION, DRIVER_VERSION, DRIVER_COPYRIGHT, DRIVER_AUTHOR); + + mutex_init(&Z80DRV_MUTEX); + + // Get device Major number. + major = register_chrdev(0, DEVICE_NAME, &z80drv_fops); + if (major < 0) { + pr_info("z80drv: fail to register major number!"); + ret = major; + goto initExit; + } + + class = class_create(THIS_MODULE, CLASS_NAME); + if (IS_ERR(class)){ + unregister_chrdev(major, DEVICE_NAME); + pr_info("z80drv: failed to register device class"); + ret = PTR_ERR(class); + goto initExit; + } + + device = device_create(class, NULL, MKDEV(major, 0), NULL, DEVICE_NAME); + if (IS_ERR(device)) { + class_destroy(class); + unregister_chrdev(major, DEVICE_NAME); + ret = PTR_ERR(device); + goto initExit; + } + + // Allocate the Z80 memory to be shared between this kernel space driver and the controlling user space application. + Z80Ctrl = (t_Z80Ctrl *)kmalloc(sizeof(t_Z80Ctrl), GFP_KERNEL); + if (Z80Ctrl == NULL) + { + pr_info("z80drv: failed to allocate ctrl memory!"); + ret = -ENOMEM; + goto initExit; + } + Z80Ctrl->ram= (uint8_t *)kmalloc(Z80_VIRTUAL_RAM_SIZE, GFP_KERNEL); + if (Z80Ctrl->ram == NULL) + { + pr_info("z80drv: failed to allocate RAM memory!"); + ret = -ENOMEM; + goto initExit; + } + Z80Ctrl->rom= (uint8_t *)kmalloc(Z80_VIRTUAL_ROM_SIZE, GFP_KERNEL); + if (Z80Ctrl->rom == NULL) + { + pr_info("z80drv: failed to allocate ROM memory!"); + ret = -ENOMEM; + goto initExit; + } + + // Initialise the hardware to host interface. + z80io_init(); + + // Initialise the virtual RAM from the HOST DRAM. This is to maintain compatibility as some applications (in my experience) have + // bugs, which Im putting down to not initialising variables. The host DRAM is in a pattern of 0x00..0x00, 0xFF..0xFF repeating + // when first powered on. + pr_info("Sync Host RAM to virtual RAM.\n"); + for(idx=0; idx < Z80_VIRTUAL_RAM_SIZE; idx++) + { + #if(TARGET_HOST_MZ700 == 1) + if(idx >= 0x1000 && idx < 0xD000) + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->ram[idx] = z80io_PRL_Read8(1); + } else + { + Z80Ctrl->ram[idx] = 0x00; + } + #endif + #if(TARGET_HOST_MZ2000 == 1) + if(idx >= 0x8000 && idx < 0x10000) + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->ram[idx-0x8000] = z80io_PRL_Read8(1); + } else + { + if(idx >= 0x0000 && idx < 0x8000) + Z80Ctrl->ram[idx+0x8000] = 0x00; + else + Z80Ctrl->ram[idx] = 0x00; + } + #endif + #if(TARGET_HOST_MZ80A == 1) + if(idx >= 0x1000 && idx < 0xD000) + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->ram[idx] = z80io_PRL_Read8(1); + } else + { + Z80Ctrl->ram[idx] = 0x00; + } + #endif + } + + // Add in a test program to guage execution speed. + #if(TARGET_HOST_MZ700 == 1) + Z80Ctrl->ram[0x1200] = 0x01; + Z80Ctrl->ram[0x1201] = 0x86; + Z80Ctrl->ram[0x1202] = 0xf2; + Z80Ctrl->ram[0x1203] = 0x3e; + Z80Ctrl->ram[0x1204] = 0x15; + Z80Ctrl->ram[0x1205] = 0x3d; + Z80Ctrl->ram[0x1206] = 0x20; + Z80Ctrl->ram[0x1207] = 0xfd; + Z80Ctrl->ram[0x1208] = 0x0b; + Z80Ctrl->ram[0x1209] = 0x78; + Z80Ctrl->ram[0x120a] = 0xb1; + Z80Ctrl->ram[0x120b] = 0x20; + Z80Ctrl->ram[0x120c] = 0xf6; + Z80Ctrl->ram[0x120d] = 0xc3; + Z80Ctrl->ram[0x120e] = 0x00; + Z80Ctrl->ram[0x120f] = 0x00; + #endif + + // Copy the host BIOS into the Virtual ROM and initialise remainder of ROM. + pr_info("Sync Host BIOS to virtual ROM.\n"); + for(idx=0; idx < Z80_VIRTUAL_ROM_SIZE; idx++) + { + #if(TARGET_HOST_MZ700 == 1) + if(idx >= 0x0000 && idx < 0x1000) + #endif + #if(TARGET_HOST_MZ80A == 1) + if((idx >= 0x0000 && idx < 0x1000) || (idx >= 0xE800 && idx < 0x10000)) + #endif + #if(TARGET_HOST_MZ2000 == 1) + if(idx >= 0x0000 && idx < 0x8000) + #endif + { + SPI_SEND32((uint32_t)idx << 16 | CPLD_CMD_READ_ADDR); + while(CPLD_READY() == 0); + Z80Ctrl->rom[idx] = z80io_PRL_Read8(1); + } else + { + Z80Ctrl->rom[idx] = 0x00; + } + } + + #if(TARGET_HOST_MZ2000 == 1) + Z80Ctrl->lowMemorySwap = 1; + #endif + + #if(TARGET_HOST_MZ80A == 1) + Z80Ctrl->memSwitch = 0; + #endif + + // Initialise the virtual device array. + for(idx=0; idx < MAX_VIRTUAL_DEVICES; idx++) + { + Z80Ctrl->virtualDevice[idx] = VIRTUAL_DEVICE_NONE; + } + Z80Ctrl->virtualDeviceCnt = 0; + Z80Ctrl->virtualDeviceBitMap = 0; + + // Setup Refresh so that an automatic refresh mode is performed by the CPLD whilst running in Virtual memory. This is necessary as opcode fetches from + // host memory, by the CPLD, normally performs the refresh and when running in virtual memory, these refresh cycles arent performed. + Z80Ctrl->refreshDRAM = 0; + + // Setup the governor delay, it is the delay per opcode fetch to restrict the Z80 CPU to a given speed. + Z80Ctrl->cpuGovernorDelayROM = ROM_DELAY_NORMAL; + Z80Ctrl->cpuGovernorDelayRAM = RAM_DELAY_NORMAL; + + // Setup the default Page Mode. This is needed if an event such as a reset occurs which needs to return the page and iotable back to default. + Z80Ctrl->defaultPageMode = USE_VIRTUAL_RAM; + + // Setup memory profile to use internal virtual RAM (SOM kernel RAM rather than HOST DRAM). + setupMemory(Z80Ctrl->defaultPageMode); + + // Initialse run control. + mutex_init(&Z80RunModeMutex); + mutex_lock(&Z80RunModeMutex); Z80RunMode = Z80_STOP; mutex_unlock(&Z80RunModeMutex); + + // Initialise control flags. + Z80Ctrl->ioReadAhead = 0; + Z80Ctrl->ioWriteAhead = 0; + + // Initialse hotkey detection variables. + Z80Ctrl->keyportStrobe = 0x00; + Z80Ctrl->keyportShiftCtrl = 0x00; + Z80Ctrl->keyportHotKey = 0x00; + + // PC to start and power on the CPU + Z80_PC(Z80CPU) = 0; + z80_power(&Z80CPU, TRUE); + + // Init done. + pr_info("Initialisation complete.\n"); + + // Create thread to run the Z80 cpu. + kthread_z80 = kthread_create(thread_z80, &threadId_z80, "kthread_z80"); + if(kthread_z80 != NULL) + { + pr_info("kthread - Thread Z80 was created, waking...!\n"); + kthread_bind(kthread_z80, 1); + wake_up_process(kthread_z80); + } + else { + pr_info("kthread - Thread Z80 could not be created!\n"); + ret = -1; + goto initExit; + } + +initExit: + return ret; +} + +// Exit +// This method is called when the device driver is removed from the kernel with the rmmod command. +// It is responsible for closing and freeing all allocated memory, terminating all threads and removing +// the device from the /dev directory. +static void __exit ModuleExit(void) +{ + // Stop the internal threads. + kthread_stop(kthread_z80); + + // Return the memory used for the Z80 'virtual memory' and control variables. + kfree(Z80Ctrl); + + // Nothing to be done for the hardware. + + // Cleanup and remove the device. + mutex_destroy(&Z80DRV_MUTEX); + device_destroy(class, MKDEV(major, 0)); + class_unregister(class); + class_destroy(class); + unregister_chrdev(major, DEVICE_NAME); + + pr_info("z80drv: unregistered!\n"); +} + +module_init(ModuleInit); +module_exit(ModuleExit); diff --git a/software/FusionX/src/driver/MZ80A/z80driver.h b/software/FusionX/src/driver/MZ80A/z80driver.h new file mode 100644 index 000000000..d92d41bd2 --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80driver.h @@ -0,0 +1,439 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80driver.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Driver +// This file contains the declarations used in the z80drv device driver. +// +// Credits: Zilog Z80 CPU Emulator v0.2 written by Manuel Sainz de Baranda y Goñi +// The Z80 CPU Emulator is the heart of this driver and in all ways, is compatible with +// the original Z80. +// Copyright: (c) 2019-2023 Philip Smart +// (c) 1999-2023 Manuel Sainz de Baranda y Goñi +// +// History: Oct 2022 - v1.0 Initial write of the z80 kernel driver software. +// Jan 2023 - v1.1 Added MZ-2000/MZ-80A modes. +// Feb 2023 - v1.2 Added RFS virtual driver. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80DRIVER_H +#define Z80DRIVER_H + +// Constants. +#define DRIVER_LICENSE "GPL" +#define DRIVER_AUTHOR "Philip D Smart" +#define DRIVER_DESCRIPTION "Z80 CPU Emulator and Hardware Interface Driver" +#define DRIVER_VERSION "v1.2" +#define DRIVER_VERSION_DATE "Feb 2023" +#define DRIVER_COPYRIGHT "(C) 2018-2023" +#define TARGET_HOST_MZ700 0 // Target compilation for an MZ700 +#define TARGET_HOST_MZ2000 0 // MZ2000 +#define TARGET_HOST_MZ80A 1 // MZ80A +#define Z80_VIRTUAL_ROM_SIZE (65536 * 32) // Sized to maximum Kernel contiguous allocation size, 2M which is 4x512K ROMS. +#define Z80_VIRTUAL_RAM_SIZE (65536 * 32) // Sized to maximum Kernel contiguous allocation size, 2M. +#define Z80_MEMORY_PAGE_SIZE 16 +#define MAX_SCREEN_WIDTH 132 // Maximum terminal screen width for memory dump output. +#define MAX_VIRTUAL_DEVICES 5 // Maximum number of allowed virtual devices. +#define DEVICE_NAME "z80drv" +#define CLASS_NAME "mogu" + +// Memory and IO page types. Used to create a memory page which maps type of address space to real address space on host or virtual memory. +#define MEMORY_TYPE_VIRTUAL_MASK 0x00FFFFFF +#define MEMORY_TYPE_REAL_MASK 0x0000FFFF +#define IO_TYPE_MASK 0x0000FFFF +#define MEMORY_TYPE_INHIBIT 0x00000000 +#define MEMORY_TYPE_PHYSICAL_RAM 0x80000000 +#define MEMORY_TYPE_PHYSICAL_ROM 0x40000000 +#define MEMORY_TYPE_PHYSICAL_VRAM 0x20000000 +#define MEMORY_TYPE_PHYSICAL_HW 0x10000000 +#define MEMORY_TYPE_VIRTUAL_RAM 0x08000000 +#define MEMORY_TYPE_VIRTUAL_ROM 0x04000000 +#define MEMORY_TYPE_VIRTUAL_HW 0x02000000 +#define IO_TYPE_PHYSICAL_HW 0x80000000 +#define IO_TYPE_VIRTUAL_HW 0x40000000 + + +// Approximate governor delays to regulate emulated CPU speed. +// MZ-700 +#if(TARGET_HOST_MZ700 == 1) +#define INSTRUCTION_DELAY_ROM_3_54MHZ 253 +#define INSTRUCTION_DELAY_ROM_7MHZ 126 +#define INSTRUCTION_DELAY_ROM_14MHZ 63 +#define INSTRUCTION_DELAY_ROM_28MHZ 32 +#define INSTRUCTION_DELAY_ROM_56MHZ 16 +#define INSTRUCTION_DELAY_ROM_112MHZ 8 +#define INSTRUCTION_DELAY_ROM_224MHZ 4 +#define INSTRUCTION_DELAY_ROM_448MHZ 1 +#define INSTRUCTION_DELAY_RAM_3_54MHZ 253 +#define INSTRUCTION_DELAY_RAM_7MHZ 126 +#define INSTRUCTION_DELAY_RAM_14MHZ 63 +#define INSTRUCTION_DELAY_RAM_28MHZ 32 +#define INSTRUCTION_DELAY_RAM_56MHZ 16 +#define INSTRUCTION_DELAY_RAM_112MHZ 8 +#define INSTRUCTION_DELAY_RAM_224MHZ 4 +#define INSTRUCTION_DELAY_RAM_448MHZ 1 + +enum Z80_INSTRUCTION_DELAY { + ROM_DELAY_NORMAL = INSTRUCTION_DELAY_ROM_3_54MHZ, + ROM_DELAY_X2 = INSTRUCTION_DELAY_ROM_7MHZ, + ROM_DELAY_X4 = INSTRUCTION_DELAY_ROM_14MHZ, + ROM_DELAY_X8 = INSTRUCTION_DELAY_ROM_28MHZ, + ROM_DELAY_X16 = INSTRUCTION_DELAY_ROM_56MHZ, + ROM_DELAY_X32 = INSTRUCTION_DELAY_ROM_112MHZ, + ROM_DELAY_X64 = INSTRUCTION_DELAY_ROM_224MHZ, + ROM_DELAY_X128 = INSTRUCTION_DELAY_ROM_448MHZ, + RAM_DELAY_NORMAL = INSTRUCTION_DELAY_RAM_3_54MHZ, + RAM_DELAY_X2 = INSTRUCTION_DELAY_RAM_7MHZ, + RAM_DELAY_X4 = INSTRUCTION_DELAY_RAM_14MHZ, + RAM_DELAY_X8 = INSTRUCTION_DELAY_RAM_28MHZ, + RAM_DELAY_X16 = INSTRUCTION_DELAY_RAM_56MHZ, + RAM_DELAY_X32 = INSTRUCTION_DELAY_RAM_112MHZ, + RAM_DELAY_X64 = INSTRUCTION_DELAY_RAM_224MHZ, + RAM_DELAY_X128 = INSTRUCTION_DELAY_RAM_448MHZ +}; +#endif + +// MZ-2000 +#if(TARGET_HOST_MZ2000 == 1) +#define INSTRUCTION_DELAY_ROM_4MHZ 243 +#define INSTRUCTION_DELAY_ROM_8MHZ 122 +#define INSTRUCTION_DELAY_ROM_16MHZ 61 +#define INSTRUCTION_DELAY_ROM_32MHZ 30 +#define INSTRUCTION_DELAY_ROM_64MHZ 15 +#define INSTRUCTION_DELAY_ROM_128MHZ 7 +#define INSTRUCTION_DELAY_ROM_256MHZ 3 +#define INSTRUCTION_DELAY_ROM_512MHZ 1 +#define INSTRUCTION_DELAY_RAM_4MHZ 218 +#define INSTRUCTION_DELAY_RAM_8MHZ 112 +#define INSTRUCTION_DELAY_RAM_16MHZ 56 +#define INSTRUCTION_DELAY_RAM_32MHZ 28 +#define INSTRUCTION_DELAY_RAM_64MHZ 14 +#define INSTRUCTION_DELAY_RAM_128MHZ 7 +#define INSTRUCTION_DELAY_RAM_256MHZ 3 +#define INSTRUCTION_DELAY_RAM_512MHZ 1 + +enum Z80_INSTRUCTION_DELAY { + ROM_DELAY_NORMAL = INSTRUCTION_DELAY_ROM_4MHZ, + ROM_DELAY_X2 = INSTRUCTION_DELAY_ROM_8MHZ, + ROM_DELAY_X4 = INSTRUCTION_DELAY_ROM_16MHZ, + ROM_DELAY_X8 = INSTRUCTION_DELAY_ROM_32MHZ, + ROM_DELAY_X16 = INSTRUCTION_DELAY_ROM_64MHZ, + ROM_DELAY_X32 = INSTRUCTION_DELAY_ROM_128MHZ, + ROM_DELAY_X64 = INSTRUCTION_DELAY_ROM_256MHZ, + ROM_DELAY_X128 = INSTRUCTION_DELAY_ROM_512MHZ, + RAM_DELAY_NORMAL = INSTRUCTION_DELAY_RAM_4MHZ, + RAM_DELAY_X2 = INSTRUCTION_DELAY_RAM_8MHZ, + RAM_DELAY_X4 = INSTRUCTION_DELAY_RAM_16MHZ, + RAM_DELAY_X8 = INSTRUCTION_DELAY_RAM_32MHZ, + RAM_DELAY_X16 = INSTRUCTION_DELAY_RAM_64MHZ, + RAM_DELAY_X32 = INSTRUCTION_DELAY_RAM_128MHZ, + RAM_DELAY_X64 = INSTRUCTION_DELAY_RAM_256MHZ, + RAM_DELAY_X128 = INSTRUCTION_DELAY_RAM_512MHZ, +}; +#endif + +// MZ-80A - These values are dependent on the CPU Freq of the SSD202. Values are for 1.2GHz, in brackets for 1.0GHz +#if(TARGET_HOST_MZ80A == 1) +#define INSTRUCTION_DELAY_ROM_2MHZ 436 // (420) +#define INSTRUCTION_DELAY_ROM_4MHZ 218 +#define INSTRUCTION_DELAY_ROM_8MHZ 109 +#define INSTRUCTION_DELAY_ROM_16MHZ 54 +#define INSTRUCTION_DELAY_ROM_32MHZ 27 +#define INSTRUCTION_DELAY_ROM_64MHZ 14 +#define INSTRUCTION_DELAY_ROM_128MHZ 7 +#define INSTRUCTION_DELAY_ROM_256MHZ 3 +#define INSTRUCTION_DELAY_RAM_2MHZ 420 +#define INSTRUCTION_DELAY_RAM_4MHZ 210 +#define INSTRUCTION_DELAY_RAM_8MHZ 105 +#define INSTRUCTION_DELAY_RAM_16MHZ 52 +#define INSTRUCTION_DELAY_RAM_32MHZ 26 +#define INSTRUCTION_DELAY_RAM_64MHZ 13 +#define INSTRUCTION_DELAY_RAM_128MHZ 7 +#define INSTRUCTION_DELAY_RAM_256MHZ 3 + +enum Z80_INSTRUCTION_DELAY { + ROM_DELAY_NORMAL = INSTRUCTION_DELAY_ROM_2MHZ, + ROM_DELAY_X2 = INSTRUCTION_DELAY_ROM_4MHZ, + ROM_DELAY_X4 = INSTRUCTION_DELAY_ROM_8MHZ, + ROM_DELAY_X8 = INSTRUCTION_DELAY_ROM_16MHZ, + ROM_DELAY_X16 = INSTRUCTION_DELAY_ROM_32MHZ, + ROM_DELAY_X32 = INSTRUCTION_DELAY_ROM_64MHZ, + ROM_DELAY_X64 = INSTRUCTION_DELAY_ROM_128MHZ, + ROM_DELAY_X128 = INSTRUCTION_DELAY_ROM_256MHZ, + RAM_DELAY_NORMAL = INSTRUCTION_DELAY_RAM_2MHZ, + RAM_DELAY_X2 = INSTRUCTION_DELAY_RAM_4MHZ, + RAM_DELAY_X4 = INSTRUCTION_DELAY_RAM_8MHZ, + RAM_DELAY_X8 = INSTRUCTION_DELAY_RAM_16MHZ, + RAM_DELAY_X16 = INSTRUCTION_DELAY_RAM_32MHZ, + RAM_DELAY_X32 = INSTRUCTION_DELAY_RAM_64MHZ, + RAM_DELAY_X64 = INSTRUCTION_DELAY_RAM_128MHZ, + RAM_DELAY_X128 = INSTRUCTION_DELAY_RAM_256MHZ, +}; +#endif + +// IOCTL commands. Passed from user space using the IOCTL method to command the driver to perform an action. +#define IOCTL_CMD_Z80_STOP 's' +#define IOCTL_CMD_Z80_START 'S' +#define IOCTL_CMD_Z80_PAUSE 'P' +#define IOCTL_CMD_Z80_RESET 'R' +#define IOCTL_CMD_Z80_CONTINUE 'C' +#define IOCTL_CMD_USE_HOST_RAM 'x' +#define IOCTL_CMD_USE_VIRTUAL_RAM 'X' +#define IOCTL_CMD_DUMP_MEMORY 'M' +#define IOCTL_CMD_Z80_CPU_FREQ 'F' +#define IOCTL_CMD_ADD_DEVICE 'A' +#define IOCTL_CMD_DEL_DEVICE 'D' +#define IOCTL_CMD_CPLD_CMD 'z' +#define IOCTL_CMD_SEND _IOW('c', 'c', int32_t *) +#define IOCTL_CMD_SETPC _IOW('p', 'p', int32_t *) +#define IOCTL_CMD_SYNC_TO_HOST_RAM 'V' +#define IOCTL_CMD_SPI_TEST '1' +#define IOCTL_CMD_PRL_TEST '2' +#define IOCTL_CMD_Z80_MEMTEST '3' + + + +// Chip Select map MZ80K-MZ700. +// +// 0000 - 0FFF = CS_ROMni : R/W : MZ80K/A/700 = Monitor ROM or RAM (MZ80A rom swap) +// 1000 - CFFF = CS_RAMni : R/W : MZ80K/A/700 = RAM +// C000 - CFFF = CS_ROMni : R/W : MZ80A = Monitor ROM (MZ80A rom swap) +// D000 - D7FF = CS_VRAMni : R/W : MZ80K/A/700 = VRAM +// D800 - DFFF = CS_VRAMni : R/W : MZ700 = Colour VRAM (MZ700) +// E000 - E003 = CS_8255n : R/W : MZ80K/A/700 = 8255 +// E004 - E007 = CS_8254n : R/W : MZ80K/A/700 = 8254 +// E008 - E00B = CS_LS367n : R/W : MZ80K/A/700 = LS367 +// E00C - E00F = CS_ESWPn : R : MZ80A = Memory Swap (MZ80A) +// E010 - E013 = CS_ESWPn : R : MZ80A = Reset Memory Swap (MZ80A) +// E014 = CS_E5n : R/W : MZ80A/700 = Normal CRT display (in Video Controller) +// E015 = CS_E6n : R/W : MZ80A/700 = Reverse CRT display (in Video Controller) +// E200 - E2FF = : R/W : MZ80A/700 = VRAM roll up/roll down. +// E800 - EFFF = : R/W : MZ80K/A/700 = User ROM socket or DD Eprom (MZ700) +// F000 - F7FF = : R/W : MZ80K/A/700 = Floppy Disk interface. +// F800 - FFFF = : R/W : MZ80K/A/700 = Floppy Disk interface. +// +// Chip Select map MZ800 +// +// FC - FF = CS_PIOn : R/W : MZ800/MZ1500 = Z80 PIO Printer Interface +// F2 = CS_PSG0n : W : MZ800/MZ1500 = Programable Sound Generator, MZ-800 = Mono, MZ-1500 = Left Channel +// F3 = CS_PSG1n : W : MZ1500 = Programable Sound Generator, MZ-1500 = Right Channel +// E9 = CS_PSG(X)n: W : MZ1500 = Simultaneous write to both PSG's. +// F0 - F1 = CS_JOYSTK : R : MZ800 = Joystick 1 and 2 +// CC = CS_GWF : W : MZ800 = CRTC GWF Write format Register +// CD = CS_GRF : W : MZ800 = CRTC GRF Read format Register +// CE = CS_GDMD : W : MZ800 = CRTC GDMD Mode Register +// CF = CS_GCRTC : W : MZ800 = CRTC GCRTC Control Register +// D4 - D7 = CS +// D000 - DFFF + +// MZ700/MZ800 memory mode switch? +// +// MZ-700 MZ-800 +// |0000:0FFF|1000:1FFF|1000:CFFF|C000:CFFF|D000:FFFF |0000:7FFF|1000:1FFF|2000:7FFF|8000:BFFF|C000:CFFF|C000:DFFF|E000:FFFF +// -------------------------------------------------- ---------------------------------------------------------------------- +// OUT 0xE0 = |DRAM | | | | |DRAM | | | | | | +// OUT 0xE1 = | | | | |DRAM | | | | | | |DRAM +// OUT 0xE2 = |MONITOR | | | | |MONITOR | | | | | | +// OUT 0xE3 = | | | | |Memory Mapped I/O | | | | | | |Upper MONITOR ROM +// OUT 0xE4 = |MONITOR | |DRAM | |Memory Mapped I/O |MONITOR |CGROM |DRAM |VRAM | |DRAM |Upper MONITOR ROM +// OUT 0xE5 = | | | | |Inhibit | | | | | | |Inhibit +// OUT 0xE6 = | | | | | | | | | | | | +// IN 0xE0 = | |CGROM* | |VRAM* | | |CGROM | |VRAM | | | +// IN 0xE1 = | |DRAM | |DRAM | | | | |DRAM | | | +// +// = Return to the state prior to the complimentary command being invoked. +// * = MZ-800 host only. + +// Macros to lookup and test to see if a given memory block or IO byte is of a given type. Also macros to read/write to the memory block and IO byte. +#define MEMORY_BLOCK_GRANULARITY 0x800 +#define MEMORY_BLOCK_SLOTS (0x10000 / MEMORY_BLOCK_GRANULARITY) +#define MEMORY_BLOCK_MASK (0x10000 - MEMORY_BLOCK_GRANULARITY) +#define MEMORY_BLOCK_SHIFT 11 +#define getPageData(a) (Z80Ctrl->page[(a & 0xF800) >> MEMORY_BLOCK_SHIFT]) +#define getIOPageData(a) (Z80Ctrl->iopage[(a & 0xFFFF]) +#define getPageType(a, mask) (getPageData(a) & mask) +#define getPageAddr(a, mask) ((getPageData(a) & mask) + (a & (MEMORY_BLOCK_GRANULARITY-1))) +#define getIOPageType(a, mask) (getIOPageData(a) & mask) +#define getIOPageAddr(a, mask) (getIOPageData(a) & mask) +#define realAddress(a) (Z80Ctrl->page[getPageAddr(a, MEMORY_TYPE_REAL_MASK)]) +#define realPort(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_MASK) +#define isPhysicalRAM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_RAM)) +#define isPhysicalVRAM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_VRAM)) +#define isPhysicalROM(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_ROM)) +#define isPhysicalMemory(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_ROM | MEMORY_TYPE_PHYSICAL_RAM | MEMORY_TYPE_PHYSICAL_VRAM))]) +#define isPhysicalHW(a) (getPageType(a, MEMORY_TYPE_PHYSICAL_HW)) +#define isPhysical(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_HW | MEMORY_TYPE_PHYSICAL_ROM | MEMORY_TYPE_PHYSICAL_RAM | MEMORY_TYPE_PHYSICAL_VRAM))) +#define isPhysicalIO(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_PHYSICAL_HW) +#define isVirtualRAM(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_RAM)) +#define isVirtualROM(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_ROM)) +#define isVirtualMemory(a) (getPageType(a, (MEMORY_TYPE_VIRTUAL_ROM | MEMORY_TYPE_VIRTUAL_RAM))) +#define isVirtualHW(a) (getPageType(a, MEMORY_TYPE_VIRTUAL_HW)) +#define isVirtualIO(a) (Z80Ctrl->iopage[a & 0xFFFF] & IO_TYPE_VIRTUAL_HW) +#define isVirtualDevice(a, d) (Z80Ctrl->iopage[a & 0xFFFF] & d) +#define isHW(a) (getPageType(a, (MEMORY_TYPE_PHYSICAL_HW | MEMORY_TYPE_VIRTUAL_HW))) +#define readVirtualRAM(a) (Z80Ctrl->ram[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) ]) +#define readVirtualROM(a) (Z80Ctrl->rom[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) ]) +#define writeVirtualRAM(a, d) { Z80Ctrl->ram[ getPageAddr(a, MEMORY_TYPE_VIRTUAL_MASK) ] = d; } +#define setMemoryType(_block_,_type_,_addr_) { Z80Ctrl->page[_block_] = _type_ | _addr_; } +#define backupMemoryType(_block_) { Z80Ctrl->shadowPage[_block_] = Z80Ctrl->page[_block_]; } +#define restoreMemoryType(_block_) { Z80Ctrl->page[_block_] = Z80Ctrl->shadowPage[_block_]; } + +#define IO_ADDR_E0 0xE0 +#define IO_ADDR_E1 0xE1 +#define IO_ADDR_E2 0xE2 +#define IO_ADDR_E3 0xE3 +#define IO_ADDR_E4 0xE4 +#define IO_ADDR_E5 0xE5 +#define IO_ADDR_E6 0xE6 +#define IO_ADDR_E7 0xE7 +#define IO_ADDR_E8 0xE8 +#define IO_ADDR_E9 0xE9 +#define IO_ADDR_EA 0xEA +#define IO_ADDR_EB 0xEB + + +enum Z80_RUN_STATES { + Z80_STOP = 0x00, + Z80_STOPPED = 0x01, + Z80_PAUSE = 0x02, + Z80_PAUSED = 0x03, + Z80_CONTINUE = 0x04, + Z80_RUNNING = 0x05, +}; +enum Z80_MEMORY_PROFILE { + USE_PHYSICAL_RAM = 0x00, + USE_VIRTUAL_RAM = 0x01 +}; +enum VIRTUAL_DEVICE { + VIRTUAL_DEVICE_NONE = 0x00000000, + VIRTUAL_DEVICE_RFS = 0x02000000, + VIRTUAL_DEVICE_TZPU = 0x01000000 +}; + +typedef struct { + // Main RAM/ROM memory, linear but indexed as though it were banks in 1K pages. + uint8_t *ram; + uint8_t *rom; + + // Compatibility mode, enables virtual mapping and virtual hardware to make the Z80 with the underlying host appear + // as a host equipped with a specific hardware add on. + // The devices are stored in an array for ease of reference and lookup in the driver and ctrl program, in actual + // use they are a bit map for performance as scanning an array is time consuming. + // + enum VIRTUAL_DEVICE virtualDevice[MAX_VIRTUAL_DEVICES]; + uint32_t virtualDeviceBitMap; + uint8_t virtualDeviceCnt; + + // Page pointer map. + // + // Each pointer points to a byte or block of bytes in the Z80 Memory frame, 64K Real + Banked. + // This is currently set at a block of size 0x800 per memory pointer for the MZ-700. + // The LSB of the pointer is a direct memory index to a byte or block of bytes, the upper byte of the pointer indicates type of memory space. + // 0x80 - physical host RAM + // 0x40 - physical host ROM + // 0x20 - physical host VRAM + // 0x10 - physical host hardware + // 0x08 - virtual host RAM + // 0x04 - virtual host ROM + // 0x02 - virtual host hardware + // 16bit Input Address -> map -> Pointer to 24bit memory address + type flag. + // -> Pointer+ to 24bit memory address + type flag. + uint32_t page[MEMORY_BLOCK_SLOTS]; + uint32_t shadowPage[MEMORY_BLOCK_SLOTS]; + + // I/O Page map. + // + // This is a map to indicate the use of the I/O page and allow any required remapping. + // <0x8000> - physical host hardware + // <0x4000> - virtual host hardware + // <0x3FFF> - bit map to indicate allocated device. + // 16bit Input Address -> map -> Actual 16bit address to use + type flag. + uint32_t iopage[65536]; + + // Default page mode configured. This value reflects the default page and iotable map. + uint8_t defaultPageMode; + + // Refresh DRAM mode. 1 = Refresh, 0 = No refresh. Only applicable when running code in virtual Kernel RAM. + uint8_t refreshDRAM; + + // Inhibit mode is where certain memory ranges are inhibitted. The memory page is set to inhibit and this flag + // blocks actions which arent allowed during inhibit. + uint8_t inhibitMode; + + // I/O lookahead flags - to overcome SSD202 io slowness. + uint8_t ioReadAhead; + uint8_t ioWriteAhead; + +#if(TARGET_HOST_MZ2000 == 1) + uint8_t lowMemorySwap; +#endif +#if(TARGET_HOST_MZ80A == 1) + // MZ-80A can relocate the lower 4K ROM by swapping RAM at 0xC000. + uint8_t memSwitch; +#endif + + // Keyboard strobe and data. Required to detect hotkey press. + uint8_t keyportStrobe; + uint8_t keyportShiftCtrl; + uint8_t keyportHotKey; + + // Governor is the delay in a 32bit loop per Z80 opcode, used to govern execution speed when using virtual memory. + // This mechanism will eventually be tied into the M/T-state calculation for a more precise delay, but at the moment, + // with the Z80 assigned to an isolated CPU, it allows time sensitive tasks such as the tape recorder to work. + // The lower the value the faster the CPU speed. Two values are present as the optimiser, seeing ROM code not changing + // is quicker than RAM (both are in the same kernel memory) as a pointer calculation needs to be made. + uint32_t cpuGovernorDelayROM; + uint32_t cpuGovernorDelayRAM; +} t_Z80Ctrl; + +// IOCTL structure for passing data from user space to driver to perform commands. +// +struct z80_addr { + uint32_t start; + uint32_t end; + uint32_t size; +}; +struct z80_ctrl { + uint16_t pc; +}; +struct speed { + uint32_t speedMultiplier; +}; +struct virtual_device { + enum VIRTUAL_DEVICE device; +}; +struct cpld_ctrl { + uint32_t cmd; +}; +struct ioctlCmd { + int32_t cmd; + union { + struct z80_addr addr; + struct z80_ctrl z80; + struct speed speed; + struct virtual_device vdev; + struct cpld_ctrl cpld; + }; +}; + +// Prototypes. +void setupMemory(enum Z80_MEMORY_PROFILE); +int thread_z80(void *); + +#endif diff --git a/software/FusionX/src/driver/MZ80A/z80io.c b/software/FusionX/src/driver/MZ80A/z80io.c new file mode 100644 index 000000000..084eeaf91 --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80io.c @@ -0,0 +1,452 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface +// This file contains the methods used in interfacing the SOM to the Z80 socket +// and host hardware via a CPLD. +// Credits: +// Copyright: (c) 2019-2023 Philip Smart +// +// History: Oct 2022 v1.0 - Initial write of the z80 kernel driver software. +// Jan 2023 v1.1 - Numerous new tries at increasing throughput to the CPLD failed. +// Maximum read throughput of an 8bit byte due to the SSD202 GPIO +// structure is approx 2MB/s - or 512K/s for a needed 32bit word. +// Write is slower as you have to clock the data so sticking with SPI. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + +//#include +//#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" + +#include +#include +#include +#include + +//------------------------------------------------------------------------------------------------------------------------------- +// +// User space driver access. +// +//------------------------------------------------------------------------------------------------------------------------------- + + +// Initialise the SOM hardware used to communicate with the z80 socket and host hardware. +// The SOM interfaces to a CPLD which provides voltage level translation and also encapsulates the Z80 timing cycles as recreating +// them within the SOM is much more tricky. +// +// As this is an embedded device and performance/latency are priorities, minimal structured code is used to keep call stack and +// generated code to a mimimum without relying on the optimiser. +int z80io_init(void) +{ + // Locals. + int ret = 0; + + // Initialise GPIO. We call the HAL api to minimise time but for actual bit set/reset and read we go directly to registers to save time, increase throughput and minimise latency. + // Initialise the HAL. + MHal_GPIO_Init(); + + // Set the pads as GPIO devices. The HAL takes care of allocating and deallocating the padmux resources. + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_0); // Word (16bit) bidirectional bus. Default is read with data set. + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_1); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_2); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_3); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_4); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_5); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_6); + MHal_GPIO_Pad_Set(PAD_Z80IO_IN_DATA_7); + MHal_GPIO_Pad_Set(PAD_Z80IO_HIGH_BYTE); + //MHal_GPIO_Pad_Set(PAD_GPIO8); // SPIO 4wire control lines setup by the spidev driver but controlled directly in this driver. + //MHal_GPIO_Pad_Set(PAD_GPIO9); + //MHal_GPIO_Pad_Set(PAD_GPIO10); + //MHal_GPIO_Pad_Set(PAD_GPIO11); + MHal_GPIO_Pad_Set(PAD_Z80IO_READY); + MHal_GPIO_Pad_Set(PAD_Z80IO_LTSTATE); + MHal_GPIO_Pad_Set(PAD_Z80IO_BUSRQ); + MHal_GPIO_Pad_Set(PAD_Z80IO_BUSACK); + MHal_GPIO_Pad_Set(PAD_Z80IO_INT); + MHal_GPIO_Pad_Set(PAD_Z80IO_NMI); + MHal_GPIO_Pad_Set(PAD_Z80IO_WAIT); + MHal_GPIO_Pad_Set(PAD_Z80IO_RESET); + MHal_GPIO_Pad_Set(PAD_Z80IO_RSV1); +#ifdef NOTNEEDED + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_0); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_1); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_2); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_3); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_4); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_5); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_6); + MHal_GPIO_Pad_Set(PAD_Z80IO_OUT_DATA_7); + MHal_GPIO_Pad_Set(PAD_Z80IO_WRITE); +#endif + + // Set required input pads. + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_0); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_1); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_2); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_3); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_4); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_5); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_6); + MHal_GPIO_Pad_Odn(PAD_Z80IO_IN_DATA_7); + MHal_GPIO_Pad_Odn(PAD_Z80IO_READY); + MHal_GPIO_Pad_Odn(PAD_Z80IO_LTSTATE); + MHal_GPIO_Pad_Odn(PAD_Z80IO_BUSRQ); + MHal_GPIO_Pad_Odn(PAD_Z80IO_BUSACK); + MHal_GPIO_Pad_Odn(PAD_Z80IO_INT); + MHal_GPIO_Pad_Odn(PAD_Z80IO_NMI); + MHal_GPIO_Pad_Odn(PAD_Z80IO_WAIT); + MHal_GPIO_Pad_Odn(PAD_Z80IO_RESET); + MHal_GPIO_Pad_Odn(PAD_Z80IO_RSV1); + + // Set required output pads. +#ifdef NOTNEEDED + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_0); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_1); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_2); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_3); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_4); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_5); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_6); + MHal_GPIO_Pad_Oen(PAD_Z80IO_OUT_DATA_7); + MHal_GPIO_Pad_Oen(PAD_Z80IO_WRITE); + MHal_GPIO_Pull_High(PAD_Z80IO_WRITE); +#endif + + // Control signals. + MHal_GPIO_Pad_Oen(PAD_Z80IO_HIGH_BYTE); + MHal_GPIO_Pull_High(PAD_Z80IO_HIGH_BYTE); + + // Setup the MSPI0 device. + // + // Setup control, interrupts are not used. + MSPI_WRITE(MSPI_CTRL_OFFSET, MSPI_CPU_CLOCK_1_2 | MSPI_CTRL_CPOL_LOW | MSPI_CTRL_CPHA_HIGH | MSPI_CTRL_RESET | MSPI_CTRL_ENABLE_SPI); + + // Setup LSB First mode. + MSPI_WRITE(MSPI_LSB_FIRST_OFFSET, 0x0); + + // Setup clock. + CLK_WRITE(MSPI0_CLK_CFG, 0x1100) + + // Setup the frame size (all buffers to 8bits). + MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET, 0xfff); + MSPI_WRITE(MSPI_FRAME_WBIT_OFFSET+1, 0xfff); + MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET, 0xfff); + MSPI_WRITE(MSPI_FRAME_RBIT_OFFSET+1, 0xfff); + + // Setup Chip Selects to inactive. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Switch Video and Audio to host. + z80io_SPI_Send16(0x00f0, NULL); + + return ret; +} + + +//-------------------------------------------------------- +// Parallel bus Methods. +//-------------------------------------------------------- + +// Methods to read data from the parallel bus. +// The CPLD returns status and Z80 data on the 8bit bus as it is marginally quicker than retrieving it over the SPI bus. +// +inline uint8_t z80io_PRL_Read8(uint8_t dataFlag) +{ + // Locals. + volatile uint8_t result = 0; + + // Byte according to flag. + if(dataFlag) + SET_CPLD_READ_DATA() + else + SET_CPLD_READ_STATUS() + + // Read the input registers and set value accordingly. + result = READ_CPLD_DATA_IN(); + + // Return 16bit value read from CPLD. + return(result); +} + +inline uint8_t z80io_PRL_Read(void) +{ + // Locals. + volatile uint8_t result = 0; + volatile uint32_t b7, b6, b5, b4, b3, b2, b1, b0; + + // Read the input registers and set value accordingly. Quicker to read registers and then apply shift/logical operators. The I/O Bus is very slow! + b7 = READ_LONG(((gRIUBaseAddr) + (((PAD_Z80IO_IN_DATA_7_ADDR) & ~1)<<1) + (PAD_Z80IO_IN_DATA_7_ADDR & 1))); + b6 = READ_LONG(((gRIUBaseAddr) + (((PAD_Z80IO_IN_DATA_6_ADDR) & ~1)<<1) + (PAD_Z80IO_IN_DATA_6_ADDR & 1))); + b5 = READ_LONG(((gRIUBaseAddr) + (((PAD_Z80IO_IN_DATA_5_ADDR) & ~1)<<1) + (PAD_Z80IO_IN_DATA_5_ADDR & 1))); + b4 = READ_LONG(((gRIUBaseAddr) + (((PAD_Z80IO_IN_DATA_4_ADDR) & ~1)<<1) + (PAD_Z80IO_IN_DATA_4_ADDR & 1))); + b3 = READ_LONG(((gRIUBaseAddr) + (((PAD_Z80IO_IN_DATA_3_ADDR) & ~1)<<1) + (PAD_Z80IO_IN_DATA_3_ADDR & 1))); + b2 = READ_LONG(((gRIUBaseAddr) + (((PAD_Z80IO_IN_DATA_2_ADDR) & ~1)<<1) + (PAD_Z80IO_IN_DATA_2_ADDR & 1))); + b1 = READ_LONG(((gRIUBaseAddr) + (((PAD_Z80IO_IN_DATA_1_ADDR) & ~1)<<1) + (PAD_Z80IO_IN_DATA_1_ADDR & 1))); + b0 = READ_LONG(((gRIUBaseAddr) + (((PAD_Z80IO_IN_DATA_0_ADDR) & ~1)<<1) + (PAD_Z80IO_IN_DATA_0_ADDR & 1))); + result = (b7 & 0x1) << 7 | (b6 & 0x1) << 6 | (b5 & 0x1) << 5 | (b4 & 0x1) << 4 | (b3 & 0x1) << 3 | (b2 & 0x1) << 2 | (b1 & 0x1) << 1 | (b0 & 0x1); + + // Return 16bit value read from CPLD. + return(result); +} + +inline uint16_t z80io_PRL_Read16(void) +{ + // Locals. + volatile uint16_t result = 0; + + // Low byte first. + CLEAR_CPLD_HIGH_BYTE(); + + // Read the input registers and set value accordingly. + result = (uint16_t)READ_CPLD_DATA_IN(); + + // High byte next. + SET_CPLD_HIGH_BYTE(); + + // Read the input registers and set value accordingly. + result |= (uint16_t)(READ_CPLD_DATA_IN() << 8); + + // Return 16bit value read from CPLD. + return(result); +} + + +// Parallel Bus methods were tried and tested but due to the GPIO bits being controlled by individual registers per bit, the setup time was longer +// than the transmission time of SPI. These methods are thus deprecated and a fusion of SPI and 8bit parallel is now used. +#ifdef NOTNEEDED +inline uint8_t z80io_PRL_Send8(uint8_t txData) +{ + // Locals. + // + + // Low byte only. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE].r_out) &= (~gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out); + + // Setup data. + if(txData & 0x0080) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x0040) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x0020) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x0010) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0008) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0004) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0002) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0001) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + return(0); +} + +inline uint8_t z80io_PRL_Send16(uint16_t txData) +{ + // Locals. + // + + // Low byte first. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE].r_out) &= (~gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out); + + // Setup data. + if(txData & 0x0080) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x0040) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x0020) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x0010) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0008) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0004) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0002) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0001) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + // High byte next. + MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + + // Setup high byte. + if(txData & 0x8000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_7].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_7].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_7].m_out); } + if(txData & 0x4000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_6].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_6].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_6].m_out); } + if(txData & 0x2000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_5].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_5].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_5].m_out); } + if(txData & 0x1000) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_4].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_4].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_4].m_out); } + if(txData & 0x0800) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_3].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_3].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_3].m_out); } + if(txData & 0x0400) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_2].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_2].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_2].m_out); } + if(txData & 0x0200) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_1].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_1].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_1].m_out); } + if(txData & 0x0100) { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) |= gpio_table[PAD_Z80IO_OUT_DATA_0].m_out; } else { MHal_RIU_REG(gpio_table[PAD_Z80IO_OUT_DATA_0].r_out) &= (~gpio_table[PAD_Z80IO_OUT_DATA_0].m_out); } + + // Clock data. + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) &= (~gpio_table[PAD_Z80IO_WRITE ].m_out); + MHal_RIU_REG(gpio_table[PAD_Z80IO_WRITE].r_out) |= gpio_table[PAD_Z80IO_WRITE ].m_out; + + return(0); +} +#endif + + +//-------------------------------------------------------- +// SPI Methods. +//-------------------------------------------------------- + +// Methods to send 8,16 or 32 bits. Each method is seperate to minimise logic and execution time, 8bit being most sensitive. +// Macros have also been defined for inline inclusion which dont read back the response data. +// +uint8_t z80io_SPI_Send8(uint8_t txData, uint8_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)txData); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 1); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = (uint8_t)MSPI_READ(MSPI_FULL_DEPLUX_RD00); + + // Done. + return(timeout == 0); +} +uint8_t z80io_SPI_Send16(uint16_t txData, uint16_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, txData); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 2); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = MSPI_READ(MSPI_FULL_DEPLUX_RD00); + + // Done. + return(timeout == 0); +} +uint8_t z80io_SPI_Send32(uint32_t txData, uint32_t *rxData) +{ + // Locals. + uint32_t timeout = MAX_CHECK_CNT; + + // Insert data into write buffers. + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)txData); + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET+1, (uint16_t)(txData >> 16)); + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 4); + + // Enable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); + + // Send. + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); + + // Wait for completion. + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) + { + if(--timeout == 0) + break; + } + + // Disable SPI select. + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); + + // Clear flag. + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); + + // Fetch data. + if(rxData != NULL) *rxData = (uint32_t)(MSPI_READ(MSPI_FULL_DEPLUX_RD00) | (MSPI_READ(MSPI_FULL_DEPLUX_RD02) << 16)); + + // Done. + return(timeout == 0); +} + +//-------------------------------------------------------- +// Test Methods. +//-------------------------------------------------------- +#ifdef INCLUDE_TEST_METHODS +#include "z80io_test.c" +#else +uint8_t z80io_Z80_TestMemory(void) +{ + pr_info("Z80 Test Memory functionality not built-in.\n"); + return(0); +} +uint8_t z80io_SPI_Test(void) +{ + pr_info("SPI Test functionality not built-in.\n"); + return(0); +} +uint8_t z80io_PRL_Test(void) +{ + pr_info("Parallel Bus Test functionality not built-in.\n"); + return(0); +} +#endif diff --git a/software/FusionX/src/driver/MZ80A/z80io.h b/software/FusionX/src/driver/MZ80A/z80io.h new file mode 100755 index 000000000..641cea5ed --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80io.h @@ -0,0 +1,507 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface +// This file contains the declarations used in interfacing the SOM to the Z80 socket +// and host hardware via a CPLD. +// Credits: +// Copyright: (c) 2019-2023 Philip Smart +// +// History: Oct 2022 v1.0 - Initial write of the z80 kernel driver software. +// Jan 2023 v1.1 - Numerous new tries at increasing throughput to the CPLD failed. +// Maximum read throughput of an 8bit byte due to the SSD202 GPIO +// structure is approx 2MB/s - or 512K/s for a needed 32bit word. +// Write is slower as you have to clock the data so sticking with SPI. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80IO_H +#define Z80IO_H + +#ifdef __cplusplus + extern "C" { +#endif + +// Definitions to control compilation. +#define INCLUDE_TEST_METHODS 1 + +// CPLD Commands. +#define CPLD_CMD_FETCH_ADDR 0x10 +#define CPLD_CMD_FETCH_ADDR_P1 0x11 +#define CPLD_CMD_FETCH_ADDR_P2 0x12 +#define CPLD_CMD_FETCH_ADDR_P3 0x13 +#define CPLD_CMD_FETCH_ADDR_P4 0x14 +#define CPLD_CMD_FETCH_ADDR_P5 0x15 +#define CPLD_CMD_FETCH_ADDR_P6 0x16 +#define CPLD_CMD_FETCH_ADDR_P7 0x17 +#define CPLD_CMD_WRITE_ADDR 0x18 +#define CPLD_CMD_WRITE_ADDR_P1 0x19 +#define CPLD_CMD_WRITE_ADDR_P2 0x1A +#define CPLD_CMD_WRITE_ADDR_P3 0x1B +#define CPLD_CMD_WRITE_ADDR_P4 0x1C +#define CPLD_CMD_WRITE_ADDR_P5 0x1D +#define CPLD_CMD_WRITE_ADDR_P6 0x1E +#define CPLD_CMD_WRITE_ADDR_P7 0x1F +#define CPLD_CMD_READ_ADDR 0x20 +#define CPLD_CMD_READ_ADDR_P1 0x21 +#define CPLD_CMD_READ_ADDR_P2 0x22 +#define CPLD_CMD_READ_ADDR_P3 0x23 +#define CPLD_CMD_READ_ADDR_P4 0x24 +#define CPLD_CMD_READ_ADDR_P5 0x25 +#define CPLD_CMD_READ_ADDR_P6 0x26 +#define CPLD_CMD_READ_ADDR_P7 0x27 +#define CPLD_CMD_WRITEIO_ADDR 0x28 +#define CPLD_CMD_WRITEIO_ADDR_P1 0x29 +#define CPLD_CMD_WRITEIO_ADDR_P2 0x2A +#define CPLD_CMD_WRITEIO_ADDR_P3 0x2B +#define CPLD_CMD_WRITEIO_ADDR_P4 0x2C +#define CPLD_CMD_WRITEIO_ADDR_P5 0x2D +#define CPLD_CMD_WRITEIO_ADDR_P6 0x2E +#define CPLD_CMD_WRITEIO_ADDR_P7 0x2F +#define CPLD_CMD_READIO_ADDR 0x30 +#define CPLD_CMD_READIO_ADDR_P1 0x31 +#define CPLD_CMD_READIO_ADDR_P2 0x32 +#define CPLD_CMD_READIO_ADDR_P3 0x33 +#define CPLD_CMD_READIO_ADDR_P4 0x34 +#define CPLD_CMD_READIO_ADDR_P5 0x35 +#define CPLD_CMD_READIO_ADDR_P6 0x36 +#define CPLD_CMD_READIO_ADDR_P7 0x37 +#define CPLD_CMD_HALT 0x50 +#define CPLD_CMD_REFRESH 0x51 +#define CPLD_CMD_SET_SIGROUP1 0xF0 +#define CPLD_CMD_SET_AUTO_REFRESH 0xF1 +#define CPLD_CMD_CLEAR_AUTO_REFRESH 0xF2 +#define CPLD_CMD_SET_SPI_LOOPBACK 0xFE +#define CPLD_CMD_NOP1 0x00 +#define CPLD_CMD_NOP2 0xFF + + +// Pad numbers for using the MHal GPIO library. +#define PAD_Z80IO_IN_DATA_0 PAD_GPIO0 +#define PAD_Z80IO_IN_DATA_1 PAD_GPIO1 +#define PAD_Z80IO_IN_DATA_2 PAD_GPIO2 +#define PAD_Z80IO_IN_DATA_3 PAD_GPIO3 +#define PAD_Z80IO_IN_DATA_4 PAD_GPIO4 +#define PAD_Z80IO_IN_DATA_5 PAD_GPIO5 +#define PAD_Z80IO_IN_DATA_6 PAD_GPIO6 +#define PAD_Z80IO_IN_DATA_7 PAD_GPIO7 +#define PAD_SPIO_0 PAD_GPIO8 +#define PAD_SPIO_1 PAD_GPIO9 +#define PAD_SPIO_2 PAD_GPIO10 +#define PAD_SPIO_3 PAD_GPIO11 +#define PAD_Z80IO_HIGH_BYTE PAD_SAR_GPIO2 // Byte requiured, 0 = Low Byte, 1 = High Byte. +#define PAD_Z80IO_READY PAD_GPIO12 +#define PAD_Z80IO_LTSTATE PAD_UART0_RX // GPIO47 +#define PAD_Z80IO_BUSRQ PAD_GPIO13 +#define PAD_Z80IO_BUSACK PAD_GPIO14 +#define PAD_Z80IO_INT PAD_PM_IRIN // IRIN +#define PAD_Z80IO_NMI PAD_UART0_TX // GPIO48 +#define PAD_Z80IO_WAIT PAD_HSYNC_OUT // GPIO85 +#define PAD_Z80IO_RESET PAD_VSYNC_OUT // GPIO86 +#define PAD_Z80IO_RSV1 PAD_SATA_GPIO // GPIO90 + +// Physical register addresses. +#define PAD_Z80IO_IN_DATA_0_ADDR 0x103C00 +#define PAD_Z80IO_IN_DATA_1_ADDR 0x103C02 +#define PAD_Z80IO_IN_DATA_2_ADDR 0x103C04 +#define PAD_Z80IO_IN_DATA_3_ADDR 0x103C06 +#define PAD_Z80IO_IN_DATA_4_ADDR 0x103C08 +#define PAD_Z80IO_IN_DATA_5_ADDR 0x103C0A +#define PAD_Z80IO_IN_DATA_6_ADDR 0x103C0C +#define PAD_Z80IO_IN_DATA_7_ADDR 0x103C0E +#define PAD_SPIO_0_ADDR 0x103C10 +#define PAD_SPIO_1_ADDR 0x103C12 +#define PAD_SPIO_2_ADDR 0x103C14 +#define PAD_SPIO_3_ADDR 0x103C16 +#define PAD_Z80IO_HIGH_BYTE_ADDR 0x1425 +#define PAD_Z80IO_READY_ADDR 0x103C18 +#define PAD_Z80IO_LTSTATE_ADDR 0x103C30 // GPIO47 +#define PAD_Z80IO_BUSRQ_ADDR 0x103C1A +#define PAD_Z80IO_BUSACK_ADDR 0x103C1C +#define PAD_Z80IO_INT_ADDR 0xF28 // IRIN +#define PAD_Z80IO_NMI_ADDR 0x103C32 // GPIO48 +#define PAD_Z80IO_WAIT_ADDR 0x103C80 // GPIO85 +#define PAD_Z80IO_RESET_ADDR 0x103C82 // GPIO86 +#define PAD_Z80IO_RSV1_ADDR 0x103C8A // GPIO90 + +#ifdef NOTNEEDED +#define PAD_Z80IO_OUT_DATA_0 PAD_GPIO12 +#define PAD_Z80IO_OUT_DATA_1 PAD_GPIO13 +#define PAD_Z80IO_OUT_DATA_2 PAD_GPIO14 +#define PAD_Z80IO_OUT_DATA_3 PAD_UART0_RX // GPIO47 +#define PAD_Z80IO_OUT_DATA_4 PAD_UART0_TX // GPIO48 +#define PAD_Z80IO_OUT_DATA_5 PAD_HSYNC_OUT // GPIO85 +#define PAD_Z80IO_OUT_DATA_6 PAD_VSYNC_OUT // GPIO86 +#define PAD_Z80IO_OUT_DATA_7 PAD_SATA_GPIO // GPIO90 +#define PAD_Z80IO_WRITE PAD_PM_IRIN // Write data clock. +#endif + +//------------------------------------------------------------------------------------------------- +// The definitions below come from SigmaStar kernel drivers. No header file exists hence the +// duplication. +//------------------------------------------------------------------------------------------------- + +#define SUPPORT_SPI_1 0 +#define MAX_SUPPORT_BITS 16 + +#define BANK_TO_ADDR32(b) (b<<9) +#define BANK_SIZE 0x200 + +#define MS_BASE_REG_RIU_PA 0x1F000000 +#define gChipBaseAddr 0xFD203C00 +#define gPmSleepBaseAddr 0xFD001C00 +#define gSarBaseAddr 0xFD002800 +#define gRIUBaseAddr 0xFD000000 +#define gMOVDMAAddr 0xFD201600 +#define gClkBaseAddr 0xFD207000 +#define gMspBaseAddr 0xfd222000 + +#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)((gChipBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)((gPmSleepBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)((gSarBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_RIU_REG(addr) (*(volatile U8*)((gRIUBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) + + +#define MSPI0_BANK_ADDR 0x1110 +#define MSPI1_BANK_ADDR 0x1111 +#define CLK__BANK_ADDR 0x1038 +#define CHIPTOP_BANK_ADDR 0x101E +#define MOVDMA_BANK_ADDR 0x100B + +#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000) +#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100) +#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800) +#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) + +//------------------------------------------------------------------------------------------------- +// Hardware Register Capability +//------------------------------------------------------------------------------------------------- +#define MSPI_WRITE_BUF_OFFSET 0x40 +#define MSPI_READ_BUF_OFFSET 0x44 +#define MSPI_WBF_SIZE_OFFSET 0x48 +#define MSPI_RBF_SIZE_OFFSET 0x48 + // read/ write buffer size +#define MSPI_RWSIZE_MASK 0xFF +#define MSPI_RSIZE_BIT_OFFSET 0x8 +#define MAX_READ_BUF_SIZE 0x8 +#define MAX_WRITE_BUF_SIZE 0x8 +// CLK config +#define MSPI_CTRL_OFFSET 0x49 +#define MSPI_CLK_CLOCK_OFFSET 0x49 +#define MSPI_CLK_CLOCK_BIT_OFFSET 0x08 +#define MSPI_CLK_CLOCK_MASK 0xFF +#define MSPI_CLK_PHASE_MASK 0x40 +#define MSPI_CLK_PHASE_BIT_OFFSET 0x06 +#define MSPI_CLK_POLARITY_MASK 0x80 +#define MSPI_CLK_POLARITY_BIT_OFFSET 0x07 +#define MSPI_CLK_PHASE_MAX 0x1 +#define MSPI_CLK_POLARITY_MAX 0x1 +#define MSPI_CLK_CLOCK_MAX 0x7 +#define MSPI_CTRL_CPOL_LOW 0x00 +#define MSPI_CTRL_CPOL_HIGH 0x80 +#define MSPI_CTRL_CPHA_LOW 0x00 +#define MSPI_CTRL_CPHA_HIGH 0x40 +#define MSPI_CTRL_3WIRE 0x10 +#define MSPI_CTRL_INTEN 0x04 +#define MSPI_CTRL_RESET 0x02 +#define MSPI_CTRL_ENABLE_SPI 0x01 +// DC config +#define MSPI_DC_MASK 0xFF +#define MSPI_DC_BIT_OFFSET 0x08 +#define MSPI_DC_TR_START_OFFSET 0x4A +#define MSPI_DC_TRSTART_MAX 0xFF +#define MSPI_DC_TR_END_OFFSET 0x4A +#define MSPI_DC_TREND_MAX 0xFF +#define MSPI_DC_TB_OFFSET 0x4B +#define MSPI_DC_TB_MAX 0xFF +#define MSPI_DC_TRW_OFFSET 0x4B +#define MSPI_DC_TRW_MAX 0xFF +// Frame Config +#define MSPI_FRAME_WBIT_OFFSET 0x4C +#define MSPI_FRAME_RBIT_OFFSET 0x4E +#define MSPI_FRAME_BIT_MAX 0x07 +#define MSPI_FRAME_BIT_MASK 0x07 +#define MSPI_FRAME_BIT_FIELD 0x03 +#define MSPI_LSB_FIRST_OFFSET 0x50 +#define MSPI_TRIGGER_OFFSET 0x5A +#define MSPI_DONE_OFFSET 0x5B +#define MSPI_DONE_CLEAR_OFFSET 0x5C +#define MSPI_CHIP_SELECT_OFFSET 0x5F +#define MSPI_CS1_DISABLE 0x01 +#define MSPI_CS1_ENABLE 0x00 +#define MSPI_CS2_DISABLE 0x02 +#define MSPI_CS2_ENABLE 0x00 +#define MSPI_CS3_DISABLE 0x04 +#define MSPI_CS3_ENABLE 0x00 +#define MSPI_CS4_DISABLE 0x08 +#define MSPI_CS4_ENABLE 0x00 +#define MSPI_CS5_DISABLE 0x10 +#define MSPI_CS5_ENABLE 0x00 +#define MSPI_CS6_DISABLE 0x20 +#define MSPI_CS6_ENABLE 0x00 +#define MSPI_CS7_DISABLE 0x40 +#define MSPI_CS7_ENABLE 0x00 +#define MSPI_CS8_DISABLE 0x80 +#define MSPI_CS8_ENABLE 0x00 + +#define MSPI_FULL_DEPLUX_RD_CNT (0x77) +#define MSPI_FULL_DEPLUX_RD00 (0x78) +#define MSPI_FULL_DEPLUX_RD01 (0x78) +#define MSPI_FULL_DEPLUX_RD02 (0x79) +#define MSPI_FULL_DEPLUX_RD03 (0x79) +#define MSPI_FULL_DEPLUX_RD04 (0x7a) +#define MSPI_FULL_DEPLUX_RD05 (0x7a) +#define MSPI_FULL_DEPLUX_RD06 (0x7b) +#define MSPI_FULL_DEPLUX_RD07 (0x7b) + +#define MSPI_FULL_DEPLUX_RD08 (0x7c) +#define MSPI_FULL_DEPLUX_RD09 (0x7c) +#define MSPI_FULL_DEPLUX_RD10 (0x7d) +#define MSPI_FULL_DEPLUX_RD11 (0x7d) +#define MSPI_FULL_DEPLUX_RD12 (0x7e) +#define MSPI_FULL_DEPLUX_RD13 (0x7e) +#define MSPI_FULL_DEPLUX_RD14 (0x7f) +#define MSPI_FULL_DEPLUX_RD15 (0x7f) + +//chip select bit map +#define MSPI_CHIP_SELECT_MAX 0x07 + +// control bit +#define MSPI_DONE_FLAG 0x01 +#define MSPI_TRIGGER 0x01 +#define MSPI_CLEAR_DONE 0x01 +#define MSPI_INT_ENABLE 0x04 +#define MSPI_RESET 0x02 +#define MSPI_ENABLE 0x01 + +// clk_mspi0 +#define MSPI0_CLK_CFG 0x33 //bit 2 ~bit 3 +#define MSPI0_CLK_108M 0x00 +#define MSPI0_CLK_54M 0x04 +#define MSPI0_CLK_12M 0x08 +#define MSPI0_CLK_MASK 0x0F + +// clk_mspi1 +#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11 +#define MSPI1_CLK_108M 0x0000 +#define MSPI1_CLK_54M 0x0400 +#define MSPI1_CLK_12M 0x0800 +#define MSPI1_CLK_MASK 0x0F00 + +// clk_mspi +#define MSPI_CLK_CFG 0x33 +#define MSPI_SELECT_0 0x0000 +#define MSPI_SELECT_1 0x4000 +#define MSPI_CLK_MASK 0xF000 + +// Clock settings +#define MSPI_CPU_CLOCK_1_2 0x0000 +#define MSPI_CPU_CLOCK_1_4 0x0100 +#define MSPI_CPU_CLOCK_1_8 0x0200 +#define MSPI_CPU_CLOCK_1_16 0x0300 +#define MSPI_CPU_CLOCK_1_32 0x0400 +#define MSPI_CPU_CLOCK_1_64 0x0500 +#define MSPI_CPU_CLOCK_1_128 0x0600 +#define MSPI_CPU_CLOCK_1_256 0x0700 + +//CHITOP 101E mspi mode select +#define MSPI0_MODE 0x0C //bit0~bit1 +#define MSPI0_MODE_MASK 0x07 +#define MSPI1_MODE 0x0C //bit4~bit5 +#define MSPI1_MODE_MASK 0x70 +#define EJTAG_MODE 0xF +#define EJTAG_MODE_1 0x01 +#define EJTAG_MODE_2 0x02 +#define EJTAG_MODE_3 0x03 +#define EJTAG_MODE_MASK 0x03 + +//MOVDMA 100B +#define MOV_DMA_SRC_ADDR_L 0x03 +#define MOV_DMA_SRC_ADDR_H 0x04 +#define MOV_DMA_DST_ADDR_L 0x05 +#define MOV_DMA_DST_ADDR_H 0x06 +#define MOV_DMA_BYTE_CNT_L 0x07 +#define MOV_DMA_BYTE_CNT_H 0x08 +#define DMA_MOVE0_IRQ_CLR 0x28 +#define MOV_DMA_IRQ_FINAL_STATUS 0x2A +#define DMA_MOVE0_ENABLE 0x00 +#define DMA_RW 0x50 //0 for dma write to device, 1 for dma read from device +#define DMA_READ 0x01 +#define DMA_WRITE 0x00 +#define DMA_DEVICE_MODE 0x51 +#define DMA_DEVICE_SEL 0x52 + +//spi dma +#define MSPI_DMA_DATA_LENGTH_L 0x30 +#define MSPI_DMA_DATA_LENGTH_H 0x31 +#define MSPI_DMA_ENABLE 0x32 +#define MSPI_DMA_RW_MODE 0x33 +#define MSPI_DMA_WRITE 0x00 +#define MSPI_DMA_READ 0x01 + +#define MSTAR_SPI_TIMEOUT_MS 30000 +#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/) + + +//------------------------------------------------------------------------------------------------- +// Macros +//------------------------------------------------------------------------------------------------- + + +#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)((gChipBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)((gPmSleepBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)((gSarBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define MHal_RIU_REG(addr) (*(volatile U8*)((gRIUBaseAddr) + (((addr) & ~1)<<1) + (addr & 1))) +#define READ_BYTE(_reg) (*(volatile u8*)(_reg)) +#define READ_WORD(_reg) (*(volatile u16*)(_reg)) +#define READ_LONG(_reg) (*(volatile u32*)(_reg)) +#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); } +#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); } +#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); } +#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); } +#define READ_CPLD_DATA_IN() ((MHal_RIU_REG(PAD_Z80IO_IN_DATA_7_ADDR) & 0x1) << 7 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_6_ADDR) & 0x1) << 6 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_5_ADDR) & 0x1) << 5 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_4_ADDR) & 0x1) << 4 |\ + (MHal_RIU_REG(PAD_Z80IO_IN_DATA_3_ADDR) & 0x1) << 3 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_2_ADDR) & 0x1) << 2 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_1_ADDR) & 0x1) << 1 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_0_ADDR) & 0x1)) +#define SET_CPLD_READ_DATA() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) |= 0x4;} +#define SET_CPLD_READ_STATUS() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) &= ~0x4;} +#define SET_CPLD_HIGH_BYTE() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) |= 0x4;} +#define CLEAR_CPLD_HIGH_BYTE() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) &= ~0x4;} +#define CPLD_READY() (MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) +#define CPLD_RESET() (MHal_RIU_REG(PAD_Z80IO_RESET_ADDR) & 0x1) +#define CPLD_LAST_TSTATE() (MHal_RIU_REG(PAD_Z80IO_LTSTATE_ADDR) & 0x4) +#define CPLD_Z80_INT() (MHal_RIU_REG(PAD_Z80IO_INT_ADDR) & 0x4) +#define CPLD_Z80_NMI() (MHal_RIU_REG(PAD_Z80IO_NMI_ADDR) & 0x4) +#define SPI_SEND8(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 1); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE);\ + } +#define SPI_SEND16(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 2); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \ + } +#define SPI_SEND32(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET+1, (uint16_t)((_d_) >> 16)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 4); \ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \ + } +#define SPI_SEND32i(_d_) { uint32_t timeout = MAX_CHECK_CNT; \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \ + MSPI_WRITE(MSPI_WRITE_BUF_OFFSET+1, (uint16_t)((_d_) >> 16)); \ + MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 4); \ + pr_info("Stage 0");\ + while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\ + pr_info("Stage 1");\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \ + MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \ + pr_info("Stage 2");\ + timeout = MAX_CHECK_CNT; \ + while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; }; \ + pr_info("Stage 3");\ + MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \ + MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \ + } + + // while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0) { if(--timeout == 0) break; }; +// read 2 byte +#define MSPI_READ(_reg_) READ_WORD(gMspBaseAddr + ((_reg_)<<2)) +// write 2 byte +//#define MSPI_WRITE(_reg_, _val_) {pr_info("PDS: MSPI_WRITE(0x%x, 0x%x, 0x%x)\n", _reg_, _val_, gMspBaseAddr + ((_reg_)<<2)); WRITE_WORD(gMspBaseAddr + ((_reg_)<<2), (_val_)); } +#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(gMspBaseAddr + ((_reg_)<<2), (_val_)); +//write 2 byte mask +//#define MSPI_WRITE_MASK(_reg_, _val_, mask) {pr_info("PDS: WRITE_LONG(0x%x, 0x%x, mask=0x%x)\n", _reg_, _val_, mask); WRITE_WORD_MASK(gMspBaseAddr + ((_reg_)<<2), (_val_), (mask)); } +#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(gMspBaseAddr + ((_reg_)<<2), (_val_), (mask)); + +#define CLK_READ(_reg_) READ_WORD(gClkBaseAddr + ((_reg_)<<2)) +//#define CLK_WRITE(_reg_, _val_) {pr_info("PDS: CLK_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gClkBaseAddr + ((_reg_)<<2), (_val_)); } +#define CLK_WRITE(_reg_, _val_) WRITE_WORD(gClkBaseAddr + ((_reg_)<<2), (_val_)); + +#define CHIPTOP_READ(_reg_) READ_WORD(gChipBaseAddr + ((_reg_)<<2)) +//#define CHIPTOP_WRITE(_reg_, _val_) {pr_info("PDS: CHIPTOP_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gChipBaseAddr + ((_reg_)<<2), (_val_)); } +#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(gChipBaseAddr + ((_reg_)<<2), (_val_)); + +#define MOVDMA_READ(_reg_) READ_WORD(gMOVDMAAddr + ((_reg_)<<2)) +//#define MOVDMA_WRITE(_reg_, _val_) {pr_info("PDS: MOVDMA_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gMOVDMAAddr + ((_reg_)<<2), (_val_)); } +#define MOVDMA_WRITE(_reg_, _val_) WRITE_WORD(gMOVDMAAddr + ((_reg_)<<2), (_val_)); + +#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE) +#define MAX_CHECK_CNT 5000 + +#define MSPI_READ_INDEX 0x0 +#define MSPI_WRITE_INDEX 0x1 + +#define SPI_MIU0_BUS_BASE 0x20000000 +#define SPI_MIU1_BUS_BASE 0xFFFFFFFF + + +// Function definitions. +// +int z80io_init(void); +uint8_t z80io_SPI_Send8(uint8_t txData, uint8_t *rxData); +uint8_t z80io_SPI_Send16(uint16_t txData, uint16_t *rxData); +uint8_t z80io_SPI_Send32(uint32_t txData, uint32_t *rxData); +#ifdef NOTNEEDED +uint8_t z80io_PRL_Send8(uint8_t txData); +uint8_t z680io_PRL_Send16(uint16_t txData); +#endif +uint8_t z80io_PRL_Read(void); +uint8_t z80io_PRL_Read8(uint8_t dataFlag); +uint16_t z80io_PRL_Read16(void); +uint8_t z80io_SPI_Test(void); +uint8_t z80io_PRL_Test(void); +uint8_t z80io_Z80_TestMemory(void); + +extern void MHal_GPIO_Init(void); +extern void MHal_GPIO_Pad_Set(uint8_t u8IndexGPIO); +extern int MHal_GPIO_PadGroupMode_Set(uint32_t u32PadMode); +extern int MHal_GPIO_PadVal_Set(uint8_t u8IndexGPIO, uint32_t u32PadMode); +extern void MHal_GPIO_Pad_Oen(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pad_Odn(uint8_t u8IndexGPIO); +extern uint8_t MHal_GPIO_Pad_Level(uint8_t u8IndexGPIO); +extern uint8_t MHal_GPIO_Pad_InOut(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pull_High(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Pull_Low(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_High(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_Low(uint8_t u8IndexGPIO); +extern void MHal_Enable_GPIO_INT(uint8_t u8IndexGPIO); +extern int MHal_GPIO_To_Irq(uint8_t u8IndexGPIO); +extern void MHal_GPIO_Set_POLARITY(uint8_t u8IndexGPIO, uint8_t reverse); +extern void MHal_GPIO_Set_Driving(uint8_t u8IndexGPIO, uint8_t setHigh); +extern void MHal_GPIO_PAD_32K_OUT(uint8_t u8Enable); + +#ifdef __cplusplus +} +#endif +#endif // Z80IO_H diff --git a/software/FusionX/src/driver/MZ80A/z80io_test.c b/software/FusionX/src/driver/MZ80A/z80io_test.c new file mode 100644 index 000000000..ac7346b57 --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80io_test.c @@ -0,0 +1,541 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80io_test.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 IO Interface Test Methods +// This file contains the methods used to test the SOM to CPLD interface and evaluate +// it's performance. Production builds wont include these methods. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include + +//-------------------------------------------------------- +// Test Methods. +//-------------------------------------------------------- +uint8_t z80io_Z80_TestMemory(void) +{ + // Locals. + // + uint32_t addr; + uint32_t fullCmd; + uint8_t cmd; + struct timeval start, stop; + uint32_t iterations = 100; + uint32_t errorCount; + uint32_t idx; + long totalTime; + long bytesMSec; + uint8_t result; + spinlock_t spinLock; + unsigned long flags; + + SPI_SEND8(CPLD_CMD_CLEAR_AUTO_REFRESH); + + SPI_SEND32(0x00E30000 | (0x07 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E80000 | (0x82 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E20000 | (0x58 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E00000 | (0xF7 << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00E90000 | (0x0F << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00EB0000 | (0xCF << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + SPI_SEND32(0x00EB0000 | (0xFF << 8) | CPLD_CMD_WRITEIO_ADDR); + udelay(100); + pr_info("Z80 Host Test - IO.\n"); +// for(idx=0; idx < 1000000; idx++) +// { +// SPI_SEND32(0x00E80000 | (0xD3 << 8) | CPLD_CMD_WRITEIO_ADDR); +// SPI_SEND32(0xD0000000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0100000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0200000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0300000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0400000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// SPI_SEND32(0xD0500000 | (0x41 << 8) | CPLD_CMD_WRITE_ADDR); +// } + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing IO Write performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + for(addr=0x0000; addr < 0x10000; addr++) + { + fullCmd = 0x00000000| ((uint8_t)addr) << 8 | CPLD_CMD_WRITEIO_ADDR; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing IO Read performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible IO ports and write to it. + for(addr=0x0000; addr < 0x10000; addr++) + { + fullCmd = 0x00000000 | ((uint8_t)addr) << 8 | CPLD_CMD_READIO_ADDR; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + spin_lock_init(&spinLock); + pr_info("Z80 Host Test - Testing RAM Write performance.\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x1000; addr < 0xD000; addr++) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write performance (opt).\n"); + do_gettimeofday(&start); + spin_lock_irqsave(&spinLock, flags); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + } + } + spin_unlock_irqrestore(&spinLock, flags); + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write/Fetch performance (opt).\n"); + errorCount = 0; + SET_CPLD_READ_DATA(); + //MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x8000; addr < 0xD000; addr++) + { + if(addr == 0x8000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + + // Read back the same byte. + cmd = 0x10; + SPI_SEND8(cmd); + while(CPLD_READY() == 0); + + result = READ_CPLD_DATA_IN(); + if(result != (uint8_t)addr) + { + if(errorCount < 50) pr_info("Read byte:0x%x, Written:0x%x\n", result, (uint8_t)addr); + errorCount++; + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, errorCount=%d, %ldBytes/sec\n", totalTime/1000, errorCount, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Write/Read performance (opt).\n"); + errorCount = 0; + SET_CPLD_READ_DATA(); + //MHal_RIU_REG(gpio_table[PAD_Z80IO_HIGH_BYTE ].r_out) |= gpio_table[PAD_Z80IO_HIGH_BYTE ].m_out; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and write to it. + for(addr=0x8000; addr < 0xD000; addr++) + { + if(addr == 0x8000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND16(((uint8_t)addr) << 8 | cmd); + } + + // Read back the same byte. + cmd = 0x20; + SPI_SEND8(cmd); + while(CPLD_READY() == 0); + + result = READ_CPLD_DATA_IN(); + if(result != (uint8_t)addr) + { + if(errorCount < 50) pr_info("Read byte:0x%x, Written:0x%x\n", result, (uint8_t)addr); + errorCount++; + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, errorCount=%d, %ldBytes/sec\n", totalTime/1000, errorCount, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Fetch performance.\n"); + SET_CPLD_READ_DATA(); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and read from it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x10; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x11; + SPI_SEND8(cmd); + } + while(CPLD_READY() == 0); + result = READ_CPLD_DATA_IN(); + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Z80 Host Test - Testing RAM Read performance (opt).\n"); + SET_CPLD_READ_DATA(); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible RAM and read from it. + for(addr=0x1000; addr < 0xD000; addr++) + { + if(addr == 0x1000) + { + fullCmd = (addr << 16) | ((uint8_t)addr) << 8 | 0x20; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x21; + SPI_SEND8(cmd); + } + while(CPLD_READY() == 0); + result = READ_CPLD_DATA_IN(); + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations*0xC000)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + // Go through all the accessible attribute VRAM and initialise it. + pr_info("Z80 Host Test - Testing VRAM Write performance.\n"); + SPI_SEND32(0x00E80000 | (0xD3 << 8) | CPLD_CMD_WRITEIO_ADDR); + iterations = 256*10; + do_gettimeofday(&start); + for(addr=0xD800; addr < 0xE000; addr++) + { + //while(CPLD_READY() == 0); + if(addr == 0xD800) + { + fullCmd = (addr << 16) |(0x71 << 8) | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND8(cmd); + } + } + for(idx=0; idx < iterations; idx++) + { + // Go through all the accessible VRAM and write to it. + for(addr=0xD000; addr < 0xD800; addr++) + { + //while(CPLD_READY() == 0); + if(addr == 0xD000) + { + fullCmd = (addr << 16) | ((uint8_t)idx << 8) | 0x18; + SPI_SEND32(fullCmd); + } else + { + cmd = 0x19; + SPI_SEND8(cmd); + } + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)((1*iterations*0x800)+0x800)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + return(0); +} + + +// A simple test to verify the SOM to CPLD SPI connectivity and give an estimate of its performance. +// The performance is based on the SPI setup and transmit time along with the close and received data processing. +// In real use, the driver will just send a command and generally ignore received data so increased throughput can be achieved. +// +uint8_t z80io_SPI_Test(void) +{ + // Locals. + // + struct timeval start, stop; + uint32_t iterations = 10000000; + uint32_t idx; + uint8_t rxData8; + uint16_t rxData16; + uint16_t rxData16Last; + uint32_t rxData32; + uint32_t rxData32Last; + uint32_t errorCount; + long totalTime; + long bytesMSec; + + // Place the CPLD into echo test mode. + z80io_SPI_Send8(0xfe, &rxData8); + + // 1st. test, 8bit. + pr_info("SPI Test - Testing 8 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + z80io_SPI_Send8((uint8_t)idx, &rxData8); + if(idx > 1 && (uint8_t)(idx-1) != rxData8) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint8_t)(idx-1), rxData8 ); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(1*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 2nd. test, 16bit. + pr_info("SPI Test - Testing 16 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Byte re-ordering required as the CPLD echo's back the last 8bits received, it doesnt know if a transmission is 8/16/32bits. + z80io_SPI_Send16((uint16_t)idx, &rxData16); + if(idx > 0 && (uint16_t)(idx-1) != (uint16_t)(((rxData16&0x00ff) << 8) | ((rxData16Last & 0xff00) >> 8))) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint16_t)(idx-1), (uint16_t)(((rxData16&0x00ff) << 8) | ((rxData16Last & 0xff00) >> 8))); + errorCount++; + } + rxData16Last = rxData16; + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 3rd. test, 32bit. + pr_info("SPI Test - Testing 32 bit performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + z80io_SPI_Send32((uint32_t)idx, &rxData32); + if(idx > 0 && (uint32_t)(idx-1) != (uint32_t)(((rxData32&0x00ff) << 8) | ((rxData32Last & 0xff000000) >> 8) | ((rxData32Last & 0xff0000) >> 8) | ((rxData32Last & 0xff00) >> 8))) + { + if(errorCount < 20) + pr_info("0x%x: Last(0x%x) /= New(0x%x)\n",idx, (uint32_t)(idx-1), (uint32_t)(((rxData32&0x00ff) << 8) | ((rxData32Last & 0xff000000) >> 8) | ((rxData32Last & 0xff0000) >> 8) | ((rxData32Last & 0xff00) >> 8))); + errorCount++; + } + rxData32Last = rxData32; + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(4*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + pr_info("Press host RESET button Once to reset the CPLD.\n"); + return(0); +} + +// Method to test the parallel bus, verifying integrity and assessing performance. +uint8_t z80io_PRL_Test(void) +{ + // Locals. + // + struct timeval start, stop; + uint32_t iterations = 10000000; + uint32_t idx; + uint8_t rxData8; + uint16_t rxData16; + long totalTime; + long bytesMSec; +#ifdef NOTNEEDED + uint32_t errorCount; +#endif + + // Place the CPLD into echo test mode. + + // 1st. test, 8bit RW. +#ifdef NOTNEEDED + pr_info("Parallel Test - Testing 8 bit r/w performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write byte and readback to compare. + z80io_PRL_Send8((uint8_t)idx); + rxData8 = z80io_PRL_Read8(); + if((uint8_t)idx != rxData8) + { + pr_info("0x%x: Written(0x%x) /= Read(0x%x)\n", idx, (uint8_t)(idx), rxData8); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 2nd. test, 8bit Write. + pr_info("Parallel Test - Testing 8 bit write performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write byte. + z80io_PRL_Send8((uint8_t)idx); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); +#endif + + // 3rd. test, 8bit Read. + pr_info("Parallel Test - Testing 8 bit read performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Read byte. + rxData8 = z80io_PRL_Read8(0); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + +#ifdef NOTNEEDED + // 4th test, 16bit. + pr_info("Parallel Test - Testing 16 bit r/w performance.\n"); + errorCount=0; + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Byte re-ordering required as the CPLD echo's back the last 8bits received, it doesnt know if a transmission is 8/16/32bits. + z80io_PRL_Send16((uint16_t)idx); + rxData16 = z80io_PRL_Read16(); + if((uint16_t)idx != rxData16) + { + pr_info("0x%x: Written(0x%x) /= Read(0x%x)\n", idx, (uint16_t)(idx), rxData16); + errorCount++; + } + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode errorCount: %d, time=%ldms, %ldBytes/sec\n", errorCount, totalTime/1000, (bytesMSec*1000)); + + // 5th test, 16bit Write. + pr_info("Parallel Test - Testing 16 bit write performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Write word. + z80io_PRL_Send16((uint16_t)idx); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); +#endif + + // 6th test, 16bit Read. + pr_info("Parallel Test - Testing 16 bit read performance.\n"); + do_gettimeofday(&start); + for(idx=0; idx < iterations; idx++) + { + // Read word. + rxData16 = z80io_PRL_Read16(); + } + do_gettimeofday(&stop); + totalTime = (stop.tv_sec - start.tv_sec) * 1000000 + stop.tv_usec - start.tv_usec; + bytesMSec = (long)(2*iterations)/((long)totalTime/1000); + pr_info("Loop mode time=%ldms, %ldBytes/sec\n", totalTime/1000, (bytesMSec*1000)); + + pr_info("Press host RESET button Once to reset the CPLD.\n"); + return(0); +} diff --git a/software/FusionX/src/driver/MZ80A/z80menu.c b/software/FusionX/src/driver/MZ80A/z80menu.c new file mode 100644 index 000000000..bcc28a2ca --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80menu.c @@ -0,0 +1,57 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80menu.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 User Menu +// This file contains the methods used to present a menu of options to a user to aid +// in configuration and load/save of applications and data. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" +#include "z80menu.h" + +#include +#include +#include +#include + +void z80menu(void) +{ + // Locals. + +} diff --git a/software/FusionX/src/driver/MZ80A/z80menu.h b/software/FusionX/src/driver/MZ80A/z80menu.h new file mode 100755 index 000000000..107583682 --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80menu.h @@ -0,0 +1,44 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80menu.h +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 User Interface Menu +// This file contains the declarations required to provide a menu system allowing a +// user to configure and load/save applications/data. +// Credits: +// Copyright: (c) 2019-2022 Philip Smart +// +// History: Oct 2022 - Initial write of the z80 kernel driver software. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// +#ifndef Z80MENU_H +#define Z80MENU_H + +#ifdef __cplusplus + extern "C" { +#endif + +// Function definitions. +// +void z80menu(void); + +#ifdef __cplusplus +} +#endif +#endif // Z80MENU_H diff --git a/software/FusionX/src/driver/MZ80A/z80vhw_rfs.c b/software/FusionX/src/driver/MZ80A/z80vhw_rfs.c new file mode 100644 index 000000000..d02a04083 --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80vhw_rfs.c @@ -0,0 +1,714 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80vhw_rfs.c.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Virtual Hardware Driver - Rom Filing System (RFS) +// This file contains the methods used to emulate the Rom Filing System add on for the +// MZ-80A. +// +// These drivers are intended to be instantiated inline to reduce overhead of a call +// and as such, they are included like header files rather than C linked object files. +// Credits: +// Copyright: (c) 2019-2023 Philip Smart +// +// History: Feb 2023 - Initial write based on the RFS hardware. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" + +#include +#include +#include +#include + +// Device constants. +#define MROM_ADDR 0x00000 // Base address of the 512K Monitor ROM. +#define USER_ROM_I_ADDR 0x80000 // Base address of the first 512K User ROM. +#define USER_ROM_II_ADDR 0x80000 // Base address of the second 512K User ROM. +#define USER_ROM_III_ADDR 0x80000 // Base address of the third 512K User ROM. + +// RFS Control Registers. +#define BNKCTRLRST 0xEFF8 // Bank control reset, returns all registers to power up default. +#define BNKCTRLDIS 0xEFF9 // Disable bank control registers by resetting the coded latch. +#define HWSPIDATA 0xEFFB // Hardware SPI Data register (read/write). +#define HWSPISTART 0xEFFC // Start an SPI transfer. +#define BNKSELMROM 0xEFFD // Select RFS Bank1 (MROM) +#define BNKSELUSER 0xEFFE // Select RFS Bank2 (User ROM) +#define BNKCTRL 0xEFFF // Bank Control register (read/write). + +// +// RFS v2 Control Register constants. +// +#define BBCLK 1 // BitBang SPI Clock. +#define SDCS 2 // SD Card Chip Select, active low. +#define BBMOSI 4 // BitBang MOSI (Master Out Serial In). +#define CDLTCH1 8 // Coded latch up count bit 1 +#define CDLTCH2 16 // Coded latch up count bit 2 +#define CDLTCH3 32 // Coded latch up count bit 3 +#define BK2A19 64 // User ROM Device Select Bit 0 (or Address bit 19). +#define BK2A20 128 // User ROM Device Select Bit 1 (or Address bit 20). + // BK2A20 : BK2A19 + // 0 0 = Flash RAM 0 (default). + // 0 1 = Flash RAM 1. + // 1 0 = Flasm RAM 2 or Static RAM 0. + // 1 1 = Reserved.` + +#define BNKCTRLDEF BBMOSI+SDCS+BBCLK // Default on startup for the Bank Control register. + +// SD Drive constants. +#define SD_CARD_FILENAME "/customer/SHARP_MZ80A_RFS_CPM_IMAGE_1.img"// SD Card Binary Image. + +// MMC/SD command (SPI mode) +#define CMD0 0x40 + 0 // GO_IDLE_STATE +#define CMD1 0x40 + 1 // SEND_OP_COND +#define ACMD41 0x40 + 41 // SEND_OP_COND (SDC) +#define CMD8 0x40 + 8 // SEND_IF_COND +#define CMD9 0x40 + 9 // SEND_CSD +#define CMD10 0x40 + 10 // SEND_CID +#define CMD12 0x40 + 12 // STOP_TRANSMISSION +#define CMD13 0x40 + 13 // SEND_STATUS +#define ACMD13 0x40 + 13 // SD_STATUS (SDC) +#define CMD16 0x40 + 16 // SET_BLOCKLEN +#define CMD17 0x40 + 17 // READ_SINGLE_BLOCK +#define CMD18 0x40 + 18 // READ_MULTIPLE_BLOCK +#define CMD23 0x40 + 23 // SET_BLOCK_COUNT +#define ACMD23 0x40 + 23 // SET_WR_BLK_ERASE_COUNT (SDC) +#define CMD24 0x40 + 24 // WRITE_BLOCK +#define CMD25 0x40 + 25 // WRITE_MULTIPLE_BLOCK +#define CMD32 0x40 + 32 // ERASE_ER_BLK_START +#define CMD33 0x40 + 33 // ERASE_ER_BLK_END +#define CMD38 0x40 + 38 // ERASE +#define CMD55 0x40 + 55 // APP_CMD +#define CMD58 0x40 + 58 // READ_OCR +#define SD_SECSIZE 512 // Default size of an SD Sector +#define SD_RETRIES 0x0100 // Number of retries before giving up. + +// Card type flags (CardType) +#define CT_MMC 0x01 // MMC ver 3 +#define CT_SD1 0x02 // SD ver 1 +#define CT_SD2 0x04 // SD ver 2 +#define CT_SDC CT_SD1|CT_SD2 // SD +#define CT_BLOCK 0x08 // Block addressing + +// SD Card control variables. +typedef struct { + uint8_t trainingCnt; // Count of training bits to indicate card being initialised. + uint8_t initialised; // Flag to indicate the SD card has been initialised. + uint8_t writeFlag; // Flag to indicate an SD Write is taking place, assembling data prior to file write. + uint8_t cmdBuf[6+SD_SECSIZE]; // SD Command Input Buffer. + uint16_t rcvCntr; // SD Received byte counter. + uint8_t const *respBuf; // SD Response buffer. + uint16_t respCntr; // SD Response buffer counter. + uint16_t respLen; // SD size of data in response buffer. + struct file *fhandle; // Filehandle for the SD card image. + uint8_t regDataIn; // SD Card data in (from virtual card) register. + uint8_t regDataOut; // SD Card data out (to virtual card) register. + uint8_t dataOutFlag; // Flag to indicate data written to the SPI. +} t_SDCtrl; + +// RFS Board registers. +typedef struct { + uint8_t regBank1; // Bank 1, MROM, bank select register. + uint8_t regBank2; // Bank 2, UROM, bank select register. + uint8_t regCtrl; // Control register. + uint8_t upCntr; // Register enable up counter. + uint32_t mromAddr; // Actual address in MROM of active bank. + uint32_t uromAddr; // Actual address in UROM of active bank. + t_SDCtrl sd; // SD Control. +} t_RFSCtrl; + +// RFS Board control. +static t_RFSCtrl RFSCtrl; + +//------------------------------------------------------------------------------------------------------------------------------- +// +// +//------------------------------------------------------------------------------------------------------------------------------- + +// Method to setup the memory page config to reflect installation of an RFS Board. +void rfsSetupMemory(enum Z80_MEMORY_PROFILE mode) +{ + // Locals. + uint32_t idx; + + // The RFS Board occupies the MROM slot 0x0000:0x0FFF and the User ROM slot 0xE800:0xEFFF. The actual part of the ROM which appears in these windows + // is controlled by the REG_BANK1 (MROM) and REG_BANK2 (UROM) registers with the upper UROM registers provided in REG_CTRL. + // So on initial setup, map the MROM page to point to the Z80 ROM area 0x00000 which is the base of the first 512K Flash ROM (virtual). + + pr_info("RFS Memory Setup complete.\n"); + + // Setup defaults. + RFSCtrl.regBank1 = 0x00; + RFSCtrl.regBank2 = 0x00; + RFSCtrl.regCtrl = 0x00; + RFSCtrl.mromAddr = MROM_ADDR; + RFSCtrl.uromAddr = USER_ROM_I_ADDR; + Z80Ctrl->memSwitch = 0; + RFSCtrl.sd.trainingCnt = 0; + RFSCtrl.sd.initialised = 0; + RFSCtrl.sd.dataOutFlag = 0; + RFSCtrl.sd.rcvCntr = 0; + RFSCtrl.sd.writeFlag = 0; + RFSCtrl.sd.respCntr = 0; + RFSCtrl.sd.respLen = 0; + RFSCtrl.sd.fhandle = NULL; + + // Setup the initial state of the latch up-counter, used to enable access to the programmable registers. + RFSCtrl.upCntr = ((RFSCtrl.regCtrl & 0x20) >> 2) | ((RFSCtrl.regCtrl & 0x10) >> 2) | ((RFSCtrl.regCtrl & 0x08) >> 2); + + // Initialise the page pointers and memory to use physical RAM. + for(idx=0x0000; idx < 0x10000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(idx >= 0x0000 && idx < 0x1000) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, (RFSCtrl.mromAddr+idx)); + } + if(idx >= 0xE800 && idx < 0xF000) + { + // Memory is both ROM and hardware, the registers share the same address space. + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM | MEMORY_TYPE_VIRTUAL_HW, (RFSCtrl.uromAddr+(idx-0xE800))); + } + } + + // No I/O Ports on the RFS board. +} + +// Perform any setup operations, such as variable initialisation, to enable use of this module. +void rfsInit(void) +{ + pr_info("Enabling RFS driver.\n"); +} + +// Method to decode an address and make any system memory map changes as required. +// +static inline void rfsDecodeMemoryMapSetup(zuint16 address, zuint8 data, uint8_t ioFlag, uint8_t readFlag) +{ + // Locals. + uint32_t idx; + + // Memory map switch. + if(readFlag) + { + if(address == 0xE00C || address == 0xE00D || address == 0xE00E || address == 0xE00F) + { + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, (0xC000+idx)); + setMemoryType((idx+0xC000)/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, (RFSCtrl.mromAddr+idx)); + } + Z80Ctrl->memSwitch = 0x01; + } + + // Reset memory map switch. + else if(address == 0xE010 || address == 0xE011 || address == 0xE012 || address == 0xE013) + { + if(readFlag) + { + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, (RFSCtrl.mromAddr+idx)); + setMemoryType((idx+0xC000)/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_RAM, (0xC000+idx)); + } + } + Z80Ctrl->memSwitch = 0x00; + } + } +} + +// Emulation of the RFS SD card. The emulation is made easier as the RFS uses automatic shift registers so we just handle byte data not assembly +// of bit data. +// +// All SD commands are added to the processor but logic (apart from a standard response) is only added for commands which RFS uses. +// +void rfsSDCard(void) +{ + // Locals. + // + uint32_t lbaAddr; + int noBytes; + + // If Chip select is active and we arent initialised, exit, need to initialise before processing data. + if((RFSCtrl.regCtrl & SDCS) == 0 && RFSCtrl.sd.initialised == 0) + return; + + // If the Chip select is inactive and we are initialised, exit, can only process data if selected. + if((RFSCtrl.regCtrl & SDCS) && RFSCtrl.sd.initialised == 1) + return; + + // SD Card initialised? If not, follow the SD protocol. + // + if(RFSCtrl.sd.initialised == 0) + { + // RFS initialisation sends 10 x 8bits, which is a little more than standard 74bits. Just check for 7 bytes and then set initialised flag. + if(++RFSCtrl.sd.trainingCnt >= 7) + { + // Try and open the SD Card image. If it cannot be open then the SD card isnt registered as initialised. + RFSCtrl.sd.fhandle = filp_open(SD_CARD_FILENAME, O_RDWR, S_IWUSR | S_IRUSR); + if(IS_ERR(RFSCtrl.sd.fhandle)) + { + pr_info("Error opening SD Card Image:%s\n:", SD_CARD_FILENAME); + } else + { + RFSCtrl.sd.initialised = 1; + RFSCtrl.sd.trainingCnt = 0; + } + } + //pr_info("Training:%d, Initialised:%d\n", RFSCtrl.sd.trainingCnt, RFSCtrl.sd.initialised); + + } else + { + // If we are not receiving a command and response data is available, send it. + if((RFSCtrl.sd.rcvCntr == 0 && RFSCtrl.sd.regDataOut == 0xFF) || RFSCtrl.sd.respBuf || RFSCtrl.sd.dataOutFlag == 0) + { + if(RFSCtrl.sd.respBuf) + { + RFSCtrl.sd.regDataIn = RFSCtrl.sd.respBuf[RFSCtrl.sd.respCntr++]; + //pr_info("Sending Response:%02x(%d)\n", RFSCtrl.sd.regDataIn, RFSCtrl.sd.respCntr); + if(RFSCtrl.sd.respCntr == RFSCtrl.sd.respLen) + { + RFSCtrl.sd.respBuf = NULL; + RFSCtrl.sd.respCntr = 0; + } + } else + { + //pr_info("Sending Response filler:0xFF\n"); + RFSCtrl.sd.regDataIn = 0xFF; + } + } + else + { + // Clear out response buffer as latest data maybe an override, such as cancel. + RFSCtrl.sd.respBuf = NULL; + RFSCtrl.sd.respCntr = 0; + + // Clear out data write flag, this indicates when data is written into the SPI for transmission. + RFSCtrl.sd.dataOutFlag = 0; + + // Store incoming data. + RFSCtrl.sd.cmdBuf[RFSCtrl.sd.rcvCntr++] = RFSCtrl.sd.regDataOut; + //pr_info("Received:%02x(%d)\n", RFSCtrl.sd.regDataOut, RFSCtrl.sd.rcvCntr); + + // 0xFF, 0xFE, + if(RFSCtrl.sd.rcvCntr == (SD_SECSIZE+2) && RFSCtrl.sd.writeFlag == 1) + { + static uint8_t response[] = { 0x05 }; + + // Write the sector to the SD card image. + RFSCtrl.sd.cmdBuf[SD_SECSIZE+2] = 0x00; // CRC but we dont set, not needed in this application. + RFSCtrl.sd.cmdBuf[SD_SECSIZE+3] = 0x00; + noBytes = kernel_write(RFSCtrl.sd.fhandle, RFSCtrl.sd.cmdBuf, SD_SECSIZE+3, RFSCtrl.sd.fhandle->f_pos); + if(noBytes == 0) response[0] = 0x06; // Write error. + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + + // Reset to idle. + RFSCtrl.sd.rcvCntr = 0; + RFSCtrl.sd.writeFlag = 0; + } + + // If we are not writing (receiving data from the Z80) and we have assembled a full command, process. + else if(RFSCtrl.sd.rcvCntr == 6 && RFSCtrl.sd.writeFlag == 0) + { + RFSCtrl.sd.rcvCntr = 0; + + //pr_info("Received Command:%02x,%02x,%02x,%02x,%02x,%02x\n", RFSCtrl.sd.cmdBuf[0],RFSCtrl.sd.cmdBuf[1],RFSCtrl.sd.cmdBuf[2],RFSCtrl.sd.cmdBuf[3],RFSCtrl.sd.cmdBuf[4],RFSCtrl.sd.cmdBuf[5]); + switch(RFSCtrl.sd.cmdBuf[0]) + { + case CMD0: // GO_IDLE_STATE + //pr_info("GO_IDLE_STATE\n"); + { + // Initialise to SPI Mode. RFS doesnt support other modes. + static const uint8_t response[] = { 0x01 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD1: // SEND_OP_COND + //pr_info("SEND_OP_COND\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case ACMD41: // SEND_OP_COND (SDC) + //pr_info("SEND_OP_COND\n"); + { + static const uint8_t response[] = { 0x00 }; // 0 = Ready, 1 = Idle + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD8: // SEND_IF_COND + //pr_info("SEND_IF_COND\n"); + { + static const uint8_t response[] = { 0x01, 0x00, 0x00, 0x01, 0xAA }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD9: // SEND_CSD + //pr_info("SEND_CSD\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD10: // SEND_CID + //pr_info("SEND_CID\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD12: // STOP_TRANSMISSION + //pr_info("STOP_TRANSMISSION\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case ACMD13: // SD_STATUS (SDC) + //pr_info("SD_STATUS\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD16: // SET_BLOCKLEN + //pr_info("SD: Set Block Size:%d\n", (RFSCtrl.sd.cmdBuf[2] << 8 | RFSCtrl.sd.cmdBuf[3])); + { + static const uint8_t response[] = { 0x01 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD17: // READ_SINGLE_BLOCK + //pr_info("READ_SINGLE_BLOCK\n"); + { + static uint8_t response[6 + SD_SECSIZE]; + memset(response, 0, sizeof(response)); + + // Assemble LBA address and seek to the right location in the SD card image. + lbaAddr = RFSCtrl.sd.cmdBuf[1] << 24 | RFSCtrl.sd.cmdBuf[2] << 16 | RFSCtrl.sd.cmdBuf[3] << 8 | RFSCtrl.sd.cmdBuf[4]; + pr_info("Reading LBA %d\n", lbaAddr); + vfs_llseek(RFSCtrl.sd.fhandle, lbaAddr * SD_SECSIZE, SEEK_SET); + + // Assemble response buffer including SD card sector. + response[0] = 0x00; // Response R1 + response[1] = 0xFE; // Start of Data marker. + noBytes = kernel_read(RFSCtrl.sd.fhandle, RFSCtrl.sd.fhandle->f_pos, &response[2], SD_SECSIZE); + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = SD_SECSIZE + 2 + 2; // Sector Size + 2 bytes (R1 + Data Start) + 2 CRC + } + break; + + case CMD18: // READ_MULTIPLE_BLOCK + //pr_info("READ_MULTIPLE_BLOCK\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case ACMD23: // SET_WR_BLK_ERASE_COUNT (SDC) + //pr_info("SET_WR_BLK_ERASE_COUNT\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD24: // WRITE_BLOCK + //pr_info("WRITE_BLOCK\n"); + { + static const uint8_t response[] = { 0x00 }; + + // Assemble LBA address and seek to the right location in the SD card image. + lbaAddr = RFSCtrl.sd.cmdBuf[1] << 24 | RFSCtrl.sd.cmdBuf[2] << 16 | RFSCtrl.sd.cmdBuf[3] << 8 | RFSCtrl.sd.cmdBuf[4]; + pr_info("Writing LBA %d\n", lbaAddr); + vfs_llseek(RFSCtrl.sd.fhandle, lbaAddr * SD_SECSIZE, SEEK_SET); + + // Assemble response which is Ready, data can now be sent for sector. Set write flag so we know data is being received as sector data. + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + RFSCtrl.sd.writeFlag = 1; + RFSCtrl.sd.cmdBuf[0] = 0xFE; // Place start of data token at beginning of buffer. + RFSCtrl.sd.rcvCntr = 1; + } + break; + + case CMD25: // WRITE_MULTIPLE_BLOCK + //pr_info("WRITE_MULTIPLE_BLOCK\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD32: // ERASE_ER_BLK_START + //pr_info("ERASE_ER_BLK_START\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD33: // ERASE_ER_BLK_END + //pr_info("ERASE_ER_BLK_END\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD38: // ERASE + //pr_info("ERASE\n"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD55: // APP_CMD + //pr_info("APP_CMD\n"); + { + static const uint8_t response[] = { 0x01 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + case CMD58: // READ_OCR + //pr_info("READ_OCR\n"); + { + static const uint8_t response[] = { 0x00, 0x00, 0x00, 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + default: + pr_info("UNHANDLED REQUESTn"); + { + static const uint8_t response[] = { 0x00 }; + RFSCtrl.sd.respBuf = response; + RFSCtrl.sd.respLen = sizeof(response); + } + break; + + } + + } + else + { + // Standard response when a byte is received but not enough assembled to process. + RFSCtrl.sd.regDataIn = 0xFF; + } + } + } + + return; +} + +// Method to read from either the memory mapped registers if enabled else the ROM. +static inline uint8_t rfsRead(zuint16 address) +{ + // Locals. + uint8_t data = 0xFF; + + //pr_info("RFS+Read:%04x, BK1:%02x, BK2:%02x, CTRL:%02x, MROM:%08x, UROM:%08x\n", address, RFSCtrl.regBank1, RFSCtrl.regBank2, RFSCtrl.regCtrl, RFSCtrl.mromAddr, RFSCtrl.uromAddr); + + // Any access to the control region increments the enable counter till it reaches terminal count and enables writes to the registers. When the counter + // gets to 15 the registers are enabled and the EPROM, in the control region, is disabled. + if(address >= BNKCTRLRST && RFSCtrl.upCntr < 15) + { + RFSCtrl.upCntr++; + } + + // Address in control region and register bank enabled? + // + if(RFSCtrl.upCntr >= 15 && address >= BNKCTRLRST) + { + switch(address) + { + // Bank control reset, returns all registers to power up default. + case BNKCTRLRST: + break; + + // Disable bank control registers by resetting the coded latch. + case BNKCTRLDIS: + RFSCtrl.upCntr = (RFSCtrl.regCtrl >> 2) & 0x0E; + break; + + // Hardware SPI Data register (read/write). + case HWSPIDATA: + // Action data, ie. run the SD emulation. + data = RFSCtrl.sd.regDataIn; + //pr_info("HWSPIDATA ReadOut:%02x\n", data); + break; + + // Start an SPI transfer. + case HWSPISTART: + break; + + // Select RFS Bank1 (MROM) - No action for read, real hardware would store an undefined value into register. + case BNKSELMROM: + break; + + // Select RFS Bank2 (User ROM) - No action for read. + case BNKSELUSER: + break; + + // Bank Control register (read/write). + case BNKCTRL: + break; + } + } else + { + // Return the contents of the ROM at given address. + data = readVirtualROM(address); + } + + //pr_info("RFS-Read:%04x, Data:%02x, BK1:%02x, BK2:%02x, CTRL:%02x, MROM:%08x, UROM:%08x\n", address, data, RFSCtrl.regBank1, RFSCtrl.regBank2, RFSCtrl.regCtrl, RFSCtrl.mromAddr, RFSCtrl.uromAddr); + return(data); +} + +// Method to handle writes to the RFS board. Generally the RFS board. +static inline void rfsWrite(zuint16 address, zuint8 data) +{ + // Locals. + uint32_t idx; + + //pr_info("RFS+Write:%04x, Data:%02x, BK1:%02x, BK2:%02x, CTRL:%02x, MROM:%08x, UROM:%08x\n", address, data, RFSCtrl.regBank1, RFSCtrl.regBank2, RFSCtrl.regCtrl, RFSCtrl.mromAddr, RFSCtrl.uromAddr); + + // Any access to the control region increments the enable counter till it reaches terminal count and enables writes to the registers. When the counter + // gets to 15 the registers are enabled and the EPROM, in the control region, is disabled. + if(address >= BNKCTRLRST && RFSCtrl.upCntr < 15) + { + RFSCtrl.upCntr++; + } + + // Address in control region and register bank enabled? + // + if(RFSCtrl.upCntr >= 15 && address >= BNKCTRLRST) + { + switch(address) + { + // Bank control reset, returns all registers to power up default. + case BNKCTRLRST: // 0xEFF8 + break; + + // Disable bank control registers by resetting the coded latch. + case BNKCTRLDIS: // 0xEFF9 + default: + RFSCtrl.upCntr = (RFSCtrl.regCtrl >> 2) & 0x0E; + break; + + // Hardware SPI Data register (read/write). + case HWSPIDATA: + RFSCtrl.sd.regDataOut = data; + RFSCtrl.sd.dataOutFlag = 1; + //pr_info("HWSPIDATA WriteIn:%02x\n", data); + break; + + // Start an SPI transfer. + case HWSPISTART: + // Action data, ie. run the SD emulation as a write to this address starts the SPI clock which clocks out 8bit and clocks in 8 bits. + //pr_info("HWSPISTART\n"); + rfsSDCard(); + break; + + // Select RFS Bank1 (MROM) + case BNKSELMROM: + RFSCtrl.regBank1 = data; + + // Update monitor ROM address as register contains upper address bits of the ROM. + RFSCtrl.mromAddr = (uint32_t)(RFSCtrl.regBank1 << 12); + + // Update memory map to reflect register change. + for(idx=0x0000; idx < 0x1000; idx+=MEMORY_BLOCK_GRANULARITY) + { + if(Z80Ctrl->memSwitch) + { + // Monitor ROM is located at 0xC000. + setMemoryType((0xC000+idx)/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, (RFSCtrl.mromAddr+idx)); + } + else + { + // Monitor ROM is located at 0x000. + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM, (RFSCtrl.mromAddr+idx)); + } + } + break; + + // Select RFS Bank2 (User ROM) + case BNKSELUSER: + // Bank Control register (read/write). + case BNKCTRL: + if(address == BNKSELUSER) { RFSCtrl.regBank2 = data; } else { RFSCtrl.regCtrl = data; } + + // Update user ROM address as register contain upper address bits of the ROM. + RFSCtrl.uromAddr = (uint32_t)(((((RFSCtrl.regCtrl&0xB0) << 2) | RFSCtrl.regBank2) << 11) + USER_ROM_I_ADDR); + + // Update memory map to reflect register change. + for(idx=0xE800; idx < 0xF000; idx+=MEMORY_BLOCK_GRANULARITY) + { + // Memory is both ROM and hardware, the registers share the same address space. + setMemoryType(idx/MEMORY_BLOCK_GRANULARITY, MEMORY_TYPE_VIRTUAL_ROM | MEMORY_TYPE_VIRTUAL_HW, (RFSCtrl.uromAddr+(idx-0xE800))); + } + break; + } + } + //pr_info("RFS-Write:%04x, Data:%02x, BK1:%02x, BK2:%02x, CTRL:%02x, MROM:%08x, UROM:%08x\n", address, data, RFSCtrl.regBank1, RFSCtrl.regBank2, RFSCtrl.regCtrl, RFSCtrl.mromAddr, RFSCtrl.uromAddr); + return; +} diff --git a/software/FusionX/src/driver/MZ80A/z80vhw_tzpu.c b/software/FusionX/src/driver/MZ80A/z80vhw_tzpu.c new file mode 100644 index 000000000..3a3e2d348 --- /dev/null +++ b/software/FusionX/src/driver/MZ80A/z80vhw_tzpu.c @@ -0,0 +1,91 @@ +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// Name: z80vhw_tzpu.c +// Created: Oct 2022 +// Author(s): Philip Smart +// Description: Z80 Virtual Hardware Driver - tranZPUter SW +// This file contains the methods used to emulate the first tranZPUter Software series +// the tranZPUter SW which used a Cortex-M4 to enhance the host machine and provide +// an upgraded monitor, the tzfs (tranZPUter Filing System). +// +// These drivers are intended to be instantiated inline to reduce overhead of a call +// and as such, they are included like header files rather than C linked object files. +// Credits: +// Copyright: (c) 2019-2023 Philip Smart +// +// History: Feb 2023 - Initial write based on the RFS hardware. +// +// Notes: See Makefile to enable/disable conditional components +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// +// This source file is free software: you can redistribute it and#or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "z80io.h" + +#include +#include +#include +#include + +//------------------------------------------------------------------------------------------------------------------------------- +// +// +//------------------------------------------------------------------------------------------------------------------------------- + +// Method to setup the memory page config to reflect installation of a tranZPUter SW Board. +void tzpuSetupMemory(enum Z80_MEMORY_PROFILE mode) +{ +} + +// Perform any setup operations, such as variable initialisation, to enable use of this module. +void tzpuInit(void) +{ +} + +// Method to decode an address and make any system memory map changes as required. +// +static inline void tzpuDecodeMemoryMapSetup(zuint16 address, zuint8 data, uint8_t ioFlag, uint8_t readFlag) +{ + // Locals. +} + +// Method to read from the tranZPUter SW memory or I/O ports. +static inline uint8_t tzpuRead(zuint16 address) +{ + // Locals. + uint8_t data = 0x00; + + return(data); +} + +// Method to write to the tranZPUter SW memory or I/O ports. +static inline void tzpuWrite(zuint16 address, zuint8 data) +{ + return; +} diff --git a/software/FusionX/src/driver/Makefile b/software/FusionX/src/driver/Makefile index cd81baf80..2a2cfc20c 100644 --- a/software/FusionX/src/driver/Makefile +++ b/software/FusionX/src/driver/Makefile @@ -1,6 +1,6 @@ -MODEL := MZ2000 +#MODEL := MZ2000 #MODEL := MZ700 -#MODEL := MZ80A +MODEL := MZ80A KERNEL := $(PWD)/../../../linux/kernel FUSIONX := $(PWD)/../.. CROSS := arm-linux-gnueabihf- diff --git a/software/linux/boot/include/ms_version.h b/software/linux/boot/include/ms_version.h index af2159248..88af49e45 100644 --- a/software/linux/boot/include/ms_version.h +++ b/software/linux/boot/include/ms_version.h @@ -1,7 +1,7 @@ -// $Change: 6322424ba $ +// $Change: ef9980d8e $ #define MVXV_HEAD_VER {'4'} #define MVXV_LIB_TYPE {'#', '#'} #define MVXV_CHIP_ID {'I', '2', 'M', '#'} -#define MVXV_CHANGELIST {'g', '6', '3', '2', '2', '4', '2', '4', 'b', 'a'} +#define MVXV_CHANGELIST {'g', 'e', 'f', '9', '9', '8', '0', 'd', '8', 'e'} #define MVXV_COMP_ID {'C', 'M', '_', 'U', 'B', 'T', '1', '5', '0', '1'} diff --git a/software/linux/kernel/arch/arm/boot/dts/aks-cdu.dts b/software/linux/kernel/arch/arm/boot/dts/aks-cdu.dts deleted file mode 100644 index 5b1bf92d9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/aks-cdu.dts +++ /dev/null @@ -1,119 +0,0 @@ -/* - * aks-cdu.dts - Device Tree file for AK signal CDU - * - * Copyright (C) 2012 AK signal Brno a.s. - * 2012 Jiri Prchal - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; - -#include "ge863-pro3.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - }; - - ahb { - apb { - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - usart2: serial@fffb8000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - usart3: serial@fffd0000 { - status = "okay"; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 0>; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "uboot"; - reg = <0x40000 0x80000>; - }; - ubootenv@c0000 { - label = "ubootenv"; - reg = <0xc0000 0x40000>; - }; - kernel@100000 { - label = "kernel"; - reg = <0x100000 0x400000>; - }; - rootfs@500000 { - label = "rootfs"; - reg = <0x500000 0x7b00000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - red { - gpios = <&pioC 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - green { - gpios = <&pioA 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "on"; - }; - - yellow { - gpios = <&pioB 20 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - blue { - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/alphascale-asm9260-devkit.dts b/software/linux/kernel/arch/arm/boot/dts/alphascale-asm9260-devkit.dts deleted file mode 100644 index c77e2c902..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/alphascale-asm9260-devkit.dts +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -/dts-v1/; -#include "alphascale-asm9260.dtsi" - -/ { - model = "Alphascale asm9260 Development Kit"; - compatible = "alphascale,asm9260devkit", "alphascale,asm9260"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/alphascale-asm9260.dtsi b/software/linux/kernel/arch/arm/boot/dts/alphascale-asm9260.dtsi deleted file mode 100644 index 907fc7bfc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/alphascale-asm9260.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -#include "skeleton.dtsi" -#include - -/ { - interrupt-parent = <&icoll>; - - memory { - device_type = "memory"; - reg = <0x20000000 0x2000000>; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - clocks = <&acc CLKID_SYS_CPU>; - }; - }; - - osc24m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-accuracy = <30000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - acc: clock-controller@80040000 { - compatible = "alphascale,asm9260-clock-controller"; - #clock-cells = <1>; - clocks = <&osc24m>; - reg = <0x80040000 0x204>; - }; - - icoll: interrupt-controller@80054000 { - compatible = "alphascale,asm9260-icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80054000 0x200>; - }; - - timer0: timer@80088000 { - compatible = "alphascale,asm9260-timer"; - reg = <0x80088000 0x4000>; - clocks = <&acc CLKID_AHB_TIMER0>; - interrupts = <29>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/alpine-db.dts b/software/linux/kernel/arch/arm/boot/dts/alpine-db.dts deleted file mode 100644 index dfb5a0802..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/alpine-db.dts +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2015 Annapurna Labs Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * Alternatively, redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/dts-v1/; - -#include "alpine.dtsi" - -/ { - model = "Annapurna Labs Alpine Dev Board"; - /* no need for anything outside SOC */ -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/alpine.dtsi b/software/linux/kernel/arch/arm/boot/dts/alpine.dtsi deleted file mode 100644 index db8752fc4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/alpine.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright 2015 Annapurna Labs Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * Alternatively, redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -#include -#include "skeleton64.dtsi" - -/ { - /* SOC compatibility */ - compatible = "al,alpine"; - - /* CPU Configuration */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "al,alpine-smp"; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <0>; /* Filled by loader */ - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - clock-frequency = <0>; /* Filled by loader */ - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - clock-frequency = <0>; /* Filled by loader */ - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - clock-frequency = <0>; /* Filled by loader */ - }; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - arch-timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = - , - , - , - ; - clock-frequency = <0>; /* Filled by loader */ - }; - - /* Interrupt Controller */ - gic: gic@fb001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xfb001000 0x0 0x1000>, - <0x0 0xfb002000 0x0 0x2000>, - <0x0 0xfb004000 0x0 0x1000>, - <0x0 0xfb006000 0x0 0x2000>; - interrupts = - ; - }; - - /* CPU Resume registers */ - cpu-resume@fbff5ec0 { - compatible = "al,alpine-cpu-resume"; - reg = <0x0 0xfbff5ec0 0x0 0x30>; - }; - - /* North Bridge Service Registers */ - sysfabric-service@fb070000 { - compatible = "al,alpine-sysfabric-service", "syscon"; - reg = <0x0 0xfb070000 0x0 0x10000>; - }; - - /* Performance Monitor Unit */ - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - }; - - uart0:uart@fd883000 { - compatible = "ns16550a"; - reg = <0x0 0xfd883000 0x0 0x1000>; - clock-frequency = <0>; /* Filled by loader */ - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart1:uart@0xfd884000 { - compatible = "ns16550a"; - reg = <0x0 0xfd884000 0x0 0x1000>; - clock-frequency = <0>; /* Filled by loader */ - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - /* Internal PCIe Controller */ - pcie-internal@0xfbc00000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #size-cells = <2>; - #address-cells = <3>; - #interrupt-cells = <1>; - reg = <0x0 0xfbc00000 0x0 0x100000>; - interrupt-map-mask = <0xf800 0 0 7>; - /* Add legacy interrupts for SATA devices only */ - interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, - <0x4800 0 0 1 &gic 0 44 4>; - - /* 32 bit non prefetchable memory space */ - ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; - - bus-range = <0x00 0x00>; - msi-parent = <&msix>; - }; - - msix: msix@fbe00000 { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <96>; - al,msi-num-spis = <64>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir2110.dts deleted file mode 100644 index a9a97307d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" - -/ { - model = "OnRISC Baltos iR 2110"; -}; - -&am33xx_pinmux { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <7>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; -}; - -&phy_sel { - rmii-clock-ext = <1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir3220.dts deleted file mode 100644 index fe002a17c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" - -/ { - model = "OnRISC Baltos iR 3220"; -}; - -&am33xx_pinmux { - tca6416_pins: pinmux_tca6416_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ - - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&i2c1 { - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <20 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&cpsw_emac0 { - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <7>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; -}; - -&phy_sel { - rmii-clock-ext = <1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir5221.dts deleted file mode 100644 index d0faa7b8c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -/dts-v1/; - -#include "am335x-baltos.dtsi" - -/ { - model = "OnRISC Baltos iR 5221"; -}; - -&am33xx_pinmux { - tca6416_pins: pinmux_tca6416_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ - >; - }; - - - dcan1_pins: pinmux_dcan1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ - AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ - - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ - >; - }; - -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - - status = "okay"; -}; - -&i2c1 { - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <20 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "otg"; -}; - -&cpsw_emac0 { - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; - fixed-link { - speed = <100>; - full-duplex; - }; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <7>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; -}; - -&phy_sel { - rmii-clock-ext = <1>; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-baltos.dtsi b/software/linux/kernel/arch/arm/boot/dts/am335x-baltos.dtsi deleted file mode 100644 index dd45d172a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-baltos.dtsi +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * VScom OnRISC - * http://www.vscom.de - */ - -#include "am33xx.dtsi" -#include -#include - -/ { - compatible = "vscom,onrisc", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - wl12xx_vmmc: fixedregulator2 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 8 0>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ - AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ - >; - }; - - tps65910_pins: pinmux_tps65910_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ - AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ - - - /* Slave 2 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - - /* Slave 2 reset value*/ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - nandflash_pins_s0: nandflash_pins_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - status = "okay"; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - ti,nand-xfer-type = "polled"; - - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - ti,elm-id = <&elm>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <28 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&tps65910_pins>; - }; - - at24@50 { - compatible = "at24,24c02"; - pagesize = <8>; - reg = <0x50>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - ti,en-ck32k-xtal = <1>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <&vmmc_reg>; - status = "okay"; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-base0033.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-base0033.dts deleted file mode 100644 index c2bee452d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-base0033.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION - * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "am335x-igep0033.dtsi" - -/ { - model = "IGEP COM AM335x on AQUILA Expansion"; - compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; - - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_pins>; - pinctrl-1 = <&nxp_hdmi_off_pins>; - status = "okay"; - }; - - leds_base { - pinctrl-names = "default"; - pinctrl-0 = <&leds_base_pins>; - - compatible = "gpio-leds"; - - led0 { - label = "base:red:user"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ - default-state = "off"; - }; - - led1 { - label = "base:green:user"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - nxp_hdmi_pins: pinmux_nxp_hdmi_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */ - >; - }; - nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ - >; - }; - - leds_base_pins: pinmux_leds_base_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */ - >; - }; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-bone-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/am335x-bone-common.dtsi deleted file mode 100644 index 007b5e5a5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-bone-common.dtsi +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led2 { - label = "beaglebone:green:heartbeat"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led3 { - label = "beaglebone:green:mmc0"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led5 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - baseboard_eeprom: baseboard_eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - - #address-cells = <1>; - #size-cells = <1>; - baseboard_data: baseboard_data@0 { - reg = <0 0x100>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <100000>; - - cape_eeprom0: cape_eeprom0@54 { - compatible = "at,24c256"; - reg = <0x54>; - #address-cells = <1>; - #size-cells = <1>; - cape0_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom1: cape_eeprom1@55 { - compatible = "at,24c256"; - reg = <0x55>; - #address-cells = <1>; - #size-cells = <1>; - cape1_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom2: cape_eeprom2@56 { - compatible = "at,24c256"; - reg = <0x56>; - #address-cells = <1>; - #size-cells = <1>; - cape2_data: cape_data@0 { - reg = <0 0x100>; - }; - }; - - cape_eeprom3: cape_eeprom3@57 { - compatible = "at,24c256"; - reg = <0x57>; - #address-cells = <1>; - #size-cells = <1>; - cape3_data: cape_data@0 { - reg = <0 0x100>; - }; - }; -}; - - -/include/ "tps65217.dtsi" - -&tps { - /* - * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only - * mode") at poweroff. Most BeagleBone versions do not support RTC-only - * mode and risk hardware damage if this mode is entered. - * - * For details, see linux-omap mailing list May 2015 thread - * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller - * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html - * - * You can override this later with - * &tps { /delete-property/ ti,pmic-shutdown-controller; } - * if you want to use RTC-only mode and made sure you are not affected - * by the hardware problems. (Tip: double-check by performing a current - * measurement after shutdown: it should be less than 1 mA.) - */ - ti,pmic-shutdown-controller; - - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3a"; - regulator-always-on; - }; - }; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "mii"; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&mmc1 { - status = "okay"; - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&aes { - status = "okay"; -}; - -&sham { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-bone.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-bone.dts deleted file mode 100644 index 6b8493720..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-bone.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" - -/ { - model = "TI AM335x BeagleBone"; - compatible = "ti,am335x-bone", "ti,am33xx"; -}; - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&ldo3_reg>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-boneblack.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-boneblack.dts deleted file mode 100644 index 6bbb1fee0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-boneblack.dts +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include - -/ { - model = "TI AM335x BeagleBone Black"; - compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; -}; - -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ - >; - }; - nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ - >; - }; - - mcasp0_pins: mcasp0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; -}; - -&lcdc { - status = "okay"; - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&hdmi_0>; - }; - }; -}; - -&i2c0 { - tda19988: tda19988 { - compatible = "nxp,tda998x"; - reg = <0x70>; - - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - - #sound-dai-cells = <0>; - audio-ports = < TDA998x_I2S 0x03>; - - ports { - port@0 { - hdmi_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; - }; - }; - }; - }; -}; - -&rtc { - system-power-controller; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -/ { - clk_mcasp0_fixed: clk_mcasp0_fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - clk_mcasp0: clk_mcasp0 { - #clock-cells = <0>; - compatible = "gpio-gate-clock"; - clocks = <&clk_mcasp0_fixed>; - enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "TI BeagleBone Black"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp0>; - clocks = <&clk_mcasp0>; - }; - - simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-bonegreen.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-bonegreen.dts deleted file mode 100644 index dce3c8657..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-bonegreen.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" - -/ { - model = "TI AM335x BeagleBone Green"; - compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; -}; - -&am33xx_pinmux { - uart2_pins: uart2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&rtc { - system-power-controller; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-chiliboard.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-chiliboard.dts deleted file mode 100644 index 2a624b3c9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-chiliboard.dts +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ - * Author: Rostislav Lisovy - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; -#include "am335x-chilisom.dtsi" - -/ { - model = "AM335x Chiliboard"; - compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", - "ti,am33xx"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_gpio_pins>; - - led0 { - label = "led0"; - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "led1"; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; - -&am33xx_pinmux { - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - usb1_drvvbus: usb1_drvvbus { - pinctrl-single,pins = < - AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ - >; - }; - - sd_pins: pinmux_sd_card { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - led_gpio_pins: led_gpio_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */ - AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&ldo4_reg { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -/* Ethernet */ -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rmii"; -}; - -&phy_sel { - rmii-clock-ext; -}; - -/* USB */ -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_drvvbus>; - - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -/* microSD */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&sd_pins>; - vmmc-supply = <&ldo4_reg>; - bus-width = <0x4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-chilisom.dtsi b/software/linux/kernel/arch/arm/boot/dts/am335x-chilisom.dtsi deleted file mode 100644 index 1b43ebd08..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-chilisom.dtsi +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ - * Author: Rostislav Lisovy - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include "am33xx.dtsi" -#include - -/ { - model = "Grinn AM335x ChiliSOM"; - compatible = "grinn,am335x-chilisom", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - nandflash_pins: nandflash_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - -}; - -/include/ "tps65217.dtsi" - -&tps { - regulators { - dcdc1_reg: regulator@0 { - regulator-name = "vdds_dpr"; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - regulator-name = "vio,vrtc,vdds"; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "vdd_3v3aux"; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - regulator-name = "vdd_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - regulator-name = "vdd_3v3d"; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&rtc { - system-power-controller; - - pinctrl-0 = <&ext_wakeup>; - pinctrl-names = "default"; - - ext_wakeup: ext-wakeup { - pins = "ext_wakeup0"; - input-enable; - }; -}; - -/* NAND Flash */ -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-cm-t335.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-cm-t335.dts deleted file mode 100644 index 947c81b7a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-cm-t335.dts +++ /dev/null @@ -1,569 +0,0 @@ -/* - * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 - * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "CompuLab CM-T335"; - compatible = "compulab,cm-t335", "ti,am33xx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_led_pins>; - led0 { - label = "cm_t335:green"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ - linux,default-trigger = "heartbeat"; - }; - }; - - /* regulator for mmc */ - vmmc_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* Regulator for WiFi */ - vwlan_fixed: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "vwlan_fixed"; - gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ - enable-active-high; - regulator-boot-off; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 0>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "cm-t335"; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Headphone", "Headphone Jack"; - - simple-audio-card,routing = - "Headphone Jack", "LHPOUT", - "Headphone Jack", "RHPOUT", - "LLINEIN", "Line In", - "RLINEIN", "Line In", - "MICIN", "Mic Jack"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic23>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&bluetooth_pins>; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) - /* i2c0_scl.i2c0_scl */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - /* uart0_ctsn.i2c1_sda */ - AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE2) - /* uart0_rtsn.i2c1_scl */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) - >; - }; - - gpio_led_pins: pinmux_gpio_led_pins { - pinctrl-single,pins = < - /* gpmc_csn3.gpio2_0 */ - AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE7) - >; - }; - - nandflash_pins: pinmux_nandflash_pins { - pinctrl-single,pins = < - /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) - /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) - /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) - /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) - /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) - /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) - /* gpmc_ben0_cle.gpmc_ben0_cle */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) - /* uart0_txd.uart0_txd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) - /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) - /* uart1_txd.uart1_txd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - >; - }; - - dcan0_pins: pinmux_dcan0_pins { - pinctrl-single,pins = < - /* uart1_ctsn.dcan0_tx */ - AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) - /* uart1_rtsn.dcan0_rx */ - AM33XX_IOPAD(0x97C, PIN_INPUT | MUX_MODE2) - >; - }; - - dcan1_pins: pinmux_dcan1_pins { - pinctrl-single,pins = < - /* uart1_rxd.dcan1_tx */ - AM33XX_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) - /* uart1_txd.dcan1_rx */ - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE2) - >; - }; - - ecap0_pins: pinmux_ecap0_pins { - pinctrl-single,pins = < - /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - AM33XX_IOPAD(0x964, 0x0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - /* mii1_tx_en.rgmii1_tctl */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) - /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) - /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) - /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) - /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) - /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) - /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) - /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) - /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) - /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) - /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) - /* mii1_rxd0.rgmii1_rd0 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) - /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - spi0_pins: pinmux_spi0_pins { - pinctrl-single,pins = < - /* spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0) - /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) - /* spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0) - /* spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) - /* spi0_cs1.spi0_cs1 */ - AM33XX_IOPAD(0x960, PIN_OUTPUT | MUX_MODE0) - >; - }; - - /* wl1271 bluetooth */ - bluetooth_pins: pinmux_bluetooth_pins { - pinctrl-single,pins = < - /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ - AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - /* TLV320AIC23B codec */ - mcasp1_pins: pinmux_mcasp1_pins { - pinctrl-single,pins = < - /* MII1_CRS.mcasp1_aclkx */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) - /* MII1_RX_ER.mcasp1_fsx */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) - /* MII1_COL.mcasp1_axr2 */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE4) - /* RMII1_REF_CLK.mcasp1_axr3 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) - >; - }; - - /* wl1271 WiFi */ - wifi_pins: pinmux_wifi_pins { - pinctrl-single,pins = < - /* EMU1.gpio3_8 - WiFi IRQ */ - AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7) - /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ - AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -/* WLS1271 bluetooth */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - -status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - /* CM-T335 board EEPROM */ - eeprom: 24c02@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - /* Real Time Clock */ - ext_rtc: em3027@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - /* Audio codec */ - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - #sound-dai-cells= <0>; - status = "okay"; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -&epwmss0 { - status = "okay"; - - ecap0: ecap@48300100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "spl"; - reg = <0x00000000 0x00200000>; - }; - partition@1 { - label = "uboot"; - reg = <0x00200000 0x00100000>; - }; - partition@2 { - label = "uboot environment"; - reg = <0x00300000 0x00100000>; - }; - partition@3 { - label = "dtb"; - reg = <0x00400000 0x00100000>; - }; - partition@4 { - label = "splash"; - reg = <0x00500000 0x00400000>; - }; - partition@5 { - label = "linux"; - reg = <0x00900000 0x00600000>; - }; - partition@6 { - label = "rootfs"; - reg = <0x00F00000 0>; - }; - }; -}; - -&elm { - status = "okay"; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - slaves = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii-txid"; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&dcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dcan0_pins>; -}; - -&dcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; -}; - -/* Touschscreen and analog digital converter */ -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x01 0x10 0x23 0x32>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -/* CPU audio */ -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcasp1_pins>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 16 serializers */ - num-serializer = <16>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; - - #sound-dai-cells= <0>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - ti,pindir-d0-out-d1-in = <1>; - /* WLS1271 WiFi */ - wlcore: wlcore@1 { - compatible = "ti,wl1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pins>; - reg = <1>; - spi-max-frequency = <48000000>; - clock-xtal; - ref-clock-frequency = <38400000>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - vwlan-supply = <&vwlan_fixed>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-evm.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-evm.dts deleted file mode 100644 index e82432c79..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-evm.dts +++ /dev/null @@ -1,785 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "TI AM335x EVM"; - compatible = "ti,am335x-evm", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - wlan_en_reg: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - /* WLAN_EN GPIO for this board - Bank1, pin16 */ - gpio = <&gpio1 16 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ - &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ - &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ - - col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ - &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ - - linux,keymap = <0x0000008b /* MENU */ - 0x0100009e /* BACK */ - 0x02000069 /* LEFT */ - 0x0001006a /* RIGHT */ - 0x0101001c /* ENTER */ - 0x0201006c>; /* DOWN */ - }; - - gpio_keys: volume_keys0 { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - switch9 { - label = "volume-up"; - linux,code = <115>; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - switch10 { - label = "volume-down"; - linux,code = <114>; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 0>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_s0>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - 800x480p62 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <39>; - hback-porch = <39>; - hsync-len = <47>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <2>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM335x-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; - - matrix_keypad_s0: matrix_keypad_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; - - volume_keys_s0: volume_keys_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - nandflash_pins_s0: nandflash_pins_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ - AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ - AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ - AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ - >; - }; - - lcd_pins_s0: lcd_pins_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1_pins_sleep { - pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tsl2550: tsl2550@39 { - compatible = "taos,tsl2550"; - reg = <0x39>; - }; - - tmp275: tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vaux2_reg>; - IOVDD-supply = <&vaux2_reg>; - DRVDD-supply = <&vaux2_reg>; - DVDD-supply = <&vbat>; - }; -}; - -&lcdc { - status = "okay"; - - blue-and-red-wiring = "crossed"; -}; - -&elm { - status = "okay"; -}; - -&epwmss0 { - status = "okay"; - - ecap0: ecap@48300100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000C0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001C0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001E0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00A00000 0x0F600000>; - }; - }; -}; - -#include "tps65910.dtsi" - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii-txid"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii-txid"; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - /* these are on the crossbar and are outlined in the - xbar-event-map element */ - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wlan_pins>; - ti,non-removable; - ti,needs-special-hs-handling; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&dcan1 { - status = "disabled"; /* Enable only if Profile 1 is selected */ - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins_default>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-evmsk.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-evmsk.dts deleted file mode 100644 index 8e6b3938b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-evmsk.dts +++ /dev/null @@ -1,718 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * AM335x Starter Kit - * http://www.ti.com/tool/tmdssk3358 - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include -#include - -/ { - model = "TI AM335x EVM-SK"; - compatible = "ti,am335x-evmsk", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - wl12xx_vmmc: fixedregulator2 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 29 0>; - startup-delay-us = <70000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator3 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led1 { - label = "evmsk:green:usr0"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "evmsk:green:usr1"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "evmsk:green:mmc0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "evmsk:green:heartbeat"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - gpio_buttons: gpio_buttons0 { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - switch1 { - label = "button0"; - linux,code = <0x100>; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - }; - - switch2 { - label = "button1"; - linux,code = <0x101>; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - - switch3 { - label = "button2"; - linux,code = <0x102>; - gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - switch4 { - label = "button3"; - linux,code = <0x103>; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 58 61 66 75 90 125 170 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM335x-EVMSK"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24000000>; - }; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default>; - pinctrl-1 = <&lcd_pins_sleep>; - status = "okay"; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - 480x272 { - hactive = <480>; - vactive = <272>; - hback-porch = <43>; - hfront-porch = <8>; - hsync-len = <4>; - vback-porch = <12>; - vfront-porch = <4>; - vsync-len = <10>; - clock-frequency = <9000000>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - - lcd_pins_default: lcd_pins_default { - pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ - >; - }; - - lcd_pins_sleep: lcd_pins_sleep { - pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ - >; - }; - - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - >; - }; - - gpio_keys_s0: gpio_keys_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ - AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - ecap2_pins: backlight_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - - /* Slave 2 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - - /* Slave 2 reset value*/ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1_pins_sleep { - pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vaux2_reg>; - IOVDD-supply = <&vaux2_reg>; - DRVDD-supply = <&vaux2_reg>; - DVDD-supply = <&vbat>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&epwmss2 { - status = "okay"; - - ecap2: ecap@48304100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1351500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ - ref-clock-frequency = <38400000>; - }; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; -}; - -&lcdc { - status = "okay"; - - blue-and-red-wiring = "crossed"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-icev2.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-icev2.dts deleted file mode 100644 index 85e04c205..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-icev2.dts +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * AM335x ICE V2 board - * http://www.ti.com/tool/tmdsice3359 - */ - -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "TI AM3359 ICE-V2"; - compatible = "ti,am3359-icev2", "ti,am33xx"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vtt_fixed: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - }; - - leds0 { - compatible = "gpio-leds"; - - led0 { - label = "out0"; - gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led1 { - label = "out1"; - gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "out2"; - gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "out3"; - gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led4 { - label = "out4"; - gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "out5"; - gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led6 { - label = "out6"; - gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led7 { - label = "out7"; - gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - /* Tricolor status LEDs */ - leds1 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>; - - led0 { - label = "status0:red:cpu0"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - led1 { - label = "status0:green:usr"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "status0:yellow:usr"; - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "status1:red:mmc0"; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - led4 { - label = "status1:green:usr"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "status1:yellow:usr"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - gpio-decoder { - compatible = "gpio-decoder"; - gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, - <&pca9536 2 GPIO_ACTIVE_HIGH>, - <&pca9536 1 GPIO_ACTIVE_HIGH>, - <&pca9536 0 GPIO_ACTIVE_HIGH>; - linux,axis = <0>; /* ABS_X */ - decoder-max-value = <9>; - }; -}; - -&am33xx_pinmux { - user_leds: user_leds { - pinctrl-single,pins = < - AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ - AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ - AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ - AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ - >; - }; - - mmc0_pins_default: mmc0_pins_default { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */ - >; - }; - - i2c0_pins_default: i2c0_pins_default { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ - >; - }; - - spi0_pins_default: spi0_pins_default { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ - >; - }; - - uart3_pins_default: uart3_pins_default { - pinctrl-single,pins = < - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_default>; - - status = "okay"; - clock-frequency = <400000>; - - tps: power-controller@2d { - reg = <0x2d>; - }; - - tpic2810: gpio@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9536: gpio@41 { - compatible = "ti,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1326000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_default>; -}; - -&gpio0 { - /* Do not idle the GPIO used for holding the VTT regulator */ - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-igep0033.dtsi b/software/linux/kernel/arch/arm/boot/dts/am335x-igep0033.dtsi deleted file mode 100644 index a5769a8f5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-igep0033.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -/* - * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x - * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - compatible = "gpio-leds"; - - led0 { - label = "com:green:user"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vmmc: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - nandflash_pins: pinmux_nandflash_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - >; - }; -}; - -&mac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rmii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rmii"; -}; - -&phy_sel { - rmii-clock-ext; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - ti,elm-id = <&elm>; - - /* MTD partition table */ - partition@0 { - label = "SPL"; - reg = <0x00000000 0x000080000>; - }; - - partition@1 { - label = "U-boot"; - reg = <0x00080000 0x001e0000>; - }; - - partition@2 { - label = "U-Boot Env"; - reg = <0x00260000 0x00020000>; - }; - - partition@3 { - label = "Kernel"; - reg = <0x00280000 0x00500000>; - }; - - partition@4 { - label = "File System"; - reg = <0x00780000 0x007880000>; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc>; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-always-on; - }; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-lxm.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-lxm.dts deleted file mode 100644 index 1d6c6fa70..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-lxm.dts +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "NovaTech OrionLXm"; - compatible = "novatech,am335x-lxm", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - /* Power supply provides a fixed 5V @2A */ - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; -}; - -&am33xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */ - - /* Slave 2 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */ - - /* Slave 2 reset value*/ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */ - AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */ - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - serial_config1: serial_config1@20 { - compatible = "nxp,pca9539"; - reg = <0x20>; - }; - - serial_config2: serial_config2@21 { - compatible = "nxp,pca9539"; - reg = <0x21>; - }; - - tps: tps@2d { - compatible = "ti,tps65910"; - reg = <0x2d>; - }; -}; - -/include/ "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - /* vrtc - unused */ - - vio_reg: regulator@1 { - regulator-name = "vio_1v5,ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd1,mpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd2_1v1,core"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd3 - unused */ - - /* vdig1 - unused */ - - vdig2_reg: regulator@6 { - regulator-name = "vdig2_1v8,vdds_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vpll - unused */ - - vdac_reg: regulator@8 { - regulator-name = "vdac_1v8,vdds"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-name = "vaux1_1v8,usb"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-name = "vaux2_3v3,io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-name = "vaux33_3v3,usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-name = "vmmc_3v3,io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <5>; - phy-mode = "rmii"; - dual_emac_res_vlan = <2>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <4>; - phy-mode = "rmii"; - dual_emac_res_vlan = <3>; -}; - -&phy_sel { - rmii-clock-ext; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; - status = "okay"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-nano.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-nano.dts deleted file mode 100644 index 483d585c8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-nano.dts +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "Newflow AM335x NanoBone"; - compatible = "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "nanobone:green:usr1"; - gpios = <&gpio1 5 0>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&misc_pins>; - - misc_pins: misc_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */ - >; - }; - - gpmc_pins: gpmc_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */ - - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */ - AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */ - AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */ - - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */ - - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */ - - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */ - >; - }; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - uart0_pins: uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart1_pins: uart1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */ - >; - }; - - uart2_pins: uart2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8c0, PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */ - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ - >; - }; - - uart3_pins: uart3_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8c8, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */ - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */ - AM33XX_IOPAD(0x964, PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ - >; - }; - - uart4_pins: uart4_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8d0, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */ - AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */ - AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */ - >; - }; - - uart5_pins: uart5_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */ - AM33XX_IOPAD(0x944, PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */ - >; - }; - - mmc1_pins: mmc1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ - AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rx-during-tx; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; - rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - - tps: tps@24 { - reg = <0x24>; - }; - - eeprom@53 { - compatible = "microchip,24c02"; - reg = <0x53>; - pagesize = <8>; - }; - - rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - status = "okay"; - gpmc,num-waitpins = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>; /* CS0: NOR 128M */ - - nor@0,0 { - reg = <0 0x00000000 0x08000000>; - compatible = "cfi-flash"; - linux,mtd-name = "spansion,s29gl010p11t"; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <10>; - gpmc,adv-rd-off-ns = <30>; - gpmc,adv-wr-off-ns = <30>; - gpmc,oe-on-ns = <40>; - gpmc,oe-off-ns = <160>; - gpmc,we-on-ns = <40>; - gpmc,we-off-ns = <160>; - gpmc,rd-cycle-ns = <160>; - gpmc,wr-cycle-ns = <160>; - gpmc,access-ns = <150>; - gpmc,page-burst-access-ns = <10>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-delay-ns = <20>; - gpmc,wr-data-mux-bus-ns = <70>; - gpmc,wr-access-ns = <80>; - - #address-cells = <1>; - #size-cells = <1>; - - /* - MTD partition table - =================== - +------------+-->0x00000000-> U-Boot start - | | - | |-->0x000BFFFF-> U-Boot end - | |-->0x000C0000-> ENV1 start - | | - | |-->0x000DFFFF-> ENV1 end - | |-->0x000E0000-> ENV2 start - | | - | |-->0x000FFFFF-> ENV2 end - | |-->0x00100000-> Kernel start - | | - | |-->0x004FFFFF-> Kernel end - | |-->0x00500000-> File system start - | | - | |-->0x01FFFFFF-> File system end - | |-->0x02000000-> User data start - | | - | |-->0x03FFFFFF-> User data end - | |-->0x04000000-> Data storage start - | | - +------------+-->0x08000000-> NOR end (Free end) - */ - partition@0 { - label = "boot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@1 { - label = "env1"; - reg = <0x000c0000 0x00020000>; /* 128KB */ - }; - - partition@2 { - label = "env2"; - reg = <0x000e0000 0x00020000>; /* 128KB */ - }; - - partition@3 { - label = "kernel"; - reg = <0x00100000 0x00400000>; /* 4MB */ - }; - - partition@4 { - label = "rootfs"; - reg = <0x00500000 0x01b00000>; /* 27MB */ - }; - - partition@5 { - label = "user"; - reg = <0x02000000 0x02000000>; /* 32MB */ - }; - - partition@6 { - label = "data"; - reg = <0x04000000 0x04000000>; /* 64MB */ - }; - }; -}; - -&mac { - dual_emac; - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "mii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "mii"; - dual_emac_res_vlan = <2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&ldo4_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; - cd-gpios = <&gpio3 8 0>; - wp-gpios = <&gpio3 18 0>; -}; - -#include "tps65217.dtsi" - -&tps { - regulators { - dcdc1_reg: regulator@0 { - /* +1.5V voltage with ±4% tolerance */ - regulator-min-microvolt = <1450000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <915000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <915000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* +1.8V voltage with ±4% tolerance */ - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1870000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - /* +3.3V voltage with ±4% tolerance */ - regulator-min-microvolt = <3175000>; - regulator-max-microvolt = <3430000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - /* +1.8V voltage with ±4% tolerance */ - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1870000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - /* +3.3V voltage with ±4% tolerance */ - regulator-min-microvolt = <3175000>; - regulator-max-microvolt = <3430000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-pepper.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-pepper.dts deleted file mode 100644 index 30e2f8770..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-pepper.dts +++ /dev/null @@ -1,656 +0,0 @@ -/* - * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include -#include "am33xx.dtsi" - -/ { - model = "Gumstix Pepper"; - compatible = "gumstix,am335x-pepper", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc3_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - buttons: user_buttons { - compatible = "gpio-keys"; - }; - - leds: user_leds { - compatible = "gpio-leds"; - }; - - panel: lcd_panel { - compatible = "ti,tilcdc,panel"; - }; - - sound: sound_iface { - compatible = "ti,da830-evm-audio"; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - }; - - v3v3c_reg: fixedregulator1 { - compatible = "regulator-fixed"; - }; - - vdd5_reg: fixedregulator2 { - compatible = "regulator-fixed"; - }; -}; - -/* I2C Busses */ -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - eeprom: eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - }; - - audio_codec: tlv320aic3106@1b { - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - ai3x-micbias-vg = <0x2>; - }; - - accel: lis331dlh@1d { - compatible = "st,lis3lv02d"; - reg = <0x1d>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; -}; - -&am33xx_pinmux { - i2c0_pins: pinmux_i2c0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - i2c1_pins: pinmux_i2c1 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x90C, PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */ - >; - }; -}; - -/* Accelerometer */ -&accel { - pinctrl-names = "default"; - pinctrl-0 = <&accel_pins>; - - Vdd-supply = <&ldo3_reg>; - Vdd_IO-supply = <&ldo3_reg>; - st,irq1-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <92>; - st,max-limit-x = <14>; - st,min-limit-y = <14>; - st,max-limit-y = <92>; - st,min-limit-z = <92>; - st,max-limit-z = <14>; -}; - -&am33xx_pinmux { - accel_pins: pinmux_accel { - pinctrl-single,pins = < - AM33XX_IOPAD(0x898, PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ - >; - }; -}; - -/* Audio */ -&audio_codec { - status = "okay"; - - gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>; - AVDD-supply = <&ldo3_reg>; - IOVDD-supply = <&ldo3_reg>; - DRVDD-supply = <&ldo3_reg>; - DVDD-supply = <&dcdc1_reg>; -}; - -&sound { - ti,model = "AM335x-EVM"; - ti,audio-codec = <&audio_codec>; - ti,mcasp-controller = <&mcasp0>; - ti,codec-clock-rate = <12000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "MIC3L", "Mic3L Switch"; -}; - -&mcasp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_pins>; - - op-mode = <0>; /* MCASP_ISS_MODE */ - tdm-slots = <2>; - serial-dir = < - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - -&am33xx_pinmux { - audio_pins: pinmux_audio { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */ - >; - }; -}; - -/* Display: 24-bit LCD Screen */ -&panel { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - native-mode = <&timing0>; - timing0: 480x272 { - clock-frequency = <18400000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vfront-porch = <4>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; -}; - -&lcdc { - status = "okay"; -}; - -&am33xx_pinmux { - lcd_pins: pinmux_lcd { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ - /* Display Enable */ - AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; -}; - -/* Ethernet */ -&cpsw_emac0 { - status = "okay"; - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii"; -}; - -&cpsw_emac1 { - status = "okay"; - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; -}; - -&davinci_mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; -}; - -&mac { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; -}; - - -&am33xx_pinmux { - ethernet_pins: pinmux_ethernet { - pinctrl-single,pins = < - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ - /* ethernet interrupt */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */ - /* ethernet PHY nReset */ - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */ - >; - }; - - mdio_pins: pinmux_mdio { - pinctrl-single,pins = < - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; -}; - -/* MMC */ -&mmc1 { - /* Bootable SD card slot */ - status = "okay"; - vmmc-supply = <&ldo3_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - /* eMMC (not populated) on MMC #2 */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&ldo3_reg>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - /* Wifi & Bluetooth on MMC #3 */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wireless_pins>; - vmmmc-supply = <&v3v3c_reg>; - bus-width = <4>; - ti,non-removable; - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; -}; - - -&am33xx_pinmux { - sd_pins: pinmux_sd_card { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - emmc_pins: pinmux_emmc { - pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - /* EMMC nReset */ - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - >; - }; - wireless_pins: pinmux_wireless { - pinctrl-single,pins = < - AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ - AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */ - AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */ - /* WLAN nReset */ - AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ - /* WLAN nPower down */ - AM33XX_IOPAD(0x870, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - /* 32kHz Clock */ - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&v3v3c_reg { - regulator-name = "v3v3c_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vbat>; -}; - -&vdd5_reg { - regulator-name = "vdd5_reg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vbat>; -}; - -/include/ "tps65217.dtsi" - -&tps { - backlight { - isel = <1>; /* ISET1 */ - fdim = <200>; /* TPS65217_BL_FDIM_200HZ */ - default-brightness = <80>; - }; - - regulators { - dcdc1_reg: regulator@0 { - /* VDD_1V8 system supply */ - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* VRTC 1.8V always-on supply */ - regulator-name = "vrtc,vdds"; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - /* 3.3V rail */ - regulator-name = "vdd_3v3aux"; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - /* VDD_3V3A 3.3V rail */ - regulator-name = "vdd_3v3a"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4_reg: regulator@6 { - /* VDD_3V3B 3.3V rail */ - regulator-name = "vdd_3v3b"; - regulator-always-on; - }; - }; -}; - -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; -}; - -&am33xx_pinmux { - spi0_pins: pinmux_spi0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ - >; - }; -}; - -/* Touch Screen */ -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -/* UARTs */ -&uart0 { - /* Serial Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - /* Broken out to J6 header */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&am33xx_pinmux { - uart0_pins: pinmux_uart0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - uart1_pins: pinmux_uart1 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ - >; - }; -}; - -/* USB */ -&usb { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins>; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&am33xx_pinmux { - usb_pins: pinmux_usb { - pinctrl-single,pins = < - /* USB0 Over-Current (active low) */ - AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */ - /* USB1 Over-Current (active low) */ - AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */ - >; - }; -}; - -/* User IO */ -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_pins>; - - led0 { - label = "pepper:user0:blue"; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - led1 { - label = "pepper:user1:red"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&user_buttons_pins>; - #address-cells = <1>; - #size-cells = <0>; - - button0 { - label = "home"; - linux,code = ; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button1 { - label = "menu"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - buttons2 { - label = "power"; - linux,code = ; - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - wakeup-source; - }; -}; - -&am33xx_pinmux { - user_leds_pins: pinmux_user_leds { - pinctrl-single,pins = < - AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - >; - }; - - user_buttons_pins: pinmux_user_buttons { - pinctrl-single,pins = < - AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x85C, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */ - AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-phycore-som.dtsi b/software/linux/kernel/arch/arm/boot/dts/am335x-phycore-som.dtsi deleted file mode 100644 index 75e24add3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "am33xx.dtsi" -#include - -/ { - model = "Phytec AM335x phyCORE"; - compatible = "phytec,am335x-phycore-som", "ti,am33xx"; - - aliases { - rtc0 = &i2c_rtc; - rtc1 = &rtc; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - regulators { - compatible = "simple-bus"; - - vcc5v: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -/* Crypto Module */ -&aes { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet0_pins: pinmux_ethernet0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ - >; - }; - - mdio_pins: pinmux_mdio { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - status = "okay"; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins>; - status = "okay"; -}; - -&phy_sel { - rmii-clock-ext; -}; - -/* I2C Busses */ -&am33xx_pinmux { - i2c0_pins: pinmux_i2c0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - status = "okay"; - - tps: pmic@2d { - reg = <0x2d>; - }; - - i2c_eeprom: eeprom@52 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x52>; - status = "disabled"; - }; - - i2c_rtc: rtc@68 { - compatible = "rv4162"; - reg = <0x68>; - status = "disabled"; - }; -}; - -/* NAND memory */ -&am33xx_pinmux { - nandflash_pins: pinmux_nandflash { - pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ - nandflash: nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <30>; - gpmc,cs-wr-off-ns = <30>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <30>; - gpmc,adv-wr-off-ns = <30>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <20>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <30>; - gpmc,access-ns = <30>; - gpmc,rd-cycle-ns = <30>; - gpmc,wr-cycle-ns = <30>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <50>; - gpmc,cycle2cycle-diffcsen; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <30>; - gpmc,wr-data-mux-bus-ns = <0>; - - ti,elm-id = <&elm>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "xload"; - reg = <0x0 0x20000>; - }; - partition@1 { - label = "xload_backup1"; - reg = <0x20000 0x20000>; - }; - partition@2 { - label = "xload_backup2"; - reg = <0x40000 0x20000>; - }; - partition@3 { - label = "xload_backup3"; - reg = <0x60000 0x20000>; - }; - partition@4 { - label = "barebox"; - reg = <0x80000 0x80000>; - }; - partition@5 { - label = "bareboxenv"; - reg = <0x100000 0x40000>; - }; - partition@6 { - label = "oftree"; - reg = <0x140000 0x40000>; - }; - partition@7 { - label = "kernel"; - reg = <0x180000 0x800000>; - }; - partition@8 { - label = "root"; - reg = <0x980000 0x0>; - }; - }; -}; - -/* Power */ -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vcc5v>; - vcc2-supply = <&vcc5v>; - vcc3-supply = <&vcc5v>; - vcc4-supply = <&vcc5v>; - vcc5-supply = <&vcc5v>; - vcc6-supply = <&vcc5v>; - vcc7-supply = <&vcc5v>; - vccio-supply = <&vcc5v>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-name = "vdig1_1p8v"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* SPI Busses */ -&am33xx_pinmux { - spi0_pins: pinmux_spi0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - >; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - serial_flash: m25p80@0 { - compatible = "m25p80"; - spi-max-frequency = <48000000>; - reg = <0x0>; - m25p,fast-read; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "xload"; - reg = <0x0 0x20000>; - }; - partition@1 { - label = "barebox"; - reg = <0x20000 0x80000>; - }; - partition@2 { - label = "bareboxenv"; - reg = <0xa0000 0x20000>; - }; - partition@3 { - label = "oftree"; - reg = <0xc0000 0x20000>; - }; - partition@4 { - label = "kernel"; - reg = <0xe0000 0x0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-sbc-t335.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-sbc-t335.dts deleted file mode 100644 index 917d7ccc9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-sbc-t335.dts +++ /dev/null @@ -1,219 +0,0 @@ -/* - * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 - * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "am335x-cm-t335.dts" - -/ { - model = "CompuLab CM-T335 on SB-T335"; - compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"; - - /* DRM display driver */ - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default>; - pinctrl-1 = <&lcd_pins_sleep>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - /* Timing selection performed by U-Boot */ - timing0: lcd {/* 800x480p62 */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <39>; - hback-porch = <39>; - hsync-len = <47>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <2>; - hsync-active = <1>; - vsync-active = <1>; - }; - timing1: dvi { /* 1024x768p60 */ - clock-frequency = <65000000>; - hactive = <1024>; - hfront-porch = <24>; - hback-porch = <160>; - hsync-len = <136>; - vactive = <768>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; -}; - -&am33xx_pinmux { - /* Display */ - lcd_pins_default: lcd_pins_default { - pinctrl-single,pins = < - /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) - /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) - /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) - /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) - /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) - /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) - /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) - /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) - /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) - /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) - /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) - /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) - /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) - /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) - /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) - /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) - /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) - /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) - /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) - /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) - /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) - /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) - /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) - /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) - /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) - /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) - /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) - /* lcd_ac_bias_en.lcd_ac_bias_en */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) - >; - }; - - lcd_pins_sleep: lcd_pins_sleep { - pinctrl-single,pins = < - /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) - /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) - /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) - /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) - /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) - /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) - /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) - /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) - /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) - /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) - /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) - /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) - /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) - /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) - /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) - /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) - /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) - /* lcd_ac_bias_en.lcd_ac_bias_en */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -}; - -&i2c0 { - /* GPIO extender */ - gpio_ext: pca9555@26 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x26>; - dvi_ena { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "dvi-enable"; - }; - lcd_ena { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "lcd-enable"; - }; - }; -}; - -/* Display */ -&lcdc { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-shc.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-shc.dts deleted file mode 100644 index bf8727a19..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-shc.dts +++ /dev/null @@ -1,577 +0,0 @@ -/* - * support for the bosch am335x based shc c3 board - * - * Copyright, C) 2015 Heiko Schocher - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include - -/ { - model = "Bosch SHC"; - compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx"; - - aliases { - mmcblk0 = &mmc1; - mmcblk1 = &mmc2; - }; - - cpus { - cpu@0 { - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 594000 1225000 - 294000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ - cpu0-supply = <&dcdc2_reg>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - back_button { - label = "Back Button"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <1000>; - wakeup-source; - }; - - front_button { - label = "Front Button"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <1000>; - wakeup-source; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led1 { - label = "shc:power:red"; - gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "shc:power:bl"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - default-state = "on"; - }; - - led3 { - label = "shc:lan:red"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led4 { - label = "shc:lan:bl"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "shc:cloud:red"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led6 { - label = "shc:cloud:bl"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&aes { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethernetphy0: ethernet-phy@0 { - reg = <0>; - smsc,disable-energy-detect; - }; -}; - -&epwmss1 { - status = "okay"; - - ehrpwm1: pwm@48302200 { - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; - status = "okay"; - }; -}; - -&gpio1 { - hmtc_rst { - gpio-hog; - gpios = <24 GPIO_ACTIVE_LOW>; - output-high; - line-name = "homematic_reset"; - }; - - hmtc_prog { - gpio-hog; - gpios = <27 GPIO_ACTIVE_LOW>; - output-high; - line-name = "homematic_program"; - }; -}; - -&gpio3 { - zgb_rst { - gpio-hog; - gpios = <18 GPIO_ACTIVE_LOW>; - output-low; - line-name = "zigbee_reset"; - }; - - zgb_boot { - gpio-hog; - gpios = <19 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "zigbee_boot"; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - at24@50 { - compatible = "at24,24c32"; - pagesize = <32>; - reg = <0x50>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - slaves = <1>; - cpsw_emac0: slave@4a100200 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "mii"; - phy-handle = <ðernetphy0>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <0x4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - cd-inverted; - max-frequency = <26000000>; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - max-frequency = <26000000>; - sd-uhs-sdr25; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - bus-width = <4>; - cap-power-off-card; - max-frequency = <26000000>; - sd-uhs-sdr25; - vmmc-supply = <&vmmcsd_fixed>; - status = "okay"; -}; - -&rtc { - ti,no-init; -}; - -&sham { - status = "okay"; -}; - -&tps { - compatible = "ti,tps65217"; - ti,pmic-shutdown-controller; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - dcdc1_reg: regulator@0 { - reg = <0>; - regulator-name = "vdds_dpr"; - regulator-compatible = "dcdc1"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1450000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - reg = <1>; - /* - * VDD_MPU voltage limits 0.95V - 1.26V with - * +/-4% tolerance - */ - regulator-compatible = "dcdc2"; - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <70000>; - }; - - dcdc3_reg: regulator@2 { - reg = <2>; - /* - * VDD_CORE voltage limits 0.95V - 1.1V with - * +/-4% tolerance - */ - regulator-name = "vdd_core"; - regulator-compatible = "dcdc3"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1125000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - reg = <3>; - regulator-name = "vio,vrtc,vdds"; - regulator-compatible = "ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - reg = <4>; - regulator-name = "vdd_3v3aux"; - regulator-compatible = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - reg = <5>; - regulator-name = "vdd_1v8"; - regulator-compatible = "ldo3"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - reg = <6>; - regulator-name = "vdd_3v3a"; - regulator-compatible = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - /* xdma_event_intr1.clkout2 */ - AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - ehrpwm1_pins: pinmux_ehrpwm1 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */ - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2) - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5) - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3) - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) - >; - }; - - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6) - >; - }; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7) - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-sl50.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-sl50.dts deleted file mode 100644 index b0dfa6f14..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-sl50.dts +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "Toby Churchill SL50 Series"; - compatible = "tcl,am335x-sl50", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - chosen { - stdout-path = &uart0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led0 { - label = "sl50:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "sl50:red:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "sl50:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "sl50:red:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - backlight0: disp0 { - compatible = "pwm-backlight"; - pwms = <&ehrpwm1 0 500000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <6>; - }; - - backlight1: disp1 { - compatible = "pwm-backlight"; - pwms = <&ehrpwm1 1 500000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - /* audio external oscillator */ - tlv320aic3x_mclk: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; /* 24.576MHz */ - }; - }; - - sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM335x-SL50"; - ti,audio-codec = <&audio_codec>; - ti,mcasp-controller = <&mcasp0>; - - clocks = <&tlv320aic3x_mclk>; - clock-names = "mclk"; - - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1R", "Line In", - "LINE1L", "Line In"; - }; - - emmc_pwrseq: pwrseq@0 { - compatible = "mmc-pwrseq-emmc"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pwrseq_pins>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&lwb_pins>; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rxd.i2c1_sda */ - AM33XX_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_txdi2c1_scl */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */ - >; - }; - - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; - - audio_pins: pinmux_audio_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ - >; - }; - - ehrpwm1_pins: pinmux_ehrpwm1a_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */ - >; - }; - - lwb_pins: pinmux_lwb_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ - /* AVR Programming - SPI Bus (bit bang) - Screen and Keyboard */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMOSI spi0_d0.gpio0_3 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMISO spi0_d1.gpio0_4 */ - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattSCLK spi0_clk.gpio0_2 */ - /* PDI Bus - Battery system */ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@24 { - reg = <0x24>; - }; - - eeprom: eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; - - audio_codec: tlv320aic3106@1b { - status = "okay"; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - - AVDD-supply = <&ldo4_reg>; - IOVDD-supply = <&ldo4_reg>; - DRVDD-supply = <&ldo4_reg>; - DVDD-supply = <&ldo3_reg>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - vmmc-supply = <&vmmcsd_fixed>; - mmc-pwrseq = <&emmc_pwrseq>; -}; - -&mcasp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_pins>; - - op-mode = <0>; /* MCASP_ISS_MODE */ - tdm-slots = <2>; - serial-dir = < - 2 0 1 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; -}; - -#include "tps65217.dtsi" - -&tps { - ti,pmic-shutdown-controller; - - interrupt-parent = <&intc>; - interrupts = <7>; /* NNMI */ - - regulators { - dcdc1_reg: regulator@0 { - /* VDDS_DDR */ - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* VRTC / VIO / VDDS*/ - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: regulator@4 { - /* VDD_3V3AUX */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo3_reg: regulator@5 { - /* VDD_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - /* VDD_3V3A */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "mii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "mii"; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; -}; - -&davinci_mdio { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&epwmss1 { - status = "okay"; -}; - -&ehrpwm1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-wega-rdk.dts b/software/linux/kernel/arch/arm/boot/dts/am335x-wega-rdk.dts deleted file mode 100644 index 6431b7db8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-wega-rdk.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "am335x-phycore-som.dtsi" -#include "am335x-wega.dtsi" - -/* SoM */ -&i2c_eeprom { - status = "okay"; -}; - -&i2c_rtc { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am335x-wega.dtsi b/software/linux/kernel/arch/arm/boot/dts/am335x-wega.dtsi deleted file mode 100644 index 02c67365c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am335x-wega.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (C) 2015 Phytec Messtechnik GmbH - * Author: Teresa Remmet - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - model = "Phytec AM335x phyBOARD-WEGA"; - compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; - - sound: sound_iface { - compatible = "ti,da830-evm-audio"; - }; - - regulators { - compatible = "simple-bus"; - - vcc3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; -}; - -/* Audio */ -&am33xx_pinmux { - mcasp0_pins: pinmux_mcasp0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ - >; - }; -}; - -&i2c0 { - tlv320aic3007: tlv320aic3007@18 { - compatible = "ti,tlv320aic3007"; - reg = <0x18>; - AVDD-supply = <&vcc3v3>; - IOVDD-supply = <&vcc3v3>; - DRVDD-supply = <&vcc3v3>; - DVDD-supply = <&vdig1_reg>; - status = "okay"; - }; -}; - -&mcasp0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < - 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ - >; - tx-num-evt = <16>; - rt-num-evt = <16>; - status = "okay"; -}; - -&sound { - ti,model = "AM335x-Wega"; - ti,audio-codec = <&tlv320aic3007>; - ti,mcasp-controller = <&mcasp0>; - ti,audio-routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - clocks = <&mcasp0_fck>; - clock-names = "mclk"; - status = "okay"; -}; - -/* CAN Busses */ -&am33xx_pinmux { - dcan1_pins: pinmux_dcan1 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -/* Ethernet */ -&am33xx_pinmux { - ethernet1_pins: pinmux_ethernet1 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ - >; - }; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "mii"; - dual_emac_res_vlan = <2>; -}; - -&mac { - slaves = <2>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet0_pins ðernet1_pins>; - dual_emac = <1>; -}; - -/* MMC */ -&am33xx_pinmux { - mmc1_pins: pinmux_mmc1 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&vcc3v3>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -/* Power */ -&vdig1_reg { - regulator-boot-on; - regulator-always-on; -}; - -/* UARTs */ -&am33xx_pinmux { - uart0_pins: pinmux_uart0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -/* USB */ -&cppi41dma { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am33xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/am33xx-clocks.dtsi deleted file mode 100644 index 8d8319590..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am33xx-clocks.dtsi +++ /dev/null @@ -1,646 +0,0 @@ -/* - * Device Tree Source for AM33xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <22>; - reg = <0x0040>; - }; - - adc_tsc_fck: adc_tsc_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan0_fck: dcan0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan1_fck: dcan1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp0_fck: mcasp0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp1_fck: mcasp1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex0_fck: smartreflex0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex1_fck: smartreflex1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sha0_fck: sha0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes0_fck: aes0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - rng_fck: rng_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; - - ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; - - ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; - }; -}; -&prcm_clocks { - clk_32768_ck: clk_32768_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_rc32k_ck: clk_rc32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_24000000_ck: virt_24000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - virt_25000000_ck: virt_25000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - dpll_core_ck: dpll_core_ck@490 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m4_ck: dpll_core_m4_ck@480 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0480>; - ti,index-starts-at-one; - }; - - dpll_core_m5_ck: dpll_core_m5_ck@484 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0484>; - ti,index-starts-at-one; - }; - - dpll_core_m6_ck: dpll_core_m6_ck@4d8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x04d8>; - ti,index-starts-at-one; - }; - - dpll_mpu_ck: dpll_mpu_ck@488 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - reg = <0x04a8>; - ti,index-starts-at-one; - }; - - dpll_ddr_ck: dpll_ddr_ck@494 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>; - }; - - dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - reg = <0x04a0>; - ti,index-starts-at-one; - }; - - dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_ddr_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_disp_ck: dpll_disp_ck@498 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; - }; - - dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_disp_ck>; - ti,max-div = <31>; - reg = <0x04a4>; - ti,index-starts-at-one; - ti,set-rate-parent; - }; - - dpll_per_ck: dpll_per_ck@48c { - #clock-cells = <0>; - compatible = "ti,am3-dpll-no-gate-j-type-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@4ac { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x04ac>; - ti,index-starts-at-one; - }; - - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - cefuse_fck: cefuse_fck@a20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <1>; - reg = <0x0a20>; - }; - - clk_24mhz: clk_24mhz { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - clkdiv32k_ck: clkdiv32k_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_24mhz>; - clock-mult = <1>; - clock-div = <732>; - }; - - clkdiv32k_ick: clkdiv32k_ick@14c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ck>; - ti,bit-shift = <1>; - reg = <0x014c>; - }; - - l3_gclk: l3_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - pruss_ocp_gclk: pruss_ocp_gclk@530 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; - reg = <0x0530>; - }; - - mmu_fck: mmu_fck@914 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_core_m4_ck>; - ti,bit-shift = <1>; - reg = <0x0914>; - }; - - timer1_fck: timer1_fck@528 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; - reg = <0x0528>; - }; - - timer2_fck: timer2_fck@508 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x0508>; - }; - - timer3_fck: timer3_fck@50c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x050c>; - }; - - timer4_fck: timer4_fck@510 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x0510>; - }; - - timer5_fck: timer5_fck@518 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x0518>; - }; - - timer6_fck: timer6_fck@51c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x051c>; - }; - - timer7_fck: timer7_fck@504 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x0504>; - }; - - usbotg_fck: usbotg_fck@47c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_ck>; - ti,bit-shift = <8>; - reg = <0x047c>; - }; - - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - ieee5000_fck: ieee5000_fck@e4 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_core_m4_div2_ck>; - ti,bit-shift = <1>; - reg = <0x00e4>; - }; - - wdt1_fck: wdt1_fck@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; - reg = <0x0538>; - }; - - l4_rtc_gclk: l4_rtc_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l4hs_gclk: l4hs_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3s_gclk: l3s_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4fw_gclk: l4fw_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4ls_gclk: l4ls_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sysclk_div_ck: sysclk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_125mhz_gclk: cpsw_125mhz_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; - reg = <0x0520>; - }; - - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; - reg = <0x053c>; - }; - - gpio0_dbclk: gpio0_dbclk@408 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&gpio0_dbclk_mux_ck>; - ti,bit-shift = <18>; - reg = <0x0408>; - }; - - gpio1_dbclk: gpio1_dbclk@ac { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00ac>; - }; - - gpio2_dbclk: gpio2_dbclk@b0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00b0>; - }; - - gpio3_dbclk: gpio3_dbclk@b4 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00b4>; - }; - - lcd_gclk: lcd_gclk@534 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; - reg = <0x0534>; - ti,set-rate-parent; - }; - - mmc_clk: mmc_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x052c>; - }; - - gfx_fck_div_ck: gfx_fck_div_ck@52c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x052c>; - ti,max-div = <2>; - }; - - sysclkout_pre_ck: sysclkout_pre_ck@700 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; - reg = <0x0700>; - }; - - clkout2_div_ck: clkout2_div_ck@700 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x0700>; - }; - - dbg_sysclk_ck: dbg_sysclk_ck@414 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <19>; - reg = <0x0414>; - }; - - dbg_clka_ck: dbg_clka_ck@414 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_core_m4_ck>; - ti,bit-shift = <30>; - reg = <0x0414>; - }; - - stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; - ti,bit-shift = <22>; - reg = <0x0414>; - }; - - trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; - ti,bit-shift = <20>; - reg = <0x0414>; - }; - - stm_clk_div_ck: stm_clk_div_ck@414 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&stm_pmd_clock_mux_ck>; - ti,bit-shift = <27>; - ti,max-div = <64>; - reg = <0x0414>; - ti,index-power-of-two; - }; - - trace_clk_div_ck: trace_clk_div_ck@414 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&trace_pmd_clk_mux_ck>; - ti,bit-shift = <24>; - ti,max-div = <64>; - reg = <0x0414>; - ti,index-power-of-two; - }; - - clkout2_ck: clkout2_ck@700 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout2_div_ck>; - ti,bit-shift = <7>; - reg = <0x0700>; - }; -}; - -&prcm_clockdomains { - clk_24mhz_clkdm: clk_24mhz_clkdm { - compatible = "ti,clockdomain"; - clocks = <&clkdiv32k_ick>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am33xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/am33xx.dtsi deleted file mode 100644 index a3277e643..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am33xx.dtsi +++ /dev/null @@ -1,945 +0,0 @@ -/* - * Device Tree Source for AM33XX SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -/ { - compatible = "ti,am33xx"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - d_can0 = &dcan0; - d_can1 = &dcan1; - usb0 = &usb0; - usb1 = &usb1; - phy0 = &usb0_phy; - phy1 = &usb1_phy; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 720000 1285000 - 600000 1225000 - 500000 1125000 - 275000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the AM33XX interconnect. - * The real AM33XX interconnect network is quite complex. Since - * it will not bring real advantage to represent that in DT - * for the moment, just use a fake OCP bus entry to represent - * the whole bus hierarchy. - */ - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - l4_wkup: l4_wkup@44c00000 { - compatible = "ti,am3-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x44c00000 0x280000>; - - wkup_m3: wkup_m3@100000 { - compatible = "ti,am3352-wkup-m3"; - reg = <0x100000 0x4000>, - <0x180000 0x2000>; - reg-names = "umem", "dmem"; - ti,hwmods = "wkup_m3"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; - - prcm: prcm@200000 { - compatible = "ti,am3-prcm"; - reg = <0x200000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@210000 { - compatible = "ti,am3-scm", "simple-bus"; - reg = <0x210000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x210000 0x2000>; - - am33xx_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x238>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7f>; - }; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am3352-wkup-m3-ipc"; - reg = <0x1324 0x24>; - interrupts = <78>; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <32>; - dma-masters = <&edma>; - }; - - scm_clockdomains: clockdomains { - }; - }; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,am33xx-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = <20 21>; - }; - - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; - }; - - gpio0: gpio@44e07000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x44e07000 0x1000>; - interrupts = <96>; - }; - - gpio1: gpio@4804c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4804c000 0x1000>; - interrupts = <98>; - }; - - gpio2: gpio@481ac000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x481ac000 0x1000>; - interrupts = <32>; - }; - - gpio3: gpio@481ae000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x481ae000 0x1000>; - interrupts = <62>; - }; - - uart0: serial@44e09000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - reg = <0x44e09000 0x2000>; - interrupts = <72>; - status = "disabled"; - dmas = <&edma 26 0>, <&edma 27 0>; - dma-names = "tx", "rx"; - }; - - uart1: serial@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - reg = <0x48022000 0x2000>; - interrupts = <73>; - status = "disabled"; - dmas = <&edma 28 0>, <&edma 29 0>; - dma-names = "tx", "rx"; - }; - - uart2: serial@48024000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - reg = <0x48024000 0x2000>; - interrupts = <74>; - status = "disabled"; - dmas = <&edma 30 0>, <&edma 31 0>; - dma-names = "tx", "rx"; - }; - - uart3: serial@481a6000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - reg = <0x481a6000 0x2000>; - interrupts = <44>; - status = "disabled"; - }; - - uart4: serial@481a8000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart5"; - clock-frequency = <48000000>; - reg = <0x481a8000 0x2000>; - interrupts = <45>; - status = "disabled"; - }; - - uart5: serial@481aa000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart6"; - clock-frequency = <48000000>; - reg = <0x481aa000 0x2000>; - interrupts = <46>; - status = "disabled"; - }; - - i2c0: i2c@44e0b000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - reg = <0x44e0b000 0x1000>; - interrupts = <70>; - status = "disabled"; - }; - - i2c1: i2c@4802a000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - reg = <0x4802a000 0x1000>; - interrupts = <71>; - status = "disabled"; - }; - - i2c2: i2c@4819c000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - reg = <0x4819c000 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - ti,needs-special-hs-handling; - dmas = <&edma_xbar 24 0 0 - &edma_xbar 25 0 0>; - dma-names = "tx", "rx"; - interrupts = <64>; - interrupt-parent = <&intc>; - reg = <0x48060000 0x1000>; - status = "disabled"; - }; - - mmc2: mmc@481d8000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&edma 2 0 - &edma 3 0>; - dma-names = "tx", "rx"; - interrupts = <28>; - interrupt-parent = <&intc>; - reg = <0x481d8000 0x1000>; - status = "disabled"; - }; - - mmc3: mmc@47810000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - interrupts = <29>; - interrupt-parent = <&intc>; - reg = <0x47810000 0x1000>; - status = "disabled"; - }; - - hwspinlock: spinlock@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - wdt2: wdt@44e35000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x44e35000 0x1000>; - interrupts = <91>; - }; - - dcan0: can@481cc000 { - compatible = "ti,am3352-d_can"; - ti,hwmods = "d_can0"; - reg = <0x481cc000 0x2000>; - clocks = <&dcan0_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 0>; - interrupts = <52>; - status = "disabled"; - }; - - dcan1: can@481d0000 { - compatible = "ti,am3352-d_can"; - ti,hwmods = "d_can1"; - reg = <0x481d0000 0x2000>; - clocks = <&dcan1_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 1>; - interrupts = <55>; - status = "disabled"; - }; - - mailbox: mailbox@480C8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480C8000 0x200>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { - ti,mbox-send-noirq; - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; - }; - - timer1: timer@44e31000 { - compatible = "ti,am335x-timer-1ms"; - reg = <0x44e31000 0x400>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@48040000 { - compatible = "ti,am335x-timer"; - reg = <0x48040000 0x400>; - interrupts = <68>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48042000 { - compatible = "ti,am335x-timer"; - reg = <0x48042000 0x400>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48044000 { - compatible = "ti,am335x-timer"; - reg = <0x48044000 0x400>; - interrupts = <92>; - ti,hwmods = "timer4"; - ti,timer-pwm; - }; - - timer5: timer@48046000 { - compatible = "ti,am335x-timer"; - reg = <0x48046000 0x400>; - interrupts = <93>; - ti,hwmods = "timer5"; - ti,timer-pwm; - }; - - timer6: timer@48048000 { - compatible = "ti,am335x-timer"; - reg = <0x48048000 0x400>; - interrupts = <94>; - ti,hwmods = "timer6"; - ti,timer-pwm; - }; - - timer7: timer@4804a000 { - compatible = "ti,am335x-timer"; - reg = <0x4804a000 0x400>; - interrupts = <95>; - ti,hwmods = "timer7"; - ti,timer-pwm; - }; - - rtc: rtc@44e3e000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x44e3e000 0x1000>; - interrupts = <75 - 76>; - ti,hwmods = "rtc"; - }; - - spi0: spi@48030000 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x48030000 0x400>; - interrupts = <65>; - ti,spi-num-cs = <2>; - ti,hwmods = "spi0"; - dmas = <&edma 16 0 - &edma 17 0 - &edma 18 0 - &edma 19 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - - spi1: spi@481a0000 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x481a0000 0x400>; - interrupts = <125>; - ti,spi-num-cs = <2>; - ti,hwmods = "spi1"; - dmas = <&edma 42 0 - &edma 43 0 - &edma 44 0 - &edma 45 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - - usb: usb@47400000 { - compatible = "ti,am33xx-usb"; - reg = <0x47400000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - status = "disabled"; - - usb_ctrl_mod: control@44e10620 { - compatible = "ti,am335x-usb-ctrl-module"; - reg = <0x44e10620 0x10 - 0x44e10648 0x4>; - reg-names = "phy_ctrl", "wakeup"; - status = "disabled"; - }; - - usb0_phy: usb-phy@47401300 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401300 0x100>; - reg-names = "phy"; - status = "disabled"; - ti,ctrl_mod = <&usb_ctrl_mod>; - }; - - usb0: usb@47401000 { - compatible = "ti,musb-am33xx"; - status = "disabled"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb0_phy>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1_phy: usb-phy@47401b00 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401b00 0x100>; - reg-names = "phy"; - status = "disabled"; - ti,ctrl_mod = <&usb_ctrl_mod>; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-am33xx"; - status = "disabled"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb1_phy>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - status = "disabled"; - }; - }; - - epwmss0: epwmss@48300000 { - compatible = "ti,am33xx-pwmss"; - reg = <0x48300000 0x10>; - ti,hwmods = "epwmss0"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0x48300100 0x48300100 0x80 /* ECAP */ - 0x48300180 0x48300180 0x80 /* EQEP */ - 0x48300200 0x48300200 0x80>; /* EHRPWM */ - - ecap0: ecap@48300100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48300100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <31>; - interrupt-names = "ecap0"; - status = "disabled"; - }; - - ehrpwm0: pwm@48300200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48300200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss1: epwmss@48302000 { - compatible = "ti,am33xx-pwmss"; - reg = <0x48302000 0x10>; - ti,hwmods = "epwmss1"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0x48302100 0x48302100 0x80 /* ECAP */ - 0x48302180 0x48302180 0x80 /* EQEP */ - 0x48302200 0x48302200 0x80>; /* EHRPWM */ - - ecap1: ecap@48302100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48302100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <47>; - interrupt-names = "ecap1"; - status = "disabled"; - }; - - ehrpwm1: pwm@48302200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48302200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss2: epwmss@48304000 { - compatible = "ti,am33xx-pwmss"; - reg = <0x48304000 0x10>; - ti,hwmods = "epwmss2"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0x48304100 0x48304100 0x80 /* ECAP */ - 0x48304180 0x48304180 0x80 /* EQEP */ - 0x48304200 0x48304200 0x80>; /* EHRPWM */ - - ecap2: ecap@48304100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48304100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <61>; - interrupt-names = "ecap2"; - status = "disabled"; - }; - - ehrpwm2: pwm@48304200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48304200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - mac: ethernet@4a100000 { - compatible = "ti,am335x-cpsw","ti,cpsw"; - ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - no_bd_ram = <0>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - reg = <0x4a100000 0x800 - 0x4a101200 0x100>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - /* - * c0_rx_thresh_pend - * c0_rx_pend - * c0_tx_pend - * c0_misc_pend - */ - interrupts = <40 41 42 43>; - ranges; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@4a101000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - reg = <0x4a101000 0x100>; - status = "disabled"; - }; - - cpsw_emac0: slave@4a100200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpsw_emac1: slave@4a100300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; - }; - }; - - ocmcram: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x10000>; /* 64k */ - }; - - elm: elm@48080000 { - compatible = "ti,am3352-elm"; - reg = <0x48080000 0x2000>; - interrupts = <4>; - ti,hwmods = "elm"; - status = "disabled"; - }; - - lcdc: lcdc@4830e000 { - compatible = "ti,am33xx-tilcdc"; - reg = <0x4830e000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <36>; - ti,hwmods = "lcdc"; - status = "disabled"; - }; - - tscadc: tscadc@44e0d000 { - compatible = "ti,am3359-tscadc"; - reg = <0x44e0d000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <16>; - ti,hwmods = "adc_tsc"; - status = "disabled"; - - tsc { - compatible = "ti,am3359-tsc"; - }; - am335x_adc: adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - ti,no-idle-on-init; - reg = <0x50000000 0x2000>; - interrupts = <100>; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - sham: sham@53100000 { - compatible = "ti,omap4-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x200>; - interrupts = <109>; - dmas = <&edma 36 0>; - dma-names = "rx"; - }; - - aes: aes@53500000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x53500000 0xa0>; - interrupts = <103>; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; - }; - - mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - - mcasp1: mcasp@4803C000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x4803C000 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <82>, <83>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; - - rng: rng@48310000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48310000 0x2000>; - interrupts = <111>; - }; - }; -}; - -/include/ "am33xx-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/am3517-craneboard.dts b/software/linux/kernel/arch/arm/boot/dts/am3517-craneboard.dts deleted file mode 100644 index 083ff5073..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am3517-craneboard.dts +++ /dev/null @@ -1,174 +0,0 @@ -/* - * See craneboard.org for more details - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am3517.dtsi" - -/ { - model = "TI AM3517 CraneBoard (TMDSEVM3517)"; - compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&davinci_emac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <2600000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - /* goes to expansion connector */ - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <400000>; - /* goes to expansion connector */ - status = "disabled"; -}; - -&mmc1 { - vmmc-supply = <&vdd2_reg>; - bus-width = <8>; -}; - -&mmc2 { - /* goes to expansion connector */ - status = "disabled"; -}; - -&mmc3 { - /* goes to expansion connector */ - status = "disabled"; -}; - -#include "tps65910.dtsi" - -&omap3_pmx_core { - tps_pins: pinmux_tps_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ - >; - }; -}; - -&tps { - pinctrl-names = "default"; - pinctrl-0 = <&tps_pins>; - - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - ti,en-ck32k-xtal; - - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - /* - * Unused: - * VDIG1=2.7V,300mA max - * VDIG2=1.8V,300mA max - */ - - vpll_reg: regulator@7 { - /* VDDS_DPLL_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - /* VDDS_SRAM_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - /* VDDA1P8V_USBPHY */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* VAUX33 unused */ - - vdac_reg: regulator@8 { - /* VDDA_DAC_1V8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - /* VDDA3P3V_USBPHY */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_CORE */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDDSHV_3V3 */ - regulator-name = "vdd_shv"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* VDD3 unused */ - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am3517-evm.dts b/software/linux/kernel/arch/arm/boot/dts/am3517-evm.dts deleted file mode 100644 index 0e4a125f7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am3517-evm.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am3517.dtsi" - -/ { - model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; - compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vmmc_fixed: vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&davinci_emac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc_fixed>; - bus-width = <4>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/am3517.dtsi b/software/linux/kernel/arch/arm/boot/dts/am3517.dtsi deleted file mode 100644 index 0db19d39d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am3517.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Device Tree Source for am3517 SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "omap3.dtsi" - -/ { - aliases { - serial3 = &uart4; - }; - - ocp@68000000 { - am35x_otg_hs: am35x_otg_hs@5c040000 { - compatible = "ti,omap3-musb"; - ti,hwmods = "am35x_otg_hs"; - status = "disabled"; - reg = <0x5c040000 0x1000>; - interrupts = <71>; - interrupt-names = "mc"; - }; - - davinci_emac: ethernet@0x5c000000 { - compatible = "ti,am3517-emac"; - ti,hwmods = "davinci_emac"; - status = "disabled"; - reg = <0x5c000000 0x30000>; - interrupts = <67 68 69 70>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0x10000>; - ti,davinci-ctrl-mod-reg-offset = <0>; - ti,davinci-ctrl-ram-offset = <0x20000>; - ti,davinci-ctrl-ram-size = <0x2000>; - ti,davinci-rmii-en = /bits/ 8 <1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - - davinci_mdio: ethernet@0x5c030000 { - compatible = "ti,davinci_mdio"; - ti,hwmods = "davinci_mdio"; - status = "disabled"; - reg = <0x5c030000 0x1000>; - bus_freq = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart4: serial@4809e000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart4"; - status = "disabled"; - reg = <0x4809e000 0x400>; - interrupts = <84>; - dmas = <&sdma 55 &sdma 54>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - omap3_pmx_core2: pinmux@480025d8 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025d8 0x24>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - }; -}; - -&iva { - status = "disabled"; -}; - -&mailbox { - status = "disabled"; -}; - -&mmu_isp { - status = "disabled"; -}; - -&smartreflex_mpu_iva { - status = "disabled"; -}; - -/include/ "am35xx-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/am3517_mt_ventoux.dts b/software/linux/kernel/arch/arm/boot/dts/am3517_mt_ventoux.dts deleted file mode 100644 index 3395783c5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am3517_mt_ventoux.dts +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2011 Ilya Yanok, EmCraft Systems - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TeeJet Mt.Ventoux"; - compatible = "teejet,mt_ventoux", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - /* AM35xx doesn't have IVA */ - soc { - iva { - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am35xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/am35xx-clocks.dtsi deleted file mode 100644 index 00dd1f091..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am35xx-clocks.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Device Tree Source for OMAP3 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&scm_clocks { - emac_ick: emac_ick@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <1>; - }; - - emac_fck: emac_fck@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&rmii_ck>; - reg = <0x032c>; - ti,bit-shift = <9>; - }; - - vpfe_ick: vpfe_ick@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <2>; - }; - - vpfe_fck: vpfe_fck@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pclk_ck>; - reg = <0x032c>; - ti,bit-shift = <10>; - }; - - hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <0>; - }; - - hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x032c>; - ti,bit-shift = <8>; - }; - - hecc_ck: hecc_ck@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&sys_ck>; - reg = <0x032c>; - ti,bit-shift = <3>; - }; -}; -&cm_clocks { - ipss_ick: ipss_ick@a10 { - #clock-cells = <0>; - compatible = "ti,am35xx-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - rmii_ck: rmii_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - pclk_ck: pclk_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - uart4_ick_am35xx: uart4_ick_am35xx@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; - - uart4_fck_am35xx: uart4_fck_am35xx@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, - <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, - <&hecc_ck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, - <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am4372.dtsi b/software/linux/kernel/arch/arm/boot/dts/am4372.dtsi deleted file mode 100644 index c9c9a4744..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am4372.dtsi +++ /dev/null @@ -1,1177 +0,0 @@ -/* - * Device Tree Source for AM4372 SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -/ { - compatible = "ti,am4372", "ti,am43"; - interrupt-parent = <&wakeupgen>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - spi0 = &qspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - operating-points-v2 = <&cpu0_opp_table>; - ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>; - ti,syscon-rev = <&scm_conf 0x600>; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - - opp50@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000 931000 969000>; - opp-supported-hw = <0xFF 0x01>; - opp-suspend; - }; - - opp100@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0xFF 0x04>; - }; - - opp120@720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0xFF 0x08>; - }; - - oppturbo@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0xFF 0x10>; - }; - - oppnitro@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1325000 1298500 1351500>; - opp-supported-hw = <0xFF 0x20>; - }; - }; - - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; - - scu: scu@48240000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x48240000 0x100>; - }; - - global_timer: timer@48240200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x48240200 0x100>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&mpu_periphclk>; - }; - - local_timer: timer@48240600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x48240600 0x100>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&mpu_periphclk>; - }; - - l2-cache-controller@48242000 { - compatible = "arm,pl310-cache"; - reg = <0x48242000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - ocp@44000000 { - compatible = "ti,am4372-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - reg = <0x44000000 0x400000 - 0x44800000 0x400000>; - interrupts = , - ; - - l4_wkup: l4_wkup@44c00000 { - compatible = "ti,am4-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x44c00000 0x287000>; - - wkup_m3: wkup_m3@100000 { - compatible = "ti,am4372-wkup-m3"; - reg = <0x100000 0x4000>, - <0x180000 0x2000>; - reg-names = "umem", "dmem"; - ti,hwmods = "wkup_m3"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; - - prcm: prcm@1f0000 { - compatible = "ti,am4-prcm"; - reg = <0x1f0000 0x11000>; - interrupts = ; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@210000 { - compatible = "ti,am4-scm", "simple-bus"; - reg = <0x210000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x210000 0x4000>; - - am43xx_pinmux: pinmux@800 { - compatible = "ti,am437-padconf", - "pinctrl-single"; - reg = <0x800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am4372-wkup-m3-ipc"; - reg = <0x1324 0x44>; - interrupts = ; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <64>; - dma-masters = <&edma>; - }; - - scm_clockdomains: clockdomains { - }; - }; - }; - - emif: emif@4c000000 { - compatible = "ti,emif-am4372"; - reg = <0x4c000000 0x1000000>; - ti,hwmods = "emif"; - }; - - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = <58 59>; - }; - - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - uart0: serial@44e09000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x44e09000 0x2000>; - interrupts = ; - ti,hwmods = "uart1"; - }; - - uart1: serial@48022000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x48022000 0x2000>; - interrupts = ; - ti,hwmods = "uart2"; - status = "disabled"; - }; - - uart2: serial@48024000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x48024000 0x2000>; - interrupts = ; - ti,hwmods = "uart3"; - status = "disabled"; - }; - - uart3: serial@481a6000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481a6000 0x2000>; - interrupts = ; - ti,hwmods = "uart4"; - status = "disabled"; - }; - - uart4: serial@481a8000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481a8000 0x2000>; - interrupts = ; - ti,hwmods = "uart5"; - status = "disabled"; - }; - - uart5: serial@481aa000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481aa000 0x2000>; - interrupts = ; - ti,hwmods = "uart6"; - status = "disabled"; - }; - - mailbox: mailbox@480C8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480C8000 0x200>; - interrupts = ; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { - ti,mbox-send-noirq; - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; - }; - - timer1: timer@44e31000 { - compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; - reg = <0x44e31000 0x400>; - interrupts = ; - ti,timer-alwon; - ti,hwmods = "timer1"; - }; - - timer2: timer@48040000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48040000 0x400>; - interrupts = ; - ti,hwmods = "timer2"; - }; - - timer3: timer@48042000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48042000 0x400>; - interrupts = ; - ti,hwmods = "timer3"; - status = "disabled"; - }; - - timer4: timer@48044000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48044000 0x400>; - interrupts = ; - ti,timer-pwm; - ti,hwmods = "timer4"; - status = "disabled"; - }; - - timer5: timer@48046000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48046000 0x400>; - interrupts = ; - ti,timer-pwm; - ti,hwmods = "timer5"; - status = "disabled"; - }; - - timer6: timer@48048000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48048000 0x400>; - interrupts = ; - ti,timer-pwm; - ti,hwmods = "timer6"; - status = "disabled"; - }; - - timer7: timer@4804a000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4804a000 0x400>; - interrupts = ; - ti,timer-pwm; - ti,hwmods = "timer7"; - status = "disabled"; - }; - - timer8: timer@481c1000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x481c1000 0x400>; - interrupts = ; - ti,hwmods = "timer8"; - status = "disabled"; - }; - - timer9: timer@4833d000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4833d000 0x400>; - interrupts = ; - ti,hwmods = "timer9"; - status = "disabled"; - }; - - timer10: timer@4833f000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4833f000 0x400>; - interrupts = ; - ti,hwmods = "timer10"; - status = "disabled"; - }; - - timer11: timer@48341000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48341000 0x400>; - interrupts = ; - ti,hwmods = "timer11"; - status = "disabled"; - }; - - counter32k: counter@44e86000 { - compatible = "ti,am4372-counter32k","ti,omap-counter32k"; - reg = <0x44e86000 0x40>; - ti,hwmods = "counter_32k"; - }; - - rtc: rtc@44e3e000 { - compatible = "ti,am4372-rtc", "ti,am3352-rtc", - "ti,da830-rtc"; - reg = <0x44e3e000 0x1000>; - interrupts = ; - ti,hwmods = "rtc"; - clocks = <&clk_32768_ck>; - clock-names = "int-clk"; - status = "disabled"; - }; - - wdt: wdt@44e35000 { - compatible = "ti,am4372-wdt","ti,omap3-wdt"; - reg = <0x44e35000 0x1000>; - interrupts = ; - ti,hwmods = "wd_timer2"; - }; - - gpio0: gpio@44e07000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x44e07000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio1"; - status = "disabled"; - }; - - gpio1: gpio@4804c000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x4804c000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio2"; - status = "disabled"; - }; - - gpio2: gpio@481ac000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x481ac000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio3"; - status = "disabled"; - }; - - gpio3: gpio@481ae000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x481ae000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio4"; - status = "disabled"; - }; - - gpio4: gpio@48320000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x48320000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio5"; - status = "disabled"; - }; - - gpio5: gpio@48322000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x48322000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio6"; - status = "disabled"; - }; - - hwspinlock: spinlock@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - i2c0: i2c@44e0b000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x44e0b000 0x1000>; - interrupts = ; - ti,hwmods = "i2c1"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@4802a000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x4802a000 0x1000>; - interrupts = ; - ti,hwmods = "i2c2"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@4819c000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x4819c000 0x1000>; - interrupts = ; - ti,hwmods = "i2c3"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@48030000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x48030000 0x400>; - interrupts = ; - ti,hwmods = "spi0"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x48060000 0x1000>; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&edma 24 0>, - <&edma 25 0>; - dma-names = "tx", "rx"; - interrupts = ; - status = "disabled"; - }; - - mmc2: mmc@481d8000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x481d8000 0x1000>; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&edma 2 0>, - <&edma 3 0>; - dma-names = "tx", "rx"; - interrupts = ; - status = "disabled"; - }; - - mmc3: mmc@47810000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x47810000 0x1000>; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - interrupts = ; - status = "disabled"; - }; - - spi1: spi@481a0000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a0000 0x400>; - interrupts = ; - ti,hwmods = "spi1"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@481a2000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a2000 0x400>; - interrupts = ; - ti,hwmods = "spi2"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@481a4000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a4000 0x400>; - interrupts = ; - ti,hwmods = "spi3"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@48345000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x48345000 0x400>; - interrupts = ; - ti,hwmods = "spi4"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mac: ethernet@4a100000 { - compatible = "ti,am4372-cpsw","ti,cpsw"; - reg = <0x4a100000 0x800 - 0x4a101200 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, - <&dpll_clksel_mac_clk>; - clock-names = "fck", "cpts", "50mclk"; - assigned-clocks = <&dpll_clksel_mac_clk>; - assigned-clock-rates = <50000000>; - status = "disabled"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - no_bd_ram = <0>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - ranges; - syscon = <&scm_conf>; - - davinci_mdio: mdio@4a101000 { - compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x4a101000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpsw_emac0: slave@4a100200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpsw_emac1: slave@4a100300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am43xx-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; - }; - }; - - epwmss0: epwmss@48300000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48300000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss0"; - status = "disabled"; - - ecap0: ecap@48300100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48300100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm0: pwm@48300200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48300200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss1: epwmss@48302000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48302000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss1"; - status = "disabled"; - - ecap1: ecap@48302100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48302100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm1: pwm@48302200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48302200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss2: epwmss@48304000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48304000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss2"; - status = "disabled"; - - ecap2: ecap@48304100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48304100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm2: pwm@48304200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48304200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss3: epwmss@48306000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48306000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss3"; - status = "disabled"; - - ehrpwm3: pwm@48306200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48306200 0x80>; - clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss4: epwmss@48308000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48308000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss4"; - status = "disabled"; - - ehrpwm4: pwm@48308200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48308200 0x80>; - clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss5: epwmss@4830a000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x4830a000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss5"; - status = "disabled"; - - ehrpwm5: pwm@4830a200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x4830a200 0x80>; - clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - tscadc: tscadc@44e0d000 { - compatible = "ti,am3359-tscadc"; - reg = <0x44e0d000 0x1000>; - ti,hwmods = "adc_tsc"; - interrupts = ; - clocks = <&adc_tsc_fck>; - clock-names = "fck"; - status = "disabled"; - - tsc { - compatible = "ti,am3359-tsc"; - }; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - - }; - - sham: sham@53100000 { - compatible = "ti,omap5-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x300>; - dmas = <&edma 36 0>; - dma-names = "rx"; - interrupts = ; - }; - - aes: aes@53501000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x53501000 0xa0>; - interrupts = ; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; - }; - - des: des@53701000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x53701000 0xa0>; - interrupts = ; - dmas = <&edma 34 0>, - <&edma 33 0>; - dma-names = "tx", "rx"; - }; - - rng: rng@48310000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48310000 0x2000>; - interrupts = ; - }; - - mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - - mcasp1: mcasp@4803C000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x4803C000 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; - - elm: elm@48080000 { - compatible = "ti,am3352-elm"; - reg = <0x48080000 0x2000>; - interrupts = ; - ti,hwmods = "elm"; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - clocks = <&l3s_gclk>; - clock-names = "fck"; - reg = <0x50000000 0x2000>; - interrupts = ; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - ocp2scp0: ocp2scp@483a8000 { - compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp0"; - - usb2_phy1: phy@483a8000 { - compatible = "ti,am437x-usb2"; - reg = <0x483a8000 0x8000>; - syscon-phy-power = <&scm_conf 0x620>; - clocks = <&usb_phy0_always_on_clk32k>, - <&usb_otg_ss0_refclk960m>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - ocp2scp1: ocp2scp@483e8000 { - compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp1"; - - usb2_phy2: phy@483e8000 { - compatible = "ti,am437x-usb2"; - reg = <0x483e8000 0x8000>; - syscon-phy-power = <&scm_conf 0x628>; - clocks = <&usb_phy1_always_on_clk32k>, - <&usb_otg_ss1_refclk960m>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - dwc3_1: omap_dwc3@48380000 { - compatible = "ti,am437x-dwc3"; - ti,hwmods = "usb_otg_ss0"; - reg = <0x48380000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <1>; - ranges; - - usb1: usb@48390000 { - compatible = "synopsys,dwc3"; - reg = <0x48390000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - status = "disabled"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - - dwc3_2: omap_dwc3@483c0000 { - compatible = "ti,am437x-dwc3"; - ti,hwmods = "usb_otg_ss1"; - reg = <0x483c0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <1>; - ranges; - - usb2: usb@483d0000 { - compatible = "synopsys,dwc3"; - reg = <0x483d0000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - status = "disabled"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - - qspi: qspi@47900000 { - compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>, - <0x30000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "qspi"; - interrupts = <0 138 0x4>; - num-cs = <4>; - status = "disabled"; - }; - - hdq: hdq@48347000 { - compatible = "ti,am4372-hdq"; - reg = <0x48347000 0x1000>; - interrupts = ; - clocks = <&func_12m_clk>; - clock-names = "fck"; - ti,hwmods = "hdq1w"; - status = "disabled"; - }; - - dss: dss@4832a000 { - compatible = "ti,omap3-dss"; - reg = <0x4832a000 0x200>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&disp_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc: dispc@4832a400 { - compatible = "ti,omap3-dispc"; - reg = <0x4832a400 0x400>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&disp_clk>; - clock-names = "fck"; - }; - - rfbi: rfbi@4832a800 { - compatible = "ti,omap3-rfbi"; - reg = <0x4832a800 0x100>; - ti,hwmods = "dss_rfbi"; - clocks = <&disp_clk>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - ocmcram: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x40000>; /* 256k */ - }; - - dcan0: can@481cc000 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - ti,hwmods = "d_can0"; - clocks = <&dcan0_fck>; - clock-names = "fck"; - reg = <0x481cc000 0x2000>; - syscon-raminit = <&scm_conf 0x644 0>; - interrupts = ; - status = "disabled"; - }; - - dcan1: can@481d0000 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - ti,hwmods = "d_can1"; - clocks = <&dcan1_fck>; - clock-names = "fck"; - reg = <0x481d0000 0x2000>; - syscon-raminit = <&scm_conf 0x644 1>; - interrupts = ; - status = "disabled"; - }; - - vpfe0: vpfe@48326000 { - compatible = "ti,am437x-vpfe"; - reg = <0x48326000 0x2000>; - interrupts = ; - ti,hwmods = "vpfe0"; - status = "disabled"; - }; - - vpfe1: vpfe@48328000 { - compatible = "ti,am437x-vpfe"; - reg = <0x48328000 0x2000>; - interrupts = ; - ti,hwmods = "vpfe1"; - status = "disabled"; - }; - }; -}; - -/include/ "am43xx-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/am437x-cm-t43.dts b/software/linux/kernel/arch/arm/boot/dts/am437x-cm-t43.dts deleted file mode 100644 index 3b9a94c27..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am437x-cm-t43.dts +++ /dev/null @@ -1,415 +0,0 @@ -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include -#include -#include -#include "am4372.dtsi" - -/ { - model = "CompuLab CM-T43"; - compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; - - leds { - compatible = "gpio-leds"; - - ledb { - label = "cm-t43:green"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vmmc_3v3: fixedregulator-v3_3 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - }; -}; - -&am43xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&cm_t43_led_pins>; - - cm_t43_led_pins: cm_t43_led_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa78, MUX_MODE7) - >; - }; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - emmc_pins: emmc_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */ - AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */ - AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */ - AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */ - AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */ - AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */ - AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */ - AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - >; - }; - - spi0_pins: pinmux_spi0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ - AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - >; - }; - - nand_flash_x8: nand_flash_x8 { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0) - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ - AM4372_IOPAD(0xa74, MUX_MODE3) - /* Slave 2 */ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.txen */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rxctl */ - AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.txd3 */ - AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.txd2 */ - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.txd1 */ - AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.txd0 */ - AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */ - AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rclk */ - AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rxd3 */ - AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rxd2 */ - AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rxd1 */ - AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rxd0 */ - AM4372_IOPAD(0xa38, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x1000000>; - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - /* MTD partition table */ - partition@0 { - label = "kernel"; - reg = <0x0 0x00980000>; - }; - partition@980000 { - label = "dtb"; - reg = <0x00980000 0x00080000>; - }; - partition@a00000 { - label = "rootfs"; - reg = <0x00a00000 0x0>; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps65218: tps65218@24 { - compatible = "ti,tps65218"; - reg = <0x24>; - interrupts = ; /* NMIn */ - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-suspend-enable; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - eeprom_module: at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - vmmc-supply = <&vmmc_3v3>; - bus-width = <8>; - ti,non-removable; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - dmas = <&edma 16 0 - &edma 17 0>; - dma-names = "tx0", "rx0"; - - flash: w25q64cvzpig@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - partition@0 { - label = "uboot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "uboot environment"; - reg = <0xc0000 0x40000>; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x100000>; - }; - }; -}; - -&mac { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; -}; - -&dwc3_1 { - status = "okay"; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - status = "okay"; -}; - -&dwc3_2 { - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; - interrupts = , - , - ; - interrupt-names = "peripheral", "host", "otg"; -}; - -&elm { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordiante-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&cpu { - cpu0-supply = <&dcdc2>; - operating-points = <1000000 1330000>, - <800000 1260000>, - <720000 1200000>, - <600000 1100000>, - <300000 950000>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am437x-gp-evm.dts b/software/linux/kernel/arch/arm/boot/dts/am437x-gp-evm.dts deleted file mode 100644 index 957840cc7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am437x-gp-evm.dts +++ /dev/null @@ -1,988 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* AM437x GP EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include - -/ { - model = "TI AM437x GP EVM"; - compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - evm_v3_3d: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "evm_v3_3d"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator-vtt { - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; - }; - - vmmcwl_fixed: fixedregulator-mmcwl { - compatible = "regulator-fixed"; - regulator-name = "vmmcwl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */ - &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ - &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ - - col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ - &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x00010202 /* P2 */ - 0x01000067 /* UP */ - 0x0101006a /* RIGHT */ - 0x02000069 /* LEFT */ - 0x0201006c>; /* DOWN */ - }; - - lcd0: display { - compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; - label = "lcd"; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <16>; - hsync-len = <30>; - vback-porch = <10>; - vfront-porch = <22>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - /* fixed 12MHz oscillator */ - refclk: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM437x-GP-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - system-clock-frequency = <12000000>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am43xx_pinmux { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default>; - pinctrl-1 = <&wlan_pins_sleep>; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: i2c1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - >; - }; - - pixcir_ts_pins: pixcir_ts_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - nand_flash_x8: nand_flash_x8 { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - dss_pins: dss_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - - >; - }; - - display_mux_pins: display_mux_pins { - pinctrl-single,pins = < - /* GPIO 5_8 to select LCD / HDMI */ - AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - dcan0_default: dcan0_default_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ - >; - }; - - dcan0_sleep: dcan0_sleep_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ - >; - }; - - dcan1_default: dcan1_default_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ - AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ - >; - }; - - dcan1_sleep: dcan1_sleep_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ - AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ - >; - }; - - vpfe0_pins_default: vpfe0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ - >; - }; - - vpfe0_pins_sleep: vpfe0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ - >; - }; - - vpfe1_pins_default: vpfe1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ - AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ - AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ - AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ - AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ - >; - }; - - vpfe1_pins_sleep: vpfe1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ - AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ - AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ - AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ - AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ - AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ - AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ - AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ - AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ - AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ - AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ - AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ - AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ - >; - }; - - mmc3_pins_default: pinmux_mmc3_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ - AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ - AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ - AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ - AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ - >; - }; - - mmc3_pins_sleep: pinmux_mmc3_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ - AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ - AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ - AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ - AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ - >; - }; - - wlan_pins_default: pinmux_wlan_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ - AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ - >; - }; - - wlan_pins_sleep: pinmux_wlan_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ - AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ - >; - }; - - uart3_pins: uart3_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ - AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ - AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ - AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_sleep_pins: mcasp1_sleep_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - gpio0_pins: gpio0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ - >; - }; - - emmc_pins_default: emmc_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - >; - }; - - emmc_pins_sleep: emmc_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ - AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps65218: tps65218@24 { - reg = <0x24>; - compatible = "ti,tps65218"; - interrupts = ; /* NMIn */ - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&refclk 0>; - clock-names = "xvclk"; - - port { - ov2659_0: endpoint { - remote-endpoint = <&vpfe1_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - pixcir_ts@5c { - compatible = "pixcir,pixcir_tangoc"; - pinctrl-names = "default"; - pinctrl-0 = <&pixcir_ts_pins>; - reg = <0x5c>; - - attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - - /* - * 0x264 represents the offset of padconf register of - * gpio3_22 from am43xx_pinmux base. - */ - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, - <&am43xx_pinmux 0x264>; - interrupt-names = "tsc", "wakeup"; - - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - wakeup-source; - }; - - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&refclk 0>; - clock-names = "xvclk"; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe0_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> EN: V1_8D -> VBAT */ - AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ - DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ - DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_pins>; - status = "okay"; - - p23 { - gpio-hog; - gpios = <23 GPIO_ACTIVE_HIGH>; - /* SelEMMCorNAND selects between eMMC and NAND: - * Low: NAND - * High: eMMC - * When changing this line make sure the newly - * selected device node is enabled and the previously - * selected device node is disabled. - */ - output-low; - line-name = "SelEMMCorNAND"; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&display_mux_pins>; - status = "okay"; - ti,no-reset-on-init; - - p8 { - /* - * SelLCDorHDMI selects between display and audio paths: - * Low: HDMI display with audio via HDMI - * High: LCD display with analog audio via aic3111 codec - */ - gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "SelLCDorHDMI"; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&evm_v3_3d>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -/* eMMC sits on mmc2 */ -&mmc2 { - /* - * When enabling eMMC, disable GPMC/NAND and set - * SelEMMCorNAND to output-high - */ - status = "disabled"; - vmmc-supply = <&evm_v3_3d>; - bus-width = <8>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&emmc_pins_default>; - pinctrl-1 = <&emmc_pins_sleep>; - ti,non-removable; -}; - -&mmc3 { - status = "okay"; - /* these are on the crossbar and are outlined in the - xbar-event-map element */ - dmas = <&edma_xbar 30 0 1>, - <&edma_xbar 31 0 2>; - dma-names = "tx", "rx"; - vmmc-supply = <&vmmcwl_fixed>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc3_pins_default>; - pinctrl-1 = <&mmc3_pins_sleep>; - cap-power-off-card; - keep-power-in-suspend; - ti,non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - /* - * When enabling GPMC, disable eMMC and set - * SelEMMCorNAND to output-low - */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch16"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <40>; - gpmc,cs-wr-off-ns = <40>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <25>; - gpmc,adv-wr-off-ns = <25>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <20>; - gpmc,oe-on-ns = <3>; - gpmc,oe-off-ns = <30>; - gpmc,access-ns = <30>; - gpmc,rd-cycle-ns = <40>; - gpmc,wr-cycle-ns = <40>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00040000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00040000 0x00040000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x000c0000 0x00040000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00100000 0x00080000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x00180000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x00280000 0x00040000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x002c0000 0x00040000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00300000 0x00700000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x1f600000>; - }; - }; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dcan0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcan0_default>; - pinctrl-1 = <&dcan0_sleep>; - status = "okay"; -}; - -&dcan1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcan1_default>; - pinctrl-1 = <&dcan1_sleep>; - status = "okay"; -}; - -&vpfe0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe0_pins_default>; - pinctrl-1 = <&vpfe0_pins_sleep>; - - port { - vpfe0_ep: endpoint { - remote-endpoint = <&ov2659_1>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&vpfe1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe1_pins_default>; - pinctrl-1 = <&vpfe1_pins_sleep>; - - port { - vpfe1_ep: endpoint { - remote-endpoint = <&ov2659_0>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_sleep_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&cpu { - cpu0-supply = <&dcdc2>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am437x-idk-evm.dts b/software/linux/kernel/arch/arm/boot/dts/am437x-idk-evm.dts deleted file mode 100644 index 25ce611c6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am437x-idk-evm.dts +++ /dev/null @@ -1,416 +0,0 @@ -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include - -/ { - model = "TI AM437x Industrial Development Kit"; - compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43"; - - v24_0d: fixed-regulator-v24_0d { - compatible = "regulator-fixed"; - regulator-name = "V24_0D"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - regulator-boot-on; - }; - - v3_3d: fixed-regulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "V3_3D"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - vdd_corereg: fixed-regulator-vdd_corereg { - compatible = "regulator-fixed"; - regulator-name = "VDD_COREREG"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - vdd_core: fixed-regulator-vdd_core { - compatible = "regulator-fixed"; - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_corereg>; - }; - - v1_8dreg: fixed-regulator-v1_8dreg{ - compatible = "regulator-fixed"; - regulator-name = "V1_8DREG"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - v1_8d: fixed-regulator-v1_8d{ - compatible = "regulator-fixed"; - regulator-name = "V1_8D"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v1_8dreg>; - }; - - v1_5dreg: fixed-regulator-v1_5dreg{ - compatible = "regulator-fixed"; - regulator-name = "V1_5DREG"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v24_0d>; - }; - - v1_5d: fixed-regulator-v1_5d{ - compatible = "regulator-fixed"; - regulator-name = "V1_5D"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&v1_5dreg>; - }; - - gpio_keys: gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins_default>; - #address-cells = <1>; - #size-cells = <0>; - - switch0 { - label = "power-button"; - linux,code = ; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - }; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; -}; - -&am43xx_pinmux { - gpio_keys_pins_default: gpio_keys_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ - >; - }; - - i2c0_pins_default: i2c0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c0_pins_sleep: i2c0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - i2c2_pins_default: i2c2_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ - AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ - >; - }; - - i2c2_pins_sleep: i2c2_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mmc1_pins_default: pinmux_mmc1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - ecap0_pins_default: backlight_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ - AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - qspi_pins_default: qspi_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ - AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ - AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ - AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ - AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ - AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ - >; - }; - - qspi_pins_sleep: qspi_pins_sleep{ - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c0_pins_default>; - pinctrl-1 = <&i2c0_pins_sleep>; - clock-frequency = <400000>; - - at24@50 { - compatible = "at24,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - tps: tps62362@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - regulator-name = "VDD_MPU"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1330000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - vin-supply = <&v3_3d>; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_default>; - pinctrl-1 = <&i2c2_pins_sleep>; - clock-frequency = <100000>; -}; - -&epwmss0 { - status = "okay"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins_default>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_sleep>; - vmmc-supply = <&v3_3d>; - bus-width = <4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_pins_default>; - pinctrl-1 = <&qspi_pins_sleep>; - - spi-max-frequency = <48000000>; - m25p80@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * MTD partition table. The ROM checks the first 512KiB for a - * valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii"; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&cpu { - cpu0-supply = <&tps>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am437x-sbc-t43.dts b/software/linux/kernel/arch/arm/boot/dts/am437x-sbc-t43.dts deleted file mode 100644 index d23260d3a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am437x-sbc-t43.dts +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "am437x-cm-t43.dts" -#include "compulab-sb-som.dtsi" - -/ { - model = "CompuLab CM-T43 on SB-SOM-T43"; - compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"; - - aliases { - display0 = &lcd0; - }; -}; - -&am43xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */ - >; - }; - - dss_pinctrl_default: dss_pinctrl_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */ - AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9b8, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9bc, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c0, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c4, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9c8, PIN_OUTPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam1 data 9 -> DSS DATA 16 */ - - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - AM4372_IOPAD(0xa20, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - uart0_pins_default: uart0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) - AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - i2c1_pins: i2c1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa6c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_cs0.i2c1_sda */ - AM4372_IOPAD(0xa60, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_sclk.i2c1_scl */ - >; - }; - - i2c2_pins: i2c2_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ - >; - }; - - usb2_phy1_default: usb2_phy1_default { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; - - usb2_phy2_default: usb2_phy2_default { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom_base: at24@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; -}; - -&mmc1 { - status = "okay"; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vsb_3v3>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pinctrl_default>; - - port { - dpi_lcd_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_default>; -}; - -&dwc3_1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_phy1_default>; -}; - -&dwc3_2 { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_phy2_default>; -}; - -&lcd0 { - enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH - &gpio4 28 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - data-lines = <24>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am437x-sk-evm.dts b/software/linux/kernel/arch/arm/boot/dts/am437x-sk-evm.dts deleted file mode 100644 index 319d94205..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am437x-sk-evm.dts +++ /dev/null @@ -1,761 +0,0 @@ -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* AM437x SK EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include - -/ { - model = "TI AM437x SK EVM"; - compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - /* fixed 32k external oscillator clock */ - clk_32k_rtc: clk_32k_rtc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM437x-SK-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24000000>; - }; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_pins>; - - debounce-delay-ms = <5>; - col-scan-delay-us = <5>; - - row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ - &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ - - col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ - &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ - - linux,keymap = < - MATRIX_KEY(0, 0, KEY_DOWN) - MATRIX_KEY(0, 1, KEY_RIGHT) - MATRIX_KEY(1, 0, KEY_LEFT) - MATRIX_KEY(1, 1, KEY_UP) - >; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - led0 { - label = "am437x-sk:red:heartbeat"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - label = "am437x-sk:green:mmc1"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "am437x-sk:blue:cpu0"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led3 { - label = "am437x-sk:blue:usr3"; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ - default-state = "off"; - }; - }; - - lcd0: display { - compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; -}; - -&am43xx_pinmux { - matrix_keypad_pins: matrix_keypad_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ - AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ - AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ - AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ - >; - }; - - leds_pins: leds_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ - AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ - AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ - AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ - >; - }; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: i2c1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ - >; - }; - - edt_ft5306_ts_pins: edt_ft5306_ts_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ - >; - }; - - vpfe0_pins_default: vpfe0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ - AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ - AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ - AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ - AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ - AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ - AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ - AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ - AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ - AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ - AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ - AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ - AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ - >; - }; - - vpfe0_pins_sleep: vpfe0_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ - AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ - AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ - AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ - - /* Slave 2 */ - AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ - AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - - /* Slave 2 reset value */ - AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - dss_pins: dss_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ - - >; - }; - - qspi_pins: qspi_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ - AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ - AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ - AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ - AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ - AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - lcd_pins: lcd_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ - >; - }; - - usb1_pins: usb1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - >; - }; - - usb2_pins: usb2_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ - >; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - - tps@24 { - compatible = "ti,tps65218"; - reg = <0x24>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - /* VDD_CORE limits min of OPP50 and max of OPP100 */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdds_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - - dcdc4: regulator-dcdc4 { - regulator-name = "v3_3d"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1: regulator-ldo1 { - regulator-name = "v1_8d"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - power-button { - compatible = "ti,tps65218-pwrbutton"; - status = "okay"; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - at24@50 { - compatible = "at24,24c256"; - pagesize = <64>; - reg = <0x50>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - edt-ft5306@38 { - status = "okay"; - compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; - pinctrl-names = "default"; - pinctrl-0 = <&edt_ft5306_ts_pins>; - - reg = <0x38>; - interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - - reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <480>; - touchscreen-size-y = <272>; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&dcdc4>; - IOVDD-supply = <&dcdc4>; - DRVDD-supply = <&dcdc4>; - DVDD-supply = <&ldo1>; - }; - - lis331dlh@18 { - compatible = "st,lis331dlh"; - reg = <0x18>; - status = "okay"; - - Vdd-supply = <&dcdc4>; - Vdd_IO-supply = <&dcdc4>; - interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - vmmc-supply = <&dcdc4>; - bus-width = <4>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; - - spi-max-frequency = <48000000>; - m25p80@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first 512KiB - * for a valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <4>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <5>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&elm { - status = "okay"; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; - tdm-slots = <2>; - serial-dir = < - 0 0 1 2 - >; - - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint@0 { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&rtc { - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&cpu { - cpu0-supply = <&dcdc2>; -}; - -&vpfe0 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe0_pins_default>; - pinctrl-1 = <&vpfe0_pins_sleep>; - - /* Camera port */ - port { - vpfe0_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am43x-epos-evm.dts b/software/linux/kernel/arch/arm/boot/dts/am43x-epos-evm.dts deleted file mode 100644 index 9d35c3f07..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am43x-epos-evm.dts +++ /dev/null @@ -1,795 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* AM43x EPOS EVM */ - -/dts-v1/; - -#include "am4372.dtsi" -#include -#include -#include -#include - -/ { - model = "TI AM43x EPOS EVM"; - compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; - - aliases { - display0 = &lcd0; - }; - - vmmcsd_fixed: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lcd0: display { - compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; - label = "lcd"; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <16>; - hsync-len = <30>; - vback-porch = <10>; - vfront-porch = <22>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - matrix_keypad: matrix_keypad0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ - &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ - &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ - &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ - - col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ - &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ - &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ - &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x01000204 /* P4 */ - 0x02000207 /* P7 */ - 0x0300020a /* NUMERIC_STAR */ - 0x00010202 /* P2 */ - 0x01010205 /* P5 */ - 0x02010208 /* P8 */ - 0x03010200 /* P0 */ - 0x00020203 /* P3 */ - 0x01020206 /* P6 */ - 0x02020209 /* P9 */ - 0x0302020b /* NUMERIC_POUND */ - 0x00030067 /* UP */ - 0x0103006a /* RIGHT */ - 0x0203006c /* DOWN */ - 0x03030069>; /* LEFT */ - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM43-EPOS-EVM"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker"; - simple-audio-card,routing = - "MIC1LP", "Microphone Jack", - "MIC1RP", "Microphone Jack", - "MIC1LP", "MICBIAS", - "MIC1RP", "MICBIAS", - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Speaker", "SPL", - "Speaker", "SPR"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - system-clock-frequency = <12000000>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3111>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&am43xx_pinmux { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ - AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - nand_flash_x8: nand_flash_x8 { - pinctrl-single,pins = < - AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ - AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ - AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ - AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ - >; - }; - - spi0_pins: pinmux_spi0_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ - AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ - >; - }; - - spi1_pins: pinmux_spi1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ - AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ - AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ - AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - qspi1_default: qspi1_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) - AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) - AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) - >; - }; - - pixcir_ts_pins: pixcir_ts_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ - >; - }; - - hdq_pins: pinmux_hdq_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ - >; - }; - - dss_pins: dss_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ - AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) - AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ - AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ - >; - }; - - display_mux_pins: display_mux_pins { - pinctrl-single,pins = < - /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ - AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) - >; - }; - - vpfe1_pins_default: vpfe1_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ - AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ - AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ - AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ - AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ - AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ - AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ - AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ - AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ - AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ - AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ - AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ - AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ - >; - }; - - vpfe1_pins_sleep: vpfe1_pins_sleep { - pinctrl-single,pins = < - AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ - AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ - AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ - AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ - >; - }; - - mcasp1_sleep_pins: mcasp1_sleep_pins { - pinctrl-single,pins = < - AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <16>; - phy-mode = "rmii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rmii"; -}; - -&phy_sel { - rmii-clock-ext; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - tps65218: tps65218@24 { - reg = <0x24>; - compatible = "ti,tps65218"; - interrupts = ; /* NMIn */ - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc4: regulator-dcdc4 { - regulator-name = "vdcdc4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - - at24@50 { - compatible = "at24,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - pixcir_ts@5c { - compatible = "pixcir,pixcir_tangoc"; - pinctrl-names = "default"; - pinctrl-0 = <&pixcir_ts_pins>; - reg = <0x5c>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - - attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; - - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - }; - - tlv320aic3111: tlv320aic3111@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3111"; - reg = <0x18>; - status = "okay"; - - ai31xx-micbias-vg = ; - - /* Regulators */ - HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ - SPRVDD-supply = <&vbat>; /* vbat */ - SPLVDD-supply = <&vbat>; /* vbat */ - AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ - IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ - DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&display_mux_pins>; - status = "okay"; - - p1 { - /* - * SelLCDorHDMI selects between display and audio paths: - * Low: HDMI display with audio via HDMI - * High: LCD display with analog audio via aic3111 codec - */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "SelLCDorHDMI"; - }; -}; - -&gpio3 { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - ti,nand-ecc-opt = "bch16"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ - gpmc,cs-wr-off-ns = <40>; - gpmc,adv-on-ns = <0>; /* cs-on-ns */ - gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ - gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ - gpmc,we-on-ns = <0>; /* cs-on-ns */ - gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ - gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ - gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ - gpmc,access-ns = <30>; /* tCEA + 4*/ - gpmc,rd-cycle-ns = <40>; - gpmc,wr-cycle-ns = <40>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00040000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00040000 0x00040000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x000C0000 0x00040000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00100000 0x00080000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x00180000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x00280000 0x00040000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x002C0000 0x00040000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00300000 0x00700000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x1f600000>; - }; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; - - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&ecap0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; -}; - -&usb2_phy1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb2_phy2 { - status = "okay"; -}; - -&usb2 { - dr_mode = "host"; - status = "okay"; -}; - -&qspi { - status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_default>; - - spi-max-frequency = <48000000>; - m25p80@0 { - compatible = "mx66l51235l"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpol; - spi-cpha; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first 512KiB - * for a valid file to boot(XIP). - */ - partition@0 { - label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; - }; - partition@1 { - label = "QSPI.U_BOOT.backup"; - reg = <0x00080000 0x00080000>; - }; - partition@2 { - label = "QSPI.U-BOOT-SPL_OS"; - reg = <0x00100000 0x00010000>; - }; - partition@3 { - label = "QSPI.U_BOOT_ENV"; - reg = <0x00110000 0x00010000>; - }; - partition@4 { - label = "QSPI.U-BOOT-ENV.backup"; - reg = <0x00120000 0x00010000>; - }; - partition@5 { - label = "QSPI.KERNEL"; - reg = <0x00130000 0x0800000>; - }; - partition@6 { - label = "QSPI.FILESYSTEM"; - reg = <0x00930000 0x36D0000>; - }; - }; -}; - -&hdq { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&vpfe1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe1_pins_default>; - pinctrl-1 = <&vpfe1_pins_sleep>; - - port { - vpfe1_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_sleep_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&synctimer_32kclk { - assigned-clocks = <&mux_synctimer32k_ck>; - assigned-clock-parents = <&clkdiv32k_ick>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am43xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/am43xx-clocks.dtsi deleted file mode 100644 index d1d73b725..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am43xx-clocks.dtsi +++ /dev/null @@ -1,836 +0,0 @@ -/* - * Device Tree Source for AM43xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; - ti,bit-shift = <31>; - reg = <0x0040>; - }; - - crystal_freq_sel_ck: crystal_freq_sel_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <29>; - reg = <0x0040>; - }; - - sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <22>; - reg = <0x0040>; - }; - - adc_tsc_fck: adc_tsc_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan0_fck: dcan0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan1_fck: dcan1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp0_fck: mcasp0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp1_fck: mcasp1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex0_fck: smartreflex0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex1_fck: smartreflex1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sha0_fck: sha0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes0_fck: aes0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - rng_fck: rng_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - ehrpwm0_tbclk: ehrpwm0_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; - - ehrpwm1_tbclk: ehrpwm1_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; - - ehrpwm2_tbclk: ehrpwm2_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; - }; - - ehrpwm3_tbclk: ehrpwm3_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <4>; - reg = <0x0664>; - }; - - ehrpwm4_tbclk: ehrpwm4_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <5>; - reg = <0x0664>; - }; - - ehrpwm5_tbclk: ehrpwm5_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <6>; - reg = <0x0664>; - }; -}; -&prcm_clocks { - clk_32768_ck: clk_32768_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_rc32k_ck: clk_rc32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_24000000_ck: virt_24000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - virt_25000000_ck: virt_25000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - dpll_core_ck: dpll_core_ck@2d20 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m4_ck: dpll_core_m4_ck@2d38 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d38>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m5_ck: dpll_core_m5_ck@2d3c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d3c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m6_ck: dpll_core_m6_ck@2d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d40>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_mpu_ck: dpll_mpu_ck@2d60 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d70>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_periphclk: mpu_periphclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_mpu_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_ddr_ck: dpll_ddr_ck@2da0 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>; - }; - - dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2db0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_disp_ck: dpll_disp_ck@2e20 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>; - }; - - dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_disp_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2e30>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - ti,set-rate-parent; - }; - - dpll_per_ck: dpll_per_ck@2de0 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-j-type-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@2df0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x2df0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - clk_24mhz: clk_24mhz { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - clkdiv32k_ck: clkdiv32k_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_24mhz>; - clock-mult = <1>; - clock-div = <732>; - }; - - clkdiv32k_ick: clkdiv32k_ick@2a38 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ck>; - ti,bit-shift = <8>; - reg = <0x2a38>; - }; - - sysclk_div: sysclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - pruss_ocp_gclk: pruss_ocp_gclk@4248 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; - reg = <0x4248>; - }; - - clk_32k_tpm_ck: clk_32k_tpm_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - timer1_fck: timer1_fck@4200 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; - reg = <0x4200>; - }; - - timer2_fck: timer2_fck@4204 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4204>; - }; - - timer3_fck: timer3_fck@4208 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4208>; - }; - - timer4_fck: timer4_fck@420c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x420c>; - }; - - timer5_fck: timer5_fck@4210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4210>; - }; - - timer6_fck: timer6_fck@4214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4214>; - }; - - timer7_fck: timer7_fck@4218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4218>; - }; - - wdt1_fck: wdt1_fck@422c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; - reg = <0x422c>; - }; - - l3_gclk: l3_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sysclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - l4hs_gclk: l4hs_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3s_gclk: l3s_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4ls_gclk: l4ls_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_125mhz_gclk: cpsw_125mhz_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; - reg = <0x4238>; - }; - - dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5_ck>; - reg = <0x4234>; - ti,bit-shift = <2>; - ti,dividers = <2>, <5>; - }; - - clk_32k_mosc_ck: clk_32k_mosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; - reg = <0x4240>; - }; - - gpio0_dbclk: gpio0_dbclk@2b68 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&gpio0_dbclk_mux_ck>; - ti,bit-shift = <8>; - reg = <0x2b68>; - }; - - gpio1_dbclk: gpio1_dbclk@8c78 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c78>; - }; - - gpio2_dbclk: gpio2_dbclk@8c80 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c80>; - }; - - gpio3_dbclk: gpio3_dbclk@8c88 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c88>; - }; - - gpio4_dbclk: gpio4_dbclk@8c90 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c90>; - }; - - gpio5_dbclk: gpio5_dbclk@8c98 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <8>; - reg = <0x8c98>; - }; - - mmc_clk: mmc_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x423c>; - }; - - gfx_fck_div_ck: gfx_fck_div_ck@423c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x423c>; - ti,max-div = <2>; - }; - - disp_clk: disp_clk@4244 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; - reg = <0x4244>; - ti,set-rate-parent; - }; - - dpll_extdev_ck: dpll_extdev_ck@2e60 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>; - }; - - dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_extdev_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x2e70>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; - reg = <0x4230>; - }; - - synctimer_32kclk: synctimer_32kclk@2a30 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&mux_synctimer32k_ck>; - ti,bit-shift = <8>; - reg = <0x2a30>; - }; - - timer8_fck: timer8_fck@421c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x421c>; - }; - - timer9_fck: timer9_fck@4220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4220>; - }; - - timer10_fck: timer10_fck@4224 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4224>; - }; - - timer11_fck: timer11_fck@4228 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4228>; - }; - - cpsw_50m_clkdiv: cpsw_50m_clkdiv { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_5m_clkdiv: cpsw_5m_clkdiv { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpsw_50m_clkdiv>; - clock-mult = <1>; - clock-div = <10>; - }; - - dpll_ddr_x2_ck: dpll_ddr_x2_ck { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clocks = <&dpll_ddr_ck>; - }; - - dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2db8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll_per_ck>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x2e14>; - ti,invert-autoidle-bit; - }; - - dll_aging_clk_div: dll_aging_clk_div@4250 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - reg = <0x4250>; - ti,dividers = <8>, <16>, <32>; - }; - - div_core_25m_ck: div_core_25m_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sysclk_div>; - clock-mult = <1>; - clock-div = <8>; - }; - - func_12m_clk: func_12m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - vtp_clk_div: vtp_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; - reg = <0x4260>; - }; - - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&usbphy_32khz_clkmux>; - ti,bit-shift = <8>; - reg = <0x2a40>; - }; - - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&usbphy_32khz_clkmux>; - ti,bit-shift = <8>; - reg = <0x2a48>; - }; - - usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x8a60>; - }; - - usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x8a68>; - }; - - clkout1_osc_div_ck: clkout1_osc_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <20>; - ti,max-div = <4>; - reg = <0x4100>; - }; - - clkout1_src2_mux_ck: clkout1_src2_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, - <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, - <&dpll_mpu_m2_ck>; - reg = <0x4100>; - }; - - clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout1_src2_mux_ck>; - ti,bit-shift = <4>; - ti,max-div = <8>; - reg = <0x4100>; - }; - - clkout1_src2_post_div_ck: clkout1_src2_post_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout1_src2_pre_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - ti,index-power-of-two; - reg = <0x4100>; - }; - - clkout1_mux_ck: clkout1_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, - <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; - ti,bit-shift = <16>; - reg = <0x4100>; - }; - - clkout1_ck: clkout1_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout1_mux_ck>; - ti,bit-shift = <23>; - reg = <0x4100>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am572x-idk.dts b/software/linux/kernel/arch/arm/boot/dts/am572x-idk.dts deleted file mode 100644 index 87bbc66f0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am572x-idk.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "dra74x.dtsi" -#include -#include -#include "am57xx-idk-common.dtsi" - -/ { - model = "TI AM5728 IDK"; - compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", - "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - }; - - status-leds { - compatible = "gpio-leds"; - cpu0-led { - label = "status0:red:cpu0"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - usr0-led { - label = "status0:green:usr"; - gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat-led { - label = "status0:blue:heartbeat"; - gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - cpu1-led { - label = "status1:red:cpu1"; - gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu1"; - }; - - usr1-led { - label = "status1:green:usr"; - gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - mmc0-led { - label = "status1:blue:mmc0"; - gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&v3_3d>; - vmmc_aux-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 0>; /* gpio 219 */ -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi deleted file mode 100644 index 6df7829a2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ /dev/null @@ -1,596 +0,0 @@ -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "dra74x.dtsi" -#include "am57xx-commercial-grade.dtsi" -#include -#include - -/ { - compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - rtc0 = &mcp_rtc; - rtc1 = &tps659038_rtc; - rtc2 = &rtc; - display0 = &hdmi0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <®en1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd_fixed"; - vin-supply = <&vdd_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&smps3_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "beagle-x15:usr0"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - label = "beagle-x15:usr1"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led2 { - label = "beagle-x15:usr2"; - gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "beagle-x15:usr3"; - gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - default-state = "off"; - }; - }; - - gpio_fan: gpio_fan { - /* Based on 5v 500mA AFB02505HHB */ - compatible = "gpio-fan"; - gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, - <13000 1>; - #cooling-cells = <2>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "BeagleBoard-X15"; - simple-audio-card,widgets = - "Line", "Line Out", - "Line", "Line In"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC2L", "Line In", - "MIC2R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3104>; - clocks = <&clkout2_clk>; - }; - }; -}; - -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; -}; -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_CORE */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS7 unused */ - - smps8_reg: smps8 { - /* VDD_1V8 */ - regulator-name = "smps8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS9 unused */ - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_SHV5 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb2: tps659038_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - }; - - tmp102: tmp102@48 { - compatible = "ti,tmp102"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - tlv320aic3104: tlv320aic3104@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3104"; - reg = <0x18>; - assigned-clocks = <&clkoutmux2_clk_mux>; - assigned-clock-parents = <&sys_clk2_dclk_div>; - - status = "okay"; - adc-settle-ms = <40>; - - AVDD-supply = <&vdd_3v3>; - IOVDD-supply = <&vdd_3v3>; - DRVDD-supply = <&vdd_3v3>; - DVDD-supply = <&aic_dvdd>; - }; - - eeprom: eeprom@50 { - compatible = "at,24c32"; - reg = <0x50>; - }; -}; - -&i2c3 { - status = "okay"; - clock-frequency = <400000>; - - mcp_rtc: rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, - <&dra7_pmx_core 0x424>; - interrupt-names = "irq", "wakeup"; - - vcc-supply = <&vdd_3v3>; - wakeup-source; - }; -}; - -&gpio7 { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&cpu0 { - cpu0-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; -}; - -&mac { - status = "okay"; - dual_emac; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <2>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&mmc1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ -}; - -&mmc2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&vdd_3v3>; - bus-width = <8>; - ti,non-removable; - cap-mmc-dual-data-rate; -}; - -&sata { - status = "okay"; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - /* - * Stand alone usage is peripheral only. - * However, with some resistor modifications - * this port can be used via expansion connectors - * as "host" or "dual-role". If so, provide - * the necessary dr_mode override in the expansion - * board's DT. - */ - dr_mode = "peripheral"; -}; - -&cpu_trips { - cpu_alert1: cpu_alert1 { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; -}; - -&cpu_cooling_maps { - map1 { - trip = <&cpu_alert1>; - cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&thermal_zones { - board_thermal: board_thermal { - polling-delay-passive = <1250>; /* milliseconds */ - polling-delay = <1500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tmp102 0>; - - board_trips: trips { - board_alert0: board_alert { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - - board_crit: board_crit { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - board_cooling_maps: cooling-maps { - map0 { - trip = <&board_alert0>; - cooling-device = - <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldoln_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&pcie1 { - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&sys_clkin2>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts deleted file mode 100644 index ca8557062..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "am57xx-beagle-x15-common.dtsi" - -/ { - model = "TI AM5728 BeagleBoard-X15 rev B1"; -}; - -&tpd12s015 { - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ -}; - -&mmc1 { - vmmc-supply = <&vdd_3v3>; - vmmc-aux-supply = <&ldo1_reg>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15.dts b/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15.dts deleted file mode 100644 index 8c66f2efd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "am57xx-beagle-x15-common.dtsi" - -/ { - /* NOTE: This describes the "original" pre-production A2 revision */ - model = "TI AM5728 BeagleBoard-X15"; -}; - -&tpd12s015 { - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ -}; - -&mmc1 { - vmmc-supply = <&ldo1_reg>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/software/linux/kernel/arch/arm/boot/dts/am57xx-cl-som-am57x.dts deleted file mode 100644 index 203266f88..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ /dev/null @@ -1,617 +0,0 @@ -/* - * Support for CompuLab CL-SOM-AM57x System-on-Module - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Dmitry Lifshitz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ - -/dts-v1/; - -#include -#include -#include "dra74x.dtsi" - -/ { - model = "CompuLab CL-SOM-AM57x"; - compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default>; - - led0 { - label = "cl-som-am57x:green"; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ads7846reg: fixedregulator-ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "CL-SOM-AM57x-Sound-Card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Microphone", "Microphone Jack", - "Line", "Line Jack"; - simple-audio-card,routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line Jack", - "MICIN", "Mic Bias", - "Mic Bias", "Microphone Jack"; - - dailink0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8731>; - system-clock-frequency = <12000000>; - }; - }; -}; - -&dra7_pmx_core { - leds_pins_default: leds_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */ - >; - }; - - i2c1_pins_default: i2c1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ - >; - }; - - i2c3_pins_default: i2c3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ - DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ - >; - }; - - i2c4_pins_default: i2c4_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */ - DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */ - >; - }; - - tps659038_pins_default: tps659038_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - qspi1_pins: pinmux_qspi1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */ - DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */ - DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ - >; - }; - - cpsw_pins_default: cpsw_pins_default { - pinctrl-single,pins = < - /* Slave at addr 0x0 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */ - DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */ - DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */ - DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */ - DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */ - DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */ - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */ - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */ - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */ - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */ - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */ - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */ - - /* Slave at addr 0x1 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - }; - - cpsw_pins_sleep: cpsw_pins_sleep { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15) - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) - >; - }; - - davinci_mdio_pins_default: davinci_mdio_pins_default { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */ - DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */ - >; - }; - - davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15) - >; - }; - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */ - >; - }; - - mcasp3_pins_default: mcasp3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ - >; - }; - - mcasp3_pins_sleep: mcasp3_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_default>; - clock-frequency = <400000>; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_default>; - clock-frequency = <400000>; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_default>; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps659038_pins_default>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU */ - regulator-name = "smps6"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDD_CORE */ - regulator-name = "smps7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1160000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_IVA */ - regulator-name = "smps8"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* PMIC_3V3 */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_1V8 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - /* regen1 not used */ - }; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - rtc0: rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - - eeprom_module: atmel@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; - - wm8731: wm8731@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8731"; - reg = <0x1a>; - status = "okay"; - }; -}; - -&cpu0 { - cpu0-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&sata { - status = "okay"; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; - -&mmc2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&vdd_3v3>; - bus-width = <8>; - ti,non-removable; - cap-mmc-dual-data-rate; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - - spi-max-frequency = <48000000>; - - spi_flash: spi_flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,m25p80", "jedec,spi-nor"; - reg = <0>; /* CS0 */ - spi-max-frequency = <48000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "uboot environment"; - reg = <0xc0000 0x40000>; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x0>; - }; - }; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <1>; /* CS1 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <31 0>; - pendown-gpio = <&gpio1 31 0>; - - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_pins_default>; - pinctrl-1 = <&cpsw_pins_sleep>; - dual_emac; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <0>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_pins_default>; - pinctrl-1 = <&davinci_mdio_pins_sleep>; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&usb2 { - dr_mode = "host"; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins_default>; - pinctrl-1 = <&mcasp3_pins_sleep>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; -}; - -&gpio3 { - status = "okay"; - ti,no-reset-on-init; -}; - -&gpio2 { - status = "okay"; - ti,no-reset-on-init; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am57xx-commercial-grade.dtsi b/software/linux/kernel/arch/arm/boot/dts/am57xx-commercial-grade.dtsi deleted file mode 100644 index c18365446..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am57xx-commercial-grade.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -&cpu_alert0 { - temperature = <80000>; /* milliCelsius */ -}; - -&cpu_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&gpu_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&core_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&dspeve_crit { - temperature = <90000>; /* milliCelsius */ -}; - -&iva_crit { - temperature = <90000>; /* milliCelsius */ -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am57xx-idk-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/am57xx-idk-common.dtsi deleted file mode 100644 index db858fff4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "am57xx-industrial-grade.dtsi" - -/ { - aliases { - rtc0 = &tps659038_rtc; - rtc1 = &rtc; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "VMAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - v3_3d: fixedregulator-v3_3d { - compatible = "regulator-fixed"; - regulator-name = "V3_3D"; - vin-supply = <&smps9_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&v3_3d>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH - &dra7_pmx_core 0x418>; - #interrupt-cells = <2>; - interrupt-controller; - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - smps12-in-supply = <&vmain>; - smps3-in-supply = <&vmain>; - smps45-in-supply = <&vmain>; - smps6-in-supply = <&vmain>; - smps7-in-supply = <&vmain>; - smps8-in-supply = <&vmain>; - smps9-in-supply = <&vmain>; - ldo1-in-supply = <&vmain>; - ldo2-in-supply = <&vmain>; - ldo3-in-supply = <&vmain>; - ldo4-in-supply = <&vmain>; - ldo9-in-supply = <&vmain>; - ldoln-in-supply = <&vmain>; - ldousb-in-supply = <&vmain>; - ldortc-in-supply = <&vmain>; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR EMIF1 EMIF2 */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE on AM572 */ - /* VDD_IVA + VDD_DSP on AM571 */ - regulator-name = "smps45"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDD_CORE */ - regulator-name = "smps7"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* 5728 - VDD_IVAHD */ - /* 5718 - N.C. test point */ - regulator-name = "smps8"; - }; - - smps9_reg: smps9 { - /* VDD_3_3D */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: ldo1 { - /* VDDSHV8 - VSDMMC */ - /* NOTE: on rev 1.3a, data supply */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDDSH18V */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* LDO5-8 unused */ - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <840000>; - regulator-max-microvolt = <1160000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldortc_reg: ldortc { - /* VDDA_RTC */ - regulator-name = "ldortc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - - regen2: regen2 { - /* Needed for PMIC internal resource */ - regulator-name = "regen2"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH - &dra7_pmx_core 0x248>; -}; - -&rtc { - status = "okay"; - ext-clk-src; -}; - -&mac { - status = "okay"; - dual_emac; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&usb2 { - dr_mode = "peripheral"; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&v3_3d>; - bus-width = <8>; - ti,non-removable; - max-frequency = <96000000>; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1", "jedec,spi-nor"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000040000>; - }; - partition@1 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@2 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@3 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@5 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@6 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am57xx-industrial-grade.dtsi b/software/linux/kernel/arch/arm/boot/dts/am57xx-industrial-grade.dtsi deleted file mode 100644 index 70c8c4ba1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am57xx-industrial-grade.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -&cpu_alert0 { - temperature = <90000>; /* milliCelsius */ -}; - -&cpu_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&gpu_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&core_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&dspeve_crit { - temperature = <105000>; /* milliCelsius */ -}; - -&iva_crit { - temperature = <105000>; /* milliCelsius */ -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/software/linux/kernel/arch/arm/boot/dts/am57xx-sbc-am57x.dts deleted file mode 100644 index 31f9be632..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/am57xx-sbc-am57x.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Support for CompuLab SBC-AM57x single board computer - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Dmitry Lifshitz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ - -#include "am57xx-cl-som-am57x.dts" -#include "compulab-sb-som.dtsi" - -/ { - model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x"; - compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - display0 = &lcd0; - display1 = &hdmi; - }; -}; - -&dra7_pmx_core { - uart3_pins_default: uart3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ - DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ - >; - }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */ - DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - i2c5_pins_default: i2c5_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - lcd_pins_default: lcd_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - hdmi_conn_pins: pinmux_hdmi_conn_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */ - >; - }; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; -}; - -&mmc1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - vmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_default>; - clock-frequency = <400000>; - - eeprom_base: atmel@54 { - compatible = "atmel,24c08"; - reg = <0x54>; - pagesize = <16>; - }; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldoln_reg>; - - port { - dpi_lcd_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&lcd0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_default>; - - enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH - &gpio4 0 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - data-lines = <24>; - }; - }; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; - -&hdmi_conn { - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_conn_pins>; - - hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/animeo_ip.dts b/software/linux/kernel/arch/arm/boot/dts/animeo_ip.dts deleted file mode 100644 index 9cc372b9f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/animeo_ip.dts +++ /dev/null @@ -1,166 +0,0 @@ -/* - * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 only. - */ - -/dts-v1/; -#include "at91sam9260.dtsi" - -/ { - model = "Somfy Animeo IP"; - compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9"; - - aliases { - serial0 = &usart1; - serial1 = &usart2; - serial2 = &usart0; - serial3 = &dbgu; - serial4 = &usart3; - serial5 = &uart0; - serial6 = &uart1; - }; - - chosen { - linux,stdout-path = &usart2; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - usart0: serial@fffb0000 { - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - usart1: serial@fffb4000 { - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - usart2: serial@fffb8000 { - pinctrl-0 = <&pinctrl_usart2>; - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>; - phy-mode = "mii"; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = <&pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - barebox@0 { - label = "barebox"; - reg = <0x0 0x58000>; - }; - - u_boot_env@58000 { - label = "u_boot_env"; - reg = <0x58000 0x8000>; - }; - - ubi@60000 { - label = "ubi"; - reg = <0x60000 0x1FA0000>; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - power_green { - label = "power_green"; - gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - power_red { - label = "power_red"; - gpios = <&pioA 2 GPIO_ACTIVE_HIGH>; - }; - - tx_green { - label = "tx_green"; - gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; - }; - - tx_red { - label = "tx_red"; - gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - keyswitch_in { - label = "keyswitch_in"; - gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; - linux,code = <28>; - wakeup-source; - }; - - error_in { - label = "error_in"; - gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; - linux,code = <29>; - wakeup-source; - }; - - btn { - label = "btn"; - gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; - linux,code = <31>; - wakeup-source; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts deleted file mode 100644 index e18769df9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp-ctrevb.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/* - * This is the EB with the new Revision D baseboard with SMSC9118 ethernet and - * the Rev B core tile. - */ -/ { - model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Core Tile Rev B"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts deleted file mode 100644 index 26b1c69e9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Rev C Core Tile"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts deleted file mode 100644 index e68527b0d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp.dts" - -/ { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; -}; - -/* - * The revision B has a distinctly different layout of the syscon, so - * append a specific compatible-string. - */ -&syscon { - compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; -}; - -&intc { - reg = <0x10101000 0x1000>, - <0x10100100 0x100>; -}; - -&L2 { - reg = <0x10102000 0x1000>; -}; - -&scu { - reg = <0x10100000 0x100>; -}; - -&twd_timer { - reg = <0x10100600 0x20>; -}; - -&twd_wdog { - reg = <0x10100620 0x20>; -}; - -/* - * On revision B, we cannot reach the secondary interrupt - * controller, as a result, some peripherals that are dependent - * on their IRQ cannot be reached, so disable them. - */ -&intc_second { - status = "disabled"; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&serial2 { - status = "disabled"; -}; - -&serial3 { - status = "disabled"; -}; - -&ssp { - status = "disabled"; -}; - -&wdog { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp.dts deleted file mode 100644 index aac1edd4b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-11mp.dts +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-eb-mp.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile"; - arm,hbi = <0x146>; - - /* - * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB. - * Reference: ARM DUI 0318F - * - * To run this machine with QEMU, specify the following: - * qemu-system-arm -M realview-eb-mpcore -smp cpus=4 - */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - MP11_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <0>; - next-level-cache = <&L2>; - }; - - MP11_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <1>; - next-level-cache = <&L2>; - }; - - MP11_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <2>; - next-level-cache = <&L2>; - }; - - MP11_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; -}; - -&pmu { - interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts deleted file mode 100644 index 42efac749..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-a9mp.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-a9mp.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-a9mp.dts deleted file mode 100644 index 967684b36..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-a9mp.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-eb-mp.dtsi" - -/ { - model = "ARM RealView EB Cortex A9 MPCore"; - - /* - * This is the Cortex A9 MPCore tile used with the - * RealView EB. - */ - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - A9_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - A9_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - A9_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - A9_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; -}; - -&pmu { - interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts deleted file mode 100644 index f533c8b49..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/* This derives from the Realview Baseboard, and overlays the new ethernet */ -#include "arm-realview-eb.dts" -#include "arm-realview-eb-bbrevd.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard Rev D"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi deleted file mode 100644 index a79e1d1d3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/ { - /* Introduce a fixed regulator for the new ethernet controller */ - veth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; -}; - -/* - * The revision D has a different ethernet controller that the elder boards: - * the older board uses LAN91C111 but the new one uses LAN9118. - */ -ðernet { - compatible = "smsc,lan9118", "smsc,lan9115"; - phy-mode = "mii"; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-mp.dtsi deleted file mode 100644 index 29b636fce..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb-mp.dtsi +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include "arm-realview-eb.dtsi" - -/* - * This is the common include file for all MPCore variants of the - * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B - * and Cortex-A9 MPCore. - */ -/ { - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-eb-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - /* Primary interrupt controller in the test chip */ - intc: interrupt-controller@1f000100 { - compatible = "arm,eb11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; - - /* Secondary interrupt controller on the FPGA */ - intc_second: interrupt-controller@10040000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - L2: l2-cache { - compatible = "arm,l220-cache"; - reg = <0x1f002000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s), probably for safety - * since th outer sync operation can cause the - * cache to hang unless disabled. - */ - cache-size = <1048576>; // 1MB - cache-sets = <4096>; - cache-line-size = <32>; - arm,shared-override; - arm,parity-enable; - arm,outer-sync-disable; - }; - - scu: scu@1f000000 { - compatible = "arm,arm11mp-scu"; - reg = <0x1f000000 0x100>; - }; - - twd_timer: timer@1f000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 13 0xf04>; - }; - - twd_wdog: watchdog@1f000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 14 0xf04>; - }; - - /* PMU with one IRQ line per core */ - pmu: pmu@0 { - compatible = "arm,arm11mpcore-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - }; -}; - -/* - * This adapts all the peripherals to the interrupt routing - * to the GIC on the core tile. - */ - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -/* - * On revision A, these peripherals does not have their IRQ lines - * routed to the core tile, but they can be reached on the secondary - * GIC. - */ -&gpio0 { - interrupt-parent = <&intc_second>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc_second>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc_second>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc_second>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&serial3 { - interrupt-parent = <&intc_second>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&ssp { - interrupt-parent = <&intc_second>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; - -&wdog { - interrupt-parent = <&intc_second>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb.dts deleted file mode 100644 index 15431077f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb.dts +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "arm-realview-eb.dtsi" - -/ { - model = "ARM RealView Emulation Baseboard"; - compatible = "arm,realview-eb"; - arm,hbi = <0x140>; - - /* - * This is the core tile with the CPU and GIC etc for the - * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache - * or PMU. - * - * To run this machine with QEMU, specify the following: - * qemu-system-arm -M realview-eb - * Unless specified, QEMU will emulate an ARM926EJ-S core tile. - * Switches -cpu arm1136 or -cpu arm1176 emulates the other - * core tiles. - */ - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-eb-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - intc: interrupt-controller@10040000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - }; - }; -}; - -/* - * This adapts all the peripherals to the interrupt routing - * to the GIC on the core tile. - */ - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&charlcd { - interrupt-parent = <&intc>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb.dtsi b/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb.dtsi deleted file mode 100644 index e2e959959..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-eb.dtsi +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "arm,realview-eb"; - - chosen { }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c; - }; - - memory { - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - }; - - flash1@44000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - }; - - /* SMSC LAN91C111 ethernet with PHY and EEPROM */ - ethernet: ethernet@4e000000 { - compatible = "smsc,lan91c111"; - reg = <0x4e000000 0x10000>; - /* - * This means the adapter can be accessed with 8, 16 or - * 32 bit reads/writes. - */ - reg-io-width = <7>; - }; - - usb: usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - port1-otg; - }; - - /* These peripherals are inside the FPGA */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: osc0@0c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: osc1@10 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: osc2@14 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: osc3@18 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: osc4@1c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - i2c: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mmc: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - charlcd: fpga_charlcd: charlcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp: ssp@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - wdog: watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - status = "disabled"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - clcd: clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - clocks = <&oscclk0>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - - port { - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pb1176.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-pb1176.dts deleted file mode 100644 index c789564f2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pb1176.dts +++ /dev/null @@ -1,570 +0,0 @@ -/* - * Copyright 2014 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "skeleton.dtsi" - -/ { - model = "ARM RealView PB1176"; - compatible = "arm,realview-pb1176"; - - chosen { }; - - aliases { - serial0 = &pb1176_serial0; - serial1 = &pb1176_serial1; - serial2 = &pb1176_serial2; - serial3 = &pb1176_serial3; - serial4 = &fpga_serial; - }; - - memory { - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash@30000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x30000000 0x4000000>; - bank-width = <4>; - }; - - fpga_flash@38000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x38000000 0x800000>; - bank-width = <4>; - }; - - /* - * The "secure flash" contains things like the boot - * monitor so we don't want people to accidentally - * screw this up. Mark the device tree node disabled - * by default. - */ - secflash@3c000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x3c000000 0x4000000>; - bank-width = <4>; - status = "disabled"; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet@3a000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x3a000000 0x10000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb@3b000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x3b000000 0x20000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - port1-otg; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb1176-soc", "simple-bus"; - regmap = <&syscon>; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: osc0@0c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: osc1@10 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: osc2@14 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: osc3@18 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: osc4@1c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - /* Primary DevChip GIC synthesized with the CPU */ - intc_dc1176: interrupt-controller@10120000 { - compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10121000 0x1000>, - <0x10120000 0x100>; - }; - - L2: l2-cache { - compatible = "arm,l220-cache"; - reg = <0x10110000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s). - */ - arm,override-auxreg; - cache-size = <131072>; // 128kB - cache-sets = <512>; - cache-line-size = <32>; - }; - - pmu { - compatible = "arm,arm1176-pmu"; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer01: timer@10104000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10104000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer23: timer@10105000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10105000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - pb1176_rtc: rtc@10108000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10108000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pb1176_gpio0: gpio@1010a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x1010a000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pb1176_ssp: ssp@1010b000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1010b000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - pb1176_serial0: serial@1010c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010c000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial1: serial@1010d000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010d000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial2: serial@1010e000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010e000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb1176_serial3: serial@1010f000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1010f000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - /* Direct-mapped development chip ROM */ - pb1176_rom@10200000 { - compatible = "direct-mapped"; - reg = <0x10200000 0x4000>; - bank-width = <1>; - }; - - clcd@10112000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10112000 0x1000>; - interrupt-parent = <&intc_dc1176>; - interrupt-names = "combined"; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&oscclk0>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - - port { - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; - }; - }; - - /* These peripherals are inside the FPGA rather than the DevChip */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - fpga_aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_mci: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 IRQ_TYPE_LEVEL_HIGH>; - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; - }; - - fpga_kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - fpga_kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - fpga_charlcd: charlcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_serial: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - /* This GIC on the board is cascaded off the DevChip GIC */ - intc_fpga1176: interrupt-controller@10040000 { - compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x10041000 0x1000>, - <0x10040000 0x100>; - interrupt-parent = <&intc_dc1176>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - }; - - fpga_gpio0: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_gpio1: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - fpga_rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - interrupt-parent = <&intc_fpga1176>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pb11mp.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-pb11mp.dts deleted file mode 100644 index 3944765ac..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ /dev/null @@ -1,682 +0,0 @@ -/* - * Copyright 2015 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "skeleton.dtsi" - -/ { - model = "ARM RealView PB11MPcore"; - compatible = "arm,realview-pb11mp"; - - chosen { }; - - aliases { - serial0 = &pb11mp_serial0; - serial1 = &pb11mp_serial1; - serial2 = &pb11mp_serial2; - serial3 = &pb11mp_serial3; - }; - - memory { - /* - * The PB11MPCore has 512 MiB memory @ 0x70000000 - * and the first 256 are also remapped @ 0x00000000 - */ - reg = <0x70000000 0x20000000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - MP11_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <0>; - next-level-cache = <&L2>; - }; - - MP11_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <1>; - next-level-cache = <&L2>; - }; - - MP11_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <2>; - next-level-cache = <&L2>; - }; - - MP11_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - /* Primary TestChip GIC synthesized with the CPU */ - intc_tc11mp: interrupt-controller@1f000100 { - compatible = "arm,tc11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,l220-cache"; - reg = <0x1f002000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, - <0 30 IRQ_TYPE_LEVEL_HIGH>, - <0 31 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s), probably for safety - * since th outer sync operation can cause the - * cache to hang unless disabled. - */ - cache-size = <1048576>; // 1MB - cache-sets = <4096>; - cache-line-size = <32>; - arm,shared-override; - arm,parity-enable; - arm,outer-sync-disable; - }; - - scu@1f000000 { - compatible = "arm,arm11mp-scu"; - reg = <0x1f000000 0x100>; - }; - - timer@1f000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <1 13 0xf04>; - }; - - watchdog@1f000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <1 14 0xf04>; - }; - - /* PMU with one IRQ line per core */ - pmu { - compatible = "arm,arm11mpcore-pmu"; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>, - <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - }; - - flash1@44000000 { - // 2 * 32MiB NOR Flash memory - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb11mp-soc", "simple-bus"; - regmap = <&pb11mp_syscon>; - ranges; - - pb11mp_syscon: syscon@10000000 { - compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - linux,default-trigger = "cpu1"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - linux,default-trigger = "cpu2"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - linux,default-trigger = "cpu3"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - - oscclk0: osc0@0c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: osc1@10 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: osc2@14 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: osc3@18 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: osc4@1c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - oscclk5: osc5@d4 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0xd4>; - clocks = <&xtal24mhz>; - }; - oscclk6: osc6@d8 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0xd8>; - clocks = <&xtal24mhz>; - }; - }; - - sp810_syscon: sysctl@10001000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x10001000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk0", - "timerclk1", - "timerclk2", - "timerclk3"; - assigned-clocks = <&sp810_syscon 0>, - <&sp810_syscon 1>, - <&sp810_syscon 2>, - <&sp810_syscon 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mci: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 IRQ_TYPE_LEVEL_HIGH>; - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - pb11mp_serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - pb11mp_serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - watchdog@1000f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x1000f000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - status = "disabled"; - }; - - watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&sp810_syscon 0>, - <&sp810_syscon 1>, - <&pclk>; - clock-names = "timerclk0", - "timerclk1", - "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - arm,sp804-has-irq = <1>; - clocks = <&sp810_syscon 2>, - <&sp810_syscon 3>, - <&pclk>; - clock-names = "timerclk2", - "timerclk3", - "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - interrupt-parent = <&intc_pb11mp>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer45: timer@10018000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10018000 0x1000>; - clocks = <&timclk>, <&pclk>; - clock-names = "timer", "apb_pclk"; - status = "disabled"; - }; - - timer67: timer@10019000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10019000 0x1000>; - clocks = <&timclk>, <&pclk>; - clock-names = "timer", "apb_pclk"; - status = "disabled"; - }; - - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-parent = <&intc_pb11mp>; - interrupt-names = "combined"; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&oscclk4>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ - - port { - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; - }; - - /* - * This GIC on the Platform Baseboard is cascaded off the - * TestChip GIC - */ - intc_pb11mp: interrupt-controller@1e000000 { - compatible = "arm,arm11mp-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000000 0x100>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet@4e000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x4e000000 0x10000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - interrupt-parent = <&intc_tc11mp>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; - port1-otg; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pba8.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-pba8.dts deleted file mode 100644 index d3238c252..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pba8.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-pbx.dtsi" - -/ { - model = "ARM RealView Platform Baseboard for Cortex-A8"; - compatible = "arm,realview-pba8"; - arm,hbi = <0x178>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - }; - }; - - pmu: pmu@0 { - compatible = "arm,cortex-a8-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; - }; - - /* Primary GIC PL390 interrupt controller in the test chip */ - intc: interrupt-controller@1e000000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000000 0x100>; - }; -}; - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&soc { - compatible = "arm,realview-pba8-soc", "simple-bus"; -}; - -&syscon { - compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd"; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog0 { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog1 { - interrupt-parent = <&intc>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer45 { - interrupt-parent = <&intc>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer67 { - interrupt-parent = <&intc>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/software/linux/kernel/arch/arm/boot/dts/arm-realview-pbx-a9.dts deleted file mode 100644 index 90d00b407..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pbx-a9.dts +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/dts-v1/; -#include "arm-realview-pbx.dtsi" - -/ { - /* - * This is the RealView Platform Baseboard Explore for Cortex-A9 - * (HBI0182 + HBI0183) as described in ARM DUI 0440B - */ - model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; - arm,hbi = <0x182>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "arm,realview-smp"; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - }; - }; - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x1>; - next-level-cache = <&L2>; - }; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x1f002000 0x1000>; - cache-unified; - cache-level = <2>; - /* - * Override default cache size, sets and - * associativity as these may be erroneously set - * up by boot loader(s). - */ - cache-size = <131072>; // 128KB - cache-sets = <512>; - cache-line-size = <32>; - arm,parity-disable; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - }; - - scu: scu@1f000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1f000000 0x100>; - }; - - twd_timer: timer@1f000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1f000600 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 13 0xf04>; - }; - - twd_wdog: watchdog@1f000620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1f000620 0x20>; - interrupt-parent = <&intc>; - interrupts = <1 14 0xf04>; - }; - - pmu: pmu@0 { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>, - <0 45 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CPU0>, <&CPU1>; - }; - - /* Primary GIC PL390 interrupt controller in the test chip */ - intc: interrupt-controller@1f000000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x1f001000 0x1000>, - <0x1f000100 0x100>; - }; -}; - -ðernet { - interrupt-parent = <&intc>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; -}; - -&usb { - interrupt-parent = <&intc>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial0 { - interrupt-parent = <&intc>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial1 { - interrupt-parent = <&intc>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial2 { - interrupt-parent = <&intc>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; -}; - -&serial3 { - interrupt-parent = <&intc>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; -}; - -&ssp { - interrupt-parent = <&intc>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog0 { - interrupt-parent = <&intc>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; -}; - -&wdog1 { - interrupt-parent = <&intc>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer01 { - interrupt-parent = <&intc>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer23 { - interrupt-parent = <&intc>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio0 { - interrupt-parent = <&intc>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio1 { - interrupt-parent = <&intc>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; -}; - -&gpio2 { - interrupt-parent = <&intc>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; -}; - -&rtc { - interrupt-parent = <&intc>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer45 { - interrupt-parent = <&intc>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; -}; - -&timer67 { - interrupt-parent = <&intc>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; -}; - -&aaci { - interrupt-parent = <&intc>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; -}; - -&mmc { - interrupt-parent = <&intc>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, - <0 18 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi0 { - interrupt-parent = <&intc>; - interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; -}; - -&kmi1 { - interrupt-parent = <&intc>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -}; - -&clcd { - interrupt-parent = <&intc>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pbx.dtsi b/software/linux/kernel/arch/arm/boot/dts/arm-realview-pbx.dtsi deleted file mode 100644 index aeb49c4bd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ /dev/null @@ -1,542 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "arm,realview-pbx"; - - chosen { }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c; - }; - - memory { - /* 128 MiB memory @ 0x0 */ - reg = <0x00000000 0x08000000>; - }; - - /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - veth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - refclk32khz: refclk32khz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - flash0@40000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x40000000 0x04000000>; - bank-width = <4>; - }; - - flash1@44000000 { - /* 2 * 32MiB NOR Flash memory */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x44000000 0x04000000>; - bank-width = <4>; - }; - - /* SMSC 9118 ethernet with PHY and EEPROM */ - ethernet: ethernet@4e000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x4e000000 0x10000>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; - }; - - usb: usb@4f000000 { - compatible = "nxp,usb-isp1761"; - reg = <0x4f000000 0x20000>; - port1-otg; - }; - - soc: soc@0 { - compatible = "arm,realview-pbx-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - regmap = <&syscon>; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; - reg = <0x10000000 0x1000>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - oscclk0: osc0@0c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0C>; - clocks = <&xtal24mhz>; - }; - oscclk1: osc1@10 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x10>; - clocks = <&xtal24mhz>; - }; - oscclk2: osc2@14 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x14>; - clocks = <&xtal24mhz>; - }; - oscclk3: osc3@18 { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x18>; - clocks = <&xtal24mhz>; - }; - oscclk4: osc4@1c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x1c>; - clocks = <&xtal24mhz>; - }; - }; - - sp810_syscon0: sysctl@10001000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x10001000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk0", - "timerclk1", - "timerclk2", - "timerclk3"; - assigned-clocks = <&sp810_syscon0 0>, - <&sp810_syscon0 1>, - <&sp810_syscon0 2>, - <&sp810_syscon0 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - - i2c: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - serial0: serial@10009000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x10009000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial1: serial@1000a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000a000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - serial2: serial@1000b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000b000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - ssp: ssp@1000d000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x1000d000 0x1000>; - clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - wdog0: watchdog@1000f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x1000f000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - status = "disabled"; - }; - - wdog1: watchdog@10010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x10010000 0x1000>; - clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; - status = "disabled"; - }; - - timer01: timer@10011000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10011000 0x1000>; - clocks = <&sp810_syscon0 0>, - <&sp810_syscon0 1>, - <&pclk>; - clock-names = "timerclk0", - "timerclk1", - "apb_pclk"; - }; - - timer23: timer@10012000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10012000 0x1000>; - clocks = <&sp810_syscon0 2>, - <&sp810_syscon0 3>, - <&pclk>; - clock-names = "timerclk2", - "timerclk3", - "apb_pclk"; - }; - - gpio0: gpio@10013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10013000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@10014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10014000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@10015000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x10015000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - /* DVI serial bus control is at 10016000 */ - - rtc: rtc@10017000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x10017000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer45: timer@10018000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10018000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timerclk4", "timerclk5", "apb_pclk"; - }; - - timer67: timer@10019000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x10019000 0x1000>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timerclk6", "timerclk7", "apb_pclk"; - }; - - sp810_syscon1: sysctl@1001a000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x1001a000 0x1000>; - clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclk4", - "timerclk5", - "timerclk6", - "timerclk7"; - assigned-clocks = <&sp810_syscon1 0>, - <&sp810_syscon1 1>, - <&sp810_syscon1 2>, - <&sp810_syscon1 3>; - assigned-clock-parents = <&timclk>, - <&timclk>, - <&timclk>, - <&timclk>; - }; - }; - - - /* These peripherals are inside the FPGA */ - fpga { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - aaci: aaci@10004000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x10004000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mmc: mmcsd@10005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x10005000 0x1000>; - - /* Due to frequent FIFO overruns, use just 500 kHz */ - max-frequency = <500000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - clocks = <&mclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - vmmc-supply = <&vmmc>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - kmi0: kmi@10006000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10006000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@10007000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x10007000 0x1000>; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - serial3: serial@1000c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x1000c000 0x1000>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - }; - - /* These peripherals are inside the NEC ISSP */ - issp { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - clcd: clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - clocks = <&oscclk4>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - - port { - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; - }; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-db.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-db.dts deleted file mode 100644 index 033fa6354..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-db.dts +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Device Tree file for Marvell Armada 370 evaluation board - * (DB-88F6710-BP-DDR3) - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-370.dtsi" - -/ { - model = "Marvell Armada 370 Evaluation Board"; - compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - status = "okay"; - audio_codec: audio-codec@4a { - #sound-dai-cells = <0>; - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - - audio-controller@30000 { - pinctrl-0 = <&i2s_pins2>; - pinctrl-names = "default"; - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins1>; - pinctrl-names = "default"; - /* - * This device is disabled by default, because - * using the SD card connector requires - * changing the default CON40 connector - * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a - * different connector - * "DB-88F6710_MPP_RGMII_SD_Jumper". - */ - status = "disabled"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; - }; - - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * both standard PCIe slots and mini-PCIe - * slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Armada 370 DB Audio"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Headphone", "Out Jack", - "Line", "In Jack"; - simple-audio-card,routing = - "Out Jack", "HPL", - "Out Jack", "HPR", - "AIN1L", "In Jack", - "AIN1L", "In Jack"; - status = "okay"; - - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 0>; - }; - - codec { - sound-dai = <&audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 1>; - }; - - codec { - sound-dai = <&spdif_out>; - }; - }; - - simple-audio-card,dai-link@2 { - format = "i2s"; - cpu { - sound-dai = <&audio_controller 1>; - }; - - codec { - sound-dai = <&spdif_in>; - }; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; - - spdif_in: spdif-in { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - }; -}; - -&spi0 { - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mx25l25635e", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-dlink-dns327l.dts deleted file mode 100644 index e2a363b1d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-dlink-dns327l.dts +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Device Tree file for D-Link DNS-327L - * - * Copyright (C) 2015, Andrew Andrianov - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* Remaining unsolved: - * There's still some unknown device on i2c address 0x13 - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "D-Link DNS-327L"; - compatible = "dlink,dns327l", - "marvell,armada370", - "marvell,armada-370-xp"; - - chosen { - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MiB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - usb@50000 { - status = "okay"; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "u-boot"; - /* 1.0 MiB */ - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - /* 128 KiB */ - reg = <0x100000 0x20000>; - read-only; - }; - - partition@120000 { - label = "uImage"; - /* 7 MiB */ - reg = <0x120000 0x700000>; - }; - - partition@820000 { - label = "ubifs"; - /* ~ 84 MiB */ - reg = <0x820000 0x54e0000>; - }; - - /* Hardcoded into stock bootloader */ - partition@5d00000 { - label = "failsafe-uImage"; - /* 5 MiB */ - reg = <0x5d00000 0x500000>; - }; - - partition@6200000 { - label = "failsafe-fs"; - /* 29 MiB */ - reg = <0x6200000 0x1d00000>; - }; - - partition@7f00000 { - label = "bbt"; - /* 1 MiB for BBT */ - reg = <0x7f00000 0x100000>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = < - &backup_button_pin - &power_button_pin - &reset_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < - &sata_l_amber_pin - &sata_r_amber_pin - &backup_led_pin - /* Ensure these are managed by hardware */ - &sata_l_white_pin - &sata_r_white_pin>; - - pinctrl-names = "default"; - - sata-r-amber-pin { - label = "dns327l:amber:sata-r"; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - sata-l-amber-pin { - label = "dns327l:amber:sata-l"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - backup-led-pin { - label = "dns327l:white:usb"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-0 = <&xhci_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "USB3.0 Port Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - - sata_r_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-0 = <&sata_r_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "SATA-R Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - - sata_l_power: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-0 = <&sata_l_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "SATA-L Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - sata_l_white_pin: sata-l-white-pin { - marvell,pins = "mpp57"; - marvell,function = "sata0"; - }; - - sata_r_white_pin: sata-r-white-pin { - marvell,pins = "mpp55"; - marvell,function = "sata1"; - }; - - sata_r_amber_pin: sata-r-amber-pin { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - sata_l_amber_pin: sata-l-amber-pin { - marvell,pins = "mpp53"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp61"; - marvell,function = "gpo"; - }; - - xhci_pwr_pin: xhci-pwr-pin { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - sata_r_pwr_pin: sata-r-pwr-pin { - marvell,pins = "mpp54"; - marvell,function = "gpio"; - }; - - sata_l_pwr_pin: sata-l-pwr-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp60", "mpp61"; - marvell,function = "uart1"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; -}; - -/* Serial console */ -&uart0 { - status = "okay"; -}; - -/* Connected to Weltrend MCU */ -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - marvell,reg-init = <0x0 0x16 0x0 0x0002>, - <0x0 0x19 0x0 0x0077>, - <0x0 0x18 0x0 0x5747>; - }; -}; - -ð1 { - phy = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - compatible = "marvell,mv64xxx-i2c"; - clock-frequency = <100000>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-mirabox.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-mirabox.dts deleted file mode 100644 index d5e19cd4d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-mirabox.dts +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Device Tree file for Globalscale Mirabox - * - * Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "armada-370.dtsi" - -/ { - model = "Globalscale Mirabox"; - compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected on the PCB to a USB 3.0 XHCI controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - timer@20300 { - clock-frequency = <600000000>; - status = "okay"; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_led_pin &stat_led_pins>; - - green_pwr_led { - label = "mirabox:green:pwr"; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - blue_stat_led { - label = "mirabox:blue:stat"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - green_stat_led { - label = "mirabox:green:stat"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - crypto@90000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins3>; - pinctrl-names = "default"; - status = "okay"; - /* - * No CD or WP GPIOs: SDIO interface used for - * Wifi/Bluetooth chip - */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - pca9505: pca9505@25 { - compatible = "nxp,pca9505"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x25>; - }; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - partition@400000 { - label = "Linux"; - reg = <0x400000 0x400000>; - }; - partition@800000 { - label = "Filesystem"; - reg = <0x800000 0x3f800000>; - }; - }; - }; - }; -}; - -&pinctrl { - pwr_led_pin: pwr-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - stat_led_pins: stat-led-pins { - marvell,pins = "mpp64", "mpp65"; - marvell,function = "gpio"; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-netgear-rn102.dts deleted file mode 100644 index 39181b3fa..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Device Tree file for NETGEAR ReadyNAS 102 - * - * Copyright (C) 2013, Arnaud EBALARD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "NETGEAR ReadyNAS 102"; - compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* Connected to Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - serial@12000 { - status = "okay"; - }; - - /* eSATA interface */ - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - clock-frequency = <100000>; - status = "okay"; - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&power_led_pin - &sata1_led_pin - &sata2_led_pin - &backup_led_pin>; - pinctrl-names = "default"; - - blue-power-led { - label = "rn102:blue:pwr"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - blue-sata1-led { - label = "rn102:blue:sata1"; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - blue-sata2-led { - label = "rn102:blue:sata2"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - blue-backup-led { - label = "rn102:blue:backup"; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin - &reset_button_pin - &backup_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - power_led_pin: power-led-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - poweroff: poweroff { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-netgear-rn104.dts deleted file mode 100644 index 11565752b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Device Tree file for NETGEAR ReadyNAS 104 - * - * Copyright (C) 2013, Arnaud EBALARD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "NETGEAR ReadyNAS 104"; - compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to Marvell 88SE9215 SATA controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - serial@12000 { - status = "okay"; - }; - - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - clock-frequency = <100000>; - status = "okay"; - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - pca9554: pca9554@23 { - compatible = "nxp,pca9554"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x23>; - }; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&backup_led_pin &power_led_pin>; - pinctrl-names = "default"; - - blue-backup-led { - label = "rn104:blue:backup"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue-power-led { - label = "rn104:blue:pwr"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "keep"; - }; - - blue-sata1-led { - label = "rn104:blue:sata1"; - gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata2-led { - label = "rn104:blue:sata2"; - gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata3-led { - label = "rn104:blue:sata3"; - gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue-sata4-led { - label = "rn104:blue:sata4"; - gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&backup_button_pin - &power_button_pin - &reset_button_pin>; - pinctrl-names = "default"; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - }; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - poweroff: poweroff { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-rd.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-rd.dts deleted file mode 100644 index fbef730e8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-rd.dts +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Device Tree file for Marvell Armada 370 Reference Design board - * (RD-88F6710-A1) - * - * Copied from arch/arm/boot/dts/armada-370-db.dts - * - * Copyright (C) 2013 Florian Fainelli - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include -#include -#include "armada-370.dtsi" - -/ { - model = "Marvell Armada 370 Reference Design"; - compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Internal mini-PCIe connector */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins1>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@1 { - label = "Software Button"; - linux,code = ; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 3000 1>; - pinctrl-0 = <&fan_pins>; - pinctrl-names = "default"; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - sw_led { - label = "370rd:green:sw"; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; - }; - - dsa@0 { - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð1>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; - }; - -&pinctrl { - fan_pins: fan-pins { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - led_pins: led-pins { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts deleted file mode 100644 index fef0110a8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate NAS 2-Bay - * Code name (board/PCB) : Dart 2-Bay - * Model name (case sticker) : SRPD20 - * Material desc (product spec) : STCTxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-nas-xbay.dtsi" - -/ { - model = "Seagate NAS 2-Bay (Dart, SRPD20)"; - compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp"; - - gpio-fan { - gpio-fan,speed-map = - < 0 3 - 950 2 - 1400 1 - 1800 0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts deleted file mode 100644 index ae2e1fe50..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate NAS 4-Bay - * Code name (board/PCB) : Dart 4-Bay - * Model name (case sticker) : SRPD40 - * Material desc (product spec) : STCUxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-nas-xbay.dtsi" -#include - -/ { - model = "Seagate NAS 4-Bay (Dart, SRPD40)"; - compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - pcie-controller { - /* SATA AHCI controller 88SE9170 */ - pcie@1,0 { - status = "okay"; - }; - }; - - internal-regs { - mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - ethernet@74000 { - status = "okay"; - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - /* I2C GPIO expander (PCA9554A) */ - pca9554: pca9554@21 { - compatible = "nxp,pca9554"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - }; - }; - - regulators { - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "SATA2 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>; - }; - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "SATA3 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - red-sata2 { - label = "dart:red:sata2"; - gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; - }; - red-sata3 { - label = "dart:red:sata3"; - gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; - }; - }; - - leds-ns2 { - compatible = "lacie,ns2-leds"; - - white-sata2 { - label = "dart:white:sata2"; - cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>; - slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>; - num-modes = <4>; - modes-map = ; - }; - white-sata3 { - label = "dart:white:sata3"; - cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; - slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>; - num-modes = <4>; - modes-map = ; - }; - }; - - gpio-fan { - gpio-fan,speed-map = - < 0 3 - 800 2 - 1050 1 - 1300 0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi deleted file mode 100644 index 3036e25c5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Vincent Donnefort - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * TODO: add support for the white SATA LEDs associated with HDD 0 and 1. - */ - -#include "armada-370.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* USB 3.0 bridge ASM1042A */ - pcie@2,0 { - status = "okay"; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - ethernet@70000 { - status = "okay"; - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - i2c@11000 { - status = "okay"; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <100000>; - - /* RTC - NXP 8563T (second source) */ - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - interrupts = <110>; - }; - /* RTC - MCP7940NT */ - rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts = <110>; - }; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x300000>; - }; - partition@300000 { - label = "device-tree"; - reg = <0x300000 0x20000>; - }; - partition@320000 { - label = "linux"; - reg = <0x320000 0x2000000>; - }; - partition@2320000 { - label = "rootfs"; - reg = <0x2320000 0xdce0000>; - }; - }; - }; - - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH - &gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - button@2 { - label = "Backup button"; - linux,code = ; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - button@3 { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - white-power { - label = "dart:white:power"; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - - }; - red-power { - label = "dart:red:power"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - }; - red-sata0 { - label = "dart:red:sata0"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - red-sata1 { - label = "dart:red:sata1"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>; - pinctrl-names = "default"; - - hdd0_led_sata_pin: hdd0-led-sata-pin { - marvell,pins = "mpp48"; - marvell,function = "sata1"; - }; - hdd0_led_gpio_pin: hdd0-led-gpio-pin { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - hdd1_led_sata_pin: hdd1-led-sata-pin { - marvell,pins = "mpp57"; - marvell,function = "sata0"; - }; - hdd1_led_gpio_pin: hdd1-led-gpio-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts deleted file mode 100644 index 3c91f9821..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate Personal Cloud 2-Bay - * Code name (board/PCB) : Cumulus Max - * Model name (case sticker) : SRN22C - * Material desc (product spec) : STCSxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-personal-cloud.dtsi" - -/ { - model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)"; - compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - internal-regs { - sata@a0000 { - status = "okay"; - nr-ports = <2>; - }; - }; - }; - - regulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts deleted file mode 100644 index aad39e97a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * Here are some information allowing to identify the device: - * - * Product name : Seagate Personal Cloud - * Code name (board/PCB) : Cumulus - * Model name (case sticker) : SRN21C - * Material desc (product spec) : STCRxxxxxxx - */ - -/dts-v1/; -#include "armada-370-seagate-personal-cloud.dtsi" - -/ { - model = "Seagate Personal Cloud (Cumulus, SRN21C)"; - compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp"; - - soc { - internal-regs { - sata@a0000 { - status = "okay"; - nr-ports = <1>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi deleted file mode 100644 index 01cded310..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay - * (Armada 370 SoC). - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * TODO: add support for the white SATA LED. - */ - -#include "armada-370.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* USB 3.0 Bridge ASM1042A */ - pcie@1,0 { - status = "okay"; - }; - }; - - internal-regs { - coherency-fabric@20200 { - broken-idle; - }; - - serial@12000 { - status = "okay"; - }; - - mdio { - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - ethernet@74000 { - status = "okay"; - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - debounce-interval = <100>; - }; - button@2 { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - button@3 { - label = "USB VBUS error"; - linux,code = ; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-sata0 { - label = "cumulus:red:sata0"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - pinctrl-0 = <&sata_led_pin>; - pinctrl-names = "default"; - - sata_led_pin: sata-led-pin { - marvell,pins = "mpp60"; - marvell,function = "sata0"; - }; - gpio_led_pin: gpio-led-pin { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - /* MX25L8006E */ - compatible = "mxicy,mx25l8005", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/software/linux/kernel/arch/arm/boot/dts/armada-370-synology-ds213j.dts deleted file mode 100644 index a9cc42776..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Device Tree file for Synology DS213j - * - * Copyright (C) 2014, Arnaud EBALARD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the old 0xd0000000). - * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot - * bootloaders provided by Marvell. It is used in recent versions of - * DSM software provided by Synology. Nonetheless, some earlier boards - * were delivered with an older version of u-boot that left internal - * registers mapped at 0xd0000000. If you have such a device you will - * not be able to directly boot a kernel based on this Device Tree. In - * that case, the preferred solution is to update your bootloader (e.g. - * by upgrading to latest version of DSM, or building a new one and - * installing it from u-boot prompt) or adjust the Devive Tree - * (s/0xf1000000/0xd0000000/ in 'ranges' below). - */ - -/dts-v1/; - -#include -#include -#include "armada-370.dtsi" - -/ { - model = "Synology DS213j"; - compatible = "synology,ds213j", "marvell,armada370", - "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - - /* RTC provided by Seiko S-35390A I2C RTC chip below */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; - - /* Main device RTC chip */ - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - /* Connected to a header on device's PCB */ - serial@12000 { - status = "okay"; - }; - - /* Connected to a TI MSP430F2111 for power control */ - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - /* rear USB port, near reset button */ - usb@50000 { - status = "okay"; - }; - - /* rear USB port, near RJ45 port */ - usb@51000 { - status = "okay"; - }; - - mdio { - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - }; - }; - - gpio-fan-32-38 { - status = "okay"; - compatible = "gpio-fan"; - pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin - &fan_ctrl_high_pin &fan_alarm_pin>; - pinctrl-names = "default"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH - &gpio2 0 GPIO_ACTIVE_HIGH - &gpio2 1 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 1000 1 - 1150 2 - 1350 4 - 1500 3 - 1650 5 - 1750 6 - 1900 7 >; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&disk1_led_pin - &disk2_led_pin>; - pinctrl-names = "default"; - - disk1-led-amber { - label = "synology:amber:disk1"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - disk2-led-amber { - label = "synology:amber:disk2"; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; - pinctrl-names = "default"; - - sata1_regulator: sata1-regulator { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - sata2_regulator: sata2-regulator { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA2 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - disk1_led_pin: disk1-led-pin { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - disk2_led_pin: disk2-led-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - sata1_pwr_pin: sata1-pwr-pin { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - sata2_pwr_pin: sata2-pwr-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - syno_id_bit0_pin: syno-id-bit0-pin { - marvell,pins = "mpp55"; - marvell,function = "gpio"; - }; - - syno_id_bit1_pin: syno-id-bit1-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - syno_id_bit2_pin: syno-id-bit2-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; - - syno_id_bit3_pin: syno-id-bit3-pin { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - - fan_ctrl_low_pin: fan-ctrl-low-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; - - fan_ctrl_mid_pin: fan-ctrl-mid-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; - - fan_ctrl_high_pin: fan-ctrl-high-pin { - marvell,pins = "mpp63"; - marvell,function = "gpio"; - }; - - fan_alarm_pin: fan-alarm-pin { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@00000000 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@000c0000 { /* uImage */ - label = "zImage"; - reg = <0x000c0000 0x002d0000>; /* 2880KB */ - }; - - partition@00390000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x00390000 0x00440000>; /* 4250KB */ - }; - - partition@007d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@007e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@007f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370-xp.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-370-xp.dtsi deleted file mode 100644 index 3ccedc9df..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370-xp.dtsi +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 370 and Armada XP SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * Ben Dooks - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * This file contains the definitions that are common to the Armada - * 370 and Armada XP SoC. - */ - -/include/ "skeleton64.dtsi" - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - model = "Marvell Armada 370 and XP SoC"; - compatible = "marvell,armada-370-xp"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "marvell,sheeva-v7"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&mpic>; - pcie-mem-aperture = <0xf8000000 0x7e00000>; - pcie-io-aperture = <0xffe00000 0x100000>; - - devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <50>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <31>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <41>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <42>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl: pin-ctrl@18000 { - reg = <0x18000 0x38>; - }; - - coredivclk: corediv-clock@18740 { - compatible = "marvell,armada-370-corediv-clock"; - reg = <0x18740 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, - <0x20250 0x8>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - }; - - coherency-fabric@20200 { - compatible = "marvell,coherency-fabric"; - reg = <0x20200 0xb0>, <0x21010 0x1c>; - }; - - timer@20300 { - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - }; - - watchdog@20300 { - reg = <0x20300 0x34>, <0x20704 0x4>; - }; - - pmsu@22000 { - compatible = "marvell,armada-370-pmsu"; - reg = <0x22000 0x1000>; - }; - - usb@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x500>; - interrupts = <45>; - status = "disabled"; - }; - - usb@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x500>; - interrupts = <46>; - status = "disabled"; - }; - - eth0: ethernet@70000 { - reg = <0x70000 0x4000>; - interrupts = <8>; - clocks = <&gateclk 4>; - status = "disabled"; - }; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x72004 0x4>; - clocks = <&gateclk 4>; - }; - - eth1: ethernet@74000 { - reg = <0x74000 0x4000>; - interrupts = <10>; - clocks = <&gateclk 3>; - status = "disabled"; - }; - - sata@a0000 { - compatible = "marvell,armada-370-sata"; - reg = <0xa0000 0x5000>; - interrupts = <55>; - clocks = <&gateclk 15>, <&gateclk 30>; - clock-names = "0", "1"; - status = "disabled"; - }; - - nand@d0000 { - compatible = "marvell,armada370-nand"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <113>; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - mvsdio@d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd4000 0x200>; - interrupts = <54>; - clocks = <&gateclk 17>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; - - spi0: spi@10600 { - reg = , /* control */ - , /* CS0 */ - , /* CS1 */ - , /* CS2 */ - , /* CS3 */ - , /* CS4 */ - , /* CS5 */ - , /* CS6 */ - ; /* CS7 */ - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - reg = , /* control */ - , /* CS0 */ - , /* CS1 */ - , /* CS2 */ - , /* CS3 */ - , /* CS4 */ - , /* CS5 */ - , /* CS6 */ - ; /* CS7 */ - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 2 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - }; - }; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-370.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-370.dtsi deleted file mode 100644 index b4258105e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-370.dtsi +++ /dev/null @@ -1,447 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 370 family SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Contains definitions specific to the Armada 370 SoC that are not - * common to all Armada SoCs. - */ - -#include "armada-370-xp.dtsi" -/include/ "skeleton.dtsi" - -/ { - model = "Marvell Armada 370 family SoC"; - compatible = "marvell,armada370", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - soc { - compatible = "marvell,armada370-mbus", "simple-bus"; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - pcie-controller { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - }; - - internal-regs { - L2: l2-cache { - compatible = "marvell,aurora-outer-cache"; - reg = <0x08000 0x1000>; - cache-id-part = <0x100>; - cache-level = <2>; - cache-unified; - wt-override; - }; - - i2c0: i2c@11000 { - reg = <0x11000 0x20>; - }; - - i2c1: i2c@11100 { - reg = <0x11100 0x20>; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - /* - * Default UART pinctrl setting without RTS/CTS, can - * be overwritten on board level if a different - * configuration is used. - */ - uart0: serial@12000 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - }; - - uart1: serial@12100 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; - - system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-370-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18230 { - compatible = "marvell,armada-370-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - - thermal@18300 { - compatible = "marvell,armada370-thermal"; - reg = <0x18300 0x4 - 0x18304 0x4>; - status = "okay"; - }; - - sscg@18330 { - reg = <0x18330 0x4>; - }; - - interrupt-controller@20a00 { - reg = <0x20a00 0x1d0>, <0x21870 0x58>; - }; - - timer@20300 { - compatible = "marvell,armada-370-timer"; - clocks = <&coreclk 2>; - }; - - watchdog@20300 { - compatible = "marvell,armada-370-wdt"; - clocks = <&coreclk 2>; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x8>; - }; - - cpu-config@21000 { - compatible = "marvell,armada-370-cpu-config"; - reg = <0x21000 0x8>; - }; - - audio_controller: audio-controller@30000 { - #sound-dai-cells = <1>; - compatible = "marvell,armada370-audio"; - reg = <0x30000 0x4000>; - interrupts = <93>; - clocks = <&gateclk 0>; - clock-names = "internal"; - status = "disabled"; - }; - - usb@50000 { - clocks = <&coreclk 0>; - }; - - usb@51000 { - clocks = <&coreclk 0>; - }; - - xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - status = "okay"; - - xor00 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - status = "okay"; - - xor10 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - ethernet@70000 { - compatible = "marvell,armada-370-neta"; - }; - - ethernet@74000 { - compatible = "marvell,armada-370-neta"; - }; - - crypto@90000 { - compatible = "marvell,armada-370-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>; - clocks = <&gateclk 23>; - clock-names = "cesa0"; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x7e0>; - }; - }; - - crypto_sram: sa-sram { - compatible = "mmio-sram"; - reg = ; - reg-names = "sram"; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; - - /* - * The Armada 370 has an erratum preventing the use of - * the standard workflow for CPU idle support (relying - * on the BootROM code to enter/exit idle state). - * Reserve some amount of the crypto SRAM to put the - * cpuidle workaround. - */ - idle-sram@0 { - reg = <0x0 0x20>; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv88f6710-pinctrl"; - - spi0_pins1: spi0-pins1 { - marvell,pins = "mpp33", "mpp34", - "mpp35", "mpp36"; - marvell,function = "spi0"; - }; - - spi0_pins2: spi0_pins2 { - marvell,pins = "mpp32", "mpp63", - "mpp64", "mpp65"; - marvell,function = "spi0"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp49", "mpp50", - "mpp51", "mpp52"; - marvell,function = "spi1"; - }; - - uart0_pins: uart0-pins { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "uart0"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp41", "mpp42"; - marvell,function = "uart1"; - }; - - sdio_pins1: sdio-pins1 { - marvell,pins = "mpp9", "mpp11", "mpp12", - "mpp13", "mpp14", "mpp15"; - marvell,function = "sd0"; - }; - - sdio_pins2: sdio-pins2 { - marvell,pins = "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52"; - marvell,function = "sd0"; - }; - - sdio_pins3: sdio-pins3 { - marvell,pins = "mpp48", "mpp49", "mpp50", - "mpp51", "mpp52", "mpp53"; - marvell,function = "sd0"; - }; - - i2c0_pins: i2c0-pins { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - i2s_pins1: i2s-pins1 { - marvell,pins = "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", - "mpp12", "mpp13"; - marvell,function = "audio"; - }; - - i2s_pins2: i2s-pins2 { - marvell,pins = "mpp49", "mpp47", "mpp50", - "mpp59", "mpp57", "mpp61", - "mpp62", "mpp60", "mpp58"; - marvell,function = "audio"; - }; - - mdio_pins: mdio-pins { - marvell,pins = "mpp17", "mpp18"; - marvell,function = "ge"; - }; - - ge0_rgmii_pins: ge0-rgmii-pins { - marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", "mpp12", - "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge1-rgmii-pins { - marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27", "mpp28", "mpp29", "mpp30"; - marvell,function = "ge1"; - }; -}; - -/* - * Default SPI pinctrl setting, can be overwritten on - * board level if a different configuration is used. - */ -&spi0 { - compatible = "marvell,armada-370-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins1>; - pinctrl-names = "default"; -}; - -&spi1 { - compatible = "marvell,armada-370-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-375-db.dts b/software/linux/kernel/arch/arm/boot/dts/armada-375-db.dts deleted file mode 100644 index cded5f0a2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-375-db.dts +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Device Tree file for Marvell Armada 375 evaluation board - * (DB-88F6720) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "armada-375.dtsi" - -/ { - model = "Marvell Armada 375 Development Board"; - compatible = "marvell,a375-db", "marvell,armada375"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - spi@10600 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - /* - * SPI conflicts with NAND, so we disable it - * here, and select NAND as the enabled device - * by default. - */ - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - }; - - i2c@11100 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - }; - - serial@12000 { - status = "okay"; - }; - - pinctrl { - sdio_st_pins: sdio-st-pins { - marvell,pins = "mpp44", "mpp45"; - marvell,function = "gpio"; - }; - }; - - sata@a0000 { - status = "okay"; - nr-ports = <2>; - }; - - nand: nand@d0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - - usb@54000 { - status = "okay"; - }; - - usb3@58000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins &sdio_st_pins>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; - }; - - ethernet@f0000 { - status = "okay"; - - eth0@c4000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - eth1@c5000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "gmii"; - }; - }; - }; - - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-375.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-375.dtsi deleted file mode 100644 index 024f1b75b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-375.dtsi +++ /dev/null @@ -1,656 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 375 family SoC - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - model = "Marvell Armada 375 family SoC"; - compatible = "marvell,armada375"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - serial0 = &uart0; - serial1 = &uart1; - }; - - clocks { - /* 2 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-375-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada375-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x58>; - }; - - timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0xc0054 0x4>; - clocks = <&gateclk 19>; - }; - - /* Network controller */ - ethernet@f0000 { - compatible = "marvell,armada-375-pp2"; - reg = <0xf0000 0xa000>, /* Packet Processor regs */ - <0xc0000 0x3060>, /* LMS regs */ - <0xc4000 0x100>, /* eth0 regs */ - <0xc5000 0x100>; /* eth1 regs */ - clocks = <&gateclk 3>, <&gateclk 19>; - clock-names = "pp_clk", "gop_clk"; - status = "disabled"; - - eth0: eth0@c4000 { - interrupts = ; - port-id = <0>; - status = "disabled"; - }; - - eth1: eth1@c5000 { - interrupts = ; - port-id = <1>; - status = "disabled"; - }; - }; - - rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = ; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-375-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-375-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl { - compatible = "marvell,mv88f6720-pinctrl"; - reg = <0x18000 0x24>; - - i2c0_pins: i2c0-pins { - marvell,pins = "mpp14", "mpp15"; - marvell,function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - marvell,pins = "mpp61", "mpp62"; - marvell,function = "i2c1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp0", "mpp1", "mpp2", - "mpp3", "mpp4", "mpp5", - "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13"; - marvell,function = "nand"; - }; - - sdio_pins: sdio-pins { - marvell,pins = "mpp24", "mpp25", "mpp26", - "mpp27", "mpp28", "mpp29"; - marvell,function = "sd"; - }; - - spi0_pins: spi0-pins { - marvell,pins = "mpp0", "mpp1", "mpp4", - "mpp5", "mpp8", "mpp9"; - marvell,function = "spi0"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - system-controller@18200 { - compatible = "marvell,armada-375-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-375-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - usbcluster: usb-cluster@18400 { - compatible = "marvell,armada-375-usb-cluster"; - reg = <0x18400 0x4>; - #phy-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer@20300 { - compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 0>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-375-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; - clocks = <&coreclk 0>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - coherency-fabric@21010 { - compatible = "marvell,armada-375-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - usb@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x500>; - interrupts = ; - clocks = <&gateclk 18>; - phys = <&usbcluster PHY_TYPE_USB2>; - phy-names = "usb"; - status = "disabled"; - }; - - usb@54000 { - compatible = "marvell,orion-ehci"; - reg = <0x54000 0x500>; - interrupts = ; - clocks = <&gateclk 26>; - status = "disabled"; - }; - - usb3@58000 { - compatible = "marvell,armada-375-xhci"; - reg = <0x58000 0x20000>,<0x5b880 0x80>; - interrupts = ; - clocks = <&gateclk 16>; - phys = <&usbcluster PHY_TYPE_USB3>; - phy-names = "usb"; - status = "disabled"; - }; - - xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 23>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - crypto@90000 { - compatible = "marvell,armada-375-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = , - ; - clocks = <&gateclk 30>, <&gateclk 31>, - <&gateclk 28>, <&gateclk 29>; - clock-names = "cesa0", "cesa1", - "cesaz0", "cesaz1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - sata@a0000 { - compatible = "marvell,armada-370-sata"; - reg = <0xa0000 0x5000>; - interrupts = ; - clocks = <&gateclk 14>, <&gateclk 20>; - clock-names = "0", "1"; - status = "disabled"; - }; - - nand@d0000 { - compatible = "marvell,armada370-nand"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = ; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - mvsdio@d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd4000 0x200>; - interrupts = ; - clocks = <&gateclk 17>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - - thermal@e8078 { - compatible = "marvell,armada375-thermal"; - reg = <0xe8078 0x4>, <0xe807c 0x8>; - status = "okay"; - }; - - coreclk: mvebu-sar@e8204 { - compatible = "marvell,armada-375-core-clock"; - reg = <0xe8204 0x04>; - #clock-cells = <1>; - }; - - coredivclk: corediv-clock@e8250 { - compatible = "marvell,armada-375-corediv-clock"; - reg = <0xe8250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - }; - - pcie-controller { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 30>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 31>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-380.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-380.dtsi deleted file mode 100644 index 5102d19cc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-380.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 380 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armada-38x.dtsi" - -/ { - model = "Marvell Armada 380 family SoC"; - compatible = "marvell,armada380"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-380-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - }; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6810-pinctrl"; - }; - }; - - pcie-controller { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; - - /* x1 port */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-385-db-ap.dts b/software/linux/kernel/arch/arm/boot/dts/armada-385-db-ap.dts deleted file mode 100644 index db5b9f6b6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-385-db-ap.dts +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Device Tree file for Marvell Armada 385 Access Point Development board - * (DB-88F6820-AP) - * - * Copyright (C) 2014 Marvell - * - * Nadav Haklai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-385.dtsi" - -#include - -/ { - model = "Marvell Armada 385 Access Point Development Board"; - compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c0: i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - /* - * This bus is wired to two EEPROM - * sockets, one of which holding the - * board ID used by the bootloader. - * Erasing this EEPROM's content will - * brick the board. - * Use this bus with caution. - */ - }; - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@4 { - reg = <4>; - }; - - phy2: ethernet-phy@6 { - reg = <6>; - }; - }; - - /* UART0 is exposed through the JP8 connector */ - uart0: serial@12000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - /* - * UART1 is exposed through a FTDI chip - * wired to the mini-USB connector - */ - uart1: serial@12100 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - }; - - pinctrl@18000 { - xhci0_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - - /* CON3 */ - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - bm,pool-short = <3>; - }; - - /* CON2 */ - ethernet@34000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - usb@58000 { - status = "okay"; - }; - - /* CON4 */ - ethernet@70000 { - pinctrl-names = "default"; - - /* - * The Reference Clock 0 is used to - * provide a clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <3>; - }; - - bm@c8000 { - status = "okay"; - }; - - nfc: flash@d0000 { - status = "okay"; - num-cs = <1>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x00000000 0x00800000>; - read-only; - }; - - partition@800000 { - label = "uImage"; - reg = <0x00800000 0x00400000>; - read-only; - }; - - partition@c00000 { - label = "Root"; - reg = <0x00c00000 0x3f400000>; - }; - }; - }; - - usb3@f0000 { - status = "okay"; - usb-phy = <&usb3_phy>; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie-controller { - status = "okay"; - - /* - * The three PCIe units are accessible through - * standard mini-PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - }; - }; - - usb3_phy: usb3_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_xhci0_vbus>; - }; - - reg_xhci0_vbus: xhci0-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-name = "xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <54000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys-caiman.dts deleted file mode 100644 index f3cee918d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys-caiman.dts +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Device Tree include for the Linksys WRT1200AC (Caiman) - * - * Copyright (C) 2015 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT1200AC"; - compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - - soc { - internal-regs{ - i2c@11000 { - - pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; - - wan_amber@0 { - label = "caiman:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "caiman:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "caiman:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "caiman:white:wlan_5g"; - reg = <0x3>; - }; - - usb2@5 { - label = "caiman:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "caiman:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "caiman:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "caiman:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "caiman:amber:wps"; - reg = <0x9>; - }; - }; - }; - }; - }; - - gpio-leds { - power { - label = "caiman:white:power"; - }; - - sata { - label = "caiman:white:sata"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys-cobra.dts deleted file mode 100644 index 111071860..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys-cobra.dts +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Device Tree file for the Linksys WRT1900ACv2 (Cobra) - * - * Copyright (C) 2015 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-385-linksys.dtsi" - -/ { - model = "Linksys WRT1900ACv2"; - compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - - soc { - internal-regs{ - i2c@11000 { - - pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; - - wan_amber@0 { - label = "cobra:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "cobra:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "cobra:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "cobra:white:wlan_5g"; - reg = <0x3>; - }; - - usb2@5 { - label = "cobra:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "cobra:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "cobra:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "cobra:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "cobra:amber:wps"; - reg = <0x9>; - }; - }; - }; - }; - }; - - gpio-leds { - power { - label = "cobra:white:power"; - }; - - sata { - label = "cobra:white:sata"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys.dtsi deleted file mode 100644 index 8f0e508f6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-385-linksys.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Device Tree include file for Armada 385 based Linksys boards - * - * Copyright (C) 2015 Imre Kaloz - * - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include "armada-385.dtsi" - -/ { - model = "Linksys boards based on Armada 385"; - compatible = "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - pca9635@68 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,pca9635"; - reg = <0x68>; - }; - }; - - /* J10: VCC, NC, RX, NC, TX, GND */ - serial@12000 { - status = "okay"; - }; - - ethernet@70000 { - status = "okay"; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - ethernet@34000 { - status = "okay"; - phy-mode = "sgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - mdio { - status = "okay"; - }; - - sata@a8000 { - status = "okay"; - }; - - /* USB part of the eSATA/USB 2.0 port */ - usb@58000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - usb-phy = <&usb3_phy>; - }; - - flash@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x200000>; /* 2MB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x200000 0x40000>; /* 256KB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x240000 0x40000>; /* 256KB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MB */ - }; - - partition@1000000 { - label = "rootfs1"; - reg = <0x1000000 0x2200000>; /* 34MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MB */ - }; - - partition@3800000 { - label = "rootfs2"; - reg = <0x3800000 0x2200000>; /* 34MB */ - }; - - /* - * 38MB, last MB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x280000 0x680000>; /* 6.5MB */ - }; - }; - }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Marvell 88W8864, 5GHz-only */ - status = "okay"; - }; - - pcie@2,0 { - /* Marvell 88W8864, 2GHz-only */ - status = "okay"; - }; - }; - }; - - usb3_phy: usb3_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_xhci0_vbus>; - }; - - reg_xhci0_vbus: xhci0-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-name = "xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&keys_pin>; - pinctrl-names = "default"; - - button@1 { - label = "WPS"; - linux,code = ; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - button@2 { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&power_led_pin &sata_led_pin>; - pinctrl-names = "default"; - - power { - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - sata { - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - dsa@0 { - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð2>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; -}; - -&pinctrl { - keys_pin: keys-pin { - marvell,pins = "mpp24", "mpp29"; - marvell,function = "gpio"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp55"; - marvell,function = "gpio"; - }; - - sata_led_pin: sata-led-pin { - marvell,pins = "mpp54"; - marvell,function = "gpio"; - }; - - xhci0_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp50"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-385.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-385.dtsi deleted file mode 100644 index 8e67d2c08..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-385.dtsi +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 385 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armada-38x.dtsi" - -/ { - model = "Marvell Armada 385 family SoC"; - compatible = "marvell,armada385", "marvell,armada380"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-380-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6820-pinctrl"; - }; - }; - - pcie-controller { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; - - /* - * This port can be either x4 or x1. When - * configured in x4 by the bootloader, then - * pcie@4,0 is not available. - */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - /* - * x1 port only available when pcie@1,0 is - * configured as a x1 port - */ - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-388-clearfog.dts b/software/linux/kernel/arch/arm/boot/dts/armada-388-clearfog.dts deleted file mode 100644 index 71ce201c9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-388-clearfog.dts +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828) - * - * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-388.dtsi" -#include "armada-38x-solidrun-microsom.dtsi" - -/ { - model = "SolidRun Clearfog A1"; - compatible = "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - aliases { - /* So that mvebu u-boot can update the MAC addresses */ - ethernet1 = ð0; - ethernet2 = ð1; - ethernet3 = ð2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - soc { - internal-regs { - ethernet@30000 { - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <1>; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - ethernet@34000 { - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - bm,pool-short = <1>; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - i2c@11000 { - /* Is there anything on this? */ - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* - * PCA9655 GPIO expander, up to 1MHz clock. - * 0-CON3 CLKREQ# - * 1-CON3 PERST# - * 2-CON2 PERST# - * 3-CON3 W_DISABLE - * 4-CON2 CLKREQ# - * 5-USB3 overcurrent - * 6-USB3 power - * 7-CON2 W_DISABLE - * 8-JP4 P1 - * 9-JP4 P4 - * 10-JP4 P5 - * 11-m.2 DEVSLP - * 12-SFP_LOS - * 13-SFP_TX_FAULT - * 14-SFP_TX_DISABLE - * 15-SFP_MOD_DEF0 - */ - expander0: gpio-expander@20 { - /* - * This is how it should be: - * compatible = "onnn,pca9655", - * "nxp,pca9555"; - * but you can't do this because of - * the way I2C works. - */ - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - - pcie1_0_clkreq { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie1.0-clkreq"; - }; - pcie1_0_w_disable { - gpio-hog; - gpios = <3 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie1.0-w-disable"; - }; - pcie2_0_clkreq { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - input; - line-name = "pcie2.0-clkreq"; - }; - pcie2_0_w_disable { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-low; - line-name = "pcie2.0-w-disable"; - }; - usb3_ilimit { - gpio-hog; - gpios = <5 GPIO_ACTIVE_LOW>; - input; - line-name = "usb3-current-limit"; - }; - usb3_power { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb3-power"; - }; - m2_devslp { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "m.2 devslp"; - }; - sfp_los { - /* SFP loss of signal */ - gpio-hog; - gpios = <12 GPIO_ACTIVE_HIGH>; - input; - line-name = "sfp-los"; - }; - sfp_tx_fault { - /* SFP laser fault */ - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - input; - line-name = "sfp-tx-fault"; - }; - sfp_tx_disable { - /* SFP transmit disable */ - gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "sfp-tx-disable"; - }; - sfp_mod_def0 { - /* SFP module present */ - gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; - input; - line-name = "sfp-mod-def0"; - }; - }; - - /* The MCP3021 is 100kHz clock only */ - mikrobus_adc: mcp3021@4c { - compatible = "microchip,mcp3021"; - reg = <0x4c>; - }; - - /* Also something at 0x64 */ - }; - - i2c@11100 { - /* - * Routed to SFP, mikrobus, and PCIe. - * SFP limits this to 100kHz, and requires - * an AT24C01A/02/04 with address pins tied - * low, which takes addresses 0x50 and 0x51. - * Mikrobus doesn't specify beyond an I2C - * bus being present. - * PCIe uses ARP to assign addresses, or - * 0x63-0x64. - */ - clock-frequency = <100000>; - pinctrl-0 = <&clearfog_i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - pinctrl@18000 { - clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { - marvell,pins = "mpp46"; - marvell,function = "ref"; - }; - clearfog_dsa0_pins: clearfog-dsa0-pins { - marvell,pins = "mpp23", "mpp41"; - marvell,function = "gpio"; - }; - clearfog_i2c1_pins: i2c1-pins { - /* SFP, PCIe, mSATA, mikrobus */ - marvell,pins = "mpp26", "mpp27"; - marvell,function = "i2c1"; - }; - clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - clearfog_sdhci_pins: clearfog-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; - clearfog_spi1_cs_pins: spi1-cs-pins { - marvell,pins = "mpp55"; - marvell,function = "spi1"; - }; - mikro_pins: mikro-pins { - /* int: mpp22 rst: mpp29 */ - marvell,pins = "mpp22", "mpp29"; - marvell,function = "gpio"; - }; - mikro_spi_pins: mikro-spi-pins { - marvell,pins = "mpp43"; - marvell,function = "spi1"; - }; - mikro_uart_pins: mikro-uart-pins { - marvell,pins = "mpp24", "mpp25"; - marvell,function = "ua1"; - }; - rear_button_pins: rear-button-pins { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - }; - - sata@a8000 { - /* pinctrl? */ - status = "okay"; - }; - - sata@e0000 { - /* pinctrl? */ - status = "okay"; - }; - - sdhci@d8000 { - bus-width = <4>; - cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - no-1-8-v; - pinctrl-0 = <&clearfog_sdhci_pins - &clearfog_sdhci_cd_pins>; - pinctrl-names = "default"; - status = "okay"; - vmmc = <®_3p3v>; - wp-inverted; - }; - - serial@12100 { - /* mikrobus uart */ - pinctrl-0 = <&mikro_uart_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - usb@58000 { - /* CON3, nearest power. */ - status = "okay"; - }; - - usb3@f0000 { - /* CON2, nearest CPU, USB2 only. */ - status = "okay"; - }; - - usb3@f8000 { - /* CON7 */ - status = "okay"; - }; - }; - - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * the mini-PCIe connectors on the board. - */ - pcie@2,0 { - /* Port 1, Lane 0. CON3, nearest power. */ - reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - pcie@3,0 { - /* Port 2, Lane 0. CON2, nearest CPU. */ - reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - }; - - dsa@0 { - compatible = "marvell,dsa"; - dsa,ethernet = <ð1>; - dsa,mii-bus = <&mdio>; - pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; - pinctrl-names = "default"; - #address-cells = <2>; - #size-cells = <0>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4 0>; - - port@0 { - reg = <0>; - label = "lan5"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - - port@6 { - /* 88E1512 external phy */ - reg = <6>; - label = "lan6"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&rear_button_pins>; - pinctrl-names = "default"; - - button_0 { - /* The rear SW3 button */ - label = "Rear Button"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; -}; - -&spi1 { - /* - * We don't seem to have the W25Q32 on the - * A1 Rev 2.0 boards, so disable SPI. - * CS0: W25Q32 (doesn't appear to be present) - * CS1: - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins - &clearfog_spi1_cs_pins - &mikro_spi_pins>; - pinctrl-names = "default"; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-388-db.dts b/software/linux/kernel/arch/arm/boot/dts/armada-388-db.dts deleted file mode 100644 index de26c7622..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-388-db.dts +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Device Tree file for Marvell Armada 388 evaluation board - * (DB-88F6820) - * - * Copyright (C) 2014 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-388.dtsi" - -/ { - model = "Marvell Armada 385 Development Board"; - compatible = "marvell,a385-db", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@11100 { - status = "okay"; - clock-frequency = <100000>; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - usb@58000 { - status = "ok"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - }; - - mdio@72004 { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - sata@a8000 { - status = "okay"; - }; - - sata@e0000 { - status = "okay"; - }; - - bm@c8000 { - status = "okay"; - }; - - flash@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - - sdhci@d8000 { - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - no-1-8-v; - }; - - usb3@f0000 { - status = "okay"; - }; - - usb3@f8000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-388-gp.dts b/software/linux/kernel/arch/arm/boot/dts/armada-388-gp.dts deleted file mode 100644 index 563901e0e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-388-gp.dts +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Device Tree file for Marvell Armada 385 development board - * (RD-88F6820-GP) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-388.dtsi" -#include - -/ { - model = "Marvell Armada 388 DB-88F6820-GP"; - compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - - expander0: pca9555@20 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - pinctrl-0 = <&pca0_pins>; - interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x20>; - }; - - expander1: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x21>; - }; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - /* - * Exported on the micro USB connector CON16 - * through an FTDI - */ - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - /* GE1 CON15 */ - ethernet@30000 { - pinctrl-names = "default"; - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; - }; - - /* CON4 */ - usb@58000 { - vcc-supply = <®_usb2_0_vbus>; - status = "okay"; - }; - - /* GE0 CON1 */ - ethernet@70000 { - pinctrl-names = "default"; - /* - * The Reference Clock 0 is used to provide a - * clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - }; - - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - sata@a8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata0_pins>, <&sata1_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata0>; - }; - - sata1: sata-port@1 { - reg = <1>; - target-supply = <®_5v_sata1>; - }; - }; - - bm@c8000 { - status = "okay"; - }; - - sata@e0000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata2_pins>, <&sata3_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata2: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata2>; - }; - - sata3: sata-port@1 { - reg = <1>; - target-supply = <®_5v_sata3>; - }; - }; - - sdhci@d8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - no-1-8-v; - /* - * A388-GP board v1.5 and higher replace - * hitherto card detection method based on GPIO - * with the one using DAT3 pin. As they are - * incompatible, software-based polling is - * enabled with 'broken-cd' property. For boards - * older than v1.5 it can be replaced with: - * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;', - * whereas for the newer ones following can be - * used instead: - * 'dat3-cd;' - * 'cd-inverted;' - */ - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - }; - - /* CON5 */ - usb3@f0000 { - usb-phy = <&usb2_1_phy>; - status = "okay"; - }; - - /* CON7 */ - usb3@f8000 { - usb-phy = <&usb3_phy>; - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - pcie-controller { - status = "okay"; - /* - * One PCIe units is accessible through - * standard PCIe slot on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * The two other PCIe units are accessible - * through mini PCIe slot on the board. - */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 3000 1>; - }; - }; - - usb2_1_phy: usb2_1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb2_1_vbus>; - }; - - usb3_phy: usb3_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_vbus>; - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; - }; - - reg_usb2_0_vbus: v5-vbus0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-vbus0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; - }; - - reg_usb2_1_vbus: v5-vbus1 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; - }; - - reg_sata0: pwr-sata0 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata0: v5-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata0>; - }; - - reg_12v_sata0: v12-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata0>; - }; - - reg_sata1: pwr-sata1 { - regulator-name = "pwr_en_sata1"; - compatible = "regulator-fixed"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata1: v5-sata1 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata1>; - }; - - reg_12v_sata1: v12-sata1 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata1"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata1>; - }; - - reg_sata2: pwr-sata2 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata2"; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata2: v5-sata2 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata2>; - }; - - reg_12v_sata2: v12-sata2 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata2"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata2>; - }; - - reg_sata3: pwr-sata3 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata3"; - enable-active-high; - regulator-boot-on; - gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata3: v5-sata3 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata3>; - }; - - reg_12v_sata3: v12-sata3 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata3"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata3>; - }; -}; - -&pinctrl { - pca0_pins: pca0_pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-388-rd.dts b/software/linux/kernel/arch/arm/boot/dts/armada-388-rd.dts deleted file mode 100644 index dd3462ddb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-388-rd.dts +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Device Tree file for Marvell Armada 388 Reference Design board - * (RD-88F6820-AP) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-388.dtsi" - -/ { - model = "Marvell Armada 385 Reference Design"; - compatible = "marvell,a385-rd", "marvell,armada388", - "marvell,armada385","marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - }; - - sdhci@d8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - broken-cd; - no-1-8-v; - wp-inverted; - bus-width = <8>; - status = "okay"; - }; - - serial@12000 { - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - - mdio@72004 { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - usb3@f0000 { - status = "okay"; - }; - }; - - pcie-controller { - status = "okay"; - /* - * One PCIe units is accessible through - * standard PCIe slot on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-388.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-388.dtsi deleted file mode 100644 index 564fa5937..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-388.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 388 SoC. - * - * Copyright (C) 2015 Marvell - * - * Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * - * The main difference with the Armada 385 is that the 388 can handle two more - * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl - * property and the name of the SoC, and add the second SATA host which control - * the 2 other ports. - */ - -#include "armada-385.dtsi" - -/ { - model = "Marvell Armada 388 family SoC"; - compatible = "marvell,armada388", "marvell,armada385", - "marvell,armada380"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6828-pinctrl"; - }; - - sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi deleted file mode 100644 index 8c9842237..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Device Tree file for SolidRun Armada 38x Microsom - * - * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; /* 256 MB */ - }; - - soc { - ranges = ; - - internal-regs { - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy_dedicated>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; - status = "okay"; - }; - - mdio@72004 { - /* - * Add the phy clock here, so the phy can be - * accessed to read its IDs prior to binding - * with the driver. - */ - pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; - pinctrl-names = "default"; - - phy_dedicated: ethernet-phy@0 { - /* - * Annoyingly, the marvell phy driver - * configures the LED register, rather - * than preserving reset-loaded setting. - * We undo that rubbish here. - */ - marvell,reg-init = <3 16 0 0x101e>; - reg = <0>; - }; - }; - - pinctrl@18000 { - microsom_phy_clk_pins: microsom-phy-clk-pins { - marvell,pins = "mpp45"; - marvell,function = "ref"; - }; - }; - - rtc@a3800 { - /* - * If the rtc doesn't work, run "date reset" - * twice in u-boot. - */ - status = "okay"; - }; - - serial@12000 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - bm@c8000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-38x.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-38x.dtsi deleted file mode 100644 index c60cfe9fd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-38x.dtsi +++ /dev/null @@ -1,678 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 38x family of SoCs. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - model = "Marvell Armada 38x family SoC"; - compatible = "marvell,armada380"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - serial0 = &uart0; - serial1 = &uart1; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada380-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - devbus-bootcs { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs0 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs1 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs2 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs3 { - compatible = "marvell,mvebu-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x58>; - }; - - timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl: pinctrl@18000 { - reg = <0x18000 0x20>; - - ge0_rgmii_pins: ge-rgmii-pins-0 { - marvell,pins = "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge-rgmii-pins-1 { - marvell,pins = "mpp21", "mpp27", "mpp28", - "mpp29", "mpp30", "mpp31", - "mpp32", "mpp37", "mpp38", - "mpp39", "mpp40", "mpp41"; - marvell,function = "ge1"; - }; - - i2c0_pins: i2c-pins-0 { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - mdio_pins: mdio-pins { - marvell,pins = "mpp4", "mpp5"; - marvell,function = "ge"; - }; - - ref_clk0_pins: ref-clk-pins-0 { - marvell,pins = "mpp45"; - marvell,function = "ref"; - }; - - ref_clk1_pins: ref-clk-pins-1 { - marvell,pins = "mpp46"; - marvell,function = "ref"; - }; - - spi0_pins: spi-pins-0 { - marvell,pins = "mpp22", "mpp23", "mpp24", - "mpp25"; - marvell,function = "spi0"; - }; - - spi1_pins: spi-pins-1 { - marvell,pins = "mpp56", "mpp57", "mpp58", - "mpp59"; - marvell,function = "spi1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp22", "mpp34", "mpp23", - "mpp33", "mpp38", "mpp28", - "mpp40", "mpp42", "mpp35", - "mpp36", "mpp25", "mpp30", - "mpp32"; - marvell,function = "dev"; - }; - - uart0_pins: uart-pins-0 { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "ua0"; - }; - - uart1_pins: uart-pins-1 { - marvell,pins = "mpp19", "mpp20"; - marvell,function = "ua1"; - }; - - sdhci_pins: sdhci-pins { - marvell,pins = "mpp48", "mpp49", "mpp50", - "mpp52", "mpp53", "mpp54", - "mpp55", "mpp57", "mpp58", - "mpp59"; - marvell,function = "sd0"; - }; - - sata0_pins: sata-pins-0 { - marvell,pins = "mpp20"; - marvell,function = "sata0"; - }; - - sata1_pins: sata-pins-1 { - marvell,pins = "mpp19"; - marvell,function = "sata1"; - }; - - sata2_pins: sata-pins-2 { - marvell,pins = "mpp47"; - marvell,function = "sata2"; - }; - - sata3_pins: sata-pins-3 { - marvell,pins = "mpp44"; - marvell,function = "sata3"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <28>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - system-controller@18200 { - compatible = "marvell,armada-380-system-controller", - "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-380-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18600 { - compatible = "marvell,armada-380-core-clock"; - reg = <0x18600 0x04>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer@20300 { - compatible = "marvell,armada-380-timer", - "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-380-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - mpcore-soc-ctrl@20d20 { - compatible = "marvell,armada-380-mpcore-soc-ctrl"; - reg = <0x20d20 0x6c>; - }; - - coherency-fabric@21010 { - compatible = "marvell,armada-380-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - pmsu@22000 { - compatible = "marvell,armada-380-pmsu"; - reg = <0x22000 0x1000>; - }; - - /* - * As a special exception to the "order by - * register address" rule, the eth0 node is - * placed here to ensure that it gets - * registered as the first interface, since - * the network subsystem doesn't allow naming - * interfaces using DT aliases. Without this, - * the ordering of interfaces is different - * from the one used in U-Boot and the - * labeling of interfaces on the boards, which - * is very confusing for users. - */ - eth0: ethernet@70000 { - compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x4000>; - interrupts-extended = <&mpic 8>; - clocks = <&gateclk 4>; - tx-csum-limit = <9800>; - status = "disabled"; - }; - - eth1: ethernet@30000 { - compatible = "marvell,armada-370-neta"; - reg = <0x30000 0x4000>; - interrupts-extended = <&mpic 10>; - clocks = <&gateclk 3>; - status = "disabled"; - }; - - eth2: ethernet@34000 { - compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x4000>; - interrupts-extended = <&mpic 12>; - clocks = <&gateclk 2>; - status = "disabled"; - }; - - usb@58000 { - compatible = "marvell,orion-ehci"; - reg = <0x58000 0x500>; - interrupts = ; - clocks = <&gateclk 18>; - status = "disabled"; - }; - - xor@60800 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor@60900 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - mdio: mdio@72004 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x72004 0x4>; - clocks = <&gateclk 4>; - }; - - crypto@90000 { - compatible = "marvell,armada-38x-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = , - ; - clocks = <&gateclk 23>, <&gateclk 21>, - <&gateclk 14>, <&gateclk 16>; - clock-names = "cesa0", "cesa1", - "cesaz0", "cesaz1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - rtc@a3800 { - compatible = "marvell,armada-380-rtc"; - reg = <0xa3800 0x20>, <0x184a0 0x0c>; - reg-names = "rtc", "rtc-soc"; - interrupts = ; - }; - - sata@a8000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xa8000 0x2000>; - interrupts = ; - clocks = <&gateclk 15>; - status = "disabled"; - }; - - bm: bm@c8000 { - compatible = "marvell,armada-380-neta-bm"; - reg = <0xc8000 0xac>; - clocks = <&gateclk 13>; - internal-mem = <&bm_bppi>; - status = "disabled"; - }; - - sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - - coredivclk: clock@e4250 { - compatible = "marvell,armada-380-corediv-clock"; - reg = <0xe4250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - thermal@e8078 { - compatible = "marvell,armada380-thermal"; - reg = <0xe4078 0x4>, <0xe4074 0x4>; - status = "okay"; - }; - - flash@d0000 { - compatible = "marvell,armada370-nand"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = ; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - sdhci@d8000 { - compatible = "marvell,armada-380-sdhci"; - reg-names = "sdhci", "mbus", "conf-sdio3"; - reg = <0xd8000 0x1000>, - <0xdc000 0x100>, - <0x18454 0x4>; - interrupts = ; - clocks = <&gateclk 17>; - mrvl,clk-delay-cycles = <0x1F>; - status = "disabled"; - }; - - usb3@f0000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf0000 0x4000>,<0xf4000 0x4000>; - interrupts = ; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - usb3@f8000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf8000 0x4000>,<0xfc000 0x4000>; - interrupts = ; - clocks = <&gateclk 10>; - status = "disabled"; - }; - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 21>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; - }; - - bm_bppi: bm-bppi { - compatible = "mmio-sram"; - reg = ; - ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gateclk 13>; - no-memory-wc; - status = "disabled"; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 2 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-390-db.dts b/software/linux/kernel/arch/arm/boot/dts/armada-390-db.dts deleted file mode 100644 index 34e279d97..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-390-db.dts +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Device Tree file for Marvell Armada 390 Development Board - * (DB-88F6920) - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-390.dtsi" - -/ { - model = "Marvell Armada 390 Development Board"; - compatible = "marvell,a390-db", "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - /* CON104 */ - serial@12000 { - status = "okay"; - }; - - /* CON97 */ - usb@58000 { - status = "okay"; - }; - - flash@d0000 { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; - - /* CON98 */ - usb3@f8000 { - status = "okay"; - }; - }; - - pcie-controller { - status = "okay"; - - /* CON30 */ - pcie@1,0 { - status = "okay"; - }; - - /* CON44 */ - pcie@2,0 { - status = "okay"; - }; - - /* CON61 */ - pcie@3,0 { - status = "okay"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - spi-flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", - "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0xc00000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-390.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-390.dtsi deleted file mode 100644 index 6cd18d8aa..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-390.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 390 SoC. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armada-39x.dtsi" - -/ { - compatible = "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6920-pinctrl"; - reg = <0x18000 0x20>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-395-gp.dts b/software/linux/kernel/arch/arm/boot/dts/armada-395-gp.dts deleted file mode 100644 index 2cdbba804..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-395-gp.dts +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Device Tree file for Marvell Armada 395 GP board - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-395.dtsi" - -/ { - model = "Marvell Armada 395 GP Board"; - compatible = "marvell,a395-gp", "marvell,armada395", - "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - /* - * Exported on the micro USB connector CON17 - * through an FTDI - */ - status = "okay"; - }; - - /* CON1 */ - usb@58000 { - status = "okay"; - }; - - /* CON2 */ - sata@a8000 { - status = "okay"; - }; - - flash@d0000 { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x00000000 0x00600000>; - read-only; - }; - - partition@800000 { - label = "uImage"; - reg = <0x00600000 0x00400000>; - read-only; - }; - - partition@1000000 { - label = "Root"; - reg = <0x00a00000 0x3f600000>; - }; - }; - }; - - /* CON18 */ - sdhci@d8000 { - clock-frequency = <200000000>; - broken-cd; - wp-inverted; - bus-width = <8>; - status = "okay"; - no-1-8-v; - }; - - /* CON4 */ - usb3@f0000 { - status = "okay"; - }; - }; - - pcie-controller { - status = "okay"; - - /* - * The two PCIe units are accessible through - * mini PCIe slot on the board. - */ - - /* CON7 */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - - /* CON8 */ - pcie@4,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-395.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-395.dtsi deleted file mode 100644 index ab5dc49f2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-395.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 395 SoC. - * - * Copyright (C) 2016 Marvell - * - * Grzegorz Jaszczyk - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armada-39x.dtsi" - -/ { - compatible = "marvell,armada395", "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6925-pinctrl"; - reg = <0x18000 0x20>; - }; - - sata@a8000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xa8000 0x2000>; - interrupts = ; - clocks = <&gateclk 15>; - status = "disabled"; - }; - - usb3@f0000 { - compatible = "marvell,armada-380-xhci"; - reg = <0xf0000 0x4000>,<0xf4000 0x4000>; - interrupts = ; - clocks = <&gateclk 9>; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-398-db.dts b/software/linux/kernel/arch/arm/boot/dts/armada-398-db.dts deleted file mode 100644 index 268c8349c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-398-db.dts +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 398 Development Board - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-398.dtsi" - -/ { - model = "Marvell Armada 398 Development Board"; - compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - clock-frequency = <100000>; - }; - - serial@12000 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - serial@12100 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - usb@58000 { - status = "okay"; - }; - - flash@d0000 { - status = "okay"; - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - - usb3@f8000 { - status = "okay"; - }; - }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - - pcie@2,0 { - status = "okay"; - }; - - pcie@3,0 { - status = "okay"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0x1000000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-398.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-398.dtsi deleted file mode 100644 index 234a99891..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-398.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 398 SoC. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "armada-395.dtsi" - -/ { - compatible = "marvell,armada398", "marvell,armada390"; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6928-pinctrl"; - reg = <0x18000 0x20>; - }; - - sata@e0000 { - compatible = "marvell,armada-380-ahci"; - reg = <0xe0000 0x2000>; - interrupts = ; - clocks = <&gateclk 30>; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-39x.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-39x.dtsi deleted file mode 100644 index aeecfa7e5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-39x.dtsi +++ /dev/null @@ -1,590 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 39x family of SoCs. - * - * Copyright (C) 2015 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - model = "Marvell Armada 39x family SoC"; - compatible = "marvell,armada390"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-390-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&mpic 3>; - }; - - soc { - compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", - "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - interrupt-parent = <&gic>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - L2: cache-controller@8000 { - compatible = "arm,pl310-cache"; - reg = <0x8000 0x1000>; - cache-unified; - cache-level = <2>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - arm,double-linefill = <0>; - prefetch-data = <1>; - }; - - scu@c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc000 0x100>; - }; - - timer@c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xc600 0x20>; - interrupts = ; - clocks = <&coreclk 2>; - }; - - gic: interrupt-controller@d000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - interrupt-controller; - reg = <0xd000 0x1000>, - <0xc100 0x100>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c2: i2c@11200 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11200 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - i2c3: i2c@11300 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11300 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - timeout-ms = <1000>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "snps,dw-apb-uart"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "snps,dw-apb-uart"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart2: serial@12200 { - compatible = "snps,dw-apb-uart"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "snps,dw-apb-uart"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - pinctrl@18000 { - i2c0_pins: i2c0-pins { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - uart0_pins: uart0-pins { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "ua0"; - }; - - uart1_pins: uart1-pins { - marvell,pins = "mpp19", "mpp20"; - marvell,function = "ua1"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; - marvell,function = "spi1"; - }; - - nand_pins: nand-pins { - marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", - "mpp38", "mpp28", "mpp40", "mpp42", - "mpp35", "mpp36", "mpp25", "mpp30", - "mpp32"; - marvell,function = "dev"; - }; - }; - - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <28>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - ; - }; - - system-controller@18200 { - compatible = "marvell,armada-390-system-controller", - "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-390-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18600 { - compatible = "marvell,armada-390-core-clock"; - reg = <0x18600 0x04>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; - }; - - mpic: interrupt-controller@20a00 { - compatible = "marvell,mpic"; - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - interrupts = ; - }; - - timer@20300 { - compatible = "marvell,armada-380-timer", - "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <&mpic 5>, - <&mpic 6>; - clocks = <&coreclk 2>, <&coreclk 5>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-380-wdt"; - reg = <0x20300 0x34>, <0x20704 0x4>, - <0x18260 0x4>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x10>; - }; - - mpcore-soc-ctrl@20d20 { - compatible = "marvell,armada-380-mpcore-soc-ctrl"; - reg = <0x20d20 0x6c>; - }; - - coherency-fabric@21010 { - compatible = "marvell,armada-380-coherency-fabric"; - reg = <0x21010 0x1c>; - }; - - pmsu@22000 { - compatible = "marvell,armada-390-pmsu", - "marvell,armada-380-pmsu"; - reg = <0x22000 0x1000>; - }; - - xor@60800 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor00 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - xor@60900 { - compatible = "marvell,armada-380-xor", "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor10 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = ; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - rtc@a3800 { - compatible = "marvell,armada-380-rtc"; - reg = <0xa3800 0x20>, <0x184a0 0x0c>; - reg-names = "rtc", "rtc-soc"; - interrupts = ; - }; - - flash@d0000 { - compatible = "marvell,armada370-nand"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = ; - clocks = <&coredivclk 0>; - status = "disabled"; - }; - - sdhci@d8000 { - compatible = "marvell,armada-380-sdhci"; - reg-names = "sdhci", "mbus", "conf-sdio3"; - reg = <0xd8000 0x1000>, - <0xdc000 0x100>, - <0x18454 0x4>; - interrupts = ; - clocks = <&gateclk 17>; - mrvl,clk-delay-cycles = <0x1F>; - status = "disabled"; - }; - - coredivclk: clock@e4250 { - compatible = "marvell,armada-390-corediv-clock", - "marvell,armada-380-corediv-clock"; - reg = <0xe4250 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - - thermal@e8078 { - compatible = "marvell,armada380-thermal"; - reg = <0xe4078 0x4>, <0xe4074 0x4>; - status = "okay"; - }; - }; - - pcie-controller { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; - - /* - * This port can be either x4 or x1. When - * configured in x4 by the bootloader, then - * pcie@4,0 is not available. - */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - /* - * x1 port only available when pcie@1,0 is - * configured as a x1 port - */ - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = ; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - }; - - clocks { - /* 2 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-axpwifiap.dts deleted file mode 100644 index ce152719b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Device Tree file for Marvell RD-AXPWiFiAP. - * - * Note: this board is shipped with a new generation boot loader that - * remaps internal registers at 0xf1000000. Therefore, if earlyprintk - * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the - * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used. - * - * Copyright (C) 2013 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Marvell RD-AXPWiFiAP"; - compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* First mini-PCIe port */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Renesas uPD720202 USB 3.0 controller */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - }; - - internal-regs { - /* UART0 */ - serial@12000 { - status = "okay"; - }; - - /* UART1 */ - serial@12100 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&keys_pin>; - pinctrl-names = "default"; - - button@1 { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pinctrl { - pinctrl-0 = <&phy_int_pin>; - pinctrl-names = "default"; - - keys_pin: keys-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - phy_int_pin: phy-int-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-db.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-db.dts deleted file mode 100644 index 075120bc3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-db.dts +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Device Tree file for Marvell Armada XP evaluation board - * (DB-78460-BP) - * - * Copyright (C) 2012-2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Evaluation Board"; - compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 16 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <2>; - }; - }; - - pcie-controller { - status = "okay"; - - /* - * All 6 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 0, Lane 2 */ - status = "okay"; - }; - pcie@4,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <25>; - }; - - phy3: ethernet-phy@3 { - reg = <27>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - - bm@c0000 { - status = "okay"; - }; - - mvsdio@d4000 { - pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - usb@52000 { - status = "okay"; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x800000>; - }; - partition@800000 { - label = "Linux"; - reg = <0x800000 0x800000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - - }; - }; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-gp.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-gp.dts deleted file mode 100644 index 190e4eccb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-gp.dts +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Device Tree file for Marvell Armada XP development board - * (DB-MV784MP-GP) - * - * Copyright (C) 2013-2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the default - * 0xd0000000). The 0xf1000000 is the default used by the recent, - * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier - * boards were delivered with an older version of the bootloader that - * left internal registers mapped at 0xd0000000. If you are in this - * situation, you should either update your bootloader (preferred - * solution) or the below Device Tree should be adjusted. - */ - -/dts-v1/; -#include -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Development Board DB-MV784MP-GP"; - compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - /* - * 8 GB of plug-in RAM modules by default.The amount - * of memory available can be changed by the - * bootloader according the size of the module - * actually plugged. However, memory between - * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is - * the address range used for I/O (internal registers, - * MBus windows). - */ - reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, - <0x00000001 0x00000000 0x00000001 0x00000000>; - }; - - cpus { - pm_pic { - ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, - <&gpio0 17 GPIO_ACTIVE_LOW>, - <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 16 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <2>; - }; - }; - - pcie-controller { - status = "okay"; - - /* - * The 3 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - pinctrl { - pinctrl-0 = <&pic_pins>; - pinctrl-names = "default"; - pic_pins: pic-pins-0 { - marvell,pins = "mpp16", "mpp17", - "mpp18"; - marvell,function = "gpio"; - }; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <16>; - }; - - phy1: ethernet-phy@1 { - reg = <17>; - }; - - phy2: ethernet-phy@2 { - reg = <18>; - }; - - phy3: ethernet-phy@3 { - reg = <19>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "qsgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - - /* Front-side USB slot */ - usb@50000 { - status = "okay"; - }; - - /* Back-side USB slot */ - usb@51000 { - status = "okay"; - }; - - bm@c0000 { - status = "okay"; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts deleted file mode 100644 index 8af463f26..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Device Tree file for Lenovo Iomega ix4-300d - * - * Copyright (C) 2014, Benoit Masson - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Lenovo Iomega ix4-300d"; - compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x20000000>; /* 512MB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* Quad port sata: Marvell 88SX7042 */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* USB 3.0 xHCI controller: NEC D720200F1 */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - serial@12000 { - status = "okay"; - }; - - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - usb@51000 { - status = "okay"; - }; - - i2c@11000 { - clock-frequency = <400000>; - status = "okay"; - - adt7473@2e { - compatible = "adi,adt7473"; - reg = <0x2e>; - }; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x000e0000>; - read-only; - }; - - partition@e0000 { - label = "u-boot-env"; - reg = <0x000e0000 0x00020000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env2"; - reg = <0x00100000 0x00020000>; - read-only; - }; - - partition@120000 { - label = "zImage"; - reg = <0x00120000 0x00400000>; - }; - - partition@520000 { - label = "initrd"; - reg = <0x00520000 0x00400000>; - }; - - partition@e00000 { - label = "boot"; - reg = <0x00e00000 0x3f200000>; - }; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin &reset_button_pin - &select_button_pin &scroll_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - select-button { - label = "Select Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - scroll-button { - label = "Scroll Button"; - linux,code = ; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - }; - - spi3 { - compatible = "spi-gpio"; - status = "okay"; - gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; - gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ - cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio_spi: gpio_spi@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&hdd_led_pin>; - pinctrl-names = "default"; - - hdd-led { - label = "ix4-300d:hdd:blue"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - power-led { - label = "ix4-300d:power:white"; - gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>; - /* init blinking while booting */ - linux,default-trigger = "timer"; - default-state = "on"; - }; - - sysfail-led { - label = "ix4-300d:sysfail:red"; - gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - sys-led { - label = "ix4-300d:sys:blue"; - gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - hddfail-led { - label = "ix4-300d:hddfail:red"; - gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - }; - - /* - * Warning: you need both eth1 & 0 PHY initialized (i.e having - * them up does the tweak) for poweroff to shutdown otherwise it - * reboots - */ - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff_pin>; - pinctrl-names = "default"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - poweroff_pin: poweroff-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - select_button_pin: select-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - scroll_button_pin: scroll-button-pin { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - hdd_led_pin: hdd-led-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-linksys-mamba.dts deleted file mode 100644 index 076f27f22..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Device Tree file for the Linksys WRT1900AC (Mamba). - * - * Note: this board is shipped with a new generation boot loader that - * remaps internal registers at 0xf1000000. Therefore, if earlyprintk - * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be - * used. - * - * Copyright (C) 2014 Imre Kaloz - * - * Based on armada-xp-axpwifiap.dts: - * - * Copyright (C) 2013 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Linksys WRT1900AC"; - compatible = "linksys,mamba", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* Etron EJ168 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* First mini-PCIe port */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Second mini-PCIe port */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - }; - - internal-regs { - - rtc@10300 { - /* No crystal connected to the internal RTC */ - status = "disabled"; - }; - - /* J10: VCC, NC, RX, NC, TX, GND */ - serial@12000 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <1>; - status = "okay"; - }; - - ethernet@70000 { - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - /* USB part of the eSATA/USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <100000>; - - tmp421@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - - tlc59116@68 { - #address-cells = <1>; - #size-cells = <0>; - #gpio-cells = <2>; - compatible = "ti,tlc59116"; - reg = <0x68>; - - wan_amber@0 { - label = "mamba:amber:wan"; - reg = <0x0>; - }; - - wan_white@1 { - label = "mamba:white:wan"; - reg = <0x1>; - }; - - wlan_2g@2 { - label = "mamba:white:wlan_2g"; - reg = <0x2>; - }; - - wlan_5g@3 { - label = "mamba:white:wlan_5g"; - reg = <0x3>; - }; - - esata@4 { - label = "mamba:white:esata"; - reg = <0x4>; - }; - - usb2@5 { - label = "mamba:white:usb2"; - reg = <0x5>; - }; - - usb3_1@6 { - label = "mamba:white:usb3_1"; - reg = <0x6>; - }; - - usb3_2@7 { - label = "mamba:white:usb3_2"; - reg = <0x7>; - }; - - wps_white@8 { - label = "mamba:white:wps"; - reg = <0x8>; - }; - - wps_amber@9 { - label = "mamba:amber:wps"; - reg = <0x9>; - }; - }; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; /* 1MB */ - read-only; - }; - - partition@100000 { - label = "u_env"; - reg = <0x100000 0x40000>; /* 256KB */ - }; - - partition@140000 { - label = "s_env"; - reg = <0x140000 0x40000>; /* 256KB */ - }; - - partition@900000 { - label = "devinfo"; - reg = <0x900000 0x100000>; /* 1MB */ - read-only; - }; - - /* kernel1 overlaps with rootfs1 by design */ - partition@a00000 { - label = "kernel1"; - reg = <0xa00000 0x2800000>; /* 40MB */ - }; - - partition@d00000 { - label = "rootfs1"; - reg = <0xd00000 0x2500000>; /* 37MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ - partition@3200000 { - label = "kernel2"; - reg = <0x3200000 0x2800000>; /* 40MB */ - }; - - partition@3500000 { - label = "rootfs2"; - reg = <0x3500000 0x2500000>; /* 37MB */ - }; - - /* - * 38MB, last MB is for the BBT, not writable - */ - partition@5a00000 { - label = "syscfg"; - reg = <0x5a00000 0x2600000>; - }; - - /* - * Unused area between "s_env" and "devinfo". - * Moved here because otherwise the renumbered - * partitions would break the bootloader - * supplied bootargs - */ - partition@180000 { - label = "unused_area"; - reg = <0x180000 0x780000>; /* 7.5MB */ - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&keys_pin>; - pinctrl-names = "default"; - - button@1 { - label = "WPS"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - - button@2 { - label = "Factory Reset Button"; - linux,code = ; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&power_led_pin>; - pinctrl-names = "default"; - - power { - label = "mamba:white:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - gpio_fan { - /* SUNON HA4010V4-0000-C99 */ - compatible = "gpio-fan"; - gpios = <&gpio0 24 0>; - - gpio-fan,speed-map = <0 0 - 4500 1>; - }; - - dsa@0 { - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; -}; - -&pinctrl { - - keys_pin: keys-pin { - marvell,pins = "mpp32", "mpp33"; - marvell,function = "gpio"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - gpio_fan_pin: gpio-fan-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <40000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-matrix.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-matrix.dts deleted file mode 100644 index 6522b04f4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-matrix.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Device Tree file for Marvell Armada XP Matrix board - * - * Copyright (C) 2013 Marvell - * - * Lior Amsalem - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Matrix Board"; - compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - /* - * This board has 4 GB of RAM, but the last 256 MB of - * RAM are not usable due to the overlap with the MBus - * Window address range - */ - reg = <0 0x00000000 0 0xf0000000>; - }; - - soc { - ranges = ; - - internal-regs { - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - serial@12200 { - status = "okay"; - }; - serial@12300 { - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy-mode = "sgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78230.dtsi deleted file mode 100644 index 6e6d0f04b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Contains definitions specific to the Armada XP MV78230 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78230 SoC"; - compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78230 has 2 PCIe units Gen2.0: One unit can be - * configured as x4 or quad x1 lanes. One unit is - * x1 only. - */ - pcie-controller { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <17>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78230-pinctrl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78260.dtsi deleted file mode 100644 index c5fdc99f0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Contains definitions specific to the Armada XP MV78260 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78260 SoC"; - compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78260 has 3 PCIe units Gen2.0: Two units can be - * configured as x4 or quad x1 lanes. One unit is - * x4 only. - */ - pcie-controller { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - status = "disabled"; - }; - - pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; - status = "disabled"; - }; - - pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - eth3: ethernet@34000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x34000 0x4000>; - interrupts = <14>; - clocks = <&gateclk 1>; - status = "disabled"; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78260-pinctrl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78460.dtsi deleted file mode 100644 index 0e24f1a38..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Contains definitions specific to the Armada XP MV78460 SoC that are not - * common to all Armada XP SoCs. - */ - -#include "armada-xp.dtsi" - -/ { - model = "Marvell Armada XP MV78460 SoC"; - compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-xp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; - clock-latency = <1000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <1>; - clocks = <&cpuclk 1>; - clock-latency = <1000000>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <2>; - clocks = <&cpuclk 2>; - clock-latency = <1000000>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "marvell,sheeva-v7"; - reg = <3>; - clocks = <&cpuclk 3>; - clock-latency = <1000000>; - }; - }; - - soc { - /* - * MV78460 has 4 PCIe units Gen2.0: Two units can be - * configured as x4 or quad x1 lanes. Two units are - * x4/x1. - */ - pcie-controller { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ - - 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ - 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - status = "disabled"; - }; - - pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; - status = "disabled"; - }; - - pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - }; - - pcie@10,0 { - device_type = "pci"; - assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; - reg = <0x5000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 - 0x81000000 0 0 0x81000000 0xa 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 103>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 27>; - status = "disabled"; - }; - }; - - internal-regs { - gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <82>, <83>, <84>, <85>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>, <90>; - }; - - gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; - reg = <0x18180 0x40>; - ngpios = <3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <91>; - }; - - eth3: ethernet@34000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x34000 0x4000>; - interrupts = <14>; - clocks = <&gateclk 1>; - status = "disabled"; - }; - }; - }; -}; - -&pinctrl { - compatible = "marvell,mv78460-pinctrl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts deleted file mode 100644 index d19f44c70..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Device Tree file for NETGEAR ReadyNAS 2120 - * - * Copyright (C) 2013, Arnaud EBALARD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "NETGEAR ReadyNAS 2120"; - compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2GB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* Connected to first Marvell 88SE9170 SATA controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to second Marvell 88SE9170 SATA controller */ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - - /* Connected to Fresco Logic FL1009 USB 3.0 controller */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - - /* RTC is provided by Intersil ISL12057 I2C RTC chip */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - clock-frequency = <400000>; - status = "okay"; - - /* Controller for rear fan #1 of 3 (Protechnic - * MGT4012XB-O20, 8000RPM) near eSATA port */ - g762_fan1: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Controller for rear (center) fan #2 of 3 */ - g762_fan2: g762@48 { - compatible = "gmt,g762"; - reg = <0x48>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Controller for rear fan #3 of 3 */ - g762_fan3: g762@49 { - compatible = "gmt,g762"; - reg = <0x49>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - - /* Temperature sensor */ - g751: g751@4c { - compatible = "gmt,g751"; - reg = <0x4c>; - }; - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; - }; - - serial@12000 { - status = "okay"; - }; - - /* Front USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1318 */ - reg = <1>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - /* Two rear eSATA ports */ - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - nand@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - - /* Use Hardware BCH ECC */ - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; /* 1.5MB */ - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; /* 128KB */ - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; /* 6MB */ - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x400000>; /* 4MB */ - }; - - /* Last MB is for the BBT, i.e. not writable */ - partition@c00000 { - label = "ubifs"; - reg = <0x0c00000 0x7400000>; /* 116MB */ - }; - }; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin - &sata3_led_pin &sata4_led_pin>; - pinctrl-names = "default"; - - red-sata1-led { - label = "rn2120:red:sata1"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata2-led { - label = "rn2120:red:sata2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata3-led { - label = "rn2120:red:sata3"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-sata4-led { - label = "rn2120:red:sata4"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red-err-led { - label = "rn2120:red:err"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin &reset_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - poweroff: poweroff { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - sata3_led_pin: sata3-led-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - sata4_led_pin: sata4-led-pin { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - sata1_power_pin: sata1-power-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - sata2_power_pin: sata2-power-pin { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - sata3_power_pin: sata3-power-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - sata4_power_pin: sata4-power-pin { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - sata3_pres_pin: sata3-pres-pin { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - sata4_pres_pin: sata4-pres-pin { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - err_led_pin: err-led-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts deleted file mode 100644 index ed3b889d1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Device Tree file for OpenBlocks AX3-4 board - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "armada-xp-mv78260.dtsi" - -/ { - model = "PlatHome OpenBlocks AX3-4 board"; - compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */ - }; - - soc { - ranges = ; - - devbus-bootcs { - status = "okay"; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <16>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 128 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x8000000>; - bank-width = <2>; - }; - }; - - pcie-controller { - status = "okay"; - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - rtc@10300 { - /* No crystal connected to the internal RTC */ - status = "disabled"; - }; - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - red_led { - label = "red_led"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - yellow_led { - label = "yellow_led"; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - green_led { - label = "green_led"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - }; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <1>; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <3>; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - }; - i2c@11100 { - status = "okay"; - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "s35390a"; - reg = <0x30>; - }; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - /* Front side USB 0 */ - usb@50000 { - status = "okay"; - }; - - /* Front side USB 1 */ - usb@51000 { - status = "okay"; - }; - - bm@c0000 { - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - }; -}; - -&pinctrl { - led_pins: led-pins-0 { - marvell,pins = "mpp49", "mpp51", "mpp53"; - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/software/linux/kernel/arch/arm/boot/dts/armada-xp-synology-ds414.dts deleted file mode 100644 index ae286736b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Device Tree file for Synology DS414 - * - * Copyright (C) 2014, Arnaud EBALARD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Note: this Device Tree assumes that the bootloader has remapped the - * internal registers to 0xf1000000 (instead of the old 0xd0000000). - * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot - * bootloaders provided by Marvell. It is used in recent versions of - * DSM software provided by Synology. Nonetheless, some earlier boards - * were delivered with an older version of u-boot that left internal - * registers mapped at 0xd0000000. If you have such a device you will - * not be able to directly boot a kernel based on this Device Tree. In - * that case, the preferred solution is to update your bootloader (e.g. - * by upgrading to latest version of DSM, or building a new one and - * installing it from u-boot prompt) or adjust the Devive Tree - * (s/0xf1000000/0xd0000000/ in 'ranges' below). - */ - -/dts-v1/; - -#include -#include -#include "armada-xp-mv78230.dtsi" - -/ { - model = "Synology DS414"; - compatible = "synology,ds414", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x40000000>; /* 1GB */ - }; - - soc { - ranges = ; - - pcie-controller { - status = "okay"; - - /* - * Connected to Marvell 88SX7042 SATA-II controller - * handling the four disks. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * Connected to EtronTech EJ168A XHCI controller - * providing the two rear USB 3.0 ports. - */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - - /* RTC is provided by Seiko S-35390A below */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - clock-frequency = <400000>; - status = "okay"; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - /* Connected to a header on device's PCB. This - * provides the main console for the device. - * - * Warning: the device may not boot with a 3.3V - * USB-serial converter connected when the power - * button is pressed. The converter needs to be - * connected a few seconds after pressing the - * power button. This is possibly due to UART0_TXD - * pin being sampled at reset (bit 0 of SAR). - */ - serial@12000 { - status = "okay"; - }; - - /* Connected to a Microchip PIC16F883 for power control */ - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - /* Front USB 2.0 port */ - usb@50000 { - status = "okay"; - }; - - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1512 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; - }; - - ethernet@70000 { - status = "okay"; - pinctrl-0 = <&ge0_rgmii_pins>; - pinctrl-names = "default"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - pinctrl-0 = <&ge1_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin - &sata3_pwr_pin &sata4_pwr_pin>; - pinctrl-names = "default"; - - sata1_regulator: sata1-regulator { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - sata2_regulator: sata2-regulator { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA2 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - sata3_regulator: sata3-regulator { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "SATA3 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <6000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - - sata4_regulator: sata4-regulator { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "SATA4 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <8000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - sata1_pwr_pin: sata1-pwr-pin { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - sata2_pwr_pin: sata2-pwr-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - sata3_pwr_pin: sata3-pwr-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - sata4_pwr_pin: sata4-pwr-pin { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - sata3_pres_pin: sata3-pres-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - sata4_pres_pin: sata4-pres-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - syno_id_bit0_pin: syno-id-bit0-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - syno_id_bit1_pin: syno-id-bit1-pin { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - syno_id_bit2_pin: syno-id-bit2-pin { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - fan1_alarm_pin: fan1-alarm-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - fan2_alarm_pin: fan2-alarm-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@00000000 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000d0000>; /* 832KB */ - }; - - partition@000c0000 { /* uImage */ - label = "zImage"; - reg = <0x000d0000 0x002d0000>; /* 2880KB */ - }; - - partition@003a0000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x003a0000 0x00430000>; /* 4250KB */ - }; - - partition@007d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@007e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@007f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armada-xp.dtsi b/software/linux/kernel/arch/arm/boot/dts/armada-xp.dtsi deleted file mode 100644 index 4a5f99e65..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armada-xp.dtsi +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada XP family SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * Ben Dooks - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Contains definitions specific to the Armada XP SoC that are not - * common to all Armada SoCs. - */ - -#include "armada-370-xp.dtsi" - -/ { - model = "Marvell Armada XP family SoC"; - compatible = "marvell,armadaxp", "marvell,armada-370-xp"; - - aliases { - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - compatible = "marvell,armadaxp-mbus", "simple-bus"; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - internal-regs { - sdramc@1400 { - compatible = "marvell,armada-xp-sdram-controller"; - reg = <0x1400 0x500>; - }; - - L2: l2-cache { - compatible = "marvell,aurora-system-cache"; - reg = <0x08000 0x1000>; - cache-id-part = <0x100>; - cache-level = <2>; - cache-unified; - wt-override; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - - uart2: serial@12200 { - compatible = "snps,dw-apb-uart"; - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = <43>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "snps,dw-apb-uart"; - pinctrl-0 = <&uart3_pins>; - pinctrl-names = "default"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = <44>; - reg-io-width = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x500>; - }; - - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-xp-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; - }; - - coreclk: mvebu-sar@18230 { - compatible = "marvell,armada-xp-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - - thermal@182b0 { - compatible = "marvell,armadaxp-thermal"; - reg = <0x182b0 0x4 - 0x184d0 0x4>; - status = "okay"; - }; - - cpuclk: clock-complex@18700 { - #clock-cells = <1>; - compatible = "marvell,armada-xp-cpu-clock"; - reg = <0x18700 0x24>, <0x1c054 0x10>; - clocks = <&coreclk 1>; - }; - - interrupt-controller@20a00 { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - }; - - timer@20300 { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-xp-wdt"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x20>; - }; - - cpu-config@21000 { - compatible = "marvell,armada-xp-cpu-config"; - reg = <0x21000 0x8>; - }; - - eth2: ethernet@30000 { - compatible = "marvell,armada-xp-neta"; - reg = <0x30000 0x4000>; - interrupts = <12>; - clocks = <&gateclk 2>; - status = "disabled"; - }; - - usb@50000 { - clocks = <&gateclk 18>; - }; - - usb@51000 { - clocks = <&gateclk 19>; - }; - - usb@52000 { - compatible = "marvell,orion-ehci"; - reg = <0x52000 0x500>; - interrupts = <47>; - clocks = <&gateclk 20>; - status = "disabled"; - }; - - xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gateclk 22>; - status = "okay"; - - xor10 { - interrupts = <51>; - dmacap,memcpy; - dmacap,xor; - }; - xor11 { - interrupts = <52>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - ethernet@70000 { - compatible = "marvell,armada-xp-neta"; - }; - - ethernet@74000 { - compatible = "marvell,armada-xp-neta"; - }; - - crypto@90000 { - compatible = "marvell,armada-xp-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>, <49>; - clocks = <&gateclk 23>, <&gateclk 23>; - clock-names = "cesa0", "cesa1"; - marvell,crypto-srams = <&crypto_sram0>, - <&crypto_sram1>; - marvell,crypto-sram-size = <0x800>; - }; - - bm: bm@c0000 { - compatible = "marvell,armada-380-neta-bm"; - reg = <0xc0000 0xac>; - clocks = <&gateclk 13>; - internal-mem = <&bm_bppi>; - status = "disabled"; - }; - - xor@f0900 { - compatible = "marvell,orion-xor"; - reg = <0xF0900 0x100 - 0xF0B00 0x100>; - clocks = <&gateclk 28>; - status = "okay"; - - xor00 { - interrupts = <94>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <95>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - }; - - crypto_sram0: sa-sram0 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; - }; - - crypto_sram1: sa-sram1 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gateclk 23>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; - }; - - bm_bppi: bm-bppi { - compatible = "mmio-sram"; - reg = ; - ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gateclk 13>; - no-memory-wc; - status = "disabled"; - }; - }; - - clocks { - /* 25 MHz reference crystal */ - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; -}; - -&pinctrl { - ge0_gmii_pins: ge0-gmii-pins { - marvell,pins = - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "ge0"; - }; - - ge0_rgmii_pins: ge0-rgmii-pins { - marvell,pins = - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - - ge1_rgmii_pins: ge1-rgmii-pins { - marvell,pins = - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "ge1"; - }; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - - spi0_pins: spi0-pins { - marvell,pins = "mpp36", "mpp37", - "mpp38", "mpp39"; - marvell,function = "spi0"; - }; - - spi1_pins: spi1-pins { - marvell,pins = "mpp13", "mpp14", - "mpp16", "mpp17"; - marvell,function = "spi1"; - }; - - uart2_pins: uart2-pins { - marvell,pins = "mpp42", "mpp43"; - marvell,function = "uart2"; - }; - - uart3_pins: uart3-pins { - marvell,pins = "mpp44", "mpp45"; - marvell,function = "uart3"; - }; -}; - -&spi0 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; -}; - -&spi1 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/armv7-m.dtsi b/software/linux/kernel/arch/arm/boot/dts/armv7-m.dtsi deleted file mode 100644 index ba332e399..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/armv7-m.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -/ { - nvic: interrupt-controller@e000e100 { - compatible = "arm,armv7m-nvic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xe000e100 0xc00>; - }; - - systick: timer@e000e010 { - compatible = "arm,armv7m-systick"; - reg = <0xe000e010 0x10>; - status = "disabled"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&nvic>; - ranges; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/artpec6-devboard.dts b/software/linux/kernel/arch/arm/boot/dts/artpec6-devboard.dts deleted file mode 100644 index f823ed382..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/artpec6-devboard.dts +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Axis ARTPEC-6 development board. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "artpec6.dtsi" - -/ { - model = "ARTPEC-6 development board"; - compatible = "axis,artpec6-dev-board", "axis,artpec6"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -ðernet { - status = "okay"; - - phy-handle = <&phy1>; - phy-mode = "gmii"; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0x0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/artpec6.dtsi b/software/linux/kernel/arch/arm/boot/dts/artpec6.dtsi deleted file mode 100644 index 3489019cc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/artpec6.dtsi +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Device Tree Source for the Axis ARTPEC-6 SoC - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "axis,artpec6"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&pl310>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&pl310>; - }; - }; - - syscon { - compatible = "axis,artpec6-syscon", "syscon"; - reg = <0xf8000000 0x48>; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - psci_version = <0x84000000>; - cpu_on = <0x84000003>; - system_reset = <0x84000009>; - }; - - scu@faf00000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfaf00000 0x58>; - }; - - /* Main external clock driving CPU and peripherals */ - ext_clk: ext_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - eth_phy_ref_clk: eth_phy_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - }; - - clkctrl: clkctrl@0xf8000000 { - #clock-cells = <1>; - compatible = "axis,artpec6-clkctrl"; - reg = <0xf8000000 0x48>; - clocks = <&ext_clk>; - clock-names = "sys_refclk"; - }; - - gtimer@faf00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfaf00200 0x20>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; - }; - - timer@faf00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfaf00600 0x20>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; - status = "disabled"; - }; - - intc: interrupt-controller@faf01000 { - interrupt-controller; - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >; - }; - - pl310: cache-controller@faf10000 { - compatible = "arm,pl310-cache"; - cache-unified; - cache-level = <2>; - reg = <0xfaf10000 0x1000>; - interrupts = ; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - arm,filter-ranges = <0x0 0x80000000>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <0>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,prefetch-offset = <0>; - arm,prefetch-drop = <1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - interrupt-parent = <&intc>; - }; - - amba@0 { - compatible = "simple-bus"; - #address-cells = <0x1>; - #size-cells = <0x1>; - interrupt-parent = <&intc>; - ranges; - dma-ranges = <0x80000000 0x00000000 0x40000000>; - dma-coherent; - - ethernet: ethernet@f8010000 { - clock-names = "phy_ref_clk", "apb_pclk"; - clocks = <ð_phy_ref_clk>, - <&clkctrl ARTPEC6_CLK_ETH_ACLK>; - compatible = "snps,dwc-qos-ethernet-4.10"; - interrupt-parent = <&intc>; - interrupts = ; - reg = <0xf8010000 0x4000>; - - snps,write-requests = <2>; - snps,read-requests = <16>; - snps,txpbl = <8>; - snps,rxpbl = <2>; - - status = "disabled"; - }; - - uart0: serial@f8036000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8036000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - status = "disabled"; - }; - uart1: serial@f8037000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8037000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - status = "disabled"; - }; - uart2: serial@f8038000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8038000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - status = "disabled"; - }; - uart3: serial@f8039000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8039000 0x1000>; - interrupts = ; - clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, - <&clkctrl ARTPEC6_CLK_UART_PCLK>; - clock-names = "uart_clk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/software/linux/kernel/arch/arm/boot/dts/aspeed-ast2500-evb.dts deleted file mode 100644 index 1b7a5ff0e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ /dev/null @@ -1,25 +0,0 @@ -/dts-v1/; - -#include "aspeed-g5.dtsi" - -/ { - model = "AST2500 EVB"; - compatible = "aspeed,ast2500"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; -}; - -&uart5 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/software/linux/kernel/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts deleted file mode 100644 index cc5fcf294..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ /dev/null @@ -1,25 +0,0 @@ -/dts-v1/; - -#include "aspeed-g4.dtsi" - -/ { - model = "Palmetto BMC"; - compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; - - aliases { - serial4 = &uart5; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,38400 earlyprintk"; - }; - - memory { - reg = <0x40000000 0x10000000>; - }; -}; - -&uart5 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/aspeed-g4.dtsi b/software/linux/kernel/arch/arm/boot/dts/aspeed-g4.dtsi deleted file mode 100644 index 22dee5937..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/aspeed-g4.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -#include "skeleton.dtsi" - -/ { - model = "Aspeed BMC"; - compatible = "aspeed,ast2400"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - clocks { - clk_clkin: clk_clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; - - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic: interrupt-controller@1e6c0080 { - compatible = "aspeed,ast2400-vic"; - interrupt-controller; - #interrupt-cells = <1>; - valid-sources = <0xffffffff 0x0007ffff>; - reg = <0x1e6c0080 0x80>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_hpll: clk_hpll@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g4-hpll-clock"; - reg = <0x1e6e2070 0x4>; - clocks = <&clk_clkin>; - }; - - clk_apb: clk_apb@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,g4-apb-clock"; - reg = <0x1e6e2008 0x4>; - clocks = <&clk_hpll>; - }; - - clk_uart: clk_uart@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,uart-clock"; - reg = <0x1e6e202c 0x4>; - }; - - sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x8000>; // 32K - }; - - timer: timer@1e782000 { - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - // The moxart_timer driver registers only one - // interrupt and assumes it's for timer 1 - //interrupts = <16 17 18 35 36 37 38 39>; - interrupts = <16>; - clocks = <&clk_apb>; - }; - - wdt1: wdt@1e785000 { - compatible = "aspeed,wdt"; - reg = <0x1e785000 0x1c>; - interrupts = <27>; - }; - - wdt2: wdt@1e785020 { - compatible = "aspeed,wdt"; - reg = <0x1e785020 0x1c>; - interrupts = <27>; - clocks = <&clk_apb>; - status = "disabled"; - }; - - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; - - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/aspeed-g5.dtsi b/software/linux/kernel/arch/arm/boot/dts/aspeed-g5.dtsi deleted file mode 100644 index dd94d9361..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/aspeed-g5.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -#include "skeleton.dtsi" - -/ { - model = "Aspeed BMC"; - compatible = "aspeed,ast2500"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm1176jzf-s"; - device_type = "cpu"; - reg = <0>; - }; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic: interrupt-controller@1e6c0080 { - compatible = "aspeed,ast2400-vic"; - interrupt-controller; - #interrupt-cells = <1>; - valid-sources = <0xfefff7ff 0x0807ffff>; - reg = <0x1e6c0080 0x80>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_clkin: clk_clkin@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-clkin-clock"; - reg = <0x1e6e2070 0x04>; - }; - - clk_hpll: clk_hpll@1e6e2024 { - #clock-cells = <0>; - compatible = "aspeed,g5-hpll-clock"; - reg = <0x1e6e2024 0x4>; - clocks = <&clk_clkin>; - }; - - clk_ahb: clk_ahb@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-ahb-clock"; - reg = <0x1e6e2070 0x4>; - clocks = <&clk_hpll>; - }; - - clk_apb: clk_apb@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,g5-apb-clock"; - reg = <0x1e6e2008 0x4>; - clocks = <&clk_hpll>; - }; - - clk_uart: clk_uart@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,uart-clock"; - reg = <0x1e6e202c 0x4>; - }; - - sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x9000>; // 36K - }; - - timer: timer@1e782000 { - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - // The moxart_timer driver registers only one - // interrupt and assumes it's for timer 1 - //interrupts = <16 17 18 35 36 37 38 39>; - interrupts = <16>; - clocks = <&clk_apb>; - }; - - wdt1: wdt@1e785000 { - compatible = "aspeed,wdt"; - reg = <0x1e785000 0x1c>; - interrupts = <27>; - }; - - wdt2: wdt@1e785020 { - compatible = "aspeed,wdt"; - reg = <0x1e785020 0x1c>; - interrupts = <27>; - status = "disabled"; - }; - - wdt3: wdt@1e785040 { - compatible = "aspeed,wdt"; - reg = <0x1e785074 0x1c>; - status = "disabled"; - }; - - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - - uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - - uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - - uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; - - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-ariag25.dts b/software/linux/kernel/arch/arm/boot/dts/at91-ariag25.dts deleted file mode 100644 index 4da011a7a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-ariag25.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based) - * - * Copyright (C) 2013 Douglas Gilbert , - * Robert Nelson - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g25.dtsi" - -/ { - model = "Acme Systems Aria G25"; - compatible = "acme,ariag25", "atmel,at91sam9x5ek", - "atmel,at91sam9x5", "atmel,at91sam9"; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - serial5 = &uart0; - serial6 = &uart1; - }; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; - }; - - memory { - /* 128 MB, change this for 256 MB revision */ - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - mmc0: mmc@f0008000 { - /* N.B. Aria has no SD card detect (CD), assumed present */ - - pinctrl-0 = < - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - i2c0: i2c@f8010000 { - status = "okay"; - }; - - i2c1: i2c@f8014000 { - status = "okay"; - }; - - /* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */ - - usart0: serial@f801c000 { - pinctrl-0 = <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; - }; - - usart1: serial@f8020000 { - pinctrl-0 = <&pinctrl_usart1 - /* &pinctrl_usart1_rts */ - /* &pinctrl_usart1_cts */ - >; - status = "okay"; - }; - - usart2: serial@f8024000 { - /* cannot activate RTS2+CTS2, clash with - * ethernet on PB0 and PB1 */ - pinctrl-0 = <&pinctrl_usart2>; - status = "okay"; - }; - - usart3: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - interrupts = <8 4 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3 - /* &pinctrl_usart3_rts */ - /* &pinctrl_usart3_cts */ - >; - status = "okay"; - }; - - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - /* - * following can be overwritten by bootloader: - * for example u-boot 'ftd set' command - */ - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - }; - - /* - * UART0/1 pins are marked as GPIO on - * Aria documentation. - * Change to "okay" if you need additional serial ports - */ - uart0: serial@f8040000 { - status = "disabled"; - }; - - uart1: serial@f8044000 { - status = "disabled"; - }; - - adc0: adc@f804c000 { - status = "okay"; - atmel,adc-channels-used = <0xf>; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - w1_0 { - pinctrl_w1_0: w1_0-0 { - atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */ - }; - }; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - }; - - usb0: ohci@00600000 { - status = "okay"; - num-ports = <3>; - }; - - usb1: ehci@00700000 { - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - /* little green LED in middle of Aria G25 module */ - aria_led { - label = "aria_led"; - gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ - linux,default-trigger = "heartbeat"; - }; - - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&pioA 21 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_w1_0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-ariettag25.dts b/software/linux/kernel/arch/arm/boot/dts/at91-ariettag25.dts deleted file mode 100644 index c51450208..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-ariettag25.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Device Tree file for Arietta G25 - * This device tree is minimal, to activate more peripherals, see: - * http://dts.acmesystems.it/arietta/ - */ -/dts-v1/; -#include "at91sam9g25.dtsi" -/ { - model = "Acme Systems Arietta G25"; - compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9"; - - aliases { - serial0 = &dbgu; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - mmc0: mmc@f0008000 { - pinctrl-0 = < - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - usb2: gadget@f803c000 { - status = "okay"; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - }; - - usb0: ohci@00600000 { - status = "okay"; - num-ports = <3>; - }; - - usb1: ehci@00700000 { - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - arietta_led { - label = "arietta_led"; - gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-cosino.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91-cosino.dtsi deleted file mode 100644 index 02d8ef43d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-cosino.dtsi +++ /dev/null @@ -1,120 +0,0 @@ -/* - * at91-cosino.dtsi - Device Tree file for Cosino core module - * - * Copyright (C) 2013 - Rodolfo Giometti - * HCE Engineering - * - * Derived from at91sam9x5ek.dtsi by: - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ - -#include "at91sam9g35.dtsi" - -/ { - model = "HCE Cosino core module"; - compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - mmc0: mmc@f0008000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - usart0: serial@f801c000 { - status = "okay"; - }; - - i2c0: i2c@f8010000 { - status = "okay"; - }; - - adc0: adc@f804c000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD15 gpio CD pin pull up and deglitch */ - }; - }; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; /* Enable PMECC */ - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0x80000>; - }; - - ubootenv@c0000 { - label = "U-Boot Env"; - reg = <0xc0000 0x140000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-cosino_mega2560.dts b/software/linux/kernel/arch/arm/boot/dts/at91-cosino_mega2560.dts deleted file mode 100644 index 27ebb0f72..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * at91-cosino_mega2560.dts - Device Tree file for Cosino board with - * Mega 2560 extension - * - * Copyright (C) 2013 - Rodolfo Giometti - * HCE Engineering - * - * Derived from at91sam9g35ek.dts by: - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; -#include "at91-cosino.dtsi" - -/ { - model = "HCE Cosino Mega 2560"; - compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; - - ahb { - apb { - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - - adc0: adc@f804c000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - - usart1: serial@f8020000 { - status = "okay"; - }; - - usart2: serial@f8024000 { - status = "okay"; - }; - - usb2: gadget@f803c000 { - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc1: mmc@f000c000 { - pinctrl-0 = < - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - non-removable; - }; - }; - }; - - usb0: ohci@00600000 { - status = "okay"; - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ - &pioD 19 GPIO_ACTIVE_LOW - &pioD 20 GPIO_ACTIVE_LOW - >; - }; - - usb1: ehci@00700000 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-foxg20.dts b/software/linux/kernel/arch/arm/boot/dts/at91-foxg20.dts deleted file mode 100644 index 50d5e719b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-foxg20.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board - * - * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC) - * - * Copyright (C) 2013 Douglas Gilbert - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g20.dtsi" - -/ { - model = "Acme Systems FoxG20"; - compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - >; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - usart2: serial@fffb8000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - - uart0: serial@fffd4000 { - status = "okay"; - }; - - uart1: serial@fffd8000 { - status = "okay"; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = - ; - }; - }; - - mmc0_slot1 { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; /* CD pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* TWCK (SCL), open drain */ - }; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - i2c-gpio,delay-us = <5>; /* ~85 kHz */ - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - /* red LED marked "PC7" near mini USB (device) receptacle */ - user_led { - label = "user_led"; - gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - btn { - label = "Button"; - gpios = <&pioC 4 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-kizbox.dts b/software/linux/kernel/arch/arm/boot/dts/at91-kizbox.dts deleted file mode 100644 index b4f147c19..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-kizbox.dts +++ /dev/null @@ -1,150 +0,0 @@ -/* - * at91-kizbox.dts - Device Tree file for Overkiz Kizbox board - * - * Copyright (C) 2012-2014 Boris BREZILLON - * 2014-2015 Gaël PORTAY - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g20.dtsi" -#include - -/ { - model = "Overkiz Kizbox"; - compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x2000000>; - }; - - clocks { - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - macb0: ethernet@fffc4000 { - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_macb_rmii - &pinctrl_macb_rmii_mii_alt>; - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - watchdog@fffffd40 { - timeout-sec = <15>; - atmel,max-heartbeat-sec = <16>; - atmel,min-heartbeat-sec = <0>; - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <1>; - status = "okay"; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - status = "okay"; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - reset { - label = "PB_RST"; - gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - - user { - label = "PB_USER"; - gpios = <&pioB 31 GPIO_ACTIVE_HIGH>; - linux,code = <0x101>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - rtc: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - - network_green { - label = "pwm:green:network"; - pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - network_red { - label = "pwm:red:network"; - pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - user_green { - label = "pwm:green:user"; - pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - user_red { - label = "pwm:red:user"; - pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - tcb_pwm: pwm { - compatible = "atmel,tcb-pwm"; - #pwm-cells = <3>; - tc-block = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tcb1_tioa0 - &pinctrl_tcb1_tioa1 - &pinctrl_tcb1_tioa2 - &pinctrl_tcb1_tiob0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-kizbox2.dts b/software/linux/kernel/arch/arm/boot/dts/at91-kizbox2.dts deleted file mode 100644 index 50a14568f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-kizbox2.dts +++ /dev/null @@ -1,216 +0,0 @@ -/* - * at91-kizbox2.dts - Device Tree file for Overkiz Kizbox 2 board - * - * Copyright (C) 2014 Gaël PORTAY - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "sama5d31.dtsi" -#include - -/ { - model = "Overkiz Kizbox 2"; - compatible = "overkiz,kizbox2", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - i2c1: i2c@f0018000 { - status = "okay"; - - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "okay"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG1 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vddana_reg: LDO_REG2 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vled_reg: LDO_REG3 { - regulator-name = "VLED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v3v8_rf_reg: LDO_REG4 { - regulator-name = "V3V8_RF"; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - regulator-always-on; - }; - }; - }; - }; - - usart0: serial@f001c000 { - status = "okay"; - }; - - usart1: serial@f0020000 { - status = "okay"; - }; - - pwm0: pwm@f002c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwmh0_1 - &pinctrl_pwm0_pwmh1_1 - &pinctrl_pwm0_pwmh2_0>; - status = "okay"; - }; - - adc0: adc@f8018000 { - atmel,adc-vref = <3333>; - status = "okay"; - }; - - usart2: serial@f8020000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - - dbgu: serial@ffffee00 { - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb1: ohci@00600000 { - status = "okay"; - }; - - usb2: ehci@00700000 { - status = "okay"; - }; - - nand0: nand@60000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - prog { - label = "PB_PROG"; - gpios = <&pioE 27 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - reset { - label = "PB_RST"; - gpios = <&pioE 29 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - - user { - label = "PB_USER"; - gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; - linux,code = <0x101>; - wakeup-source; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - - blue { - label = "pwm:blue:user"; - pwms = <&pwm0 2 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - green { - label = "pwm:green:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - red { - label = "pwm:red:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-kizboxmini.dts b/software/linux/kernel/arch/arm/boot/dts/at91-kizboxmini.dts deleted file mode 100644 index 9682d105d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-kizboxmini.dts +++ /dev/null @@ -1,129 +0,0 @@ -/* - * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board - * - * Copyright (C) 2014 Gaël PORTAY - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g25.dtsi" -#include - -/ { - model = "Overkiz Kizbox mini"; - compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "ubi.mtd=ubi"; - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - usart0: serial@f801c000 { - status = "okay"; - }; - - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - - pwm0: pwm@f8034000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm0_1 - &pinctrl_pwm0_pwm1_1>; - status = "okay"; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb0: ohci@00600000 { - num-ports = <1>; - status = "okay"; - }; - - usb1: ehci@00700000 { - status = "okay"; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - bootstrap@0 { - label = "bootstrap"; - reg = <0x0 0x20000>; - }; - - ubi@20000 { - label = "ubi"; - reg = <0x20000 0x7fe0000>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - prog { - label = "PB_PROG"; - gpios = <&pioC 17 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - wakeup-source; - }; - - reset { - label = "PB_RST"; - gpios = <&pioC 16 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - - green { - label = "pwm:green:user"; - pwms = <&pwm0 0 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - - red { - label = "pwm:red:user"; - pwms = <&pwm0 1 10000000 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-qil_a9260.dts b/software/linux/kernel/arch/arm/boot/dts/at91-qil_a9260.dts deleted file mode 100644 index 8f019184f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-qil_a9260.dts +++ /dev/null @@ -1,184 +0,0 @@ -/* - * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board - * - * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9260.dtsi" -/ { - model = "Calao QIL A9260"; - compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - pinctrl-0 = - <&pinctrl_usart1 - &pinctrl_usart1_rts - &pinctrl_usart1_cts>; - status = "okay"; - }; - - usart2: serial@fffb8000 { - pinctrl-0 = - <&pinctrl_usart2 - &pinctrl_usart2_rts - &pinctrl_usart2_cts>; - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - spi0: spi@fffc8000 { - status = "okay"; - cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>; - - m41t94@0 { - compatible = "st,m41t94"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@a0000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@c0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4c0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7cc0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-sam9_l9260.dts b/software/linux/kernel/arch/arm/boot/dts/at91-sam9_l9260.dts deleted file mode 100644 index 171243ca4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-sam9_l9260.dts +++ /dev/null @@ -1,121 +0,0 @@ -/* - * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board - * - * Copyright (C) 2016 Raashid Muhammed - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9260.dtsi" - -/ { - model = "Olimex sam9-l9260"; - compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; - }; - }; - - macb0: ethernet@fffc4000 { - pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii_alt>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - }; - }; - - spi0: spi@fffc8000 { - cs-gpios = <&pioC 11 0>, <0>, <0>, <0>; - status = "okay"; - - flash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* WP pin */ - }; - }; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt = <1>; - status = "okay"; - }; - - usb0: ohci@500000 { - status = "okay"; - }; - - }; - - i2c-gpio-0 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - pwr_led { - label = "sam9-l9260:yellow:pwr"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - }; - - status_led { - label = "sam9-l9260:green:status"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "timer"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/software/linux/kernel/arch/arm/boot/dts/at91-sama5d2_xplained.dts deleted file mode 100644 index 30fac0428..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ /dev/null @@ -1,507 +0,0 @@ -/* - * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board - * - * Copyright (C) 2015 Atmel, - * 2015 Nicolas Ferre - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" -#include -#include - -/ { - model = "Atmel SAMA5D2 Xplained"; - compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x80000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - usb0: gadget@00300000 { - atmel,vbus-gpio = <&pioA 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@00400000 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioA 41 GPIO_ACTIVE_HIGH */ - &pioA 42 GPIO_ACTIVE_HIGH - 0 - >; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_default>; - status = "okay"; - }; - - usb2: ehci@00500000 { - status = "okay"; - }; - - sdmmc0: sdio-host@a0000000 { - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_default>; - non-removable; - mmc-ddr-1_8v; - status = "okay"; - }; - - sdmmc1: sdio-host@b0000000 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_default>; - status = "okay"; /* conflict with qspi0 */ - }; - - apb { - spi0: spi@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - status = "okay"; - - m25p80@0 { - compatible = "atmel,at25df321a"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - macb0: ethernet@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioA>; - interrupts = <73 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - pdmic@f8018000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdmic_default>; - atmel,model = "PDMIC @ sama5d2_xplained"; - atmel,mic-min-freq = <1000000>; - atmel,mic-max-freq = <3246000>; - atmel,mic-offset = <0x0>; - status = "okay"; - }; - - uart1: serial@f8020000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - i2c0: i2c@f8028000 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - i2c-sda-hold-time-ns = <350>; - status = "okay"; - - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - active-semi,vsel-high; - active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; - active-semi,irq_gpios = <&pioA 45 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; - status = "okay"; - - regulators { - vdd_1v35_reg: REG_DCDC1 { - regulator-name = "VDD_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd_1v2_reg: REG_DCDC2 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - vdd_3v3_reg: REG_DCDC3 { - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_fuse_reg: REG_LDO1 { - regulator-name = "VDD_FUSE"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_3v3_lp_reg: REG_LDO2 { - regulator-name = "VDD_3V3_LP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_led_reg: REG_LDO3 { - regulator-name = "VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sdhc_1v8_reg: REG_LDO4 { - regulator-name = "VDD_SDHC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; - }; - - flx0: flexcom@f8034000 { - atmel,flexcom-mode = ; - status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ - - uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&flx0_clk>; - clock-names = "usart"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; - status = "okay"; - }; - }; - - shdwc@f8048010 { - atmel,shdwc-debouncer = <976>; - - input@0 { - reg = <0>; - atmel,wakeup-type = "low"; - }; - }; - - watchdog@f8048040 { - status = "okay"; - }; - - uart3: serial@fc008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_default>; - status = "okay"; - }; - - flx4: flexcom@fc018000 { - atmel,flexcom-mode = ; - status = "okay"; - - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx4_clk>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; - status = "okay"; - }; - }; - - i2c1: i2c@fc028000 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - status = "okay"; - - at24@54 { - compatible = "atmel,24c02"; - reg = <0x54>; - pagesize = <16>; - }; - }; - - adc: adc@fc030000 { - vddana-supply = <&vdd_3v3_lp_reg>; - vref-supply = <&vdd_3v3_lp_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc_default>; - status = "okay"; - }; - - pinctrl@fc038000 { - /* - * There is no real pinmux for ADC, if the pin - * is not requested by another peripheral then - * the muxing is done when channel is enabled. - * Requesting pins for ADC is GPIO is - * encouraged to prevent conflicts and to - * disable bias in order to be in the same - * state when the pin is not muxed to the adc. - */ - pinctrl_adc_default: adc_default { - pinmux = ; - bias-disable; - }; - - pinctrl_charger_chglev: charger_chglev { - pinmux = ; - bias-disable; - }; - - pinctrl_charger_irq: charger_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_charger_lbo: charger_lbo { - pinmux = ; - bias-pull-up; - }; - - pinctrl_flx0_default: flx0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_flx4_default: flx4_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_key_gpio_default: key_gpio_default { - pinmux = ; - bias-pull-up; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - , - ; - bias-pull-up; - }; - - pinctrl_macb0_default: macb0_default { - pinmux = , - , - , - , - , - , - , - , - , - ; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = ; - bias-disable; - }; - - pinctrl_pdmic_default: pdmic_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - cmd_data { - pinmux = , - , - , - , - , - , - , - , - ; - bias-pull-up; - }; - - ck_cd_rstn_vddsel { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-pull-up; - }; - - conf-ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - - pinctrl_spi0_default: spi0_default { - pinmux = , - , - , - ; - bias-disable; - }; - - pinctrl_uart1_default: uart1_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_uart3_default: uart3_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_usb_default: usb_default { - pinmux = ; - bias-disable; - }; - - pinctrl_usba_vbus: usba_vbus { - pinmux = ; - bias-disable; - }; - - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio_default>; - - bp1 { - label = "PB_USER"; - gpios = <&pioA 41 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_gpio_default>; - status = "okay"; - - red { - label = "red"; - gpios = <&pioA 38 GPIO_ACTIVE_LOW>; - }; - - green { - label = "green"; - gpios = <&pioA 37 GPIO_ACTIVE_LOW>; - }; - - blue { - label = "blue"; - gpios = <&pioA 32 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/software/linux/kernel/arch/arm/boot/dts/at91-sama5d3_xplained.dts deleted file mode 100644 index 5a53fcf54..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ /dev/null @@ -1,336 +0,0 @@ -/* - * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "sama5d36.dtsi" - -/ { - model = "SAMA5D3 Xplained"; - compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - mmc0: mmc@f0000000 { - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; - }; - }; - - mmc1: mmc@f8000000 { - vmmc-supply = <&vcc_3v3_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "disabled"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>; - }; - }; - - spi0: spi@f0004000 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - pinctrl-0 = <&pinctrl_i2c0_pu>; - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - status = "disabled"; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG1 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vddana_reg: LDO_REG2 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - }; - - macb0: ethernet@f0028000 { - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@7 { - reg = <0x7>; - }; - }; - - pwm0: pwm@f002c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; - status = "okay"; - }; - - usart0: serial@f001c000 { - status = "okay"; - }; - - usart1: serial@f0020000 { - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - status = "okay"; - }; - - uart0: serial@f0024000 { - status = "okay"; - }; - - mmc1: mmc@f8000000 { - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>; - }; - }; - - spi1: spi@f8008000 { - cs-gpios = <&pioC 25 0>; - status = "okay"; - }; - - adc0: adc@f8018000 { - atmel,adc-vref = <3300>; - atmel,adc-channels-used = <0xfe>; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7 - >; - status = "okay"; - }; - - i2c2: i2c@f801c000 { - dmas = <0>, <0>; /* Do not use DMA for i2c2 */ - pinctrl-0 = <&pinctrl_i2c2_pu>; - status = "okay"; - }; - - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - }; - }; - - dbgu: serial@ffffee00 { - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_i2c0_pu: i2c0_pu { - atmel,pins = - , - ; - }; - - pinctrl_i2c2_pu: i2c2_pu { - atmel,pins = - , - ; - }; - - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; /* PE9, conflicts with A9 */ - }; - }; - }; - }; - - nand0: nand@60000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - - usb0: gadget@00500000 { - atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@00600000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 3 GPIO_ACTIVE_LOW - &pioE 4 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@00700000 { - status = "okay"; - }; - }; - - vcc_mmc0_reg: fixedregulator_mmc0 { - compatible = "regulator-fixed"; - gpio = <&pioE 2 GPIO_ACTIVE_LOW>; - regulator-name = "mmc0-card-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - bp3 { - label = "PB_USER"; - gpios = <&pioE 29 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - d2 { - label = "d2"; - gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ - linux,default-trigger = "heartbeat"; - }; - - d3 { - label = "d3"; - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi deleted file mode 100644 index a92c6e0ca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "sama5d4.dtsi" - -/ { - model = "DENX MA5D4"; - compatible = "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - - clk20m: clk20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "clk20m"; - }; - }; - - ahb { - apb { - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - broken-cd; - }; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - spi1: spi@fc018000 { - cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <6 GPIO_ACTIVE_LOW>; - spi-max-frequency = <10000000>; - }; - - can1: can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <7 GPIO_ACTIVE_LOW>; - spi-max-frequency = <10000000>; - }; - }; - - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - atmel,adc-vref = <3300>; - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - }; - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mmc0_reg: fixedregulator_mmc0 { - compatible = "regulator-fixed"; - gpio = <&pioE 15 GPIO_ACTIVE_HIGH>; - regulator-name = "RST_n MCI0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - regulator-boot-on; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts deleted file mode 100644 index eac4ea274..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "at91-sama5d4_ma5d4.dtsi" - -/ { - model = "DENX MA5D4EVK"; - compatible = "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - ahb { - usb0: gadget@00400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@00500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_LOW - &pioE 14 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@00600000 { - status = "okay"; - }; - - apb { - hlcdc: hlcdc@f0000000 { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - usart0: serial@f802c000 { - status = "okay"; - }; - - usart1: serial@f8030000 { - status = "okay"; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - vmmc-supply = <&vcc_mmc1_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 5 0>; - }; - }; - - adc0: adc@fc034000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - }; - - - pinctrl@fc06a000 { - board { - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - user1 { - label = "user1"; - gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "user2"; - gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user3 { - label = "user3"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel: panel { - /* Actually Ampire 800480R2 */ - compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; - backlight = <&backlight>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - vcc_mmc1_reg: fixedregulator_mmc1 { - compatible = "regulator-fixed"; - gpio = <&pioE 17 GPIO_ACTIVE_LOW>; - regulator-name = "VDD MCI1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_xplained.dts deleted file mode 100644 index 44d1171c7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ /dev/null @@ -1,275 +0,0 @@ -/* - * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board - * - * Copyright (C) 2015 Atmel, - * 2015 Josh Wu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "sama5d4.dtsi" - -/ { - model = "Atmel SAMA5D4 Xplained"; - compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; - - phy0: ethernet-phy@1 { - interrupt-parent = <&pioE>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - reg = <1>; - }; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - vmmc-supply = <&vcc_mmc1_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 3 0>; - }; - }; - - usart3: serial@fc00c000 { - atmel,use-dma-rx; - atmel,use-dma-tx; - status = "okay"; - }; - - usart4: serial@fc010000 { - status = "okay"; - }; - - spi1: spi@fc018000 { - cs-gpios = <&pioB 21 0>; - status = "okay"; - }; - - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - atmel,adc-vref = <3300>; - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; - }; - pinctrl_macb0_phy_irq: macb0_phy_irq_0 { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@00400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@00500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_HIGH - &pioE 14 GPIO_ACTIVE_HIGH - >; - status = "okay"; - }; - - usb2: ehci@00600000 { - status = "okay"; - }; - - nand0: nand@80000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - atmel,has-pmecc; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - d8 { - label = "d8"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - d10 { - label = "d10"; - gpios = <&pioE 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mmc1_reg: fixedregulator_mmc1 { - compatible = "regulator-fixed"; - gpio = <&pioE 4 GPIO_ACTIVE_LOW>; - regulator-name = "VDD MCI1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - regulator-always-on; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4ek.dts deleted file mode 100644 index f8b96cef5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-sama5d4ek.dts +++ /dev/null @@ -1,329 +0,0 @@ -/* - * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "sama5d4.dtsi" - -/ { - model = "Atmel SAMA5D4-EK"; - compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ - atmel,adc-vref = <3300>; - /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ - status = "okay"; /* Enable ADC IIO support */ - }; - - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 5 0>; - }; - }; - - ssc0: ssc@f8008000 { - status = "okay"; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - - wm8904: codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pck2>; - clock-names = "mclk"; - }; - - qt1070:keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioE>; - interrupts = <25 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; - - atmel_mxt_ts@4c { - compatible = "atmel,atmel_mxt_ts"; - reg = <0x4c>; - interrupt-parent = <&pioE>; - interrupts = <24 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mxt_ts>; - }; - }; - - macb0: ethernet@f8020000 { - pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioE>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 6 0>; - }; - }; - - usart2: serial@fc008000 { - status = "okay"; - }; - - usart3: serial@fc00c000 { - status = "okay"; - }; - - usart4: serial@fc010000 { - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_macb0_phy_irq: macb0_phy_irq { - atmel,pins = - ; - }; - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; - }; - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; - }; - pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { - atmel,pins = - ; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - pinctrl_key_gpio: key_gpio_0 { - atmel,pins = - ; /* PE13 gpio */ - }; - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - pinctrl_mxt_ts: mxt_irq { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@00400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@00500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ - &pioE 11 GPIO_ACTIVE_LOW - &pioE 12 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@00600000 { - status = "okay"; - }; - - nand0: nand@80000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - atmel,has-pmecc; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_key_gpio>; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - d8 { - label = "d8"; - /* PE28, conflicts with usart4 rts pin */ - gpios = <&pioE 28 GPIO_ACTIVE_LOW>; - }; - - d9 { - label = "d9"; - gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; - }; - - d10 { - label = "d10"; - gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; - - atmel,model = "wm8904 @ SAMA5D4EK"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN1L", "Line In Jack", - "IN1R", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91-vinco.dts b/software/linux/kernel/arch/arm/boot/dts/at91-vinco.dts deleted file mode 100644 index e0c0b2897..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91-vinco.dts +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Device Tree file for VInCo platform - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - * 2015 Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "sama5d4.dtsi" - -/ { - model = "L+G VInCo platform"; - compatible = "l+g,vinco", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - - adc0: adc@fc034000 { - status = "okay"; /* Enable ADC IIO support */ - }; - - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 - &pinctrl_mmc0_dat1_3 - &pinctrl_mmc0_dat4_7>; - vqmmc-supply = <&vcc_3v3_reg>; - vmmc-supply = <&vcc_3v3_reg>; - no-1-8-v; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - non-removable; - broken-cd; - status = "okay"; - }; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - m25p80@0 { - compatible = "n25q32b", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - i2c1: i2c@f8018000 { - status = "okay"; - /* kerkey security module */ - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - reset-gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - interrupt-parent = <&pioB>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - }; - - }; - - i2c2: i2c@f8024000 { - status = "okay"; - - rtc1: rtc@64 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - }; - - usart2: serial@fc008000 { - /* MBUS */ - status = "okay"; - }; - - usart3: serial@fc00c000 { - /* debug */ - status = "okay"; - }; - - usart4: serial@fc010000 { - /* LMN */ - pinctrl-0 = <&pinctrl_usart4 &pinctrl_usart4_rts>; - linux,rs485-enabled-at-boot-time; - status = "okay"; - }; - - macb1: ethernet@fc028000 { - phy-mode = "rmii"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>; - }; - }; - - watchdog@fc068640 { - status = "okay"; - }; - - pinctrl@fc06a000 { - board { - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; - }; - }; - }; - }; - - usb0: gadget@00400000 { - atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "disable"; - }; - - usb1: ohci@00500000 { - num-ports = <3>; - atmel,vbus-gpio = <0 - &pioE 11 GPIO_ACTIVE_LOW - &pioE 12 GPIO_ACTIVE_LOW - >; - status = "disable"; - }; - - usb2: ehci@00600000 { - /* 4G Modem */ - status = "okay"; - }; - - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - led_err { - label = "err"; - gpios = <&pioA 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_rssi { - label = "rssi"; - gpios = <&pioA 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_tls { - label = "tls"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_lmc { - label = "lmc"; - gpios = <&pioA 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_wmt { - label = "wmt"; - gpios = <&pioA 29 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led_pwr { - label = "pwr"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91rm9200.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91rm9200.dtsi deleted file mode 100644 index 4e913c2cc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91rm9200.dtsi +++ /dev/null @@ -1,965 +0,0 @@ -/* - * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre , - * 2012 Joachim Eastwood - * - * Based on at91sam9260.dtsi - * - * Licensed under GPLv2 or later. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include - -/ { - model = "Atmel AT91RM9200 family SoC"; - compatible = "atmel,at91rm9200"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - ssc2 = &ssc2; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm920t"; - device_type = "cpu"; - }; - }; - - memory { - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@00200000 { - compatible = "mmio-sram"; - reg = <0x00200000 0x4000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <25 26 27 28 29 30 31>; - }; - - ramc0: ramc@ffffff00 { - compatible = "atmel,at91rm9200-sdramc", "syscon"; - reg = <0xffffff00 0x100>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 80000000>; - atmel,clk-divisors = <1 2 3 4>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 0 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - udpck: udpck { - #clock-cells = <0>; - reg = <2>; - clocks = <&usb>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <4>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - reg = <12>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc2_clk: ssc2_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - tc3_clk: tc3_clk { - #clock-cells = <0>; - reg = <20>; - }; - - tc4_clk: tc4_clk { - #clock-cells = <0>; - reg = <21>; - }; - - tc5_clk: tc5_clk { - #clock-cells = <0>; - reg = <22>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <23>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <24>; - }; - }; - }; - - st: timer@fffffd00 { - compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; - reg = <0xfffffd00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - - watchdog { - compatible = "atmel,at91rm9200-wdt"; - }; - }; - - rtc: rtc@fffffe00 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffe00 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffa4000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffa4000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 - 21 IRQ_TYPE_LEVEL_HIGH 0 - 22 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - i2c0: i2c@fffb8000 { - compatible = "atmel,at91rm9200-i2c"; - reg = <0xfffb8000 0x4000>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_twi>; - clocks = <&twi0_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@fffb4000 { - compatible = "atmel,hsmci"; - reg = <0xfffb4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - ssc0: ssc@fffd0000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd0000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffd4000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd4000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc2: ssc@fffd8000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffd8000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&ssc2_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91rm9200-emac", "cdns,emac"; - reg = <0xfffbc000 0x4000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>; - clock-names = "ether_clk"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffffffff /* pioA */ - 0xffffffff 0x083fffff /* pioB */ - 0xffff3fff 0x00000000 /* pioC */ - 0x03ff87ff 0x0fffff80 /* pioD */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* PA31 periph with pullup */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PA18 periph A */ - }; - - pinctrl_uart0_cts: uart0_cts-0 { - atmel,pins = - ; /* PA20 periph A */ - }; - - pinctrl_uart0_rts: uart0_rts-0 { - atmel,pins = - ; /* PA21 periph A */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* PB21 periph A */ - }; - - pinctrl_uart1_rts: uart1_rts-0 { - atmel,pins = - ; /* PB24 periph A */ - }; - - pinctrl_uart1_cts: uart1_cts-0 { - atmel,pins = - ; /* PB26 periph A */ - }; - - pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { - atmel,pins = - ; /* PB25 periph A */ - }; - - pinctrl_uart1_dcd: uart1_dcd-0 { - atmel,pins = - ; /* PB23 periph A */ - }; - - pinctrl_uart1_ri: uart1_ri-0 { - atmel,pins = - ; /* PB18 periph A */ - }; - }; - - uart2 { - pinctrl_uart2: uart2-0 { - atmel,pins = - ; /* PA23 periph A with pullup */ - }; - - pinctrl_uart2_rts: uart2_rts-0 { - atmel,pins = - ; /* PA30 periph B */ - }; - - pinctrl_uart2_cts: uart2_cts-0 { - atmel,pins = - ; /* PA31 periph B */ - }; - }; - - uart3 { - pinctrl_uart3: uart3-0 { - atmel,pins = - ; /* PA6 periph B */ - }; - - pinctrl_uart3_rts: uart3_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_uart3_cts: uart3_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PB1 gpio CD pin pull_up */ - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA16 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PB19 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA27 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA29 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PB5 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA9 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA12 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB2 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB5 periph A */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PB8 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PB11 periph A */ - }; - }; - - ssc2 { - pinctrl_ssc2_tx: ssc2_tx-0 { - atmel,pins = - ; /* PB14 periph A */ - }; - - pinctrl_ssc2_rx: ssc2_rx-0 { - atmel,pins = - ; /* PB17 periph A */ - }; - }; - - twi { - pinctrl_twi: twi-0 { - atmel,pins = - ; /* PA26 periph A with multi drive */ - }; - - pinctrl_twi_gpio: twi_gpio-0 { - atmel,pins = - ; /* PA26 GPIO with multi drive */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph A SPI0_SPCK pin */ - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fffc0000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc0000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffc4000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc4000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffc8000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffc8000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffcc000 { - compatible = "atmel,at91rm9200-usart"; - reg = <0xfffcc000 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usb1: gadget@fffb0000 { - compatible = "atmel,at91rm9200-udc"; - reg = <0xfffb0000 0x4000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - spi0: spi@fffe0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffe0000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-ecc-mode = "soft"; - gpios = <&pioC 2 GPIO_ACTIVE_HIGH - 0 - &pioB 1 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - }; - - usb0: ohci@00300000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00300000 0x100000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ - &pioA 26 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_twi_gpio>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91rm9200_pqfp.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91rm9200_pqfp.dtsi deleted file mode 100644 index 93ca66f80..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91rm9200_pqfp.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -/* - * at91rm9200_pqfp.dtsi - Device Tree Include file for AT91RM9200 PQFP family SoC - * - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 or later. - */ - -#include "at91rm9200.dtsi" - -/ { - compatible = "atmel,at91rm9200-pqfp", "atmel,at91rm9200"; -}; - -&pioD { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91rm9200ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91rm9200ek.dts deleted file mode 100644 index f90e1c2d3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91rm9200ek.dts +++ /dev/null @@ -1,136 +0,0 @@ -/* - * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit - * - * Copyright (C) 2012 Joachim Eastwood - * - * Licensed under GPLv2 only - */ -/dts-v1/; -#include "at91rm9200.dtsi" - -/ { - model = "Atmel AT91RM9200 evaluation kit"; - compatible = "atmel,at91rm9200ek", "atmel,at91rm9200"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - usb1: gadget@fffb0000 { - atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; - atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - - phy0: ethernet-phy { - interrupt-parent = <&pioC>; - interrupts = <4 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - usart1: serial@fffc4000 { - pinctrl-0 = - <&pinctrl_uart1 - &pinctrl_uart1_rts - &pinctrl_uart1_cts - &pinctrl_uart1_dtr_dsr - &pinctrl_uart1_dcd - &pinctrl_uart1_ri>; - status = "okay"; - }; - - spi0: spi@fffe0000 { - status = "okay"; - cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - rtc: rtc@fffffe00 { - status = "okay"; - }; - }; - - usb0: ohci@00300000 { - num-ports = <2>; - status = "okay"; - }; - - nor_flash@10000000 { - compatible = "cfi-flash"; - reg = <0x10000000 0x800000>; - linux,mtd-name = "physmap-flash.0"; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - barebox@0 { - label = "barebox"; - reg = <0x00000 0x40000>; - }; - - bareboxenv@40000 { - label = "bareboxenv"; - reg = <0x40000 0x10000>; - }; - - kernel@50000 { - label = "kernel"; - reg = <0x50000 0x300000>; - }; - - root@350000 { - label = "root"; - reg = <0x350000 0x4B0000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds2 { - label = "green"; - gpios = <&pioB 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - ds4 { - label = "yellow"; - gpios = <&pioB 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - ds6 { - label = "red"; - gpios = <&pioB 2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9260.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9260.dtsi deleted file mode 100644 index a3e363d79..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9260.dtsi +++ /dev/null @@ -1,1030 +0,0 @@ -/* - * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre , - * 2011 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 or later. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include - -/ { - model = "Atmel AT91SAM9260 family SoC"; - compatible = "atmel,at91sam9260"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - serial5 = &uart0; - serial6 = &uart1; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - ssc0 = &ssc0; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <5000000>; - }; - }; - - sram0: sram@002ff000 { - compatible = "mmio-sram"; - reg = <0x002ff000 0x2000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <29 30 31>; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9260-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9260-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_xtal>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 160000000 0 1>, - <150000000 240000000 2 1>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 5000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 105000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 4 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <9>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <10>; - }; - - twi0_clk: twi0_clk { - reg = <11>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <20>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <22>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <23>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <24>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <25>; - }; - - tc3_clk: tc3_clk { - #clock-cells = <0>; - reg = <26>; - }; - - tc4_clk: tc4_clk { - #clock-cells = <0>; - reg = <27>; - }; - - tc5_clk: tc5_clk { - #clock-cells = <0>; - reg = <28>; - }; - }; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffdc000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 - 27 IRQ_TYPE_LEVEL_HIGH 0 - 28 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x600>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffc00c3b /* pioA */ - 0xffffffff 0x7fff3ccf /* pioB */ - 0xffffffff 0x007fffff /* pioC */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* PB15 periph with pullup */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; /* PB5 periph A */ - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PB26 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PB27 periph A */ - }; - - pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { - atmel,pins = - ; /* PB22 periph A */ - }; - - pinctrl_usart0_dcd: usart0_dcd-0 { - atmel,pins = - ; /* PB23 periph A */ - }; - - pinctrl_usart0_ri: usart0_ri-0 { - atmel,pins = - ; /* PB25 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; /* PB7 periph A */ - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PB28 periph A */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PB29 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* PB9 periph A */ - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PA4 periph A */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PA5 periph A */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* PB11 periph A */ - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PA30 periph B */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* PB13 periph A */ - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PC14 gpio enable pin pull_up */ - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA21 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - - pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA8 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA6 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA11 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA0 periph B with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA3 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB18 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB21 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB2 periph A SPI1_SPCK pin */ - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffd0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd0000 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart0: serial@fffd4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd4000 0x200>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@fffd8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffd8000 0x200>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - macb0: ethernet@fffc4000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffc4000 0x100>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - usb1: gadget@fffa4000 { - compatible = "atmel,at91sam9260-udc"; - reg = <0xfffa4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffac000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - mmc0: mmc@fffa8000 { - compatible = "atmel,hsmci"; - reg = <0xfffa8000 0x600>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi0: spi@fffc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffc8000 0x200>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - adc0: adc@fffe0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9260-adc"; - reg = <0xfffe0000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0xf>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <15>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "timer-counter-0"; - trigger-value = <0x1>; - }; - trigger1 { - trigger-name = "timer-counter-1"; - trigger-value = <0x3>; - }; - - trigger2 { - trigger-name = "timer-counter-2"; - trigger-value = <0x5>; - }; - - trigger3 { - trigger-name = "external"; - trigger-value = <0xd>; - trigger-external; - }; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - gpbr: syscon@fffffd50 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd50 0x10>; - status = "disabled"; - }; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe800 0x200 - >; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioC 13 GPIO_ACTIVE_HIGH - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - - usb0: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ - &pioA 24 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9260ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9260ek.dts deleted file mode 100644 index 2c87f5844..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9260ek.dts +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Device Tree file for Atmel at91sam9260 Evaluation Kit - * - * Copyright (C) 2016 Atmel, - * 2016 Nicolas Ferre - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "at91sam9260.dtsi" - -/ { - model = "Atmel at91sam9260ek"; - compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - stdout-path = &dbgu; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0_slot1 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - ssc0: ssc@fffbc000 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - spi0: spi@fffc8000 { - cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <1>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - board { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; - }; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - gpbr: syscon@fffffd50 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - btn3 { - label = "Button 3"; - gpios = <&pioA 30 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - gpio-key,wakeup; - }; - - btn4 { - label = "Button 4"; - gpios = <&pioA 31 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - gpio-key,wakeup; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "24c512"; - reg = <0x50>; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9261.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9261.dtsi deleted file mode 100644 index 32752d788..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9261.dtsi +++ /dev/null @@ -1,876 +0,0 @@ -/* - * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC - * - * Copyright (C) 2013 Jean-Jacques Hiblot - * - * Licensed under GPLv2 only. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include - -/ { - model = "Atmel AT91SAM9261 family SoC"; - compatible = "atmel,at91sam9261"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - tcb0 = &tcb0; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - ssc2 = &ssc2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - reg = <0x20000000 0x08000000>; - }; - - clocks { - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x28000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usb0: ohci@00500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&hclk0>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - fb0: fb@0x00600000 { - compatible = "atmel,at91sam9261-lcdc"; - reg = <0x00600000 0x1000>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&hclk1>; - clock-names = "lcdc_clk", "hclk"; - status = "disabled"; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000>; - atmel,nand-addr-offset = <22>; - atmel,nand-cmd-offset = <21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - - gpios = <&pioC 15 GPIO_ACTIVE_HIGH>, - <&pioC 14 GPIO_ACTIVE_HIGH>, - <0>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, - <18 IRQ_TYPE_LEVEL_HIGH 0>, - <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - usb1: gadget@fffa4000 { - compatible = "atmel,at91sam9261-udc"; - reg = <0xfffa4000 0x4000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; - clock-names = "pclk", "hclk"; - atmel,matrix = <&matrix>; - status = "disabled"; - }; - - mmc0: mmc@fffa8000 { - compatible = "atmel,hsmci"; - reg = <0xfffa8000 0x600>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9261-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_twi>; - reg = <0xfffac000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000{ - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffc0000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffc0000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc2: ssc@fffc4000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffc4000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&ssc2_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi0: spi@fffc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffc8000 0x200>; - cs-gpios = <0>, <0>, <0>, <0>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ramc: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - matrix: matrix@ffffee00 { - compatible = "atmel,at91sam9260-bus-matrix", "syscon"; - reg = <0xffffee00 0x200>; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <29 30 31>; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x600>; - - atmel,mux-mask = - /* A B */ - <0xffffffff 0xfffffff7>, /* pioA */ - <0xffffffff 0xfffffff4>, /* pioB */ - <0xffffffff 0xffffff07>; /* pioC */ - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - , - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - , - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - , - ; - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc2 { - pinctrl_ssc2_tx: ssc2_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc2_rx: ssc2_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - , - , - ; - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - , - , - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - i2c0 { - pinctrl_i2c_bitbang: i2c-0-bitbang { - atmel,pins = - , - ; - }; - pinctrl_i2c_twi: i2c-0-twi { - atmel,pins = - , - ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, - <190000000 240000000 2 1>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 5000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 94000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 4 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - - hclk0: hclk0 { - #clock-cells = <0>; - reg = <16>; - clocks = <&mck>; - }; - - hclk1: hclk1 { - #clock-cells = <0>; - reg = <17>; - clocks = <&mck>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <9>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <10>; - }; - - twi0_clk: twi0_clk { - reg = <11>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc2_clk: ssc2_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <20>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <21>; - }; - }; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&slow_xtal>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&slow_xtal>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - gpbr: syscon@fffffd50 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd50 0x10>; - status = "disabled"; - }; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_bitbang>; - gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9261ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9261ek.dts deleted file mode 100644 index 55bd51f07..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9261ek.dts +++ /dev/null @@ -1,211 +0,0 @@ -/* - * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board - * - * Copyright (C) 2013 Jean-Jacques Hiblot - * - * Licensed under GPLv2 only. - */ -/dts-v1/; -#include "at91sam9261.dtsi" - -/ { - model = "Atmel at91sam9261ek"; - compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9"; - - chosen { - bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - usb0: ohci@00500000 { - status = "okay"; - }; - - fb0: fb@0x00600000 { - display = <&display0>; - atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>; - status = "okay"; - - display0: display { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - atmel,lcd-wiring-mode = "BRG"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - - apb { - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffc8000 { - cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; - status = "okay"; - - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - reg = <0>; - spi-max-frequency = <15000000>; - }; - - tsc2046@0 { - reg = <2>; - compatible = "ti,ads7843"; - interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>; - spi-max-frequency = <3000000>; - pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <150>; - ti,x-max = /bits/ 16 <3830>; - ti,y-min = /bits/ 16 <190>; - ti,y-max = /bits/ 16 <3830>; - ti,vref-delay-usecs = /bits/ 16 <450>; - ti,x-plate-ohms = /bits/ 16 <450>; - ti,y-plate-ohms = /bits/ 16 <250>; - ti,pressure-max = /bits/ 16 <15000>; - ti,debounce-rep = /bits/ 16 <0>; - ti,debounce-tol = /bits/ 16 <65535>; - ti,debounce-max = /bits/ 16 <1>; - - wakeup-source; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - }; - }; - - leds { - compatible = "gpio-leds"; - - ds8 { - label = "ds8"; - gpios = <&pioA 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - ds7 { - label = "ds7"; - gpios = <&pioA 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - ds1 { - label = "ds1"; - gpios = <&pioA 23 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button_0 { - label = "button_0"; - gpios = <&pioA 27 GPIO_ACTIVE_LOW>; - linux,code = <256>; - wakeup-source; - }; - - button_1 { - label = "button_1"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - linux,code = <257>; - wakeup-source; - }; - - button_2 { - label = "button_2"; - gpios = <&pioA 25 GPIO_ACTIVE_LOW>; - linux,code = <258>; - wakeup-source; - }; - - button_3 { - label = "button_3"; - gpios = <&pioA 24 GPIO_ACTIVE_LOW>; - linux,code = <259>; - wakeup-source; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9263.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9263.dtsi deleted file mode 100644 index aeb1a3637..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9263.dtsi +++ /dev/null @@ -1,1034 +0,0 @@ -/* - * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 only. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include - -/ { - model = "Atmel AT91SAM9263 family SoC"; - compatible = "atmel,at91sam9263"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - i2c0 = &i2c0; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - reg = <0x20000000 0x08000000>; - }; - - clocks { - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram0: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x14000>; - }; - - sram1: sram@00500000 { - compatible = "mmio-sram"; - reg = <0x00500000 0x4000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <30 31>; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, - <190000000 240000000 2 1>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, - <190000000 240000000 2 1>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 120000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 4 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioCDE_clk: pioCDE_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <11>; - }; - - can_clk: can_clk { - #clock-cells = <0>; - reg = <12>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - ac97_clk: ac97_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tcb_clk: tcb_clk { - #clock-cells = <0>; - reg = <19>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <20>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - g2de_clk: g2de_clk { - #clock-cells = <0>; - reg = <23>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <24>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <25>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <26>; - }; - - dma_clk: dma_clk { - #clock-cells = <0>; - reg = <27>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <29>; - }; - }; - }; - - ramc0: ramc@ffffe200 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe200 0x200>; - }; - - ramc1: ramc@ffffe800 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe800 0x200>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfff7c000 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&slow_xtal>; - clock-names = "t0_clk", "slow_clk"; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&slow_xtal>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&slow_xtal>; - }; - - pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - - atmel,mux-mask = < - /* A B */ - 0xfffffffb 0xffffe07f /* pioA */ - 0x0007ffff 0x39072fff /* pioB */ - 0xffffffff 0x3ffffff8 /* pioC */ - 0xfffffbff 0xffffffff /* pioD */ - 0xffe00fff 0xfbfcff00 /* pioE */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* PC31 periph with pullup */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; /* PA27 periph A */ - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA28 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA29 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; /* PD1 periph A */ - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PD7 periph B */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PD8 periph B */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* PD3 periph A */ - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PD5 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PD6 periph B */ - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PD15 gpio enable pin pull_up */ - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PE30 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PE22 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; /* PA12 periph A */ - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA0 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA5 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA17 periph A with pullup */ - }; - - pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_clk: mmc1_clk-0 { - atmel,pins = - ; /* PA6 periph A */ - }; - - pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { - atmel,pins = - ; /* PA8 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA11 periph A with pullup */ - }; - - pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { - atmel,pins = - ; /* PA22 periph A with pullup */ - }; - - pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { - atmel,pins = - ; /* PA25 periph A with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PB2 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PB5 periph B */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PB8 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PB11 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA2 periph B SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB14 periph A SPI1_SPCK pin */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - ; /* PC27 periph A */ - }; - }; - - can { - pinctrl_can_rx_tx: can_rx_tx { - atmel,pins = - ; /* CANTX, conflicts with PCK0 */ - }; - }; - - ac97 { - pinctrl_ac97: ac97-0 { - atmel,pins = - ; /* PB14 periph A AC97RX pin */ - }; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - }; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xffffee00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fff90000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff90000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fff94000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff94000 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fff98000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfff98000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fff9c000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfff9c000 0x4000>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ac97: sound@fffa0000 { - compatible = "atmel,at91sam9263-ac97c"; - reg = <0xfffa0000 0x4000>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ac97>; - clocks = <&ac97_clk>; - clock-names = "ac97_clk"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffbc000 0x100>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - usb1: gadget@fff78000 { - compatible = "atmel,at91sam9263-udc"; - reg = <0xfff78000 0x4000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - i2c0: i2c@fff88000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfff88000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - mmc0: mmc@fff80000 { - compatible = "atmel,hsmci"; - reg = <0xfff80000 0x600>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - mmc1: mmc@fff84000 { - compatible = "atmel,hsmci"; - reg = <0xfff84000 0x600>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci1_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - spi0: spi@fffa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa4000 0x200>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa8000 0x200>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - pwm0: pwm@fffb8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffb8000 0x300>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - clock-names = "pwm_clk"; - status = "disabled"; - }; - - can: can@fffac000 { - compatible = "atmel,at91sam9263-can"; - reg = <0xfffac000 0x300>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_rx_tx>; - clocks = <&can_clk>; - clock-names = "can_clk"; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - rtc@fffffd50 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd50 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&slow_xtal>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x50>; - status = "disabled"; - }; - }; - - fb0: fb@0x00700000 { - compatible = "atmel,at91sam9263-lcdc"; - reg = <0x00700000 0x1000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; - clock-names = "lcdc_clk", "hclk"; - status = "disabled"; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe000 0x200 - >; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioA 22 GPIO_ACTIVE_HIGH - &pioD 15 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - - usb0: ohci@00a00000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00a00000 0x100000>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ - &pioB 5 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9263ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9263ek.dts deleted file mode 100644 index 127cc42e9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9263ek.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 only - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Atmel at91sam9263ek"; - compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <16367660>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - usart0: serial@fff8c000 { - pinctrl-0 = < - &pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff200 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PE19 gpio WP pin pull up */ - }; - }; - }; - - spi0: spi@fffa4000 { - status = "okay"; - cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - fb0: fb@0x00700000 { - display = <&display0>; - status = "okay"; - - display0: display { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt = <1>; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - - usb0: ohci@00a00000 { - num-ports = <2>; - status = "okay"; - atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH - &pioA 21 GPIO_ACTIVE_HIGH - >; - }; - }; - - leds { - compatible = "gpio-leds"; - - d3 { - label = "d3"; - gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - d2 { - label = "d2"; - gpios = <&pioC 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - left_click { - label = "left_click"; - gpios = <&pioC 5 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - - right_click { - label = "right_click"; - gpios = <&pioC 4 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "24c512"; - reg = <0x50>; - pagesize = <128>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g15.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9g15.dtsi deleted file mode 100644 index 27de7dc0f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g15.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -/* - * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" - -/ { - model = "Atmel AT91SAM9G15 SoC"; - compatible = "atmel,at91sam9g15", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0x00000000 /* pioA */ - 0x00040000 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g15ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9g15ek.dts deleted file mode 100644 index d1d2b400f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g15ek.dts +++ /dev/null @@ -1,41 +0,0 @@ -/* - * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g15.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G15-EK"; - compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - ahb { - apb { - hlcdc: hlcdc@f8038000 { - status = "okay"; - }; - }; - }; - - backlight: backlight { - status = "okay"; - }; - - bl_reg: backlight_regulator { - status = "okay"; - }; - - panel: panel { - status = "okay"; - }; - - panel_reg: panel_regulator { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g20.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9g20.dtsi deleted file mode 100644 index f59301618..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g20.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -/* - * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ - -#include "at91sam9260.dtsi" - -/ { - model = "Atmel AT91SAM9G20 family SoC"; - compatible = "atmel,at91sam9g20"; - - memory { - reg = <0x20000000 0x08000000>; - }; - - sram0: sram@002ff000 { - status = "disabled"; - }; - - sram1: sram@002fc000 { - compatible = "mmio-sram"; - reg = <0x002fc000 0x8000>; - }; - - ahb { - apb { - i2c0: i2c@fffac000 { - compatible = "atmel,at91sam9g20-i2c"; - }; - - ssc0: ssc@fffbc000 { - compatible = "atmel,at91sam9rl-ssc"; - }; - - adc0: adc@fffe0000 { - atmel,adc-startup-time = <40>; - }; - - pmc: pmc@fffffc00 { - plla: pllack { - atmel,clk-input-range = <2000000 32000000>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, - <695000000 750000000 1 0>, - <645000000 700000000 2 0>, - <595000000 650000000 3 0>, - <545000000 600000000 0 1>, - <495000000 550000000 1 1>, - <445000000 500000000 2 1>, - <400000000 450000000 3 1>; - }; - - pllb: pllbck { - compatible = "atmel,at91sam9g20-clk-pllb"; - atmel,clk-input-range = <2000000 32000000>; - atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; - }; - - mck: masterck { - atmel,clk-output-range = <0 133000000>; - atmel,clk-divisors = <1 2 4 6>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek.dts deleted file mode 100644 index bbfd75311..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9g20ek_common.dtsi" - -/ { - model = "Atmel at91sam9g20ek"; - compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioA 6 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts deleted file mode 100644 index bdb799bad..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9g20ek_common.dtsi" - -/ { - model = "Atmel at91sam9g20ek 2 mmc"; - compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; - - ahb { - apb{ - mmc0: mmc@fffa8000 { - /* clk already mux wuth slot0 */ - pinctrl-0 = < - &pinctrl_board_mmc0_slot0 - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff400 { - mmc0_slot0 { - pinctrl_board_mmc0_slot0: mmc0_slot0-board { - atmel,pins = - ; /* PC2 gpio CD pin pull up and deglitch */ - }; - }; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds1 { - label = "ds1"; - gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - ds5 { - label = "ds5"; - gpios = <&pioB 8 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek_common.dtsi deleted file mode 100644 index 27847a47c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ /dev/null @@ -1,225 +0,0 @@ -/* - * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ -#include "at91sam9g20.dtsi" - -/ { - - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - pinctrl@fffff400 { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = - ; /* PC1 periph B */ - }; - - }; - - mmc0_slot1 { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - ; /* PC9 gpio CD pin pull up and deglitch */ - }; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - mmc0: mmc@fffa8000 { - pinctrl-0 = < - &pinctrl_board_mmc0_slot1 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot1_cmd_dat0 - &pinctrl_mmc0_slot1_dat1_3>; - status = "okay"; - slot@1 { - reg = <1>; - bus-width = <4>; - cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; - }; - }; - - ssc0: ssc@fffbc000 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; - }; - - spi0: spi@fffc8000 { - cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <1>; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - gpbr: syscon@fffffd50 { - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - 24c512@50 { - compatible = "24c512"; - reg = <0x50>; - }; - - wm8731: wm8731@1b { - compatible = "wm8731"; - reg = <0x1b>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - btn3 { - label = "Button 3"; - gpios = <&pioA 30 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - wakeup-source; - }; - - btn4 { - label = "Button 4"; - gpios = <&pioA 31 GPIO_ACTIVE_LOW>; - linux,code = <0x104>; - wakeup-source; - }; - }; - - sound { - compatible = "atmel,at91sam9g20ek-wm8731-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8731 @ AT91SAMG20EK"; - - atmel,audio-routing = - "Ext Spk", "LHPOUT", - "Int Mic", "MICIN"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g25.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9g25.dtsi deleted file mode 100644 index a7da0dd0c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g25.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -/* - * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_isi.dtsi" -#include "at91sam9x5_usart3.dtsi" -#include "at91sam9x5_macb0.dtsi" - -/ { - model = "Atmel AT91SAM9G25 SoC"; - compatible = "atmel,at91sam9g25", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0xc000001c /* pioA */ - 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */ - 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g25ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9g25ek.dts deleted file mode 100644 index 91a717744..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g25ek.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g25.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G25-EK"; - compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - ahb { - apb { - spi0: spi@f0000000 { - status = "disabled"; - }; - - mmc1: mmc@f000c000 { - status = "disabled"; - }; - - i2c0: i2c@f8010000 { - ov2640: camera@0x30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck0>; - clock-names = "xvclk"; - assigned-clocks = <&pck0>; - assigned-clock-rates = <25000000>; - status = "okay"; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - - isi: isi@f8048000 { - status = "okay"; - port { - isi_0: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g35.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9g35.dtsi deleted file mode 100644 index ff4115886..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g35.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -/* - * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" -#include "at91sam9x5_macb0.dtsi" - -/ { - model = "Atmel AT91SAM9G35 SoC"; - compatible = "atmel,at91sam9g35", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe0399f 0xc000000c /* pioA */ - 0x000406ff 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g35ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9g35ek.dts deleted file mode 100644 index 23ec8b13f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g35ek.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g35.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9G35-EK"; - compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - ahb { - apb { - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - - hlcdc: hlcdc@f8038000 { - status = "okay"; - }; - }; - }; - - backlight: backlight { - status = "okay"; - }; - - bl_reg: backlight_regulator { - status = "okay"; - }; - - panel: panel { - status = "okay"; - }; - - panel_reg: panel_regulator { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9g45.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9g45.dtsi deleted file mode 100644 index b3501ae2a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9g45.dtsi +++ /dev/null @@ -1,1331 +0,0 @@ -/* - * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC - * applies to AT91SAM9G45, AT91SAM9M10, - * AT91SAM9G46, AT91SAM9M11 SoC - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Atmel AT91SAM9G45 family SoC"; - compatible = "atmel,at91sam9g45"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - reg = <0x70000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000>; - }; - }; - - sram: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - ramc0: ramc@ffffe400 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe400 0x200>; - clocks = <&ddrck>; - clock-names = "ddrck"; - }; - - ramc1: ramc@ffffe600 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe600 0x200>; - clocks = <&ddrck>; - clock-names = "ddrck"; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9g45-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0 - 695000000 750000000 1 0 - 645000000 700000000 2 0 - 595000000 650000000 3 0 - 545000000 600000000 0 1 - 495000000 555000000 1 1 - 445000000 500000000 2 1 - 400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKU>; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9g45-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioDE_clk: pioDE_clk { - #clock-cells = <0>; - reg = <5>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <9>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <18>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <19>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <23>; - }; - - ac97_clk: ac97_clk { - #clock-cells = <0>; - reg = <24>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <25>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <26>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <27>; - }; - - aestdessha_clk: aestdessha_clk { - #clock-cells = <0>; - reg = <28>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <29>; - }; - - vdec_clk: vdec_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - - shdwc@fffffd10 { - compatible = "atmel,at91sam9rl-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfff7c000 0x100>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - tcb1: timer@fffd4000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffd4000 0x100>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffc003ff /* pioA */ - 0xffffffff 0x800f8f00 /* pioB */ - 0xffffffff 0x00000e00 /* pioC */ - 0xffffffff 0xff0c1381 /* pioD */ - 0xffffffff 0x81ffff81 /* pioE */ - >; - - /* shared pinctrl settings */ - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = ; - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = ; - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = ; - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = ; - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = ; - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = ; - }; - pinctrl_adc0_ad5: adc0_ad5 { - atmel,pins = ; - }; - pinctrl_adc0_ad6: adc0_ad6 { - atmel,pins = ; - }; - pinctrl_adc0_ad7: adc0_ad7 { - atmel,pins = ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* PB13 periph A */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA20 periph A TWD0 */ - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PB10 periph A TWD1 */ - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* HSYNC */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* D9 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* D11 */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; /* PB18 periph A */ - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PB17 periph B */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PB15 periph B */ - }; - }; - - uart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; /* PB5 periph A */ - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PD16 periph A */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PD17 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* PB7 periph A */ - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PC9 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PC11 periph B */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* PB8 periph A */ - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PA23 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PA24 periph B */ - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PC14 gpio enable pin pull_up */ - }; - }; - - macb { - pinctrl_macb_rmii: macb_rmii-0 { - atmel,pins = - ; /* PA19 periph A */ - }; - - pinctrl_macb_rmii_mii: macb_rmii_mii-0 { - atmel,pins = - ; /* PA30 periph B */ - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA2 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA5 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { - atmel,pins = - ; /* PA9 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA23 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA26 periph A with pullup */ - }; - - pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { - atmel,pins = - ; /* PA30 periph A with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PD2 periph A */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PD5 periph A */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - ; /* PD12 periph A */ - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - ; /* PD15 periph A */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PB2 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PB16 periph A SPI1_SPCK pin */ - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - ; /* PE30 periph A */ - }; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; - }; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xffffee00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fff90000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff90000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fff94000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff94000 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fff98000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff98000 0x200>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - macb0: ethernet@fffbc000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xfffbc000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - trng@fffcc000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfffcc000 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; - }; - - i2c0: i2c@fff84000 { - compatible = "atmel,at91sam9g10-i2c"; - reg = <0xfff84000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@fff88000 { - compatible = "atmel,at91sam9g10-i2c"; - reg = <0xfff88000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - ssc0: ssc@fff9c000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfff9c000 0x4000>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - ssc1: ssc@fffa0000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfffa0000 0x4000>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - adc0: adc@fffb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9g45-adc"; - reg = <0xfffb0000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0xff>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; - }; - - isi@fffb4000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xfffb4000 0x4000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&isi_clk>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pwm0: pwm@fffb8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffb8000 0x300>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - status = "disabled"; - }; - - mmc0: mmc@fff80000 { - compatible = "atmel,hsmci"; - reg = <0xfff80000 0x600>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - mmc1: mmc@fffd0000 { - compatible = "atmel,hsmci"; - reg = <0xfffd0000 0x600>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; - dma-names = "rxtx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci1_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - spi0: spi@fffa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa4000 0x200>; - interrupts = <14 4 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@fffa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffa8000 0x200>; - interrupts = <15 4 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - usb2: gadget@fff78000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9g45-udc"; - reg = <0x00600000 0x80000 - 0xfff78000 0x400>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&udphs_clk>, <&utmi>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - }; - - sckc@fffffd50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffd50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - atmel,startup-time-usec = <1200000>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - atmel,startup-time-usec = <75>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - rtc@fffffdb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffdb0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x10>; - status = "disabled"; - }; - }; - - fb0: fb@0x00500000 { - compatible = "atmel,at91sam9g45-lcdc"; - reg = <0x00500000 0x1000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; - clock-names = "hclk", "lcdc_clk"; - status = "disabled"; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe200 0x200 - >; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioC 8 GPIO_ACTIVE_HIGH - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - - usb0: ohci@00700000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00700000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb1: ehci@00800000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00800000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ - &pioA 21 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <5>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9m10g45ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9m10g45ek.dts deleted file mode 100644 index 2400c9913..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ /dev/null @@ -1,357 +0,0 @@ -/* - * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board - * - * Copyright (C) 2011 Atmel, - * 2011 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9g45.dtsi" -#include - -/ { - model = "Atmel AT91SAM9M10G45-EK"; - compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x70000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - usart1: serial@fff90000 { - pinctrl-0 = - <&pinctrl_usart1 - &pinctrl_usart1_rts - &pinctrl_usart1_cts>; - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - i2c0: i2c@fff84000 { - status = "okay"; - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck1>; - clock-names = "xvclk"; - assigned-clocks = <&pck1>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - i2c1: i2c@fff88000 { - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; - }; - }; - - mmc1: mmc@fffd0000 { - pinctrl-0 = < - &pinctrl_board_mmc1 - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; - wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff200 { - camera_sensor { - pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; - }; - }; - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD10 gpio CD pin pull up and deglitch */ - }; - }; - - mmc1 { - pinctrl_board_mmc1: mmc1-board { - atmel,pins = - ; /* PD29 gpio WP pin pull up */ - }; - }; - - pwm0 { - pinctrl_pwm_leds: pwm-led { - atmel,pins = - ; /* PD31 periph B */ - }; - }; - }; - - spi0: spi@fffa4000{ - status = "okay"; - cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <13000000>; - reg = <0>; - }; - }; - - usb2: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - adc0: adc@fffb0000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7>; - atmel,adc-ts-wires = <4>; - status = "okay"; - }; - - isi@fffb4000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - status = "okay"; - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - - pwm0: pwm@fffb8000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_leds>; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - gpbr: syscon@fffffd60 { - status = "okay"; - }; - - rtc@fffffdb0 { - status = "okay"; - }; - }; - - fb0: fb@0x00500000 { - display = <&display0>; - status = "okay"; - - display0: display { - bits-per-pixel = <32>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <9>; - atmel,lcd-wiring-mode = "RGB"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hback-porch = <1>; - hfront-porch = <1>; - vback-porch = <40>; - vfront-porch = <1>; - hsync-len = <45>; - vsync-len = <1>; - }; - }; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - boot@0 { - label = "bootstrap/uboot/kernel"; - reg = <0x0 0x400000>; - }; - - rootfs@400000 { - label = "rootfs"; - reg = <0x400000 0x3C00000>; - }; - - data@4000000 { - label = "data"; - reg = <0x4000000 0xC000000>; - }; - }; - - usb0: ohci@00700000 { - status = "okay"; - num-ports = <2>; - atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW - &pioD 3 GPIO_ACTIVE_LOW>; - }; - - usb1: ehci@00800000 { - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - d8 { - label = "d8"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - d6 { - label = "d6"; - pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "nand-disk"; - }; - - d7 { - label = "d7"; - pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - linux,default-trigger = "mmc0"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - left_click { - label = "left_click"; - gpios = <&pioB 6 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - - right_click { - label = "right_click"; - gpios = <&pioB 7 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - - left { - label = "Joystick Left"; - gpios = <&pioB 14 GPIO_ACTIVE_LOW>; - linux,code = <105>; - }; - - right { - label = "Joystick Right"; - gpios = <&pioB 15 GPIO_ACTIVE_LOW>; - linux,code = <106>; - }; - - up { - label = "Joystick Up"; - gpios = <&pioB 16 GPIO_ACTIVE_LOW>; - linux,code = <103>; - }; - - down { - label = "Joystick Down"; - gpios = <&pioB 17 GPIO_ACTIVE_LOW>; - linux,code = <108>; - }; - - enter { - label = "Joystick Press"; - gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - linux,code = <28>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9n12.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9n12.dtsi deleted file mode 100644 index 3b3eb3edc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9n12.dtsi +++ /dev/null @@ -1,1045 +0,0 @@ -/* - * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC - * - * Copyright (C) 2012 Atmel, - * 2012 Hong Xu - * - * Licensed under GPLv2 or later. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Atmel AT91SAM9N12 SoC"; - compatible = "atmel,at91sam9n12"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - sram: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x8000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - ramc0: ramc@ffffe800 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe800 0x200>; - clocks = <&ddrck>; - clock-names = "ddrck"; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9n12-pmc", "syscon"; - reg = <0xfffffc00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; - clocks = <&main_rc_osc>, <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, - <695000000 750000000 1 0>, - <645000000 700000000 2 0>, - <595000000 650000000 3 0>, - <545000000 600000000 0 1>, - <495000000 555000000 1 1>, - <445000000 500000000 2 1>, - <400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <30000000 100000000 0>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - atmel,master-clk-have-div3-pres; - }; - - usb: usbck { - compatible = "atmel,at91sam9n12-clk-usb"; - #clock-cells = <0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioAB_clk: pioAB_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioCD_clk: pioCD_clk { - #clock-cells = <0>; - reg = <3>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <8>; - }; - - twi0_clk: twi0_clk { - reg = <9>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tcb_clk: tcb_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <18>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <20>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <23>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <25>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <27>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <28>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <29>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; - }; - - rstc@fffffe00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - shdwc@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - sckc@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_osc>; - }; - }; - - mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf8008000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf800c000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - hlcdc: hlcdc@f8038000 { - compatible = "atmel,at91sam9n12-hlcdc"; - reg = <0xf8038000 0x2000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk", "sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe07983 0x00000000 /* pioA */ - 0x00040000 0x00047e0f 0x00000000 /* pioB */ - 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* PA10 periph with pullup */ - }; - }; - - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; /* PA0 periph A */ - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA2 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA3 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; /* PA5 periph A */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* PA7 periph A */ - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* PC22 periph B */ - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PC24 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PC25 periph B */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PC8 periph C */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* PC16 periph C */ - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PD4 gpio enable pin pull_up */ - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA15 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { - atmel,pins = - ; /* PA14 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PA26 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA13 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PA23 periph B SPI1_SPCK pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - }; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, - <&dma 0 AT91_DMA_CFG_PER_ID(22)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - usart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x4000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x4000>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x4000>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x4000>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, - <&dma 1 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@f8014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8014000 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, - <&dma 1 AT91_DMA_CFG_PER_ID(16)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - spi0: spi@f0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0000000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, - <&dma 1 AT91_DMA_CFG_PER_ID(4)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - rtc@fffffeb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffeb0 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x300>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - status = "disabled"; - }; - - usb1: gadget@f803c000 { - compatible = "atmel,at91sam9260-udc"; - reg = <0xf803c000 0x4000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&udpck>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x40000000 0x10000000 - 0xffffe000 0x00000600 - 0xffffe600 0x00000200 - 0x00108000 0x00018000 - >; - atmel,pmecc-lookup-table-offset = <0x0 0x8000>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 5 GPIO_ACTIVE_HIGH - &pioD 4 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - - usb0: ohci@00500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x00100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ - &pioA 31 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9n12ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9n12ek.dts deleted file mode 100644 index 626c67d66..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9n12ek.dts +++ /dev/null @@ -1,262 +0,0 @@ -/* - * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Hong Xu - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9n12.dtsi" - -/ { - model = "Atmel AT91SAM9N12-EK"; - compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; - - chosen { - bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <16000000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - ssc0: ssc@f0010000 { - status = "okay"; - }; - - i2c0: i2c@f8010000 { - status = "okay"; - - wm8904: codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pck0>; - clock-names = "mclk"; - }; - - qt1070: keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioA>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - }; - }; - - mmc0: mmc@f0008000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; - }; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PA7 gpio CD pin pull up and deglitch */ - }; - }; - - qt1070 { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - }; - - sound { - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - ; - }; - }; - - usb1 { - pinctrl_usb1_vbus_sense: usb1_vbus_sense { - atmel,pins = - ; /* PB16 gpio usb vbus sense, no pull up and deglitch */ - }; - }; - }; - - spi0: spi@f0000000 { - status = "okay"; - cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - hlcdc: hlcdc@f8038000 { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - usb1: gadget@f803c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus_sense>; - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <2>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - }; - - usb0: ohci@00500000 { - num-ports = <1>; - atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <&bl_reg>; - status = "okay"; - }; - - bl_reg: backlight_regulator { - compatible = "regulator-fixed"; - regulator-name = "backlight-power-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - d8 { - label = "d8"; - gpios = <&pioB 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - d9 { - label = "d9"; - gpios = <&pioB 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - d10 { - label = "d10"; - gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - enter { - label = "Enter"; - gpios = <&pioB 3 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "qiaodian,qd43003c0-40", "simple-panel"; - backlight = <&backlight>; - power-supply = <&panel_reg>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - panel_reg: panel_regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "okay"; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ AT91SAM9N12"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9rl.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9rl.dtsi deleted file mode 100644 index 70adf940d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9rl.dtsi +++ /dev/null @@ -1,1119 +0,0 @@ -/* - * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC - * - * Copyright (C) 2014 Alexandre Belloni - * - * Licensed under GPLv2 or later. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Atmel AT91SAM9RL family SoC"; - compatible = "atmel,at91sam9rl", "atmel,at91sam9"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - i2c0 = &i2c0; - i2c1 = &i2c1; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - reg = <0x20000000 0x04000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fb0: fb@00500000 { - compatible = "atmel,at91sam9rl-lcdc"; - reg = <0x00500000 0x1000>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; - clock-names = "hclk", "lcdc_clk"; - status = "disabled"; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000>, - <0xffffe800 0x200>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 17 GPIO_ACTIVE_HIGH>, - <&pioB 6 GPIO_ACTIVE_HIGH>, - <0>; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tcb0: timer@fffa0000 { - compatible = "atmel,at91rm9200-tcb"; - reg = <0xfffa0000 0x100>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, - <17 IRQ_TYPE_LEVEL_HIGH 0>, - <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; - clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; - }; - - mmc0: mmc@fffa4000 { - compatible = "atmel,hsmci"; - reg = <0xfffa4000 0x600>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - status = "disabled"; - }; - - i2c0: i2c@fffa8000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffa8000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@fffac000 { - compatible = "atmel,at91sam9260-i2c"; - reg = <0xfffac000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usart0: serial@fffb0000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb0000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@fffb4000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb4000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fffb8000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffb8000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fffbc000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffbc000 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@fffc0000 { - compatible = "atmel,at91sam9rl-ssc"; - reg = <0xfffc0000 0x4000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - status = "disabled"; - }; - - ssc1: ssc@fffc4000 { - compatible = "atmel,at91sam9rl-ssc"; - reg = <0xfffc4000 0x4000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - status = "disabled"; - }; - - pwm0: pwm@fffc8000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xfffc8000 0x300>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - clock-names = "pwm_clk"; - status = "disabled"; - }; - - spi0: spi@fffcc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - adc0: adc@fffd0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9rl-adc"; - reg = <0xfffd0000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0x3f>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "timer-counter-0"; - trigger-value = <0x1>; - }; - trigger1 { - trigger-name = "timer-counter-1"; - trigger-value = <0x3>; - }; - - trigger2 { - trigger-name = "timer-counter-2"; - trigger-value = <0x5>; - }; - - trigger3 { - trigger-name = "external"; - trigger-value = <0x13>; - trigger-external; - }; - }; - - usb0: gadget@fffd4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9rl-udc"; - reg = <0x00600000 0x100000>, - <0xfffd4000 0x4000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - }; - - dma0: dma-controller@ffffe600 { - compatible = "atmel,at91sam9rl-dma"; - reg = <0xffffe600 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffea00 0x200>; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - atmel,mux-mask = - /* A B */ - <0xffffffff 0xe05c6738>, /* pioA */ - <0xffffffff 0x0000c780>, /* pioB */ - <0xffffffff 0xe3ffff0e>, /* pioC */ - <0x003fffff 0x0001ff3c>; /* pioD */ - - /* shared pinctrl settings */ - adc0 { - pinctrl_adc0_ts: adc0_ts-0 { - atmel,pins = - , - , - , - ; - }; - - pinctrl_adc0_ad0: adc0_ad0-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad1: adc0_ad1-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad2: adc0_ad2-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad3: adc0_ad3-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad4: adc0_ad4-0 { - atmel,pins = ; - }; - - pinctrl_adc0_ad5: adc0_ad5-0 { - atmel,pins = ; - }; - - pinctrl_adc0_adtrg: adc0_adtrg-0 { - atmel,pins = ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - , - ; - }; - }; - - fb { - pinctrl_fb: fb-0 { - atmel,pins = - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - , - ; - }; - }; - - i2c_gpio1 { - pinctrl_i2c_gpio1: i2c_gpio1-0 { - atmel,pins = - , - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk: mmc0_clk-0 { - atmel,pins = - ; - }; - - pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { - atmel,pins = - , - ; - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - , - , - ; - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - , - ; - }; - - pinctrl_nand0_ale_cle: nand_ale_cle-0 { - atmel,pins = - , - ; - }; - - pinctrl_nand0_oe_we: nand_oe_we-0 { - atmel,pins = - , - ; - }; - - pinctrl_nand0_cs: nand_cs-0 { - atmel,pins = - ; - }; - }; - - pwm0 { - pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { - atmel,pins = ; - }; - - pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { - atmel,pins = ; - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx-0 { - atmel,pins = - , - , - ; - }; - - pinctrl_ssc1_rx: ssc1_rx-0 { - atmel,pins = - , - , - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart0_dcd: usart0_dcd-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_ri: usart0_ri-0 { - atmel,pins = - ; - }; - - pinctrl_usart0_sck: usart0_sck-0 { - atmel,pins = - ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart1_sck: usart1_sck-0 { - atmel,pins = - ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart2_sck: usart2_sck-0 { - atmel,pins = - ; - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - , - ; - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; - }; - - pinctrl_usart3_sck: usart3_sck-0 { - atmel,pins = - ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - }; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9g45-pmc", "syscon"; - reg = <0xfffffc00 0x100>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 200000000 0>, - <190000000 240000000 2>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plla>, <&utmi>; - atmel,clk-output-range = <0 94000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <18>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <19>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <23>; - }; - }; - }; - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffd30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffd30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - sckc@fffffd50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffd50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - atmel,startup-time-usec = <1200000>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - atmel,startup-time-usec = <75>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; - }; - - rtc@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - gpbr: syscon@fffffd60 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd60 0x10>; - status = "disabled"; - }; - - rtc@fffffe00 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffe00 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ - <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio1>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9rlek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9rlek.dts deleted file mode 100644 index 2e567d90f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9rlek.dts +++ /dev/null @@ -1,237 +0,0 @@ -/* - * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board - * - * Copyright (C) 2014 Alexandre Belloni - * - * Licensed under GPLv2 only - */ -/dts-v1/; -#include "at91sam9rl.dtsi" - -/ { - model = "Atmel at91sam9rlek"; - compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9"; - - chosen { - bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - fb0: fb@00500000 { - display = <&display0>; - status = "okay"; - - display0: display { - bits-per-pixel = <16>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <1>; - atmel,lcd-wiring-mode = "RGB"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <4965000>; - hactive = <240>; - vactive = <320>; - hback-porch = <1>; - hfront-porch = <33>; - vback-porch = <1>; - vfront-porch = <0>; - hsync-len = <5>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt = <1>; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - - apb { - mmc0: mmc@fffa4000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_clk - &pinctrl_mmc0_slot0_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; - }; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = < - &pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts>; - status = "okay"; - }; - - adc0: adc@fffd0000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_adtrg>; - atmel,adc-ts-wires = <4>; - status = "okay"; - }; - - usb0: gadget@fffd4000 { - atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffcc000 { - status = "okay"; - cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <15000000>; - reg = <0>; - }; - }; - - pwm0: pwm@fffc8000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, - <&pinctrl_pwm0_pwm2_2>; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - pinctrl@fffff400 { - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; - }; - }; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - - rtc@fffffe00 { - status = "okay"; - }; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - ds1 { - label = "ds1"; - pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - }; - - ds2 { - label = "ds2"; - pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; - max-brightness = <255>; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds3 { - label = "ds3"; - gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - right_click { - label = "right_click"; - gpios = <&pioB 0 GPIO_ACTIVE_LOW>; - linux,code = <273>; - wakeup-source; - }; - - left_click { - label = "left_click"; - gpios = <&pioB 1 GPIO_ACTIVE_LOW>; - linux,code = <272>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - - i2c-gpio-1 { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x25.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x25.dtsi deleted file mode 100644 index 3c5fa3388..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x25.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -/* - * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_usart3.dtsi" -#include "at91sam9x5_macb0.dtsi" -#include "at91sam9x5_macb1.dtsi" -#include "at91sam9x5_can.dtsi" - -/ { - model = "Atmel AT91SAM9X25 SoC"; - compatible = "atmel,at91sam9x25", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe03fff 0xc000001c /* pioA */ - 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ - 0x80000000 0xfffd0000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x25ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9x25ek.dts deleted file mode 100644 index 494864836..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x25ek.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9x25.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9X25-EK"; - compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - ahb { - apb { - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - - macb1: ethernet@f8030000 { - phy-mode = "rmii"; - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x35.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x35.dtsi deleted file mode 100644 index d9054e816..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x35.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -/* - * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ - -#include "at91sam9x5.dtsi" -#include "at91sam9x5_lcd.dtsi" -#include "at91sam9x5_macb0.dtsi" -#include "at91sam9x5_can.dtsi" - -/ { - model = "Atmel AT91SAM9X35 SoC"; - compatible = "atmel,at91sam9x35", "atmel,at91sam9x5"; - - ahb { - apb { - pinctrl@fffff400 { - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xffe03fff 0xc000000c /* pioA */ - 0x000406ff 0x00047e3f 0x00000000 /* pioB */ - 0xfdffffff 0x00000000 0xb83fffff /* pioC */ - 0x003fffff 0x003f8000 0x00000000 /* pioD */ - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x35ek.dts b/software/linux/kernel/arch/arm/boot/dts/at91sam9x35ek.dts deleted file mode 100644 index fcb67180e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x35ek.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9x35.dtsi" -#include "at91sam9x5dm.dtsi" -#include "at91sam9x5ek.dtsi" - -/ { - model = "Atmel AT91SAM9X35-EK"; - compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - ahb { - apb { - macb0: ethernet@f802c000 { - phy-mode = "rmii"; - status = "okay"; - }; - hlcdc: hlcdc@f8038000 { - status = "okay"; - }; - }; - }; - - backlight: backlight { - status = "okay"; - }; - - bl_reg: backlight_regulator { - status = "okay"; - }; - - panel: panel { - status = "okay"; - }; - - panel_reg: panel_regulator { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5.dtsi deleted file mode 100644 index ed4e4bd8a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5.dtsi +++ /dev/null @@ -1,1285 +0,0 @@ -/* - * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC - * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, - * AT91SAM9X25, AT91SAM9X35 SoC - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Atmel AT91SAM9x5 family SoC"; - compatible = "atmel,at91sam9x5"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - ssc0 = &ssc0; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x8000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <31>; - }; - - ramc0: ramc@ffffe800 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe800 0x200>; - clocks = <&ddrck>; - clock-names = "ddrck"; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9x5-pmc", "syscon"; - reg = <0xfffffc00 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; - clocks = <&main_rc_osc>, <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0 - 695000000 750000000 1 0 - 645000000 700000000 2 0 - 595000000 650000000 3 0 - 545000000 600000000 0 1 - 495000000 555000000 1 1 - 445000000 500000000 2 1 - 400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKU>; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - atmel,master-clk-have-div3-pres; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioAB_clk: pioAB_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioCD_clk: pioCD_clk { - #clock-cells = <0>; - reg = <3>; - }; - - smd_clk: smd_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <7>; - }; - - twi0_clk: twi0_clk { - reg = <9>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <10>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <11>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <18>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <21>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <23>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <26>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <28>; - }; - }; - }; - - rstc@fffffe00 { - compatible = "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - shdwc@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; - }; - - sckc@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_osc>; - }; - }; - - tcb0: timer@f8008000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf8008000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf800c000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - dma0: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - dma1: dma-controller@ffffee00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffee00 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma1_clk>; - clock-names = "dma_clk"; - }; - - pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfffff400 0xfffff400 0x800>; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* PA10 periph A with pullup */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; /* PA1 periph A */ - }; - - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = - ; /* PA2 periph A */ - }; - - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = - ; /* PA3 periph A */ - }; - - pinctrl_usart0_sck: usart0_sck-0 { - atmel,pins = - ; /* PA4 periph A */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; /* PA6 periph A */ - }; - - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = - ; /* PC27 periph C */ - }; - - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = - ; /* PC28 periph C */ - }; - - pinctrl_usart1_sck: usart1_sck-0 { - atmel,pins = - ; /* PC29 periph C */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* PA8 periph A */ - }; - - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = - ; /* PB0 periph B */ - }; - - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = - ; /* PB1 periph B */ - }; - - pinctrl_usart2_sck: usart2_sck-0 { - atmel,pins = - ; /* PB2 periph B */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PC9 periph C with pullup */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* PC17 periph C with pullup */ - }; - }; - - nand { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PD13 periph A Data bit 7 */ - }; - - pinctrl_nand_16bits: nand_16bits-0 { - atmel,pins = - ; /* PD21 periph A Data bit 15 */ - }; - }; - - mmc0 { - pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA15 periph A with pullup */ - }; - - pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { - atmel,pins = - ; /* PA20 periph A with pullup */ - }; - }; - - mmc1 { - pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { - atmel,pins = - ; /* PA11 periph B with pullup */ - }; - - pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { - atmel,pins = - ; /* PA4 periph B with pullup */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx-0 { - atmel,pins = - ; /* PA26 periph B */ - }; - - pinctrl_ssc0_rx: ssc0_rx-0 { - atmel,pins = - ; /* PA29 periph B */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PA13 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PA23 periph B SPI1_SPCK pin */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA31 periph A I2C0 clock */ - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PC1 periph C I2C1 clock */ - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* PB5 periph B I2C2 clock */ - }; - }; - - i2c_gpio0 { - pinctrl_i2c_gpio0: i2c_gpio0-0 { - atmel,pins = - ; /* PA31 gpio multidrive I2C0 clock */ - }; - }; - - i2c_gpio1 { - pinctrl_i2c_gpio1: i2c_gpio1-0 { - atmel,pins = - ; /* PC1 gpio multidrive I2C1 clock */ - }; - }; - - i2c_gpio2 { - pinctrl_i2c_gpio2: i2c_gpio2-0 { - atmel,pins = - ; /* PB5 gpio multidrive I2C2 clock */ - }; - }; - - pwm0 { - pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { - atmel,pins = - ; - }; - - pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { - atmel,pins = - ; - }; - pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { - atmel,pins = - ; - }; - }; - - tcb0 { - pinctrl_tcb0_tclk0: tcb0_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk1: tcb0_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tclk2: tcb0_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa0: tcb0_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa1: tcb0_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tioa2: tcb0_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob0: tcb0_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob1: tcb0_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb0_tiob2: tcb0_tiob2-0 { - atmel,pins = ; - }; - }; - - tcb1 { - pinctrl_tcb1_tclk0: tcb1_tclk0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk1: tcb1_tclk1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tclk2: tcb1_tclk2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa0: tcb1_tioa0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa1: tcb1_tioa1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tioa2: tcb1_tioa2-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob0: tcb1_tiob0-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob1: tcb1_tiob1-0 { - atmel,pins = ; - }; - - pinctrl_tcb1_tiob2: tcb1_tiob2-0 { - atmel,pins = ; - }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <19>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <22>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - }; - }; - - ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc1: mmc@f000c000 { - compatible = "atmel,hsmci"; - reg = <0xf000c000 0x600>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - clocks = <&mci1_clk>; - clock-names = "mci_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&mck>; - clock-names = "usart"; - status = "disabled"; - }; - - usart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x200>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, - <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x200>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@f8014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8014000 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, - <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - i2c2: i2c@f8018000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8018000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&twi2_clk>; - status = "disabled"; - }; - - uart0: serial@f8040000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8040000 0x200>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8044000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8044000 0x200>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - adc0: adc@f804c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9x5-adc"; - reg = <0xf804c000 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-use-external-triggers; - atmel,adc-channels-used = <0xffff>; - atmel,adc-vref = <3300>; - atmel,adc-startup-time = <40>; - atmel,adc-sample-hold-time = <11>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; - }; - - spi0: spi@f0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0000000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi1: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, - <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - usb2: gadget@f803c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9g45-udc"; - reg = <0x00500000 0x80000 - 0xf803c000 0x400>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&utmi>, <&udphs_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - }; - - watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - rtc@fffffeb0 { - compatible = "atmel,at91sam9x5-rtc"; - reg = <0xfffffeb0 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x300>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - clocks = <&pwm_clk>; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe000 0x600 /* PMECC Registers */ - 0xffffe600 0x200 /* PMECC Error Location Registers */ - 0x00108000 0x18000 /* PMECC looup table in ROM code */ - >; - atmel,pmecc-lookup-table-offset = <0x0 0x8000>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 5 GPIO_ACTIVE_HIGH - &pioD 4 GPIO_ACTIVE_HIGH - 0 - >; - status = "disabled"; - }; - - usb0: ohci@00600000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00600000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb1: ehci@00700000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00700000 0x100000>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ - &pioA 31 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio0>; - status = "disabled"; - }; - - i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ - &pioC 1 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio1>; - status = "disabled"; - }; - - i2c-gpio-2 { - compatible = "i2c-gpio"; - gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ - &pioB 5 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio2>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_can.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_can.dtsi deleted file mode 100644 index 8eb2f9c1b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_can.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -/* - * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 - * Ethernet interface. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - pmc: pmc@fffffc00 { - periphck { - can0_clk: can0_clk { - #clock-cells = <0>; - reg = <29>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; - }; - - can0: can@f8000000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8000000 0x300>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&can0_clk>; - clock-names = "can_clk"; - status = "disabled"; - }; - - can1: can@f8004000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8004000 0x300>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&can1_clk>; - clock-names = "can_clk"; - status = "disabled"; - }; - - pinctrl@fffff400 { - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - ; /* CANTX0, conflicts with DTXD */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - ; /* CANTX1, conflicts with TXD1 */ - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_isi.dtsi deleted file mode 100644 index 8fc45ca4d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_isi.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -/* - * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an - * Image Sensor Interface. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* ISI_VSYNC, conflicts with LCDDAT13 */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* ISI_D9, conflicts with LCDDAT9 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* ISI_D11, conflicts with LCDDAT11 */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <25>; - }; - }; - }; - - isi: isi@f8048000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf8048000 0x4000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_lcd.dtsi deleted file mode 100644 index 1629db9dd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_lcd.dtsi +++ /dev/null @@ -1,165 +0,0 @@ -/* - * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an - * LCD controller. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - hlcdc: hlcdc@f8038000 { - compatible = "atmel,at91sam9x5-hlcdc"; - reg = <0xf8038000 0x4000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - pinctrl@fffff400 { - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <25>; - }; - }; - - systemck { - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_macb0.dtsi deleted file mode 100644 index 73d7e3096..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_macb0.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -/* - * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 - * Ethernet interface. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - ; /* PB10 periph A */ - }; - - pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { - atmel,pins = - ; /* PB17 periph A */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <24>; - }; - }; - }; - - macb0: ethernet@f802c000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_macb1.dtsi deleted file mode 100644 index d81980c40..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_macb1.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -/* - * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 - * Ethernet interfaces. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff400 { - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; /* PC31 periph B */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <27>; - }; - }; - }; - - macb1: ethernet@f8030000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf8030000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&macb1_clk>, <&macb1_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_usart3.dtsi deleted file mode 100644 index 43bb5b51c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -/* - * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * 4 USART. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - aliases { - serial4 = &usart3; - }; - - ahb { - apb { - pinctrl@fffff400 { - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* PC23 periph B */ - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - ; /* PC24 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - ; /* PC25 periph B */ - }; - - pinctrl_usart3_sck: usart3_sck-0 { - atmel,pins = - ; /* PC26 periph B */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <8>; - }; - }; - }; - - usart3: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, - <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5cm.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5cm.dtsi deleted file mode 100644 index b098ad8cd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ /dev/null @@ -1,100 +0,0 @@ -/* - * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ - -/ { - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - pinctrl@fffff400 { - 1wire_cm { - pinctrl_1wire_cm: 1wire_cm-0 { - atmel,pins = ; /* PB18 multidrive, conflicts with led */ - }; - }; - }; - - rtc@fffffeb0 { - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; /* Enable PMECC */ - atmel,pmecc-cap = <2>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - uboot@40000 { - label = "u-boot"; - reg = <0x40000 0x80000>; - }; - - ubootenv@c0000 { - label = "U-Boot Env"; - reg = <0xc0000 0x140000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x1f800000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pb18 { - label = "pb18"; - gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - pd21 { - label = "pd21"; - gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; - }; - }; - - 1wire_cm { - compatible = "w1-gpio"; - gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; - linux,open-drain; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_1wire_cm>; - status = "okay"; - }; - -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5dm.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5dm.dtsi deleted file mode 100644 index 34c089fe0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5dm.dtsi +++ /dev/null @@ -1,101 +0,0 @@ -/* - * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module - * - * Copyright (C) 2014 Atmel, - * 2014 Free Electrons - * - * Author: Boris Brezillon - * - * Licensed under GPLv2 or later. - */ - -/ { - ahb { - apb { - i2c0: i2c@f8010000 { - qt1070: keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioA>; - interrupts = <7 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; - }; - - hlcdc: hlcdc@f8038000 { - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - adc0: adc@f804c000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; - }; - - pinctrl@fffff400 { - board { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; - }; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <&bl_reg>; - status = "disabled"; - }; - - bl_reg: backlight_regulator { - compatible = "regulator-fixed"; - regulator-name = "backlight-power-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "disabled"; - }; - - panel: panel { - compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; - backlight = <&backlight>; - power-supply = <&panel_reg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - panel_reg: panel_regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5ek.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9x5ek.dtsi deleted file mode 100644 index 696b8ba06..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ /dev/null @@ -1,165 +0,0 @@ -/* - * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board - * - * Copyright (C) 2012 Atmel, - * 2012 Nicolas Ferre - * - * Licensed under GPLv2 or later. - */ -#include "at91sam9x5cm.dtsi" - -/ { - model = "Atmel AT91SAM9X5-EK"; - compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; - - chosen { - bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; - stdout-path = "serial0:115200n8"; - }; - - ahb { - apb { - mmc0: mmc@f0008000 { - pinctrl-0 = < - &pinctrl_board_mmc0 - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; - }; - }; - - mmc1: mmc@f000c000 { - pinctrl-0 = < - &pinctrl_board_mmc1 - &pinctrl_mmc1_slot0_clk_cmd_dat0 - &pinctrl_mmc1_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; - }; - }; - - dbgu: serial@fffff200 { - status = "okay"; - }; - - usart0: serial@f801c000 { - status = "okay"; - }; - - usb2: gadget@f803c000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_board_usb2>; - atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - i2c0: i2c@f8010000 { - status = "okay"; - - wm8731: wm8731@1a { - compatible = "wm8731"; - reg = <0x1a>; - }; - }; - - adc0: adc@f804c000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; - }; - - pinctrl@fffff400 { - camera_sensor { - pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { - atmel,pins = - ; /* ISI_MCK */ - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_board_mmc0: mmc0-board { - atmel,pins = - ; /* PD15 gpio CD pin pull up and deglitch */ - }; - }; - - mmc1 { - pinctrl_board_mmc1: mmc1-board { - atmel,pins = - ; /* PD14 gpio CD pin pull up and deglitch */ - }; - }; - - usb2 { - pinctrl_board_usb2: usb2-board { - atmel,pins = - ; /* PB16 gpio vbus sense, deglitch */ - }; - }; - }; - - spi0: spi@f0000000 { - status = "okay"; - cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - - ssc0: ssc@f0010000 { - status = "okay"; - }; - }; - - usb0: ohci@00600000 { - status = "okay"; - num-ports = <3>; - atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ - &pioD 19 GPIO_ACTIVE_LOW - &pioD 20 GPIO_ACTIVE_LOW - >; - }; - - usb1: ehci@00700000 { - status = "okay"; - }; - }; - - sound { - compatible = "atmel,sam9x5-wm8731-audio"; - - atmel,model = "wm8731 @ AT91SAM9X5EK"; - - atmel,audio-routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/at91sam9xe.dtsi b/software/linux/kernel/arch/arm/boot/dts/at91sam9xe.dtsi deleted file mode 100644 index 0278f63b2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/at91sam9xe.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC - * - * Copyright (C) 2015 Atmel, - * 2015 Alexandre Belloni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "at91sam9260.dtsi" - -/ { - model = "Atmel AT91SAM9XE family SoC"; - compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; - - sram0: sram@002ff000 { - status = "disabled"; - }; - - sram1: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x4000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/atlas6-evb.dts b/software/linux/kernel/arch/arm/boot/dts/atlas6-evb.dts deleted file mode 100644 index ab042ca8d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/atlas6-evb.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * DTS file for CSR SiRFatlas6 Evaluation Board - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; - -/include/ "atlas6.dtsi" - -/ { - model = "CSR SiRFatlas6 Evaluation Board"; - compatible = "sirf,atlas6-cb", "sirf,atlas6"; - - memory { - reg = <0x00000000 0x20000000>; - }; - - axi { - peri-iobg { - uart@b0060000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - }; - spi@b00d0000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - spi@b0170000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - }; - i2c0: i2c@b00e0000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - lcd@40 { - compatible = "sirf,lcd"; - reg = <0x40>; - }; - }; - - }; - disp-iobg { - lcd@90010000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_24pins_a>; - }; - }; - }; - display: display@0 { - panels { - panel0: panel@0 { - panel-name = "Innolux TFT"; - hactive = <800>; - vactive = <480>; - left_margin = <20>; - right_margin = <234>; - upper_margin = <3>; - lower_margin = <41>; - hsync_len = <3>; - vsync_len = <2>; - pixclock = <33264000>; - sync = <3>; - timing = <0x88>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/atlas6.dtsi b/software/linux/kernel/arch/arm/boot/dts/atlas6.dtsi deleted file mode 100644 index 295986674..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/atlas6.dtsi +++ /dev/null @@ -1,802 +0,0 @@ -/* - * DTS file for CSR SiRFatlas6 SoC - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -/include/ "skeleton.dtsi" -/ { - compatible = "sirf,atlas6"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - clocks = <&clks 12>; - operating-points = < - /* kHz uV */ - 200000 1025000 - 400000 1025000 - 600000 1050000 - 800000 1100000 - >; - clock-latency = <150000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <29>; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clks: clock-controller@88000000 { - compatible = "sirf,atlas6-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - #clock-cells = <1>; - }; - - rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - - cphifbg@88030000 { - compatible = "sirf,prima2-cphifbg"; - reg = <0x88030000 0x1000>; - clocks = <&clks 42>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x2000>; - interrupts = <27>; - clocks = <&clks 5>; - }; - - memc-monitor { - compatible = "sirf,prima2-memcmon"; - reg = <0x90002000 0x200>; - interrupts = <4>; - clocks = <&clks 32>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - lcd@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - clocks = <&clks 34>; - display=<&display>; - /* later transfer to pwm */ - bl-gpio = <&gpio 7 0>; - default-panel = <&panel0>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx510"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - clocks = <&clks 32>; - }; - }; - - graphics2d-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - ble@a0000000 { - compatible = "sirf,atlas6-ble"; - reg = <0xa0000000 0x2000>; - interrupts = <5>; - clocks = <&clks 33>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - resets = <&rstc 1>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - clocks = <&clks 9>; - resets = <&rstc 2>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - clocks = <&clks 8>; - resets = <&rstc 0>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>, - <0x56000000 0x56000000 0x1b00000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - clocks = <&clks 11>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - clocks = <&clks 26>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - clocks = <&clks 27>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x1000>; - interrupts = <17>; - fifosize = <128>; - clocks = <&clks 13>; - dmas = <&dmac1 5>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x1000>; - interrupts = <18>; - fifosize = <32>; - clocks = <&clks 14>; - dma-names = "no-rx", "no-tx"; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x1000>; - interrupts = <19>; - fifosize = <128>; - clocks = <&clks 15>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - fifosize = <128>; - clocks = <&clks 28>; - dmas = <&dmac1 1>, <&dmac1 2>; - dma-names = "rx", "tx"; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - fifosize = <128>; - clocks = <&clks 29>; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "rx", "tx"; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - clocks = <&clks 24>; - #dma-cells = <1>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - clocks = <&clks 25>; - #dma-cells = <1>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - clocks = <&clks 31>; - interrupts = <14>; - sirf,vip-dma-rx-channel = <16>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 19>; - resets = <&rstc 26>; - status = "disabled"; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac0 12>, - <&dmac0 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 20>; - resets = <&rstc 27>; - status = "disabled"; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 17>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 18>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - clocks = <&clks 16>; - }; - - gpio: pinctrl@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas6-pinctrl"; - reg = <0xb0120000 0x10000>; - interrupts = <43 44 45 46 47>; - gpio-controller; - interrupt-controller; - - lcd_16pins_a: lcd0@0 { - lcd { - sirf,pins = "lcd_16bitsgrp"; - sirf,function = "lcd_16bits"; - }; - }; - lcd_18pins_a: lcd0@1 { - lcd { - sirf,pins = "lcd_18bitsgrp"; - sirf,function = "lcd_18bits"; - }; - }; - lcd_24pins_a: lcd0@2 { - lcd { - sirf,pins = "lcd_24bitsgrp"; - sirf,function = "lcd_24bits"; - }; - }; - lcdrom_pins_a: lcdrom0@0 { - lcd { - sirf,pins = "lcdromgrp"; - sirf,function = "lcdrom"; - }; - }; - uart0_pins_a: uart0@0 { - uart { - sirf,pins = "uart0grp"; - sirf,function = "uart0"; - }; - }; - uart0_noflow_pins_a: uart0@1 { - uart { - sirf,pins = "uart0_nostreamctrlgrp"; - sirf,function = "uart0_nostreamctrl"; - }; - }; - uart1_pins_a: uart1@0 { - uart { - sirf,pins = "uart1grp"; - sirf,function = "uart1"; - }; - }; - uart2_pins_a: uart2@0 { - uart { - sirf,pins = "uart2grp"; - sirf,function = "uart2"; - }; - }; - uart2_noflow_pins_a: uart2@1 { - uart { - sirf,pins = "uart2_nostreamctrlgrp"; - sirf,function = "uart2_nostreamctrl"; - }; - }; - spi0_pins_a: spi0@0 { - spi { - sirf,pins = "spi0grp"; - sirf,function = "spi0"; - }; - }; - spi1_pins_a: spi1@0 { - spi { - sirf,pins = "spi1grp"; - sirf,function = "spi1"; - }; - }; - i2c0_pins_a: i2c0@0 { - i2c { - sirf,pins = "i2c0grp"; - sirf,function = "i2c0"; - }; - }; - i2c1_pins_a: i2c1@0 { - i2c { - sirf,pins = "i2c1grp"; - sirf,function = "i2c1"; - }; - }; - pwm0_pins_a: pwm0@0 { - pwm { - sirf,pins = "pwm0grp"; - sirf,function = "pwm0"; - }; - }; - pwm1_pins_a: pwm1@0 { - pwm { - sirf,pins = "pwm1grp"; - sirf,function = "pwm1"; - }; - }; - pwm2_pins_a: pwm2@0 { - pwm { - sirf,pins = "pwm2grp"; - sirf,function = "pwm2"; - }; - }; - pwm3_pins_a: pwm3@0 { - pwm { - sirf,pins = "pwm3grp"; - sirf,function = "pwm3"; - }; - }; - pwm4_pins_a: pwm4@0 { - pwm { - sirf,pins = "pwm4grp"; - sirf,function = "pwm4"; - }; - }; - gps_pins_a: gps@0 { - gps { - sirf,pins = "gpsgrp"; - sirf,function = "gps"; - }; - }; - vip_pins_a: vip@0 { - vip { - sirf,pins = "vipgrp"; - sirf,function = "vip"; - }; - }; - sdmmc0_pins_a: sdmmc0@0 { - sdmmc0 { - sirf,pins = "sdmmc0grp"; - sirf,function = "sdmmc0"; - }; - }; - sdmmc1_pins_a: sdmmc1@0 { - sdmmc1 { - sirf,pins = "sdmmc1grp"; - sirf,function = "sdmmc1"; - }; - }; - sdmmc2_pins_a: sdmmc2@0 { - sdmmc2 { - sirf,pins = "sdmmc2grp"; - sirf,function = "sdmmc2"; - }; - }; - sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { - sdmmc2_nowp { - sirf,pins = "sdmmc2_nowpgrp"; - sirf,function = "sdmmc2_nowp"; - }; - }; - sdmmc3_pins_a: sdmmc3@0 { - sdmmc3 { - sirf,pins = "sdmmc3grp"; - sirf,function = "sdmmc3"; - }; - }; - sdmmc5_pins_a: sdmmc5@0 { - sdmmc5 { - sirf,pins = "sdmmc5grp"; - sirf,function = "sdmmc5"; - }; - }; - i2s_mclk_pins_a: i2s_mclk@0 { - i2s_mclk { - sirf,pins = "i2smclkgrp"; - sirf,function = "i2s_mclk"; - }; - }; - i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { - i2s_ext_clk_input { - sirf,pins = "i2s_ext_clk_inputgrp"; - sirf,function = "i2s_ext_clk_input"; - }; - }; - i2s_pins_a: i2s@0 { - i2s { - sirf,pins = "i2sgrp"; - sirf,function = "i2s"; - }; - }; - i2s_no_din_pins_a: i2s_no_din@0 { - i2s_no_din { - sirf,pins = "i2s_no_dingrp"; - sirf,function = "i2s_no_din"; - }; - }; - i2s_6chn_pins_a: i2s_6chn@0 { - i2s_6chn { - sirf,pins = "i2s_6chngrp"; - sirf,function = "i2s_6chn"; - }; - }; - ac97_pins_a: ac97@0 { - ac97 { - sirf,pins = "ac97grp"; - sirf,function = "ac97"; - }; - }; - nand_pins_a: nand@0 { - nand { - sirf,pins = "nandgrp"; - sirf,function = "nand"; - }; - }; - usp0_pins_a: usp0@0 { - usp0 { - sirf,pins = "usp0grp"; - sirf,function = "usp0"; - }; - }; - usp0_uart_nostreamctrl_pins_a: usp0@1 { - usp0 { - sirf,pins = "usp0_uart_nostreamctrl_grp"; - sirf,function = "usp0_uart_nostreamctrl"; - }; - }; - usp0_only_utfs_pins_a: usp0@2 { - usp0 { - sirf,pins = "usp0_only_utfs_grp"; - sirf,function = "usp0_only_utfs"; - }; - }; - usp0_only_urfs_pins_a: usp0@3 { - usp0 { - sirf,pins = "usp0_only_urfs_grp"; - sirf,function = "usp0_only_urfs"; - }; - }; - usp1_pins_a: usp1@0 { - usp1 { - sirf,pins = "usp1grp"; - sirf,function = "usp1"; - }; - }; - usp1_uart_nostreamctrl_pins_a: usp1@1 { - usp1 { - sirf,pins = "usp1_uart_nostreamctrl_grp"; - sirf,function = "usp1_uart_nostreamctrl"; - }; - }; - usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { - usb0_upli_drvbus { - sirf,pins = "usb0_upli_drvbusgrp"; - sirf,function = "usb0_upli_drvbus"; - }; - }; - usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { - usb1_utmi_drvbus { - sirf,pins = "usb1_utmi_drvbusgrp"; - sirf,function = "usb1_utmi_drvbus"; - }; - }; - usb1_dp_dn_pins_a: usb1_dp_dn@0 { - usb1_dp_dn { - sirf,pins = "usb1_dp_dngrp"; - sirf,function = "usb1_dp_dn"; - }; - }; - uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { - uart1_route_io_usb1 { - sirf,pins = "uart1_route_io_usb1grp"; - sirf,function = "uart1_route_io_usb1"; - }; - }; - warm_rst_pins_a: warm_rst@0 { - warm_rst { - sirf,pins = "warm_rstgrp"; - sirf,function = "warm_rst"; - }; - }; - pulse_count_pins_a: pulse_count@0 { - pulse_count { - sirf,pins = "pulse_countgrp"; - sirf,function = "pulse_count"; - }; - }; - cko0_pins_a: cko0@0 { - cko0 { - sirf,pins = "cko0grp"; - sirf,function = "cko0"; - }; - }; - cko1_pins_a: cko1@0 { - cko1 { - sirf,pins = "cko1grp"; - sirf,function = "cko1"; - }; - }; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - clocks = <&clks 21>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - clocks = <&clks 22>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - clocks = <&clks 23>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - bus-width = <8>; - clocks = <&clks 36>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 36>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 37>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 37>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 38>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - minigpsrtc@2000 { - compatible = "sirf,prima2-minigpsrtc"; - reg = <0x2000 0x1000>; - interrupts = <54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - clocks = <&clks 40>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - clocks = <&clks 41>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - clocks = <&clks 7>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/atlas7-evb.dts b/software/linux/kernel/arch/arm/boot/dts/atlas7-evb.dts deleted file mode 100644 index 1e9cd1a85..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/atlas7-evb.dts +++ /dev/null @@ -1,128 +0,0 @@ -/* - * DTS file for CSR SiRFatlas7 Evaluation Board - * - * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; - -/include/ "atlas7.dtsi" - -#include -#include - -/ { - model = "CSR SiRFatlas7 Evaluation Board"; - compatible = "sirf,atlas7-cb", "sirf,atlas7"; - - chosen { - bootargs = "console=ttySiRF1,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vpp_reserved: vpp_mem@5e800000 { - compatible = "sirf,reserved-memory"; - reg = <0x5e800000 0x800000>; - }; - - nanddisk_reserved: nanddisk@46000000 { - reg = <0x46000000 0x200000>; - no-map; - }; - }; - - - noc { - mediam { - nand@17050000 { - memory-region = <&nanddisk_reserved>; - }; - }; - - gnssm { - spi1: spi@18200000 { - status = "okay"; - spiflash: macronix@0{ - status = "okay"; - compatible = "macronix,mx25l6405d"; - reg = <0>; - spi-max-frequency = <37500000>; - spi-cpha; - spi-cpol; - #address-cells = <1>; - #size-cells = <1>; - partitions@0 { - label = "myspiboot"; - reg = <0x0 0x800000>; - }; - }; - }; - }; - - btm { - uart6: uart@11000000 { - status = "okay"; - sirf,uart-has-rtscts; - }; - }; - - disp-iobg { - vpp@13110000 { - memory-region = <&vpp_reserved>; - }; - }; - - display0: display@0 { - compatible = "lvds-panel"; - source = "lvds.0"; - - bl-gpios = <&gpio_1 63 0>; - data-lines = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <220>; - hback-porch = <100>; - hsync-len = <1>; - vback-porch = <10>; - vfront-porch = <25>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - rearview_key { - label = "rearview key"; - linux,code = ; - gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>; - debounce_interval = <100>; - }; - }; - - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/atlas7.dtsi b/software/linux/kernel/arch/arm/boot/dts/atlas7.dtsi deleted file mode 100644 index 83449b33d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/atlas7.dtsi +++ /dev/null @@ -1,1957 +0,0 @@ -/* - * DTS file for CSR SiRFatlas7 SoC - * - * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -/include/ "skeleton.dtsi" -/ { - compatible = "sirf,atlas7"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial9 = &usp2; - spi1 = &spi1; - spi2 = &usp1; - spi3 = &usp2; - spi4 = &usp3; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - }; - }; - - clocks { - xinw { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xinw"; - }; - xin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "xin"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 29 4>, <0 82 4>; - }; - - noc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10000000 0x10000000 0xc0000000>; - - gic: interrupt-controller@10301000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x10301000 0x1000>, - <0x10302000 0x0100>; - }; - - pmu_regulator: pmu_regulator@10E30020 { - compatible = "sirf,atlas7-pmu-ldo"; - reg = <0x10E30020 0x4>; - ldo: ldo { - regulator-name = "ldo"; - }; - }; - - atlas7_codec: atlas7_codec@10E30000 { - #sound-dai-cells = <0>; - compatible = "sirf,atlas7-codec"; - reg = <0x10E30000 0x400>; - clocks = <&car 62>; - ldo-supply = <&ldo>; - }; - - atlas7_iacc: atlas7_iacc@10D01000 { - #sound-dai-cells = <0>; - compatible = "sirf,atlas7-iacc"; - reg = <0x10D01000 0x100>; - dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>, - <&dmac3 3>, <&dmac3 9>; - dma-names = "rx", "tx0", "tx1", "tx2", "tx3"; - clocks = <&car 62>; - }; - - ipc@13240000 { - compatible = "sirf,atlas7-ipc"; - ranges = <0x13240000 0x13240000 0x00010000>; - #address-cells = <1>; - #size-cells = <1>; - - hwspinlock { - compatible = "sirf,hwspinlock"; - reg = <0x13240000 0x00010000>; - - num-spinlocks = <30>; - }; - - ns_m3_rproc@0 { - compatible = "sirf,ns2m30-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 123 0>; - }; - - ns_m3_rproc@1 { - compatible = "sirf,ns2m31-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 126 0>; - }; - - ns_kal_rproc@0 { - compatible = "sirf,ns2kal0-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 124 0>; - }; - - ns_kal_rproc@1 { - compatible = "sirf,ns2kal1-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 127 0>; - }; - }; - - pinctrl: ioc@18880000 { - compatible = "sirf,atlas7-ioc"; - reg = <0x18880000 0x1000>, - <0x10E40000 0x1000>; - - audio_ac97_pmx: audio_ac97@0 { - audio_ac97 { - groups = "audio_ac97_grp"; - function = "audio_ac97"; - }; - }; - - audio_func_dbg_pmx: audio_func_dbg@0 { - audio_func_dbg { - groups = "audio_func_dbg_grp"; - function = "audio_func_dbg"; - }; - }; - - audio_i2s_pmx: audio_i2s@0 { - audio_i2s { - groups = "audio_i2s_grp"; - function = "audio_i2s"; - }; - }; - - audio_i2s_2ch_pmx: audio_i2s_2ch@0 { - audio_i2s_2ch { - groups = "audio_i2s_2ch_grp"; - function = "audio_i2s_2ch"; - }; - }; - - audio_i2s_extclk_pmx: audio_i2s_extclk@0 { - audio_i2s_extclk { - groups = "audio_i2s_extclk_grp"; - function = "audio_i2s_extclk"; - }; - }; - - audio_uart0_pmx: audio_uart0@0 { - audio_uart0 { - groups = "audio_uart0_grp"; - function = "audio_uart0"; - }; - }; - - audio_uart1_pmx: audio_uart1@0 { - audio_uart1 { - groups = "audio_uart1_grp"; - function = "audio_uart1"; - }; - }; - - audio_uart2_pmx0: audio_uart2@0 { - audio_uart2_0 { - groups = "audio_uart2_grp0"; - function = "audio_uart2_m0"; - }; - }; - - audio_uart2_pmx1: audio_uart2@1 { - audio_uart2_1 { - groups = "audio_uart2_grp1"; - function = "audio_uart2_m1"; - }; - }; - - c_can_trnsvr_pmx: c_can_trnsvr@0 { - c_can_trnsvr { - groups = "c_can_trnsvr_grp"; - function = "c_can_trnsvr"; - }; - }; - - c0_can_pmx0: c0_can@0 { - c0_can_0 { - groups = "c0_can_grp0"; - function = "c0_can_m0"; - }; - }; - - c0_can_pmx1: c0_can@1 { - c0_can_1 { - groups = "c0_can_grp1"; - function = "c0_can_m1"; - }; - }; - - c1_can_pmx0: c1_can@0 { - c1_can_0 { - groups = "c1_can_grp0"; - function = "c1_can_m0"; - }; - }; - - c1_can_pmx1: c1_can@1 { - c1_can_1 { - groups = "c1_can_grp1"; - function = "c1_can_m1"; - }; - }; - - c1_can_pmx2: c1_can@2 { - c1_can_2 { - groups = "c1_can_grp2"; - function = "c1_can_m2"; - }; - }; - - ca_audio_lpc_pmx: ca_audio_lpc@0 { - ca_audio_lpc { - groups = "ca_audio_lpc_grp"; - function = "ca_audio_lpc"; - }; - }; - - ca_bt_lpc_pmx: ca_bt_lpc@0 { - ca_bt_lpc { - groups = "ca_bt_lpc_grp"; - function = "ca_bt_lpc"; - }; - }; - - ca_coex_pmx: ca_coex@0 { - ca_coex { - groups = "ca_coex_grp"; - function = "ca_coex"; - }; - }; - - ca_curator_lpc_pmx: ca_curator_lpc@0 { - ca_curator_lpc { - groups = "ca_curator_lpc_grp"; - function = "ca_curator_lpc"; - }; - }; - - ca_pcm_debug_pmx: ca_pcm_debug@0 { - ca_pcm_debug { - groups = "ca_pcm_debug_grp"; - function = "ca_pcm_debug"; - }; - }; - - ca_pio_pmx: ca_pio@0 { - ca_pio { - groups = "ca_pio_grp"; - function = "ca_pio"; - }; - }; - - ca_sdio_debug_pmx: ca_sdio_debug@0 { - ca_sdio_debug { - groups = "ca_sdio_debug_grp"; - function = "ca_sdio_debug"; - }; - }; - - ca_spi_pmx: ca_spi@0 { - ca_spi { - groups = "ca_spi_grp"; - function = "ca_spi"; - }; - }; - - ca_trb_pmx: ca_trb@0 { - ca_trb { - groups = "ca_trb_grp"; - function = "ca_trb"; - }; - }; - - ca_uart_debug_pmx: ca_uart_debug@0 { - ca_uart_debug { - groups = "ca_uart_debug_grp"; - function = "ca_uart_debug"; - }; - }; - - clkc_pmx0: clkc@0 { - clkc_0 { - groups = "clkc_grp0"; - function = "clkc_m0"; - }; - }; - - clkc_pmx1: clkc@1 { - clkc_1 { - groups = "clkc_grp1"; - function = "clkc_m1"; - }; - }; - - gn_gnss_i2c_pmx: gn_gnss_i2c@0 { - gn_gnss_i2c { - groups = "gn_gnss_i2c_grp"; - function = "gn_gnss_i2c"; - }; - }; - - gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 { - gn_gnss_uart_nopause { - groups = "gn_gnss_uart_nopause_grp"; - function = "gn_gnss_uart_nopause"; - }; - }; - - gn_gnss_uart_pmx: gn_gnss_uart@0 { - gn_gnss_uart { - groups = "gn_gnss_uart_grp"; - function = "gn_gnss_uart"; - }; - }; - - gn_trg_spi_pmx0: gn_trg_spi@0 { - gn_trg_spi_0 { - groups = "gn_trg_spi_grp0"; - function = "gn_trg_spi_m0"; - }; - }; - - gn_trg_spi_pmx1: gn_trg_spi@1 { - gn_trg_spi_1 { - groups = "gn_trg_spi_grp1"; - function = "gn_trg_spi_m1"; - }; - }; - - cvbs_dbg_pmx: cvbs_dbg@0 { - cvbs_dbg { - groups = "cvbs_dbg_grp"; - function = "cvbs_dbg"; - }; - }; - - cvbs_dbg_test_pmx0: cvbs_dbg_test@0 { - cvbs_dbg_test_0 { - groups = "cvbs_dbg_test_grp0"; - function = "cvbs_dbg_test_m0"; - }; - }; - - cvbs_dbg_test_pmx1: cvbs_dbg_test@1 { - cvbs_dbg_test_1 { - groups = "cvbs_dbg_test_grp1"; - function = "cvbs_dbg_test_m1"; - }; - }; - - cvbs_dbg_test_pmx2: cvbs_dbg_test@2 { - cvbs_dbg_test_2 { - groups = "cvbs_dbg_test_grp2"; - function = "cvbs_dbg_test_m2"; - }; - }; - - cvbs_dbg_test_pmx3: cvbs_dbg_test@3 { - cvbs_dbg_test_3 { - groups = "cvbs_dbg_test_grp3"; - function = "cvbs_dbg_test_m3"; - }; - }; - - cvbs_dbg_test_pmx4: cvbs_dbg_test@4 { - cvbs_dbg_test_4 { - groups = "cvbs_dbg_test_grp4"; - function = "cvbs_dbg_test_m4"; - }; - }; - - cvbs_dbg_test_pmx5: cvbs_dbg_test@5 { - cvbs_dbg_test_5 { - groups = "cvbs_dbg_test_grp5"; - function = "cvbs_dbg_test_m5"; - }; - }; - - cvbs_dbg_test_pmx6: cvbs_dbg_test@6 { - cvbs_dbg_test_6 { - groups = "cvbs_dbg_test_grp6"; - function = "cvbs_dbg_test_m6"; - }; - }; - - cvbs_dbg_test_pmx7: cvbs_dbg_test@7 { - cvbs_dbg_test_7 { - groups = "cvbs_dbg_test_grp7"; - function = "cvbs_dbg_test_m7"; - }; - }; - - cvbs_dbg_test_pmx8: cvbs_dbg_test@8 { - cvbs_dbg_test_8 { - groups = "cvbs_dbg_test_grp8"; - function = "cvbs_dbg_test_m8"; - }; - }; - - cvbs_dbg_test_pmx9: cvbs_dbg_test@9 { - cvbs_dbg_test_9 { - groups = "cvbs_dbg_test_grp9"; - function = "cvbs_dbg_test_m9"; - }; - }; - - cvbs_dbg_test_pmx10: cvbs_dbg_test@10 { - cvbs_dbg_test_10 { - groups = "cvbs_dbg_test_grp10"; - function = "cvbs_dbg_test_m10"; - }; - }; - - cvbs_dbg_test_pmx11: cvbs_dbg_test@11 { - cvbs_dbg_test_11 { - groups = "cvbs_dbg_test_grp11"; - function = "cvbs_dbg_test_m11"; - }; - }; - - cvbs_dbg_test_pmx12: cvbs_dbg_test@12 { - cvbs_dbg_test_12 { - groups = "cvbs_dbg_test_grp12"; - function = "cvbs_dbg_test_m12"; - }; - }; - - cvbs_dbg_test_pmx13: cvbs_dbg_test@13 { - cvbs_dbg_test_13 { - groups = "cvbs_dbg_test_grp13"; - function = "cvbs_dbg_test_m13"; - }; - }; - - cvbs_dbg_test_pmx14: cvbs_dbg_test@14 { - cvbs_dbg_test_14 { - groups = "cvbs_dbg_test_grp14"; - function = "cvbs_dbg_test_m14"; - }; - }; - - cvbs_dbg_test_pmx15: cvbs_dbg_test@15 { - cvbs_dbg_test_15 { - groups = "cvbs_dbg_test_grp15"; - function = "cvbs_dbg_test_m15"; - }; - }; - - gn_gnss_power_pmx: gn_gnss_power@0 { - gn_gnss_power { - groups = "gn_gnss_power_grp"; - function = "gn_gnss_power"; - }; - }; - - gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 { - gn_gnss_sw_status { - groups = "gn_gnss_sw_status_grp"; - function = "gn_gnss_sw_status"; - }; - }; - - gn_gnss_eclk_pmx: gn_gnss_eclk@0 { - gn_gnss_eclk { - groups = "gn_gnss_eclk_grp"; - function = "gn_gnss_eclk"; - }; - }; - - gn_gnss_irq1_pmx0: gn_gnss_irq1@0 { - gn_gnss_irq1_0 { - groups = "gn_gnss_irq1_grp0"; - function = "gn_gnss_irq1_m0"; - }; - }; - - gn_gnss_irq2_pmx0: gn_gnss_irq2@0 { - gn_gnss_irq2_0 { - groups = "gn_gnss_irq2_grp0"; - function = "gn_gnss_irq2_m0"; - }; - }; - - gn_gnss_tm_pmx: gn_gnss_tm@0 { - gn_gnss_tm { - groups = "gn_gnss_tm_grp"; - function = "gn_gnss_tm"; - }; - }; - - gn_gnss_tsync_pmx: gn_gnss_tsync@0 { - gn_gnss_tsync { - groups = "gn_gnss_tsync_grp"; - function = "gn_gnss_tsync"; - }; - }; - - gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 { - gn_io_gnsssys_sw_cfg { - groups = "gn_io_gnsssys_sw_cfg_grp"; - function = "gn_io_gnsssys_sw_cfg"; - }; - }; - - gn_trg_pmx0: gn_trg@0 { - gn_trg_0 { - groups = "gn_trg_grp0"; - function = "gn_trg_m0"; - }; - }; - - gn_trg_pmx1: gn_trg@1 { - gn_trg_1 { - groups = "gn_trg_grp1"; - function = "gn_trg_m1"; - }; - }; - - gn_trg_shutdown_pmx0: gn_trg_shutdown@0 { - gn_trg_shutdown_0 { - groups = "gn_trg_shutdown_grp0"; - function = "gn_trg_shutdown_m0"; - }; - }; - - gn_trg_shutdown_pmx1: gn_trg_shutdown@1 { - gn_trg_shutdown_1 { - groups = "gn_trg_shutdown_grp1"; - function = "gn_trg_shutdown_m1"; - }; - }; - - gn_trg_shutdown_pmx2: gn_trg_shutdown@2 { - gn_trg_shutdown_2 { - groups = "gn_trg_shutdown_grp2"; - function = "gn_trg_shutdown_m2"; - }; - }; - - gn_trg_shutdown_pmx3: gn_trg_shutdown@3 { - gn_trg_shutdown_3 { - groups = "gn_trg_shutdown_grp3"; - function = "gn_trg_shutdown_m3"; - }; - }; - - i2c0_pmx: i2c0@0 { - i2c0 { - groups = "i2c0_grp"; - function = "i2c0"; - }; - }; - - i2c1_pmx: i2c1@0 { - i2c1 { - groups = "i2c1_grp"; - function = "i2c1"; - }; - }; - - jtag_pmx0: jtag@0 { - jtag_0 { - groups = "jtag_grp0"; - function = "jtag_m0"; - }; - }; - - ks_kas_spi_pmx0: ks_kas_spi@0 { - ks_kas_spi_0 { - groups = "ks_kas_spi_grp0"; - function = "ks_kas_spi_m0"; - }; - }; - - ld_ldd_pmx: ld_ldd@0 { - ld_ldd { - groups = "ld_ldd_grp"; - function = "ld_ldd"; - }; - }; - - ld_ldd_16bit_pmx: ld_ldd_16bit@0 { - ld_ldd_16bit { - groups = "ld_ldd_16bit_grp"; - function = "ld_ldd_16bit"; - }; - }; - - ld_ldd_fck_pmx: ld_ldd_fck@0 { - ld_ldd_fck { - groups = "ld_ldd_fck_grp"; - function = "ld_ldd_fck"; - }; - }; - - ld_ldd_lck_pmx: ld_ldd_lck@0 { - ld_ldd_lck { - groups = "ld_ldd_lck_grp"; - function = "ld_ldd_lck"; - }; - }; - - lr_lcdrom_pmx: lr_lcdrom@0 { - lr_lcdrom { - groups = "lr_lcdrom_grp"; - function = "lr_lcdrom"; - }; - }; - - lvds_analog_pmx: lvds_analog@0 { - lvds_analog { - groups = "lvds_analog_grp"; - function = "lvds_analog"; - }; - }; - - nd_df_pmx: nd_df@0 { - nd_df { - groups = "nd_df_grp"; - function = "nd_df"; - }; - }; - - nd_df_nowp_pmx: nd_df_nowp@0 { - nd_df_nowp { - groups = "nd_df_nowp_grp"; - function = "nd_df_nowp"; - }; - }; - - ps_pmx: ps@0 { - ps { - groups = "ps_grp"; - function = "ps"; - }; - }; - - pwc_core_on_pmx: pwc_core_on@0 { - pwc_core_on { - groups = "pwc_core_on_grp"; - function = "pwc_core_on"; - }; - }; - - pwc_ext_on_pmx: pwc_ext_on@0 { - pwc_ext_on { - groups = "pwc_ext_on_grp"; - function = "pwc_ext_on"; - }; - }; - - pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 { - pwc_gpio3_clk { - groups = "pwc_gpio3_clk_grp"; - function = "pwc_gpio3_clk"; - }; - }; - - pwc_io_on_pmx: pwc_io_on@0 { - pwc_io_on { - groups = "pwc_io_on_grp"; - function = "pwc_io_on"; - }; - }; - - pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 { - pwc_lowbatt_b_0 { - groups = "pwc_lowbatt_b_grp0"; - function = "pwc_lowbatt_b_m0"; - }; - }; - - pwc_mem_on_pmx: pwc_mem_on@0 { - pwc_mem_on { - groups = "pwc_mem_on_grp"; - function = "pwc_mem_on"; - }; - }; - - pwc_on_key_b_pmx0: pwc_on_key_b@0 { - pwc_on_key_b_0 { - groups = "pwc_on_key_b_grp0"; - function = "pwc_on_key_b_m0"; - }; - }; - - pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 { - pwc_wakeup_src0 { - groups = "pwc_wakeup_src0_grp"; - function = "pwc_wakeup_src0"; - }; - }; - - pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 { - pwc_wakeup_src1 { - groups = "pwc_wakeup_src1_grp"; - function = "pwc_wakeup_src1"; - }; - }; - - pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 { - pwc_wakeup_src2 { - groups = "pwc_wakeup_src2_grp"; - function = "pwc_wakeup_src2"; - }; - }; - - pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 { - pwc_wakeup_src3 { - groups = "pwc_wakeup_src3_grp"; - function = "pwc_wakeup_src3"; - }; - }; - - pw_cko0_pmx0: pw_cko0@0 { - pw_cko0_0 { - groups = "pw_cko0_grp0"; - function = "pw_cko0_m0"; - }; - }; - - pw_cko0_pmx1: pw_cko0@1 { - pw_cko0_1 { - groups = "pw_cko0_grp1"; - function = "pw_cko0_m1"; - }; - }; - - pw_cko0_pmx2: pw_cko0@2 { - pw_cko0_2 { - groups = "pw_cko0_grp2"; - function = "pw_cko0_m2"; - }; - }; - - pw_cko1_pmx0: pw_cko1@0 { - pw_cko1_0 { - groups = "pw_cko1_grp0"; - function = "pw_cko1_m0"; - }; - }; - - pw_cko1_pmx1: pw_cko1@1 { - pw_cko1_1 { - groups = "pw_cko1_grp1"; - function = "pw_cko1_m1"; - }; - }; - - pw_i2s01_clk_pmx0: pw_i2s01_clk@0 { - pw_i2s01_clk_0 { - groups = "pw_i2s01_clk_grp0"; - function = "pw_i2s01_clk_m0"; - }; - }; - - pw_i2s01_clk_pmx1: pw_i2s01_clk@1 { - pw_i2s01_clk_1 { - groups = "pw_i2s01_clk_grp1"; - function = "pw_i2s01_clk_m1"; - }; - }; - - pw_pwm0_pmx: pw_pwm0@0 { - pw_pwm0 { - groups = "pw_pwm0_grp"; - function = "pw_pwm0"; - }; - }; - - pw_pwm1_pmx: pw_pwm1@0 { - pw_pwm1 { - groups = "pw_pwm1_grp"; - function = "pw_pwm1"; - }; - }; - - pw_pwm2_pmx0: pw_pwm2@0 { - pw_pwm2_0 { - groups = "pw_pwm2_grp0"; - function = "pw_pwm2_m0"; - }; - }; - - pw_pwm2_pmx1: pw_pwm2@1 { - pw_pwm2_1 { - groups = "pw_pwm2_grp1"; - function = "pw_pwm2_m1"; - }; - }; - - pw_pwm3_pmx0: pw_pwm3@0 { - pw_pwm3_0 { - groups = "pw_pwm3_grp0"; - function = "pw_pwm3_m0"; - }; - }; - - pw_pwm3_pmx1: pw_pwm3@1 { - pw_pwm3_1 { - groups = "pw_pwm3_grp1"; - function = "pw_pwm3_m1"; - }; - }; - - pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 { - pw_pwm_cpu_vol_0 { - groups = "pw_pwm_cpu_vol_grp0"; - function = "pw_pwm_cpu_vol_m0"; - }; - }; - - pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 { - pw_pwm_cpu_vol_1 { - groups = "pw_pwm_cpu_vol_grp1"; - function = "pw_pwm_cpu_vol_m1"; - }; - }; - - pw_backlight_pmx0: pw_backlight@0 { - pw_backlight_0 { - groups = "pw_backlight_grp0"; - function = "pw_backlight_m0"; - }; - }; - - pw_backlight_pmx1: pw_backlight@1 { - pw_backlight_1 { - groups = "pw_backlight_grp1"; - function = "pw_backlight_m1"; - }; - }; - - rg_eth_mac_pmx: rg_eth_mac@0 { - rg_eth_mac { - groups = "rg_eth_mac_grp"; - function = "rg_eth_mac"; - }; - }; - - rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 { - rg_gmac_phy_intr_n { - groups = "rg_gmac_phy_intr_n_grp"; - function = "rg_gmac_phy_intr_n"; - }; - }; - - rg_rgmii_mac_pmx: rg_rgmii_mac@0 { - rg_rgmii_mac { - groups = "rg_rgmii_mac_grp"; - function = "rg_rgmii_mac"; - }; - }; - - rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 { - rg_rgmii_phy_ref_clk_0 { - groups = - "rg_rgmii_phy_ref_clk_grp0"; - function = - "rg_rgmii_phy_ref_clk_m0"; - }; - }; - - rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 { - rg_rgmii_phy_ref_clk_1 { - groups = - "rg_rgmii_phy_ref_clk_grp1"; - function = - "rg_rgmii_phy_ref_clk_m1"; - }; - }; - - sd0_pmx: sd0@0 { - sd0 { - groups = "sd0_grp"; - function = "sd0"; - }; - }; - - sd0_4bit_pmx: sd0_4bit@0 { - sd0_4bit { - groups = "sd0_4bit_grp"; - function = "sd0_4bit"; - }; - }; - - sd1_pmx: sd1@0 { - sd1 { - groups = "sd1_grp"; - function = "sd1"; - }; - }; - - sd1_4bit_pmx0: sd1_4bit@0 { - sd1_4bit_0 { - groups = "sd1_4bit_grp0"; - function = "sd1_4bit_m0"; - }; - }; - - sd1_4bit_pmx1: sd1_4bit@1 { - sd1_4bit_1 { - groups = "sd1_4bit_grp1"; - function = "sd1_4bit_m1"; - }; - }; - - sd2_pmx0: sd2@0 { - sd2_0 { - groups = "sd2_grp0"; - function = "sd2_m0"; - }; - }; - - sd2_no_cdb_pmx0: sd2_no_cdb@0 { - sd2_no_cdb_0 { - groups = "sd2_no_cdb_grp0"; - function = "sd2_no_cdb_m0"; - }; - }; - - sd3_pmx: sd3@0 { - sd3 { - groups = "sd3_grp"; - function = "sd3"; - }; - }; - - sd5_pmx: sd5@0 { - sd5 { - groups = "sd5_grp"; - function = "sd5"; - }; - }; - - sd6_pmx0: sd6@0 { - sd6_0 { - groups = "sd6_grp0"; - function = "sd6_m0"; - }; - }; - - sd6_pmx1: sd6@1 { - sd6_1 { - groups = "sd6_grp1"; - function = "sd6_m1"; - }; - }; - - sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 { - sp0_ext_ldo_on { - groups = "sp0_ext_ldo_on_grp"; - function = "sp0_ext_ldo_on"; - }; - }; - - sp0_qspi_pmx: sp0_qspi@0 { - sp0_qspi { - groups = "sp0_qspi_grp"; - function = "sp0_qspi"; - }; - }; - - sp1_spi_pmx: sp1_spi@0 { - sp1_spi { - groups = "sp1_spi_grp"; - function = "sp1_spi"; - }; - }; - - tpiu_trace_pmx: tpiu_trace@0 { - tpiu_trace { - groups = "tpiu_trace_grp"; - function = "tpiu_trace"; - }; - }; - - uart0_pmx: uart0@0 { - uart0 { - groups = "uart0_grp"; - function = "uart0"; - }; - }; - - uart0_nopause_pmx: uart0_nopause@0 { - uart0_nopause { - groups = "uart0_nopause_grp"; - function = "uart0_nopause"; - }; - }; - - uart1_pmx: uart1@0 { - uart1 { - groups = "uart1_grp"; - function = "uart1"; - }; - }; - - uart2_pmx: uart2@0 { - uart2 { - groups = "uart2_grp"; - function = "uart2"; - }; - }; - - uart3_pmx0: uart3@0 { - uart3_0 { - groups = "uart3_grp0"; - function = "uart3_m0"; - }; - }; - - uart3_pmx1: uart3@1 { - uart3_1 { - groups = "uart3_grp1"; - function = "uart3_m1"; - }; - }; - - uart3_pmx2: uart3@2 { - uart3_2 { - groups = "uart3_grp2"; - function = "uart3_m2"; - }; - }; - - uart3_pmx3: uart3@3 { - uart3_3 { - groups = "uart3_grp3"; - function = "uart3_m3"; - }; - }; - - uart3_nopause_pmx0: uart3_nopause@0 { - uart3_nopause_0 { - groups = "uart3_nopause_grp0"; - function = "uart3_nopause_m0"; - }; - }; - - uart3_nopause_pmx1: uart3_nopause@1 { - uart3_nopause_1 { - groups = "uart3_nopause_grp1"; - function = "uart3_nopause_m1"; - }; - }; - - uart4_pmx0: uart4@0 { - uart4_0 { - groups = "uart4_grp0"; - function = "uart4_m0"; - }; - }; - - uart4_pmx1: uart4@1 { - uart4_1 { - groups = "uart4_grp1"; - function = "uart4_m1"; - }; - }; - - uart4_pmx2: uart4@2 { - uart4_2 { - groups = "uart4_grp2"; - function = "uart4_m2"; - }; - }; - - uart4_nopause_pmx: uart4_nopause@0 { - uart4_nopause { - groups = "uart4_nopause_grp"; - function = "uart4_nopause"; - }; - }; - - usb0_drvvbus_pmx: usb0_drvvbus@0 { - usb0_drvvbus { - groups = "usb0_drvvbus_grp"; - function = "usb0_drvvbus"; - }; - }; - - usb1_drvvbus_pmx: usb1_drvvbus@0 { - usb1_drvvbus { - groups = "usb1_drvvbus_grp"; - function = "usb1_drvvbus"; - }; - }; - - visbus_dout_pmx: visbus_dout@0 { - visbus_dout { - groups = "visbus_dout_grp"; - function = "visbus_dout"; - }; - }; - - vi_vip1_pmx: vi_vip1@0 { - vi_vip1 { - groups = "vi_vip1_grp"; - function = "vi_vip1"; - }; - }; - - vi_vip1_ext_pmx: vi_vip1_ext@0 { - vi_vip1_ext { - groups = "vi_vip1_ext_grp"; - function = "vi_vip1_ext"; - }; - }; - - vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 { - vi_vip1_low8bit { - groups = "vi_vip1_low8bit_grp"; - function = "vi_vip1_low8bit"; - }; - }; - - vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 { - vi_vip1_high8bit { - groups = "vi_vip1_high8bit_grp"; - function = "vi_vip1_high8bit"; - }; - }; - }; - - pmipc { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13240000 0x13240000 0x00010000>; - pmipc@0x13240000 { - compatible = "sirf,atlas7-pmipc"; - reg = <0x13240000 0x00010000>; - }; - }; - - dramfw { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10830000 0x10830000 0x18000>; - dramfw@10820000 { - compatible = "sirf,nocfw-dramfw"; - reg = <0x10830000 0x18000>; - }; - }; - - spramfw { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10250000 0x10250000 0x3000>; - spramfw@10820000 { - compatible = "sirf,nocfw-spramfw"; - reg = <0x10250000 0x3000>; - }; - }; - - cpum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10200000 0x10200000 0x3000>; - cpum@10200000 { - compatible = "sirf,nocfw-cpum"; - reg = <0x10200000 0x3000>; - }; - }; - - cgum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18641000 0x18641000 0x3000>, - <0x18620000 0x18620000 0x1000>, - <0x18630000 0x18630000 0x10000>; - - cgum@18641000 { - compatible = "sirf,nocfw-cgum"; - reg = <0x18641000 0x3000>; - }; - - car: clock-controller@18620000 { - compatible = "sirf,atlas7-car"; - reg = <0x18620000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - pwm: pwm@18630000 { - compatible = "sirf,prima2-pwm"; - #pwm-cells = <2>; - reg = <0x18630000 0x10000>; - clocks = <&car 138>, <&car 139>, <&car 237>, - <&car 240>, <&car 140>, <&car 246>; - clock-names = "pwmc", "sigsrc0", "sigsrc1", - "sigsrc2", "sigsrc3", "sigsrc4"; - }; - }; - - gnssm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18000000 0x18000000 0x0000ffff>, - <0x18010000 0x18010000 0x1000>, - <0x18020000 0x18020000 0x1000>, - <0x18030000 0x18030000 0x1000>, - <0x18040000 0x18040000 0x1000>, - <0x18050000 0x18050000 0x1000>, - <0x18060000 0x18060000 0x1000>, - <0x180b0000 0x180b0000 0x4000>, - <0x18100000 0x18100000 0x3000>, - <0x18250000 0x18250000 0x10000>, - <0x18200000 0x18200000 0x1000>; - - dmac0: dma-controller@18000000 { - cell-index = <0>; - compatible = "sirf,atlas7-dmac"; - reg = <0x18000000 0x1000>; - interrupts = <0 12 0>; - clocks = <&car 89>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - gnssmfw@0x18100000 { - compatible = "sirf,nocfw-gnssm"; - reg = <0x18100000 0x3000>; - }; - - uart0: uart@18010000 { - cell-index = <0>; - compatible = "sirf,atlas7-uart"; - reg = <0x18010000 0x1000>; - interrupts = <0 17 0>; - clocks = <&car 90>; - fifosize = <128>; - dmas = <&dmac0 3>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@18020000 { - cell-index = <1>; - compatible = "sirf,atlas7-uart"; - reg = <0x18020000 0x1000>; - interrupts = <0 18 0>; - clocks = <&car 88>; - fifosize = <32>; - }; - - uart2: uart@18030000 { - cell-index = <2>; - compatible = "sirf,atlas7-uart"; - reg = <0x18030000 0x1000>; - interrupts = <0 19 0>; - clocks = <&car 91>; - fifosize = <128>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart3: uart@18040000 { - cell-index = <3>; - compatible = "sirf,atlas7-uart"; - reg = <0x18040000 0x1000>; - interrupts = <0 66 0>; - clocks = <&car 92>; - fifosize = <128>; - dmas = <&dmac0 4>, <&dmac0 5>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart4: uart@18050000 { - cell-index = <4>; - compatible = "sirf,atlas7-uart"; - reg = <0x18050000 0x1000>; - interrupts = <0 69 0>; - clocks = <&car 93>; - fifosize = <128>; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart5: uart@18060000 { - cell-index = <5>; - compatible = "sirf,atlas7-uart"; - reg = <0x18060000 0x1000>; - interrupts = <0 71 0>; - clocks = <&car 94>; - fifosize = <128>; - dmas = <&dmac0 8>, <&dmac0 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - gmac: eth@180b0000 { - compatible = "snps, dwc-eth-qos"; - reg = <0x180b0000 0x4000>; - interrupts = <0 59 0>, <0 70 0>; - interrupt-names = "macirq", "macpmt"; - clocks = <&car 39>, <&car 45>, - <&car 86>, <&car 87>; - clock-names = "gnssm_rgmii", "gnssm_gmac", - "rgmii", "gmac"; - local-mac-address = [00 00 00 00 00 00]; - phy-mode = "rgmii"; - }; - dspub@18250000 { - compatible = "dx,cc44p"; - reg = <0x18250000 0x10000>; - interrupts = <0 27 0>; - }; - - spi1: spi@18200000 { - compatible = "sirf,prima2-spi"; - reg = <0x18200000 0x1000>; - interrupts = <0 16 0>; - clocks = <&car 95>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - - gpum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13000000 0x13000000 0x3000>, - <0x13010000 0x13010000 0x1400>, - <0x13010800 0x13010800 0x100>, - <0x13011000 0x13011000 0x100>; - gpum@0x13000000 { - compatible = "sirf,nocfw-gpum"; - reg = <0x13000000 0x3000>; - }; - dmacsdrr: dma-controller@13010800 { - cell-index = <5>; - compatible = "sirf,atlas7-dmac-v2"; - reg = <0x13010800 0x100>; - interrupts = <0 8 0>; - clocks = <&car 127>; - #dma-cells = <1>; - #dma-channels = <1>; - }; - dmacsdrw: dma-controller@13011000 { - cell-index = <6>; - compatible = "sirf,atlas7-dmac-v2"; - reg = <0x13011000 0x100>; - interrupts = <0 9 0>; - clocks = <&car 127>; - #dma-cells = <1>; - #dma-channels = <1>; - }; - sdr@0x13010000 { - compatible = "sirf,atlas7-sdr"; - reg = <0x13010000 0x1400>; - interrupts = <0 7 0>, - <0 8 0>, - <0 9 0>; - clocks = <&car 127>; - dmas = <&dmacsdrr 0>, <&dmacsdrw 0>; - dma-names = "tx", "rx"; - }; - }; - - mediam { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x15000000 0x15000000 0x00600000>, - <0x16000000 0x16000000 0x00200000>, - <0x17000000 0x17000000 0x10000>, - <0x17020000 0x17020000 0x1000>, - <0x17030000 0x17030000 0x1000>, - <0x17040000 0x17040000 0x1000>, - <0x17050000 0x17050000 0x10000>, - <0x17060000 0x17060000 0x200>, - <0x17060200 0x17060200 0x100>, - <0x17070000 0x17070000 0x200>, - <0x17070200 0x17070200 0x100>, - <0x170A0000 0x170A0000 0x3000>; - - multimedia@15000000 { - compatible = "sirf,atlas7-video-codec"; - reg = <0x15000000 0x10000>; - interrupts = <0 5 0>; - clocks = <&car 102>; - }; - - mediam@170A0000 { - compatible = "sirf,nocfw-mediam"; - reg = <0x170A0000 0x3000>; - }; - - gpio_0: gpio_mediam@17040000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x17040000 0x1000>; - interrupts = <0 13 0>, <0 14 0>; - clocks = <&car 107>; - clock-names = "gpio0_io"; - gpio-controller; - interrupt-controller; - - gpio-banks = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 32 0 0>; - gpio-ranges-group-names = "lvds_gpio_grp", - "uart_nand_gpio_grp"; - }; - - nand@17050000 { - compatible = "sirf,atlas7-nand"; - reg = <0x17050000 0x10000>; - pinctrl-names = "default"; - pinctrl-0 = <&nd_df_pmx>; - interrupts = <0 41 0>; - clocks = <&car 108>, <&car 112>; - clock-names = "nand_io", "nand_nand"; - }; - - sd0: sdhci@16000000 { - cell-index = <0>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x16000000 0x100000>; - interrupts = <0 38 0>; - clocks = <&car 109>, <&car 111>; - clock-names = "core", "iface"; - wp-inverted; - non-removable; - status = "disabled"; - bus-width = <8>; - }; - - sd1: sdhci@16100000 { - cell-index = <1>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x16100000 0x100000>; - interrupts = <0 38 0>; - clocks = <&car 109>, <&car 111>; - clock-names = "core", "iface"; - non-removable; - status = "disabled"; - bus-width = <8>; - }; - - jpeg@17000000 { - compatible = "sirf,atlas7-jpeg"; - reg = <0x17000000 0x10000>; - interrupts = <0 72 0>, - <0 73 0>; - clocks = <&car 103>; - }; - - usb0: usb@17060000 { - cell-index = <0>; - compatible = "sirf,atlas7-usb"; - reg = <0x17060000 0x200>; - interrupts = <0 10 0>; - clocks = <&car 113>; - sirf,usbphy = <&usbphy0>; - phy_type = "utmi"; - dr_mode = "otg"; - maximum-speed = "high-speed"; - status = "okay"; - }; - - usb1: usb@17070000 { - cell-index = <1>; - compatible = "sirf,atlas7-usb"; - reg = <0x17070000 0x200>; - interrupts = <0 11 0>; - clocks = <&car 114>; - sirf,usbphy = <&usbphy1>; - phy_type = "utmi"; - dr_mode = "host"; - maximum-speed = "high-speed"; - status = "okay"; - }; - - usbphy0: usbphy@0 { - compatible = "sirf,atlas7-usbphy"; - reg = <0x17060200 0x100>; - clocks = <&car 115>; - status = "okay"; - }; - - usbphy1: usbphy@1 { - compatible = "sirf,atlas7-usbphy"; - reg = <0x17070200 0x100>; - clocks = <&car 116>; - status = "okay"; - }; - - i2c0: i2c@17020000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0x17020000 0x1000>; - interrupts = <0 24 0>; - clocks = <&car 105>; - #address-cells = <1>; - #size-cells = <0>; - }; - - }; - - vdifm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13290000 0x13290000 0x3000>, - <0x13300000 0x13300000 0x1000>, - <0x14200000 0x14200000 0x600000>; - - vdifm@13290000 { - compatible = "sirf,nocfw-vdifm"; - reg = <0x13290000 0x3000>; - }; - - gpio_1: gpio_vdifm@13300000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x13300000 0x1000>; - interrupts = <0 43 0>, <0 44 0>, - <0 45 0>, <0 46 0>; - clocks = <&car 84>; - clock-names = "gpio1_io"; - gpio-controller; - interrupt-controller; - - gpio-banks = <4>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 32 0 0>, - <&pinctrl 64 0 0>, - <&pinctrl 96 0 0>; - gpio-ranges-group-names = "gnss_gpio_grp", - "lcd_vip_gpio_grp", - "sdio_i2s_gpio_grp", - "sp_rgmii_gpio_grp"; - }; - - sd2: sdhci@14200000 { - cell-index = <2>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14200000 0x100000>; - interrupts = <0 23 0>; - clocks = <&car 70>, <&car 75>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - sd-uhs-sdr50; - vqmmc-supply = <&vqmmc>; - vqmmc: vqmmc@2 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-name = "vqmmc-ldo"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-allow-bypass; - }; - }; - - sd3: sdhci@14300000 { - cell-index = <3>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14300000 0x100000>; - interrupts = <0 23 0>; - clocks = <&car 76>, <&car 81>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - - sd5: sdhci@14500000 { - cell-index = <5>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14500000 0x100000>; - interrupts = <0 39 0>; - clocks = <&car 71>, <&car 76>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - loop-dma; - }; - - sd6: sdhci@14600000 { - cell-index = <6>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14600000 0x100000>; - interrupts = <0 98 0>; - clocks = <&car 72>, <&car 77>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - - sd7: sdhci@14700000 { - cell-index = <7>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14700000 0x100000>; - interrupts = <0 98 0>; - clocks = <&car 72>, <&car 77>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - }; - - audiom { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10d50000 0x10d50000 0x0000ffff>, - <0x10d60000 0x10d60000 0x0000ffff>, - <0x10d80000 0x10d80000 0x0000ffff>, - <0x10d90000 0x10d90000 0x0000ffff>, - <0x10ED0000 0x10ED0000 0x3000>, - <0x10dc8000 0x10dc8000 0x1000>, - <0x10dc0000 0x10dc0000 0x1000>, - <0x10db0000 0x10db0000 0x4000>, - <0x10d40000 0x10d40000 0x1000>, - <0x10d30000 0x10d30000 0x1000>; - - timer@10dc0000 { - compatible = "sirf,atlas7-tick"; - reg = <0x10dc0000 0x1000>; - interrupts = <0 0 0>, - <0 1 0>, - <0 2 0>, - <0 49 0>, - <0 50 0>, - <0 51 0>; - clocks = <&car 47>; - }; - - timerb@10dc8000 { - compatible = "sirf,atlas7-tick"; - reg = <0x10dc8000 0x1000>; - interrupts = <0 74 0>, - <0 75 0>, - <0 76 0>, - <0 77 0>, - <0 78 0>, - <0 79 0>; - clocks = <&car 47>; - }; - - vip0@10db0000 { - compatible = "sirf,atlas7-vip0"; - reg = <0x10db0000 0x2000>; - interrupts = <0 85 0>; - sirf,vip_cma_size = <0xC00000>; - }; - - cvd@10db2000 { - compatible = "sirf,cvd"; - reg = <0x10db2000 0x2000>; - clocks = <&car 46>; - }; - - dmac2: dma-controller@10d50000 { - cell-index = <2>; - compatible = "sirf,atlas7-dmac"; - reg = <0x10d50000 0xffff>; - interrupts = <0 55 0>; - clocks = <&car 60>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - dmac3: dma-controller@10d60000 { - cell-index = <3>; - compatible = "sirf,atlas7-dmac"; - reg = <0x10d60000 0xffff>; - interrupts = <0 56 0>; - clocks = <&car 61>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - adc: adc@10d80000 { - compatible = "sirf,atlas7-adc"; - reg = <0x10d80000 0xffff>; - interrupts = <0 34 0>; - clocks = <&car 49>; - #io-channel-cells = <1>; - }; - - pulsec@10d90000 { - compatible = "sirf,prima2-pulsec"; - reg = <0x10d90000 0xffff>; - interrupts = <0 42 0>; - clocks = <&car 54>; - }; - - audiom@10ED0000 { - compatible = "sirf,nocfw-audiom"; - reg = <0x10ED0000 0x3000>; - interrupts = <0 102 0>; - }; - - usp1: usp@10d30000 { - cell-index = <1>; - reg = <0x10d30000 0x1000>; - fifosize = <512>; - clocks = <&car 58>; - dmas = <&dmac2 6>, <&dmac2 7>; - dma-names = "rx", "tx"; - }; - - usp2: usp@10d40000 { - cell-index = <2>; - reg = <0x10d40000 0x1000>; - interrupts = <0 22 0>; - clocks = <&car 59>; - dmas = <&dmac2 12>, <&dmac2 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - ddrm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10820000 0x10820000 0x3000>, - <0x10800000 0x10800000 0x2000>; - ddrm@10820000 { - compatible = "sirf,nocfw-ddrm"; - reg = <0x10820000 0x3000>; - interrupts = <0 105 0>; - }; - - memory-controller@0x10800000 { - compatible = "sirf,atlas7-memc"; - reg = <0x10800000 0x2000>; - }; - - }; - - btm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x11002000 0x11002000 0x0000ffff>, - <0x11010000 0x11010000 0x3000>, - <0x11000000 0x11000000 0x1000>, - <0x11001000 0x11001000 0x1000>; - - dmac4: dma-controller@11002000 { - cell-index = <4>; - compatible = "sirf,atlas7-dmac"; - reg = <0x11002000 0x1000>; - interrupts = <0 99 0>; - clocks = <&car 130>; - dma-channels = <16>; - #dma-cells = <1>; - }; - uart6: uart@11000000 { - cell-index = <6>; - compatible = "sirf,atlas7-bt-uart", - "sirf,atlas7-uart"; - reg = <0x11000000 0x1000>; - interrupts = <0 100 0>; - clocks = <&car 131>, <&car 133>, <&car 134>; - clock-names = "uart", "general", "noc"; - fifosize = <128>; - dmas = <&dmac4 12>, <&dmac4 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usp3: usp@11001000 { - compatible = "sirf,atlas7-bt-usp", - "sirf,prima2-usp-pcm"; - cell-index = <3>; - reg = <0x11001000 0x1000>; - fifosize = <512>; - clocks = <&car 132>, <&car 129>, <&car 133>, - <&car 134>, <&car 135>; - clock-names = "usp3_io", "a7ca_btss", "a7ca_io", - "noc_btm_io", "thbtm_io"; - dmas = <&dmac4 0>, <&dmac4 1>; - dma-names = "rx", "tx"; - }; - - btm@11010000 { - compatible = "sirf,nocfw-btm"; - reg = <0x11010000 0x3000>; - }; - }; - - rtcm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18810000 0x18810000 0x3000>, - <0x18840000 0x18840000 0x1000>, - <0x18890000 0x18890000 0x1000>, - <0x188B0000 0x188B0000 0x10000>, - <0x188D0000 0x188D0000 0x1000>; - rtcm@18810000 { - compatible = "sirf,nocfw-rtcm"; - reg = <0x18810000 0x3000>; - interrupts = <0 109 0>; - }; - - gpio_2: gpio_rtcm@18890000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x18890000 0x1000>; - interrupts = <0 47 0>; - gpio-controller; - interrupt-controller; - - gpio-banks = <1>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "rtc_gpio_grp"; - }; - - rtc-iobg@18840000 { - compatible = "sirf,prima2-rtciobg", - "sirf-prima2-rtciobg-bus", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18840000 0x1000>; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x100>; - interrupts = <0 52 0>; - }; - pwrc@3000 { - compatible = "sirf,atlas7-pwrc"; - reg = <0x3000 0x100>; - }; - }; - - qspi: flash@188B0000 { - cell-index = <0>; - compatible = "sirf,atlas7-qspi-nor"; - reg = <0x188B0000 0x10000>; - interrupts = <0 15 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - retain@0x188D0000 { - compatible = "sirf,atlas7-retain"; - reg = <0x188D0000 0x1000>; - }; - - }; - disp-iobg { - /* lcdc0 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13100000 0x13100000 0x20000>, - <0x10e10000 0x10e10000 0x10000>, - <0x17010000 0x17010000 0x10000>; - - lcd@13100000 { - compatible = "sirf,atlas7-lcdc"; - reg = <0x13100000 0x10000>; - interrupts = <0 30 0>; - clocks = <&car 79>; - }; - vpp@13110000 { - compatible = "sirf,atlas7-vpp"; - reg = <0x13110000 0x10000>; - interrupts = <0 31 0>; - clocks = <&car 78>; - resets = <&car 29>; - }; - lvds@10e10000 { - compatible = "sirf,atlas7-lvdsc"; - reg = <0x10e10000 0x10000>; - interrupts = <0 64 0>; - clocks = <&car 54>; - resets = <&car 29>; - }; - g2d@17010000 { - compatible = "sirf, atlas7-g2d"; - reg = <0x17010000 0x10000>; - interrupts = <0 61 0>; - clocks = <&car 104>; - }; - - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x12000000 0x12000000 0x1000000>; - - graphics@12000000 { - compatible = "powervr,sgx531"; - reg = <0x12000000 0x1000000>; - interrupts = <0 6 0>; - clocks = <&car 126>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/axm5516-amarillo.dts b/software/linux/kernel/arch/arm/boot/dts/axm5516-amarillo.dts deleted file mode 100644 index a9d60471d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/axm5516-amarillo.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * arch/arm/boot/dts/axm5516-amarillo.dts - * - * Copyright (C) 2013 LSI - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/dts-v1/; - -/memreserve/ 0x00000000 0x00400000; - -#include "axm55xx.dtsi" -#include "axm5516-cpus.dtsi" - -/ { - model = "Amarillo AXM5516"; - compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0x02 0x00000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/axm5516-cpus.dtsi b/software/linux/kernel/arch/arm/boot/dts/axm5516-cpus.dtsi deleted file mode 100644 index b85f360cb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/axm5516-cpus.dtsi +++ /dev/null @@ -1,204 +0,0 @@ -/* - * arch/arm/boot/dts/axm5516-cpus.dtsi - * - * Copyright (C) 2013 LSI - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - cluster2 { - core0 { - cpu = <&CPU8>; - }; - core1 { - cpu = <&CPU9>; - }; - core2 { - cpu = <&CPU10>; - }; - core3 { - cpu = <&CPU11>; - }; - }; - cluster3 { - core0 { - cpu = <&CPU12>; - }; - core1 { - cpu = <&CPU13>; - }; - core2 { - cpu = <&CPU14>; - }; - core3 { - cpu = <&CPU15>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x00>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x01>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x02>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x03>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x102>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x103>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU8: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x200>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU9: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x201>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU10: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x202>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU11: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x203>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU12: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x300>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU13: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x301>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU14: cpu@302 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x302>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - - CPU15: cpu@303 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x303>; - clock-frequency= <1400000000>; - cpu-release-addr = <0>; // Fixed by the boot loader - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/axm55xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/axm55xx.dtsi deleted file mode 100644 index a9d6d593f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/axm55xx.dtsi +++ /dev/null @@ -1,204 +0,0 @@ -/* - * arch/arm/boot/dts/axm55xx.dtsi - * - * Copyright (C) 2013 LSI - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include - -#include "skeleton64.dtsi" - -/ { - interrupt-parent = <&gic>; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - timer = &timer0; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clk_ref0: clk_ref0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk_ref1: clk_ref1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk_ref2: clk_ref2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clks: clock-controller@2010020000 { - compatible = "lsi,axm5516-clks"; - #clock-cells = <1>; - reg = <0x20 0x10020000 0 0x20000>; - }; - }; - - gic: interrupt-controller@2001001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x20 0x01001000 0 0x1000>, - <0x20 0x01002000 0 0x1000>, - <0x20 0x01004000 0 0x2000>, - <0x20 0x01006000 0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - device_type = "soc"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - ranges; - - syscon: syscon@2010030000 { - compatible = "lsi,axxia-syscon", "syscon"; - reg = <0x20 0x10030000 0 0x2000>; - }; - - reset: reset@2010031000 { - compatible = "lsi,axm55xx-reset"; - syscon = <&syscon>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - serial0: uart@2010080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10080000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial1: uart@2010081000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10081000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial2: uart@2010082000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10082000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial3: uart@2010083000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10083000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer0: timer@2010091000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x20 0x10091000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "okay"; - }; - - gpio0: gpio@2010092000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x20 0x10092000 0x00 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio1: gpio@2010093000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x20 0x10093000 0x00 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - }; - }; -}; - -/* - Local Variables: - mode: C - End: -*/ diff --git a/software/linux/kernel/arch/arm/boot/dts/axp152.dtsi b/software/linux/kernel/arch/arm/boot/dts/axp152.dtsi deleted file mode 100644 index f90ad6c64..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/axp152.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&axp152 { - compatible = "x-powers,axp152"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/axp209.dtsi b/software/linux/kernel/arch/arm/boot/dts/axp209.dtsi deleted file mode 100644 index 675bb0f30..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/axp209.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP202/209 Integrated Power Management Chip - * http://www.x-powers.com/product/AXP20X.php - * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf - */ - -&axp209 { - compatible = "x-powers,axp209"; - interrupt-controller; - #interrupt-cells = <1>; - - axp_gpio: gpio { - compatible = "x-powers,axp209-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <1500>; - - reg_dcdc2: dcdc2 { - regulator-name = "dcdc2"; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "dcdc3"; - }; - - reg_ldo1: ldo1 { - /* LDO1 is a fixed output regulator */ - regulator-always-on; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-name = "ldo1"; - }; - - reg_ldo2: ldo2 { - regulator-name = "ldo2"; - }; - - reg_ldo3: ldo3 { - regulator-name = "ldo3"; - }; - - reg_ldo4: ldo4 { - regulator-name = "ldo4"; - }; - - reg_ldo5: ldo5 { - regulator-name = "ldo5"; - status = "disabled"; - }; - }; - - usb_power_supply: usb_power_supply { - compatible = "x-powers,axp202-usb-power-supply"; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/axp22x.dtsi b/software/linux/kernel/arch/arm/boot/dts/axp22x.dtsi deleted file mode 100644 index 458b6681e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/axp22x.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP221/221s/223 Integrated Power Management Chip - * http://www.x-powers.com/product/AXP22X.php - * http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf - */ - -&axp22x { - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; - - reg_dcdc1: dcdc1 { - regulator-name = "dcdc1"; - }; - - reg_dcdc2: dcdc2 { - regulator-name = "dcdc2"; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "dcdc3"; - }; - - reg_dcdc4: dcdc4 { - regulator-name = "dcdc4"; - }; - - reg_dcdc5: dcdc5 { - regulator-name = "dcdc5"; - }; - - reg_dc1sw: dc1sw { - regulator-name = "dc1sw"; - }; - - reg_dc5ldo: dc5ldo { - regulator-name = "dc5ldo"; - }; - - reg_aldo1: aldo1 { - regulator-name = "aldo1"; - }; - - reg_aldo2: aldo2 { - regulator-name = "aldo2"; - }; - - reg_aldo3: aldo3 { - regulator-name = "aldo3"; - }; - - reg_dldo1: dldo1 { - regulator-name = "dldo1"; - }; - - reg_dldo2: dldo2 { - regulator-name = "dldo2"; - }; - - reg_dldo3: dldo3 { - regulator-name = "dldo3"; - }; - - reg_dldo4: dldo4 { - regulator-name = "dldo4"; - }; - - reg_eldo1: eldo1 { - regulator-name = "eldo1"; - }; - - reg_eldo2: eldo2 { - regulator-name = "eldo2"; - }; - - reg_eldo3: eldo3 { - regulator-name = "eldo3"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-name = "ldo_io0"; - status = "disabled"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-name = "ldo_io1"; - status = "disabled"; - }; - - reg_rtc_ldo: rtc_ldo { - /* RTC_LDO is a fixed, always-on regulator */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "rtc_ldo"; - }; - - reg_drivevbus: drivevbus { - regulator-name = "drivevbus"; - status = "disabled"; - }; - }; - - usb_power_supply: usb_power_supply { - compatible = "x-powers,axp221-usb-power-supply"; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/axp809.dtsi b/software/linux/kernel/arch/arm/boot/dts/axp809.dtsi deleted file mode 100644 index ab8e5f2d9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/axp809.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * AXP809 Integrated Power Management Chip - */ - -&axp809 { - compatible = "x-powers,axp809"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm-cygnus-clock.dtsi deleted file mode 100644 index 80b6ba4ca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm-cygnus-clock.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - /* Cygnus ARM PLL */ - armpll: armpll { - #clock-cells = <0>; - compatible = "brcm,cygnus-armpll"; - clocks = <&osc>; - reg = <0x19000000 0x1000>; - }; - - /* peripheral clock for system timer */ - periph_clk: arm_periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* APB bus clock */ - apb_clk: apb_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <4>; - clock-mult = <1>; - }; - - genpll: genpll { - #clock-cells = <1>; - compatible = "brcm,cygnus-genpll"; - reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", - "enet_sw", "audio_125", "can"; - }; - - /* always 1/2 of the axi21 clock */ - axi41_clk: axi41_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll 1>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* always 1/4 of the axi21 clock */ - axi81_clk: axi81_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll 1>; - clock-div = <4>; - clock-mult = <1>; - }; - - lcpll0: lcpll0 { - #clock-cells = <1>; - compatible = "brcm,cygnus-lcpll0"; - reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio", - "usb_phy", "smart_card", "ch5"; - }; - - mipipll: mipipll { - #clock-cells = <1>; - compatible = "brcm,cygnus-mipipll"; - reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>; - clocks = <&osc>; - clock-output-names = "mipipll", "ch0_unused", "ch1_lcd", - "ch2_v3d", "ch3_unused", "ch4_unused", - "ch5_unused"; - }; - - asiu_clks: asiu_clks { - #clock-cells = <1>; - compatible = "brcm,cygnus-asiu-clk"; - reg = <0x0301d048 0xc>, <0x180aa024 0x4>; - - clocks = <&osc>; - clock-output-names = "keypad", "adc/touch", "pwm"; - }; - - audiopll: audiopll { - #clock-cells = <1>; - compatible = "brcm,cygnus-audiopll"; - reg = <0x180aeb00 0x68>; - clocks = <&osc>; - clock-output-names = "audiopll", "ch0_audio", - "ch1_audio", "ch2_audio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm-cygnus.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm-cygnus.dtsi deleted file mode 100644 index fabc9f36c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm-cygnus.dtsi +++ /dev/null @@ -1,381 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -#include "skeleton.dtsi" - -/ { - compatible = "brcm,cygnus"; - model = "Broadcom Cygnus SoC"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; - - /include/ "bcm-cygnus-clock.dtsi" - - core { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - cache-level = <2>; - }; - }; - - axi { - compatible = "simple-bus"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - pcie_phy: phy@0301d0a0 { - compatible = "brcm,cygnus-pcie-phy"; - reg = <0x0301d0a0 0x14>; - #address-cells = <1>; - #size-cells = <0>; - - pcie0_phy: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - pcie1_phy: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - pinctrl: pinctrl@0x0301d0c8 { - compatible = "brcm,cygnus-pinmux"; - reg = <0x0301d0c8 0x30>, - <0x0301d24c 0x2c>; - }; - - gpio_crmu: gpio@03024800 { - compatible = "brcm,cygnus-crmu-gpio"; - reg = <0x03024800 0x50>, - <0x03024008 0x18>; - ngpios = <6>; - #gpio-cells = <2>; - gpio-controller; - }; - - i2c0: i2c@18008000 { - compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; - reg = <0x18008000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - wdt0: wdt@18009000 { - compatible = "arm,sp805" , "arm,primecell"; - reg = <0x18009000 0x1000>; - interrupts = ; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; - }; - - gpio_ccm: gpio@1800a000 { - compatible = "brcm,cygnus-ccm-gpio"; - reg = <0x1800a000 0x50>, - <0x0301d164 0x20>; - ngpios = <24>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - }; - - i2c1: i2c@1800b000 { - compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; - reg = <0x1800b000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; - - phys = <&pcie0_phy>; - phy-names = "pcie-phy"; - - status = "disabled"; - - msi-parent = <&msi0>; - msi0: msi@18012000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; - - phys = <&pcie1_phy>; - phy-names = "pcie-phy"; - - status = "disabled"; - - msi-parent = <&msi1>; - msi1: msi@18013000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - uart0: serial@18020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18020000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart1: serial@18021000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18021000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart2: serial@18022000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18020000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - uart3: serial@18023000 { - compatible = "snps,dw-apb-uart"; - reg = <0x18023000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clocks = <&axi81_clk>; - clock-frequency = <100000000>; - status = "disabled"; - }; - - nand: nand@18046000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x18046000 0x600>, <0xf8105408 0x600>, - <0x18046f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - gpio_asiu: gpio@180a5000 { - compatible = "brcm,cygnus-asiu-gpio"; - reg = <0x180a5000 0x668>; - ngpios = <146>; - #gpio-cells = <2>; - gpio-controller; - - interrupt-controller; - interrupts = ; - gpio-ranges = <&pinctrl 0 42 1>, - <&pinctrl 1 44 3>, - <&pinctrl 4 48 1>, - <&pinctrl 5 50 3>, - <&pinctrl 8 126 1>, - <&pinctrl 9 155 1>, - <&pinctrl 10 152 1>, - <&pinctrl 11 154 1>, - <&pinctrl 12 153 1>, - <&pinctrl 13 127 3>, - <&pinctrl 16 140 1>, - <&pinctrl 17 145 7>, - <&pinctrl 24 130 10>, - <&pinctrl 34 141 4>, - <&pinctrl 38 54 1>, - <&pinctrl 39 56 3>, - <&pinctrl 42 60 3>, - <&pinctrl 45 64 3>, - <&pinctrl 48 68 2>, - <&pinctrl 50 84 6>, - <&pinctrl 56 94 6>, - <&pinctrl 62 72 1>, - <&pinctrl 63 70 1>, - <&pinctrl 64 80 1>, - <&pinctrl 65 74 3>, - <&pinctrl 68 78 1>, - <&pinctrl 69 82 1>, - <&pinctrl 70 156 17>, - <&pinctrl 87 104 12>, - <&pinctrl 99 102 2>, - <&pinctrl 101 90 4>, - <&pinctrl 105 116 6>, - <&pinctrl 111 100 2>, - <&pinctrl 113 122 4>, - <&pinctrl 123 11 1>, - <&pinctrl 124 38 4>, - <&pinctrl 128 43 1>, - <&pinctrl 129 47 1>, - <&pinctrl 130 49 1>, - <&pinctrl 131 53 1>, - <&pinctrl 132 55 1>, - <&pinctrl 133 59 1>, - <&pinctrl 134 63 1>, - <&pinctrl 135 67 1>, - <&pinctrl 136 71 1>, - <&pinctrl 137 73 1>, - <&pinctrl 138 77 1>, - <&pinctrl 139 79 1>, - <&pinctrl 140 81 1>, - <&pinctrl 141 83 1>, - <&pinctrl 142 10 1>; - }; - - ts_adc_syscon: ts_adc_syscon@180a6000 { - compatible = "brcm,iproc-ts-adc-syscon", "syscon"; - reg = <0x180a6000 0xc30>; - }; - - touchscreen: touchscreen@180a6000 { - compatible = "brcm,iproc-touchscreen"; - #address-cells = <1>; - #size-cells = <1>; - ts_syscon = <&ts_adc_syscon>; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; - clock-names = "tsc_clk"; - interrupts = ; - status = "disabled"; - }; - - adc: adc@180a6000 { - compatible = "brcm,iproc-static-adc"; - #io-channel-cells = <1>; - io-channel-ranges; - adc-syscon = <&ts_adc_syscon>; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; - clock-names = "tsc_clk"; - interrupts = ; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm-nsp.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm-nsp.dtsi deleted file mode 100644 index 65e0db1d3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm-nsp.dtsi +++ /dev/null @@ -1,479 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -#include "skeleton.dtsi" - -/ { - compatible = "brcm,nsp"; - model = "Broadcom Northstar Plus SoC"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - enable-method = "brcm,bcm-nsp-smp"; - secondary-boot-reg = <0xffff0fec>; - reg = <0x1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - mpcore { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - - a9pll: arm_clk@00000 { - #clock-cells = <0>; - compatible = "brcm,nsp-armpll"; - clocks = <&osc>; - reg = <0x00000 0x1000>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - twd-watchdog@20620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x20620 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - cache-level = <2>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - axi { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x0011ba08>; - #address-cells = <1>; - #size-cells = <1>; - - gpioa: gpio@0020 { - compatible = "brcm,nsp-gpio-a"; - reg = <0x0020 0x70>, - <0x3f1c4 0x1c>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <32>; - interrupt-controller; - interrupts = ; - gpio-ranges = <&pinctrl 0 0 32>; - }; - - uart0: serial@0300 { - compatible = "ns16550a"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - uart1: serial@0400 { - compatible = "ns16550a"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&osc>; - status = "disabled"; - }; - - dma@20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - amac0: ethernet@22000 { - compatible = "brcm,nsp-amac"; - reg = <0x022000 0x1000>, - <0x110000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - status = "disabled"; - }; - - amac1: ethernet@23000 { - compatible = "brcm,nsp-amac"; - reg = <0x023000 0x1000>, - <0x111000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; - status = "disabled"; - }; - - nand: nand@26000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x026000 0x600>, - <0x11b408 0x600>, - <0x026f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - pwm: pwm@31000 { - compatible = "brcm,iproc-pwm"; - reg = <0x31000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rng: rng@33000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x33000 0x14>; - }; - - ccbtimer0: timer@34000 { - compatible = "arm,sp804"; - reg = <0x34000 0x1000>; - interrupts = , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - }; - - ccbtimer1: timer@35000 { - compatible = "arm,sp804"; - reg = <0x35000 0x1000>; - interrupts = , - ; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - }; - - srab: srab@36000 { - compatible = "brcm,nsp-srab"; - reg = <0x36000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - /* ports are defined in board DTS */ - }; - - i2c0: i2c@38000 { - compatible = "brcm,iproc-i2c"; - reg = <0x38000 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - }; - - watchdog@39000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x39000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "wdogclk", "apb_pclk"; - }; - - lcpll0: lcpll0@3f100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x3f100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "sdio", - "ddr_phy"; - }; - - genpll: genpll@3f140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x3f140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", "ethernetclk", - "usbclk", "iprocfast", "sata1", - "sata2"; - }; - - pinctrl: pinctrl@3f1c0 { - compatible = "brcm,nsp-pinmux"; - reg = <0x3f1c0 0x04>, - <0x30028 0x04>, - <0x3f408 0x04>; - }; - - sata_phy: sata_phy@40100 { - compatible = "brcm,iproc-nsp-sata-phy"; - reg = <0x40100 0x340>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - sata_phy1: sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - sata: ahci@41000 { - compatible = "brcm,bcm-nsp-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0x41000 0x1000>, <0x40020 0x1c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - phy-names = "sata-phy"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy1>; - phy-names = "sata-phy"; - }; - }; - }; - - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; - - status = "disabled"; - - msi-parent = <&msi0>; - msi0: msi@18012000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; - - status = "disabled"; - - msi-parent = <&msi1>; - msi1: msi@18013000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; - - pcie2: pcie@18014000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18014000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>; - - linux,pci-domain = <2>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; - - status = "disabled"; - - msi-parent = <&msi2>; - msi2: msi@18014000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - brcm,pcie-msi-inten; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm11351.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm11351.dtsi deleted file mode 100644 index 18045c38b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm11351.dtsi +++ /dev/null @@ -1,424 +0,0 @@ -/* - * Copyright (C) 2012-2013 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "dt-bindings/clock/bcm281xx.h" - -#include "skeleton.dtsi" - -/ { - model = "BCM11351 SoC"; - compatible = "brcm,bcm11351"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; - reg = <1>; - }; - }; - - gic: interrupt-controller@3ff00100 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x3ff01000 0x1000>, - <0x3ff00100 0x100>; - }; - - smc@0x3404c000 { - compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; - reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ - }; - - uart@3e000000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e000000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e001000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e001000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e002000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e002000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e003000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e003000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - L2: l2-cache { - compatible = "brcm,bcm11351-a2-pl310-cache"; - reg = <0x3ff20000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - watchdog@35002f40 { - compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; - reg = <0x35002f40 0x6c>; - }; - - timer@35006000 { - compatible = "brcm,kona-timer"; - reg = <0x35006000 0x1000>; - interrupts = ; - clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; - }; - - gpio: gpio@35003000 { - compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; - reg = <0x35003000 0x800>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - sdio1: sdio@3f180000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f180000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: sdio@3f190000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f190000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: sdio@3f1a0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1a0000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: sdio@3f1b0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1b0000 0x10000>; - interrupts = ; - clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - pinctrl@35004800 { - compatible = "brcm,bcm11351-pinctrl"; - reg = <0x35004800 0x430>; - }; - - i2c@3e016000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e016000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - i2c@3e017000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e017000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - i2c@3e018000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3e018000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - i2c@3500d000 { - compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; - reg = <0x3500d000 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; - status = "disabled"; - }; - - pwm: pwm@3e01a000 { - compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; - reg = <0x3e01a000 0xcc>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; - #pwm-cells = <3>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - root_ccu: root_ccu { - compatible = "brcm,bcm11351-root-ccu"; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - hub_ccu: hub_ccu { - compatible = "brcm,bcm11351-hub-ccu"; - reg = <0x34000000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "tmon_1m"; - }; - - aon_ccu: aon_ccu { - compatible = "brcm,bcm11351-aon-ccu"; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer", - "pmu_bsc", - "pmu_bsc_var"; - }; - - master_ccu: master_ccu { - compatible = "brcm,bcm11351-master-ccu"; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "usb_ic", - "hsic2_48m", - "hsic2_12m"; - }; - - slave_ccu: slave_ccu { - compatible = "brcm,bcm11351-slave-ccu"; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "uartb4", - "ssp0", - "ssp2", - "bsc1", - "bsc2", - "bsc3", - "pwm"; - }; - - ref_1m_clk: ref_1m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - }; - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_cx40_clk: ref_cx40 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <40000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - compatible = "fixed-clock"; - clock-frequency = <52000000>; - #clock-cells = <0>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - ref_208m_clk: ref_208m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <208000000>; - }; - - var_208m_clk: var_208m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <208000000>; - }; - - ref_312m_clk: ref_312m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <312000000>; - }; - - var_312m_clk: var_312m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <312000000>; - }; - }; - - usbotg: usb@3f120000 { - compatible = "snps,dwc2"; - reg = <0x3f120000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@3f130000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x3f130000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm21664-garnet.dts b/software/linux/kernel/arch/arm/boot/dts/bcm21664-garnet.dts deleted file mode 100644 index e87cb26dd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm21664-garnet.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2014 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; - -#include - -#include "bcm21664.dtsi" - -/ { - model = "BCM21664 Garnet board"; - compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; - - memory { - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - uart@3e000000 { - status = "okay"; - }; - - sdio1: sdio@3f180000 { - max-frequency = <48000000>; - status = "okay"; - }; - - sdio2: sdio@3f190000 { - non-removable; - max-frequency = <48000000>; - status = "okay"; - }; - - sdio4: sdio@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - usbotg: usb@3f120000 { - status = "okay"; - }; - - usbphy: usb-phy@3f130000 { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm21664.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm21664.dtsi deleted file mode 100644 index 6dde95f21..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm21664.dtsi +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright (C) 2014 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "dt-bindings/clock/bcm21664.h" - -#include "skeleton.dtsi" - -/ { - model = "BCM21664 SoC"; - compatible = "brcm,bcm21664"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x35004178>; - reg = <1>; - }; - }; - - gic: interrupt-controller@3ff00100 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x3ff01000 0x1000>, - <0x3ff00100 0x100>; - }; - - smc@0x3404e000 { - compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; - reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ - }; - - uart@3e000000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e000000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e001000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e001000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e002000 { - compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e002000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x3ff20000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - brcm,resetmgr@35001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x35001f00 0x24>; - }; - - timer@35006000 { - compatible = "brcm,kona-timer"; - reg = <0x35006000 0x1c>; - interrupts = ; - clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; - }; - - gpio: gpio@35003000 { - compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; - reg = <0x35003000 0x524>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - sdio1: sdio@3f180000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f180000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: sdio@3f190000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f190000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: sdio@3f1a0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1a0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: sdio@3f1b0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1b0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - i2c@3e016000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e016000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - i2c@3e017000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e017000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - i2c@3e018000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e018000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - i2c@3e01c000 { - compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; - reg = <0x3e01c000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed clocks are defined before CCUs whose - * clocks may depend on them. - */ - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - root_ccu: root_ccu { - compatible = BCM21664_DT_ROOT_CCU_COMPAT; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - aon_ccu: aon_ccu { - compatible = BCM21664_DT_AON_CCU_COMPAT; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer"; - }; - - master_ccu: master_ccu { - compatible = BCM21664_DT_MASTER_CCU_COMPAT; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "sdio1_sleep", - "sdio2_sleep", - "sdio3_sleep", - "sdio4_sleep"; - }; - - slave_ccu: slave_ccu { - compatible = BCM21664_DT_SLAVE_CCU_COMPAT; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "bsc1", - "bsc2", - "bsc3", - "bsc4"; - }; - }; - - usbotg: usb@3f120000 { - compatible = "snps,dwc2"; - reg = <0x3f120000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@3f130000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x3f130000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm23550-sparrow.dts b/software/linux/kernel/arch/arm/boot/dts/bcm23550-sparrow.dts deleted file mode 100644 index 4d525ccb4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm23550-sparrow.dts +++ /dev/null @@ -1,80 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include - -#include "bcm23550.dtsi" - -/ { - model = "BCM23550 Sparrow board"; - compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550"; - - chosen { - stdout-path = "/slaves@3e000000/serial@0:115200n8"; - bootargs = "console=ttyS0,115200n8"; - }; - - memory { - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&uartb { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&sdio1 { - max-frequency = <48000000>; - status = "okay"; -}; - -&sdio2 { - non-removable; - max-frequency = <48000000>; - status = "okay"; -}; - -&sdio4 { - max-frequency = <48000000>; - cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm23550.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm23550.dtsi deleted file mode 100644 index a7a643f38..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm23550.dtsi +++ /dev/null @@ -1,415 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -/* BCM23550 and BCM21664 have almost identical clocks */ -#include "dt-bindings/clock/bcm21664.h" - -#include "skeleton.dtsi" - -/ { - model = "BCM23550 SoC"; - compatible = "brcm,bcm23550"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <1>; - clock-frequency = <1000000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <2>; - clock-frequency = <1000000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x35004178>; - reg = <3>; - clock-frequency = <1000000000>; - }; - }; - - /* Hub bus */ - hub@34000000 { - compatible = "simple-bus"; - ranges = <0 0x34000000 0x102f83ac>; - #address-cells = <1>; - #size-cells = <1>; - - smc@4e000 { - compatible = "brcm,bcm23550-smc", "brcm,kona-smc"; - reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */ - }; - - resetmgr: reset-controller@1001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x01001f00 0x24>; - }; - - gpio: gpio@1003000 { - compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio"; - reg = <0x01003000 0x524>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - - timer@1006000 { - compatible = "brcm,kona-timer"; - reg = <0x01006000 0x1c>; - interrupts = ; - clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; - }; - }; - - /* Slaves bus */ - slaves@3e000000 { - compatible = "simple-bus"; - ranges = <0 0x3e000000 0x0001c070>; - #address-cells = <1>; - #size-cells = <1>; - - uartb: serial@0 { - compatible = "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x00000000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uartb2: serial@1000 { - compatible = "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x00001000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uartb3: serial@2000 { - compatible = "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x00002000 0x118>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - - bsc1: i2c@16000 { - compatible = "brcm,kona-i2c"; - reg = <0x00016000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; - status = "disabled"; - }; - - bsc2: i2c@17000 { - compatible = "brcm,kona-i2c"; - reg = <0x00017000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; - status = "disabled"; - }; - - bsc3: i2c@18000 { - compatible = "brcm,kona-i2c"; - reg = <0x00018000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; - status = "disabled"; - }; - - bsc4: i2c@1c000 { - compatible = "brcm,kona-i2c"; - reg = <0x0001c000 0x70>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; - status = "disabled"; - }; - }; - - /* Apps bus */ - apps@3e300000 { - compatible = "simple-bus"; - ranges = <0 0x3e300000 0x01b77000>; - #address-cells = <1>; - #size-cells = <1>; - - usbotg: usb@e20000 { - compatible = "snps,dwc2"; - reg = <0x00e20000 0x10000>; - interrupts = ; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usbphy: usb-phy@e30000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x00e30000 0x28>; - #phy-cells = <0>; - status = "disabled"; - }; - - sdio1: sdio@e80000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00e80000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; - status = "disabled"; - }; - - sdio2: sdio@e90000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00e90000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; - status = "disabled"; - }; - - sdio3: sdio@ea0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00ea0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; - status = "disabled"; - }; - - sdio4: sdio@eb0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x00eb0000 0x801c>; - interrupts = ; - clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; - status = "disabled"; - }; - - cdc: cdc@1b0e000 { - compatible = "brcm,bcm23550-cdc"; - reg = <0x01b0e000 0x78>; - }; - - gic: interrupt-controller@1b21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x01b21000 0x1000>, - <0x01b22000 0x1000>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed clocks are defined before CCUs whose - * clocks may depend on them. - */ - - ref_32k_clk: ref_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - bbl_32k_clk: bbl_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - ref_13m_clk: ref_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - var_13m_clk: var_13m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - dft_19_5m_clk: dft_19_5m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19500000>; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - ref_52m_clk: ref_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - var_52m_clk: var_52m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - usb_otg_ahb_clk: usb_otg_ahb { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <52000000>; - }; - - ref_96m_clk: ref_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - var_96m_clk: var_96m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <96000000>; - }; - - ref_104m_clk: ref_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - var_104m_clk: var_104m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104000000>; - }; - - ref_156m_clk: ref_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - var_156m_clk: var_156m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <156000000>; - }; - - root_ccu: root_ccu { - compatible = BCM21664_DT_ROOT_CCU_COMPAT; - reg = <0x35001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "frac_1m"; - }; - - aon_ccu: aon_ccu { - compatible = BCM21664_DT_AON_CCU_COMPAT; - reg = <0x35002000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "hub_timer"; - }; - - slave_ccu: slave_ccu { - compatible = BCM21664_DT_SLAVE_CCU_COMPAT; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "bsc1", - "bsc2", - "bsc3", - "bsc4"; - }; - - master_ccu: master_ccu { - compatible = BCM21664_DT_MASTER_CCU_COMPAT; - reg = <0x3f001000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "sdio1", - "sdio2", - "sdio3", - "sdio4", - "sdio1_sleep", - "sdio2_sleep", - "sdio3_sleep", - "sdio4_sleep"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm28155-ap.dts b/software/linux/kernel/arch/arm/boot/dts/bcm28155-ap.dts deleted file mode 100644 index 9ce91dd60..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm28155-ap.dts +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 2013 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; - -#include - -#include "bcm11351.dtsi" - -/ { - model = "BCM28155 AP board"; - compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; - - memory { - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - uart@3e000000 { - status = "okay"; - }; - - i2c@3e016000 { - status="okay"; - clock-frequency = <400000>; - }; - - i2c@3e017000 { - status="okay"; - clock-frequency = <400000>; - }; - - i2c@3e018000 { - status="okay"; - clock-frequency = <400000>; - }; - - i2c@3500d000 { - status="okay"; - clock-frequency = <100000>; - - pmu: pmu@8 { - reg = <0x08>; - }; - }; - - sdio2: sdio@3f190000 { - non-removable; - max-frequency = <48000000>; - vmmc-supply = <&camldo1_reg>; - vqmmc-supply = <&iosr1_reg>; - status = "okay"; - }; - - sdio4: sdio@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - vmmc-supply = <&sdldo_reg>; - vqmmc-supply = <&sdxldo_reg>; - status = "okay"; - }; - - pwm: pwm@3e01a000 { - status = "okay"; - }; - - usbotg: usb@3f120000 { - vusb_d-supply = <&usbldo_reg>; - vusb_a-supply = <&iosr1_reg>; - status = "okay"; - }; - - usbphy: usb-phy@3f130000 { - status = "okay"; - }; -}; - -#include "bcm59056.dtsi" - -&pmu { - compatible = "brcm,bcm59056"; - interrupts = ; - regulators { - camldo1_reg: camldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdldo_reg: sdldo { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - sdxldo_reg: sdxldo { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - }; - - usbldo_reg: usbldo { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - iosr1_reg: iosr1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts deleted file mode 100644 index f7f9db355..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ /dev/null @@ -1,36 +0,0 @@ -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; - model = "Raspberry Pi Model A+"; - - leds { - act { - gpios = <&gpio 47 0>; - }; - - pwr { - label = "PWR"; - gpios = <&gpio 35 0>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; -}; - -&gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-a.dts b/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-a.dts deleted file mode 100644 index 8be102f5d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ /dev/null @@ -1,29 +0,0 @@ -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-a", "brcm,bcm2835"; - model = "Raspberry Pi Model A"; - - leds { - act { - gpios = <&gpio 16 1>; - }; - }; -}; - -&gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; - - /* I2S interface */ - i2s_alt2: i2s_alt2 { - brcm,pins = <28 29 30 31>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts deleted file mode 100644 index 35cde65c9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ /dev/null @@ -1,37 +0,0 @@ -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-smsc9514.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; - model = "Raspberry Pi Model B+"; - - leds { - act { - gpios = <&gpio 47 0>; - }; - - pwr { - label = "PWR"; - gpios = <&gpio 35 0>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; -}; - -&gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts deleted file mode 100644 index 84df85ea6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ /dev/null @@ -1,30 +0,0 @@ -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-smsc9512.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; - model = "Raspberry Pi Model B rev2"; - - leds { - act { - gpios = <&gpio 16 1>; - }; - }; -}; - -&gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; - - /* I2S interface */ - i2s_alt2: i2s_alt2 { - brcm,pins = <28 29 30 31>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b.dts b/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b.dts deleted file mode 100644 index 8e626a80f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ /dev/null @@ -1,24 +0,0 @@ -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-smsc9512.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-b", "brcm,bcm2835"; - model = "Raspberry Pi Model B"; - - leds { - act { - gpios = <&gpio 16 1>; - }; - }; -}; - -&gpio { - pinctrl-0 = <&gpioout &alt0 &alt3>; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-zero.dts deleted file mode 100644 index 60e359faf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2016 Stefan Wahren - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "bcm2835.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,model-zero", "brcm,bcm2835"; - model = "Raspberry Pi Zero"; - - leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi.dtsi deleted file mode 100644 index e9b47b2bb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -#include - -/ { - memory { - device_type = "memory"; - reg = <0 0x10000000>; - }; - - leds { - compatible = "gpio-leds"; - - act { - label = "ACT"; - default-state = "keep"; - linux,default-trigger = "heartbeat"; - }; - }; - - soc { - firmware: firmware { - compatible = "raspberrypi,bcm2835-firmware"; - mboxes = <&mailbox>; - }; - - power: power { - compatible = "raspberrypi,bcm2835-power"; - firmware = <&firmware>; - #power-domain-cells = <1>; - }; - }; -}; - -&gpio { - pinctrl-names = "default"; - - gpioout: gpioout { - brcm,pins = <6>; - brcm,function = ; - }; - - alt0: alt0 { - brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; - brcm,function = ; - }; - - alt3: alt3 { - brcm,pins = <48 49 50 51 52 53>; - brcm,function = ; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c2 { - status = "okay"; -}; - -&sdhci { - status = "okay"; - bus-width = <4>; -}; - -&pwm { - status = "okay"; -}; - -&usb { - power-domains = <&power RPI_POWER_DOMAIN_USB>; -}; - -&v3d { - power-domains = <&power RPI_POWER_DOMAIN_V3D>; -}; - -&hdmi { - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2835.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm2835.dtsi deleted file mode 100644 index a78759e73..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2835.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -#include "bcm283x.dtsi" - -/ { - compatible = "brcm,bcm2835"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm1176jzf-s"; - reg = <0x0>; - }; - }; - - soc { - ranges = <0x7e000000 0x20000000 0x02000000>; - dma-ranges = <0x40000000 0x00000000 0x20000000>; - - arm-pmu { - compatible = "arm,arm1176-pmu"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/software/linux/kernel/arch/arm/boot/dts/bcm2836-rpi-2-b.dts deleted file mode 100644 index 39dccf62a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ /dev/null @@ -1,41 +0,0 @@ -/dts-v1/; -#include "bcm2836.dtsi" -#include "bcm2835-rpi.dtsi" -#include "bcm283x-rpi-smsc9514.dtsi" -#include "bcm283x-rpi-usb-host.dtsi" - -/ { - compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; - model = "Raspberry Pi 2 Model B"; - - memory { - reg = <0 0x40000000>; - }; - - leds { - act { - gpios = <&gpio 47 0>; - }; - - pwr { - label = "PWR"; - gpios = <&gpio 35 0>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; -}; - -&gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; - - /* I2S interface */ - i2s_alt0: i2s_alt0 { - brcm,pins = <18 19 20 21>; - brcm,function = ; - }; -}; - -&hdmi { - hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm2836.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm2836.dtsi deleted file mode 100644 index 9d0651d8f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm2836.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -#include "bcm283x.dtsi" - -/ { - compatible = "brcm,bcm2836"; - - soc { - ranges = <0x7e000000 0x3f000000 0x1000000>, - <0x40000000 0x40000000 0x00001000>; - dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - - local_intc: local_intc { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&local_intc>; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&local_intc>; - interrupts = <9>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&local_intc>; - interrupts = <0>, // PHYS_SECURE_PPI - <1>, // PHYS_NONSECURE_PPI - <3>, // VIRT_PPI - <2>; // HYP_PPI - always-on; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - - v7_cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - clock-frequency = <800000000>; - }; - - v7_cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - clock-frequency = <800000000>; - }; - - v7_cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - clock-frequency = <800000000>; - }; - - v7_cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - clock-frequency = <800000000>; - }; - }; -}; - -/* Make the BCM2835-style global interrupt controller be a child of the - * CPU-local interrupt controller. - */ -&intc { - compatible = "brcm,bcm2836-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-parent = <&local_intc>; - interrupts = <8>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi deleted file mode 100644 index 12c981e51..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -/ { - aliases { - ethernet = ðernet; - }; -}; - -&usb { - usb1@1 { - compatible = "usb424,9512"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: usbether@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi deleted file mode 100644 index 3f0a56ebc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -/ { - aliases { - ethernet = ðernet; - }; -}; - -&usb { - usb1@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: usbether@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi deleted file mode 100644 index 73f4ece8d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi +++ /dev/null @@ -1,3 +0,0 @@ -&usb { - dr_mode = "host"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm283x.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm283x.dtsi deleted file mode 100644 index 74dd21b73..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm283x.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -#include -#include -#include -#include - -/* This include file covers the common peripherals and configuration between - * bcm2835 and bcm2836 implementations, leaving the CPU configuration to - * bcm2835.dtsi and bcm2836.dtsi. - */ - -/ { - compatible = "brcm,bcm2835"; - model = "BCM2835"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - bootargs = "earlyprintk console=ttyAMA0"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - timer@7e003000 { - compatible = "brcm,bcm2835-system-timer"; - reg = <0x7e003000 0x1000>; - interrupts = <1 0>, <1 1>, <1 2>, <1 3>; - /* This could be a reference to BCM2835_CLOCK_TIMER, - * but we don't have the driver using the common clock - * support yet. - */ - clock-frequency = <1000000>; - }; - - dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xf00>; - interrupts = <1 16>, - <1 17>, - <1 18>, - <1 19>, - <1 20>, - <1 21>, - <1 22>, - <1 23>, - <1 24>, - <1 25>, - <1 26>, - /* dma channel 11-14 share one irq */ - <1 27>, - <1 27>, - <1 27>, - <1 27>, - /* unused shared irq for all channels */ - <1 28>; - interrupt-names = "dma0", - "dma1", - "dma2", - "dma3", - "dma4", - "dma5", - "dma6", - "dma7", - "dma8", - "dma9", - "dma10", - "dma11", - "dma12", - "dma13", - "dma14", - "dma-shared-all"; - #dma-cells = <1>; - brcm,dma-channel-mask = <0x7f35>; - }; - - intc: interrupt-controller@7e00b200 { - compatible = "brcm,bcm2835-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - watchdog@7e100000 { - compatible = "brcm,bcm2835-pm-wdt"; - reg = <0x7e100000 0x28>; - }; - - clocks: cprman@7e101000 { - compatible = "brcm,bcm2835-cprman"; - #clock-cells = <1>; - reg = <0x7e101000 0x2000>; - - /* CPRMAN derives everything from the platform's - * oscillator. - */ - clocks = <&clk_osc>; - }; - - rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - }; - - mailbox: mailbox@7e00b880 { - compatible = "brcm,bcm2835-mbox"; - reg = <0x7e00b880 0x40>; - interrupts = <0 1>; - #mbox-cells = <0>; - }; - - gpio: gpio@7e200000 { - compatible = "brcm,bcm2835-gpio"; - reg = <0x7e200000 0xb4>; - /* - * The GPIO IP block is designed for 3 banks of GPIOs. - * Each bank has a GPIO interrupt for itself. - * There is an overall "any bank" interrupt. - * In order, these are GIC interrupts 17, 18, 19, 20. - * Since the BCM2835 only has 2 banks, the 2nd bank - * interrupt output appears to be mirrored onto the - * 3rd bank's interrupt signal. - * So, a bank0 interrupt shows up on 17, 20, and - * a bank1 interrupt shows up on 18, 19, 20! - */ - interrupts = <2 17>, <2 18>, <2 19>, <2 20>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0: serial@7e201000 { - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; - reg = <0x7e201000 0x1000>; - interrupts = <2 25>; - clocks = <&clocks BCM2835_CLOCK_UART>, - <&clocks BCM2835_CLOCK_VPU>; - clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; - }; - - i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x20>, - <0x7e101098 0x02>; - - dmas = <&dma 2>, - <&dma 3>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi: spi@7e204000 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204000 0x1000>; - interrupts = <2 22>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@7e205000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pixelvalve@7e206000 { - compatible = "brcm,bcm2835-pixelvalve0"; - reg = <0x7e206000 0x100>; - interrupts = <2 13>; /* pwa0 */ - }; - - pixelvalve@7e207000 { - compatible = "brcm,bcm2835-pixelvalve1"; - reg = <0x7e207000 0x100>; - interrupts = <2 14>; /* pwa1 */ - }; - - aux: aux@0x7e215000 { - compatible = "brcm,bcm2835-aux"; - #clock-cells = <1>; - reg = <0x7e215000 0x8>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - }; - - uart1: serial@7e215040 { - compatible = "brcm,bcm2835-aux-uart"; - reg = <0x7e215040 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_UART>; - status = "disabled"; - }; - - spi1: spi@7e215080 { - compatible = "brcm,bcm2835-aux-spi"; - reg = <0x7e215080 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_SPI1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@7e2150c0 { - compatible = "brcm,bcm2835-aux-spi"; - reg = <0x7e2150c0 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_SPI2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@7e20c000 { - compatible = "brcm,bcm2835-pwm"; - reg = <0x7e20c000 0x28>; - clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; - assigned-clock-rates = <10000000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - sdhci: sdhci@7e300000 { - compatible = "brcm,bcm2835-sdhci"; - reg = <0x7e300000 0x100>; - interrupts = <2 30>; - clocks = <&clocks BCM2835_CLOCK_EMMC>; - status = "disabled"; - }; - - hvs@7e400000 { - compatible = "brcm,bcm2835-hvs"; - reg = <0x7e400000 0x6000>; - interrupts = <2 1>; - }; - - i2c1: i2c@7e804000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e804000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@7e805000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e805000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pixelvalve@7e807000 { - compatible = "brcm,bcm2835-pixelvalve2"; - reg = <0x7e807000 0x100>; - interrupts = <2 10>; /* pixelvalve */ - }; - - hdmi: hdmi@7e902000 { - compatible = "brcm,bcm2835-hdmi"; - reg = <0x7e902000 0x600>, - <0x7e808000 0x100>; - interrupts = <2 8>, <2 9>; - ddc = <&i2c2>; - clocks = <&clocks BCM2835_PLLH_PIX>, - <&clocks BCM2835_CLOCK_HSM>; - clock-names = "pixel", "hdmi"; - status = "disabled"; - }; - - usb: usb@7e980000 { - compatible = "brcm,bcm2835-usb"; - reg = <0x7e980000 0x10000>; - interrupts = <1 9>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk_usb>; - clock-names = "otg"; - }; - - v3d: v3d@7ec00000 { - compatible = "brcm,bcm2835-v3d"; - reg = <0x7ec00000 0x1000>; - interrupts = <1 10>; - }; - - vc4: gpu { - compatible = "brcm,bcm2835-vc4"; - }; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - /* The oscillator is the root of the clock tree. */ - clk_osc: clock@3 { - compatible = "fixed-clock"; - reg = <3>; - #clock-cells = <0>; - clock-output-names = "osc"; - clock-frequency = <19200000>; - }; - - clk_usb: clock@4 { - compatible = "fixed-clock"; - reg = <4>; - #clock-cells = <0>; - clock-output-names = "otg"; - clock-frequency = <480000000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts deleted file mode 100644 index 112a5a834..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC56U - * - * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac56u", "brcm,bcm4708"; - model = "Asus RT-AC56U (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - wan { - label = "bcm53xx:blue:wan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - lan { - label = "bcm53xx:blue:lan"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - all { - label = "bcm53xx:blue:all"; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - 2ghz { - label = "bcm53xx:blue:2ghz"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - - usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts deleted file mode 100644 index 3600f56f4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC68U - * - * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac68u", "brcm,bcm4708"; - model = "Asus RT-AC68U (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts deleted file mode 100644 index 9cb186ea2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-1750DHP - * - * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; - model = "Buffalo WZR-1750DHP (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - usb { - label = "bcm53xx:blue:usb"; - gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - power0 { - label = "bcm53xx:red:power"; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - power1 { - label = "bcm53xx:white:power"; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router0 { - label = "bcm53xx:blue:router"; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router1 { - label = "bcm53xx:amber:router"; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wan { - label = "bcm53xx:blue:wan"; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - wireless0 { - label = "bcm53xx:blue:wireless"; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wireless1 { - label = "bcm53xx:amber:wireless"; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ - mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ - sw_ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts deleted file mode 100644 index 1c7e53d60..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Luxul XWC-1000 - * - * Copyright 2014 Luxul Inc. - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "luxul,xwc-1000", "brcm,bcm4708"; - model = "Luxul XWC-1000 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - nand: nand@18028000 { - nandcs@0 { - partition@0 { - label = "ubi"; - reg = <0x00000000 0x08000000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "timer"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4708-netgear-r6250.dts deleted file mode 100644 index 8ce39d58e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X arm platform code. - * DTS for Netgear R6250 V1 - * - * Copyright 2013 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r6250v1", "brcm,bcm4708"; - model = "Netgear R6250 V1 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power0 { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - usb { - label = "bcm53xx:blue:usb"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - wireless { - label = "bcm53xx:blue:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb3 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts deleted file mode 100644 index 6229ef283..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R6300 V2 - * - * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r6300v2", "brcm,bcm4708"; - model = "Netgear R6300 V2 (BCM4708)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - logo { - label = "bcm53xx:white:logo"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power0 { - label = "bcm53xx:green:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb { - label = "bcm53xx:blue:usb"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - wireless { - label = "bcm53xx:blue:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts deleted file mode 100644 index 70f4bb9d8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X arm platform code. - * DTS for SmartRG SR400ac - * - * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "smartrg,sr400ac", "brcm,bcm4708"; - model = "SmartRG SR400ac"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - usb3-white { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - usb3-green { - label = "bcm53xx:green:usb3"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - status-red { - label = "bcm53xx:red:status"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - status-green { - label = "bcm53xx:green:status"; - gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - status-blue { - label = "bcm53xx:blue:status"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wan-red { - label = "bcm53xx:red:wan"; - gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4708.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm4708.dtsi deleted file mode 100644 index eed4dd159..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4708.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for BCM4708 SoC. - * - * Copyright 2013-2014 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include "bcm5301x.dtsi" - -/ { - compatible = "brcm,bcm4708"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm-nsp-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - secondary-boot-reg = <0xffff0400>; - reg = <0x1>; - }; - }; - -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/software/linux/kernel/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts deleted file mode 100644 index 71b98cfaf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-N18U - * - * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; - model = "Asus RT-N18U (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb2 { - label = "bcm53xx:blue:usb2"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - wan { - label = "bcm53xx:blue:wan"; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - lan { - label = "bcm53xx:blue:lan"; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - usb3 { - label = "bcm53xx:blue:usb3"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/software/linux/kernel/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts deleted file mode 100644 index a9c8defed..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-600DHP2 - * - * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; - model = "Buffalo WZR-600DHP2 (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; - cs-gpios = <&chipcommon 6 0>; - #address-cells = <1>; - #size-cells = <0>; - - hc595: gpio_spi@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - registers-number = <1>; - spi-max-frequency = <100000>; - - gpio-controller; - #gpio-cells = <2>; - - }; - }; - - leds { - compatible = "gpio-leds"; - - power0 { - label = "bcm53xx:green:power"; - gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - power1 { - label = "bcm53xx:red:power"; - gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - router0 { - label = "bcm53xx:green:router"; - gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router1 { - label = "bcm53xx:amber:router"; - gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wan { - label = "bcm53xx:green:wan"; - gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - wireless0 { - label = "bcm53xx:green:wireless"; - gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wireless1 { - label = "bcm53xx:amber:wireless"; - gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - /* Switch device mode? */ - mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - - eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/software/linux/kernel/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts deleted file mode 100644 index 184fd9214..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WZR-900DHP - * - * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm47081.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708"; - model = "Buffalo WZR-900DHP (BCM47081)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm47081.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm47081.dtsi deleted file mode 100644 index f720012ee..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm47081.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for BCM47081 SoC. - * - * Copyright © 2014 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include "bcm5301x.dtsi" - -/ { - compatible = "brcm,bcm47081"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts deleted file mode 100644 index 8ade7def2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Asus RT-AC87U - * - * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; - model = "Asus RT-AC87U"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - wps { - label = "bcm53xx:blue:wps"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - power { - label = "bcm53xx:blue:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - wan { - label = "bcm53xx:red:wan"; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts deleted file mode 100644 index 0653e7ef2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Buffalo WXR-1900DHP - * - * Copyright (C) 2015 Felix Fietkau - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "buffalo,wxr-1900dhp", "brcm,bcm4709", "brcm,bcm4708"; - model = "Buffalo WXR-1900DHP"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - usb { - label = "bcm53xx:green:usb"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - router-amber { - label = "bcm53xx:amber:router"; - gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - router-white { - label = "bcm53xx:white:router"; - gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wireless-amber { - label = "bcm53xx:amber:wireless"; - gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wireless-white { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power"; - linux,code = ; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - - aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ - mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ - sw_ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - - eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - }; - }; -}; - - -&usb2 { - vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4709-netgear-r7000.dts deleted file mode 100644 index a22ed1440..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R7000 - * - * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; - model = "Netgear R7000"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - 5ghz { - label = "bcm53xx:white:5ghz"; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - 2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wireless { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - usb3 { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/software/linux/kernel/arch/arm/boot/dts/bcm4709-netgear-r8000.dts deleted file mode 100644 index ca181516c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for Netgear R8000 - * - * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; - model = "Netgear R8000 (BCM4709)"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - leds { - compatible = "gpio-leds"; - - power0 { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - power1 { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - 5ghz-1 { - label = "bcm53xx:white:5ghz-1"; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - 2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - wireless { - label = "bcm53xx:white:wireless"; - gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - wps { - label = "bcm53xx:white:wps"; - gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; - }; - - 5ghz-2 { - label = "bcm53xx:white:5ghz-2"; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - usb3 { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - usb2 { - label = "bcm53xx:white:usb2"; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&usb2 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/software/linux/kernel/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts deleted file mode 100644 index c8c0b3616..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * DTS for D-Link DIR-885L - * - * Copyright (C) 2016 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch1.dtsi" - -/ { - compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708"; - model = "D-Link DIR-885L"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - nand: nand@18028000 { - nandcs@0 { - partition@0 { - label = "firmware"; - reg = <0x00000000 0x08000000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - power-white { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - wan-white { - label = "bcm53xx:white:wan"; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - power-amber { - label = "bcm53xx:amber:power"; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - wan-amber { - label = "bcm53xx:amber:wan"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - usb3-white { - label = "bcm53xx:white:usb3"; - gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - 2ghz { - label = "bcm53xx:white:2ghz"; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - - 5ghz { - label = "bcm53xx:white:5ghz"; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - /* Switch: router / extender */ - extender { - label = "Extender"; - linux,code = ; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; - clock-frequency = <125000000>; -}; - -&usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -}; - -&spi_nor { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi deleted file mode 100644 index 24b099c00..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Broadcom Northstar NAND. - * - * Copyright (C) 2016 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the ISC license. - */ - -#include "bcm5301x-nand-cs0.dtsi" - -&nandcs { - nand-ecc-algo = "bch"; - nand-ecc-strength = <1>; - nand-ecc-step-size = <512>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi deleted file mode 100644 index 9a9630ded..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X Nand chip defaults. - * - * This should be included if the NAND controller is on chip select 0 - * and uses 8 bit ECC. - * - * Copyright (C) 2015 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include "bcm5301x-nand-cs0.dtsi" - -&nandcs { - nand-ecc-algo = "bch"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi deleted file mode 100644 index 168495106..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Broadcom Northstar NAND. - * - * Copyright (C) 2015 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -/ { - nand@18028000 { - nandcs: nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm5301x.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm5301x.dtsi deleted file mode 100644 index 4616452ce..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm5301x.dtsi +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Broadcom BCM470X / BCM5301X ARM platform code. - * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, - * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs - * - * Copyright 2013-2014 Hauke Mehrtens - * - * Licensed under the GNU/GPL. See COPYING for details. - */ - -#include -#include -#include -#include -#include -#include "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - chosen { - stdout-path = &uart0; - }; - - chipcommonA { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - uart0: serial@0300 { - compatible = "ns16550"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&iprocslow>; - status = "disabled"; - }; - - uart1: serial@0400 { - compatible = "ns16550"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&iprocslow>; - status = "disabled"; - }; - }; - - mpcore { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - - a9pll: arm_clk@00000 { - #clock-cells = <0>; - compatible = "brcm,nsp-armpll"; - clocks = <&osc>; - reg = <0x00000 0x1000>; - }; - - scu@20000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x20000 0x100>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - local-timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - arm,shared-override; - prefetch-data = <1>; - prefetch-instr = <1>; - cache-level = <2>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&a9pll>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - usb2_phy: usb2-phy { - compatible = "brcm,ns-usb2-phy"; - reg = <0x1800c000 0x1000>; - reg-names = "dmu"; - #phy-cells = <0>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - }; - - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* ChipCommon */ - <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - - /* Switch Register Access Block */ - <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 1 */ - <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 2 */ - <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 2.0 Controller */ - <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 3.0 Controller */ - <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 2 */ - <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 3 */ - <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - - /* NAND Controller */ - <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon: chipcommon@0 { - reg = <0x00000000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - - usb2: usb2@21000 { - reg = <0x00021000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - - phys = <&usb2_phy>; - }; - - usb3: usb3@23000 { - reg = <0x00023000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - }; - - spi@29000 { - reg = <0x00029000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - spi_nor: spi-nor@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - linux,part-probe = "ofpart", "bcm47xxpart"; - status = "disabled"; - }; - }; - - gmac0: ethernet@24000 { - reg = <0x24000 0x800>; - }; - - gmac1: ethernet@25000 { - reg = <0x25000 0x800>; - }; - - gmac2: ethernet@26000 { - reg = <0x26000 0x800>; - }; - - gmac3: ethernet@27000 { - reg = <0x27000 0x800>; - }; - }; - - lcpll0: lcpll0@1800c100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x1800c100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "sdio", - "ddr_phy"; - }; - - genpll: genpll@1800c140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x1800c140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", "ethernetclk", - "usbclk", "iprocfast", "sata1", - "sata2"; - }; - - srab: srab@18007000 { - compatible = "brcm,bcm5301x-srab"; - reg = <0x18007000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - /* ports are defined in board DTS */ - }; - - rng: rng@18004000 { - compatible = "brcm,bcm5301x-rng"; - reg = <0x18004000 0x14>; - }; - - nand: nand@18028000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; - reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm59056.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm59056.dtsi deleted file mode 100644 index 066adfb10..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm59056.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -/* -* Copyright 2014 Linaro Limited -* Author: Matt Porter -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -*/ - -&pmu { - compatible = "brcm,bcm59056"; - regulators { - rfldo_reg: rfldo { - }; - - camldo1_reg: camldo1 { - }; - - camldo2_reg: camldo2 { - }; - - simldo1_reg: simldo1 { - }; - - simldo2_reg: simldo2 { - }; - - sdldo_reg: sdldo { - }; - - sdxldo_reg: sdxldo { - }; - - mmcldo1_reg: mmcldo1 { - }; - - mmcldo2_reg: mmcldo2 { - }; - - audldo_reg: audldo { - }; - - micldo_reg: micldo { - }; - - usbldo_reg: usbldo { - }; - - vibldo_reg: vibldo { - }; - - csr_reg: csr { - }; - - iosr1_reg: iosr1 { - }; - - iosr2_reg: iosr2 { - }; - - msr_reg: msr { - }; - - sdsr1_reg: sdsr1 { - }; - - sdsr2_reg: sdsr2 { - }; - - vsr_reg: vsr { - }; - - gpldo1_reg: gpldo1 { - }; - - gpldo2_reg: gpldo2 { - }; - - gpldo3_reg: gpldo3 { - }; - - gpldo4_reg: gpldo4 { - }; - - gpldo5_reg: gpldo5 { - }; - - gpldo6_reg: gpldo6 { - }; - - vbus_reg: vbus { - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm63138.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm63138.dtsi deleted file mode 100644 index d0560e8cd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm63138.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Broadcom BCM63138 DSL SoCs Device Tree - */ - -#include -#include - -#include "skeleton.dtsi" - -/ { - compatible = "brcm,bcm63138"; - model = "Broadcom BCM63138 DSL SoC"; - interrupt-parent = <&gic>; - - aliases { - uart0 = &serial0; - uart1 = &serial1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0>; - enable-method = "brcm,bcm63138"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <1>; - enable-method = "brcm,bcm63138"; - resets = <&pmb0 4 1>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - /* UBUS peripheral clock */ - periph_clk: periph_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "periph"; - }; - - /* peripheral clock for system timer */ - axi_clk: axi_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* APB bus clock */ - apb_clk: apb_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&armpll>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - /* ARM bus */ - axi@80000000 { - compatible = "simple-bus"; - ranges = <0 0x80000000 0x784000>; - #address-cells = <1>; - #size-cells = <1>; - - L2: cache-controller@1d000 { - compatible = "arm,pl310-cache"; - reg = <0x1d000 0x1000>; - cache-unified; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <1024>; - cache-line-size = <32>; - interrupts = ; - }; - - scu: scu@1e000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000 0x100>; - }; - - gic: interrupt-controller@1e100 { - compatible = "arm,cortex-a9-gic"; - reg = <0x1f000 0x1000 - 0x1e100 0x100>; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - }; - - global_timer: timer@1e200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1e200 0x20>; - interrupts = ; - clocks = <&axi_clk>; - }; - - local_timer: local-timer@1e600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e600 0x20>; - interrupts = ; - clocks = <&axi_clk>; - }; - - twd_watchdog: watchdog@1e620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1e620 0x20>; - interrupts = ; - }; - - armpll: armpll { - #clock-cells = <0>; - compatible = "brcm,bcm63138-armpll"; - clocks = <&periph_clk>; - reg = <0x20000 0xf00>; - }; - - pmb0: reset-controller@4800c0 { - compatible = "brcm,bcm63138-pmb"; - reg = <0x4800c0 0x10>; - #reset-cells = <2>; - }; - - pmb1: reset-controller@4800e0 { - compatible = "brcm,bcm63138-pmb"; - reg = <0x4800e0 0x10>; - #reset-cells = <2>; - }; - }; - - /* Legacy UBUS base */ - ubus@fffe8000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffe8000 0x8100>; - - timer: timer@80 { - compatible = "brcm,bcm6328-timer", "syscon"; - reg = <0x80 0x3c>; - }; - - serial0: serial@600 { - compatible = "brcm,bcm6345-uart"; - reg = <0x600 0x1b>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "periph"; - status = "disabled"; - }; - - serial1: serial@620 { - compatible = "brcm,bcm6345-uart"; - reg = <0x620 0x1b>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "periph"; - status = "disabled"; - }; - - nand: nand@2000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; - reg = <0x2000 0x600>, <0xf0 0x10>; - reg-names = "nand", "nand-int-base"; - status = "disabled"; - interrupts = ; - interrupt-names = "nand"; - }; - - bootlut: bootlut@8000 { - compatible = "brcm,bcm63138-bootlut"; - reg = <0x8000 0x50>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&timer>; - offset = <0x34>; - mask = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/software/linux/kernel/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts deleted file mode 100644 index 0bb8d17e4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts +++ /dev/null @@ -1,37 +0,0 @@ -/dts-v1/; -#include "bcm7445.dtsi" - -/ { - model = "Broadcom STB (bcm7445), SVMB reference board"; - compatible = "brcm,bcm7445", "brcm,brcmstb"; - - memory { - device_type = "memory"; - reg = <0x00 0x00000000 0x00 0x40000000>, - <0x00 0x40000000 0x00 0x40000000>, - <0x00 0x80000000 0x00 0x40000000>; - }; -}; - -&nand { - status = "okay"; - - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <1>; - nand-ecc-step-size = <512>; - nand-ecc-strength = <8>; - nand-on-flash-bbt; - - #size-cells = <2>; - #address-cells = <2>; - - flash1.rootfs0@0 { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - flash1.rootfs1@80000000 { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm7445.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm7445.dtsi deleted file mode 100644 index 479132196..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm7445.dtsi +++ /dev/null @@ -1,316 +0,0 @@ -#include - -#include "skeleton.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "Broadcom STB (bcm7445)"; - compatible = "brcm,bcm7445", "brcm,brcmstb"; - interrupt-parent = <&gic>; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <0>; - }; - - cpu@1 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <1>; - }; - - cpu@2 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <2>; - }; - - cpu@3 { - compatible = "brcm,brahma-b15"; - device_type = "cpu"; - enable-method = "brcm,brahma-b15"; - reg = <3>; - }; - }; - - gic: interrupt-controller@ffd00000 { - compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic"; - reg = <0x00 0xffd01000 0x00 0x1000>, - <0x00 0xffd02000 0x00 0x2000>, - <0x00 0xffd04000 0x00 0x2000>, - <0x00 0xffd06000 0x00 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - rdb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x00 0xf0000000 0x1000000>; - - serial@40ab00 { - compatible = "ns16550a"; - reg = <0x40ab00 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <81000000>; - }; - - sun_top_ctrl: syscon@404000 { - compatible = "brcm,bcm7445-sun-top-ctrl", - "syscon"; - reg = <0x404000 0x51c>; - }; - - hif_cpubiuctrl: syscon@3e2400 { - compatible = "brcm,bcm7445-hif-cpubiuctrl", - "syscon"; - reg = <0x3e2400 0x5b4>; - }; - - hif_continuation: syscon@452000 { - compatible = "brcm,bcm7445-hif-continuation", - "syscon"; - reg = <0x452000 0x100>; - }; - - irq0_intc: interrupt-controller@40a780 { - compatible = "brcm,bcm7120-l2-intc"; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - reg = <0x40a780 0x8>; - interrupt-controller; - interrupts = , - ; - brcm,int-map-mask = <0x25c>, <0x7000000>; - brcm,int-fwd-mask = <0x70000>; - }; - - irq0_aon_intc: interrupt-controller@417280 { - compatible = "brcm,bcm7120-l2-intc"; - reg = <0x417280 0x8>; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = , - , - ; - brcm,int-map-mask = <0x1e3 0x18000000 0x100000>; - brcm,int-fwd-mask = <0x0>; - brcm,irq-can-wake; - }; - - hif_intr2_intc: interrupt-controller@3e1000 { - compatible = "brcm,l2-intc"; - reg = <0x3e1000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-names = "hif"; - }; - - aon_pm_l2_intc: interrupt-controller@410640 { - compatible = "brcm,l2-intc"; - reg = <0x410640 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = ; - interrupt-parent = <&gic>; - brcm,irq-can-wake; - }; - - aon-ctrl@410000 { - compatible = "brcm,brcmstb-aon-ctrl"; - reg = <0x410000 0x200>, <0x410200 0x400>; - reg-names = "aon-ctrl", "aon-sram"; - }; - - nand: nand@3e2800 { - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; - reg-names = "nand", "flash-dma"; - reg = <0x3e2800 0x600>, <0x3e3000 0x2c>; - interrupt-parent = <&hif_intr2_intc>; - interrupts = <24>, <4>; - interrupt-names = "nand_ctlrdy", "flash_dma_done"; - }; - - sata@45a000 { - compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0x45a000 0xa9c>, <0x458040 0x24>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy1>; - }; - }; - - sata_phy: sata-phy@458100 { - compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; - reg = <0x458100 0x1f00>; - reg-names = "phy"; - #address-cells = <0x1>; - #size-cells = <0x0>; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - sata_phy1: sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - upg_gio: gpio@40a700 { - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - reg = <0x40a700 0x80>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - interrupt-parent = <&irq0_intc>; - interrupts = <6>; - brcm,gpio-bank-widths = <32 32 32 24>; - }; - - upg_gio_aon: gpio@4172c0 { - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - reg = <0x4172c0 0x40>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - interrupts-extended = <&irq0_aon_intc 0x6>, - <&aon_pm_l2_intc 0x5>; - wakeup-source; - brcm,gpio-bank-widths = <18 4>; - }; - - }; - - memory_controllers { - compatible = "simple-bus"; - ranges = <0x0 0x0 0xf1100000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - - memc@0 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - - memc@1 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - - memc@2 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x100000 0x80000>; - - memc-ddr@2000 { - compatible = "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x800>; - }; - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0x6000 0x21c>; - }; - - shimphy@8000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0x8000 0xe4>; - }; - }; - }; - - sram@ffe00000 { - compatible = "brcm,boot-sram", "mmio-sram"; - reg = <0x0 0xffe00000 0x0 0x10000>; - }; - - smpboot { - compatible = "brcm,brcmstb-smpboot"; - syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; - syscon-cont = <&hif_continuation>; - }; - - reboot { - compatible = "brcm,brcmstb-reboot"; - syscon = <&sun_top_ctrl 0x304 0x308>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm911360_entphn.dts b/software/linux/kernel/arch/arm/boot/dts/bcm911360_entphn.dts deleted file mode 100644 index 8b3800f46..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm911360_entphn.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "dt-bindings/input/input.h" - -/ { - model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; - compatible = "brcm,bcm11360", "brcm,cygnus"; - - chosen { - stdout-path = &uart3; - bootargs = "console=ttyS0,115200"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - hook { - label = "HOOK"; - linux,code = ; - gpios = <&gpio_asiu 48 0>; - }; - }; -}; - -&uart3 { - status = "okay"; -}; - -&nand { - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm911360k.dts b/software/linux/kernel/arch/arm/boot/dts/bcm911360k.dts deleted file mode 100644 index 091c73a46..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm911360k.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" - -/ { - model = "Cygnus SVK (BCM911360K)"; - compatible = "brcm,bcm11360", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm94708.dts b/software/linux/kernel/arch/arm/boot/dts/bcm94708.dts deleted file mode 100644 index 251a486f2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm94708.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM94708)"; - compatible = "brcm,bcm94708", "brcm,bcm4708"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm94709.dts b/software/linux/kernel/arch/arm/boot/dts/bcm94709.dts deleted file mode 100644 index b16cac929..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm94709.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM94709)"; - compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm953012er.dts b/software/linux/kernel/arch/arm/boot/dts/bcm953012er.dts deleted file mode 100644 index 0a9abecf9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm953012er.dts +++ /dev/null @@ -1,104 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" - -/ { - model = "NorthStar Enterprise Router (BCM953012ER)"; - compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x8000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - - restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&spi_nor { - status = "okay"; -}; - -&srab { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "port0"; - }; - - port@1 { - reg = <1>; - label = "port1"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm953012k.dts b/software/linux/kernel/arch/arm/boot/dts/bcm953012k.dts deleted file mode 100644 index 6208e85ac..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm953012k.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm4708.dtsi" - -/ { - model = "NorthStar SVK (BCM953012K)"; - compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x80000000 0x10000000>; - }; -}; - -&uart0 { - clock-frequency = <62499840>; - status = "okay"; -}; - -&uart1 { - clock-frequency = <62499840>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958300k.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958300k.dts deleted file mode 100644 index b4a1392bd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958300k.dts +++ /dev/null @@ -1,77 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2014 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "bcm9hmidc.dtsi" - -/ { - model = "Cygnus SVK (BCM958300K)"; - compatible = "brcm,bcm58300", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&nand { - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958305k.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958305k.dts deleted file mode 100644 index 337868332..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958305k.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-cygnus.dtsi" -#include "bcm9hmidc.dtsi" - -/ { - model = "Cygnus Wireless Audio (BCM958305K)"; - compatible = "brcm,bcm58305", "brcm,cygnus"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&nand { - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958522er.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958522er.dts deleted file mode 100644 index 417f65738..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958522er.dts +++ /dev/null @@ -1,131 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958522ER)"; - compatible = "brcm,bcm58522", "brcm,nsp"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 2/3 support needed to be complete */ - -&amac0 { - status = "okay"; -}; - - -&amac1 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958525er.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958525er.dts deleted file mode 100644 index 5279b769f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958525er.dts +++ /dev/null @@ -1,143 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958525ER)"; - compatible = "brcm,bcm58525", "brcm,nsp"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 2/3 support needed to be complete */ - -&amac0 { - status = "okay"; -}; - - -&amac1 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958525xmc.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958525xmc.dts deleted file mode 100644 index 872882bd0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958525xmc.dts +++ /dev/null @@ -1,152 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus XMC (BCM958525xmc)"; - compatible = "brcm,bcm58525", "brcm,nsp"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 31 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -&i2c0 { - temperature-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "st,m41t81"; - reg = <0x68>; - }; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -/* XHCI, MMC, and Ethernet support needed to be complete */ - -&uart0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958622hr.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958622hr.dts deleted file mode 100644 index a340e1d93..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958622hr.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958622HR)"; - compatible = "brcm,bcm58622", "brcm,nsp"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 2/3 and SLIC support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&srab { - compatible = "brcm,bcm58622-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@5 { - ethernet = <&amac0>; - label = "cpu"; - reg = <5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958623hr.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958623hr.dts deleted file mode 100644 index 226b652cc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958623hr.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958623HR)"; - compatible = "brcm,bcm58623", "brcm,nsp"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 2/3 and SLIC support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&srab { - compatible = "brcm,bcm58623-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@5 { - ethernet = <&amac0>; - label = "cpu"; - reg = <5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958625hr.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958625hr.dts deleted file mode 100644 index a1658d072..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958625hr.dts +++ /dev/null @@ -1,181 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright (c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM958625HR)"; - compatible = "brcm,bcm58625", "brcm,nsp"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&amac0 { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@5 { - ethernet = <&amac0>; - label = "cpu"; - reg = <5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm958625k.dts b/software/linux/kernel/arch/arm/boot/dts/bcm958625k.dts deleted file mode 100644 index 05c5f98c8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm958625k.dts +++ /dev/null @@ -1,141 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" - -/ { - model = "NorthStar Plus SVK (BCM958625K)"; - compatible = "brcm,bcm58625", "brcm,nsp"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&amac0 { - status = "okay"; -}; - -&amac1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@1 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@2 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@3 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm963138dvt.dts b/software/linux/kernel/arch/arm/boot/dts/bcm963138dvt.dts deleted file mode 100644 index 370aa2cfd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm963138dvt.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Broadcom BCM63138 Reference Board DTS - */ - -/dts-v1/; - -#include "bcm63138.dtsi" - -/ { - compatible = "brcm,BCM963138DVT", "brcm,bcm63138"; - model = "Broadcom BCM963138DVT"; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; - }; - - memory { - reg = <0x0 0x08000000>; - }; - -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - brcm,nand-oob-sectors-size = <16>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm988312hr.dts b/software/linux/kernel/arch/arm/boot/dts/bcm988312hr.dts deleted file mode 100644 index ed05e33d5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm988312hr.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm-nsp.dtsi" -#include - -/ { - model = "NorthStar Plus SVK (BCM988312HR)"; - compatible = "brcm,bcm88312", "brcm,nsp"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; - open-source; - priority = <200>; - }; -}; - -/* USB 2/3 support needed to be complete */ - -&amac0 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - - brcm,nand-oob-sector-size = <27>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00200000>; - read-only; - }; - partition@200000 { - label = "nenv"; - reg = <0x00200000 0x00400000>; - }; - partition@600000 { - label = "nsystem"; - reg = <0x00600000 0x00a00000>; - }; - partition@1000000 { - label = "nrootfs"; - reg = <0x01000000 0x03000000>; - }; - partition@4000000 { - label = "ncustfs"; - reg = <0x04000000 0x3c000000>; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&srab { - compatible = "brcm,bcm88312-srab", "brcm,nsp-srab"; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "port0"; - reg = <0>; - }; - - port@1 { - label = "port1"; - reg = <1>; - }; - - port@2 { - label = "port2"; - reg = <2>; - }; - - port@3 { - label = "port3"; - reg = <3>; - }; - - port@4 { - label = "port4"; - reg = <4>; - }; - - port@5 { - ethernet = <&amac0>; - label = "cpu"; - reg = <5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/bcm9hmidc.dtsi b/software/linux/kernel/arch/arm/boot/dts/bcm9hmidc.dtsi deleted file mode 100644 index 65397c088..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/bcm9hmidc.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Broadcom human machine interface daughter card (bcm9hmidc) installed on - * bcm958300k/bcm958305k boards - */ - -&touchscreen { - touchscreen-inverted-x; - touchscreen-inverted-y; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/software/linux/kernel/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts deleted file mode 100644 index 1c475796d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Device Tree file for Sony NSZ-GS7 - * - * Sebastian Hesselbarth - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "berlin2.dtsi" - -/ { - model = "Sony NSZ-GS7"; - compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; -}; - -&ahci { status = "okay"; }; - -ð1 { status = "okay"; }; - -/* Unpopulated SATA plug on solder side */ -&sata0 { status = "okay"; }; - -&sata_phy { status = "okay"; }; - -/* Samsung M8G2FA 8GB eMMC */ -&sdhci2 { - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&uart0 { status = "okay"; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/berlin2.dtsi b/software/linux/kernel/arch/arm/boot/dts/berlin2.dtsi deleted file mode 100644 index 425c48971..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/berlin2.dtsi +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC - * - * Sebastian Hesselbarth - * - * based on GPL'ed 2.6 kernel sources - * (c) Marvell International Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - model = "Marvell Armada 1500 (BG2) SoC"; - compatible = "marvell,berlin2", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,berlin-smp"; - - cpu@0 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu@1 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - }; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - ranges = <0 0xf7000000 0x1000000>; - - sdhci0: sdhci@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci1: sdhci@ab0800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0800 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci2: sdhci@ab1000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab1000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; - clock-names = "io", "core"; - pinctrl-0 = <&emmc_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - l2: l2-cache-controller@ac0000 { - compatible = "marvell,tauros3-cache", "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - scu: snoop-control-unit@ad0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xad0000 0x58>; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - eth1: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH1>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy1>; - status = "disabled"; - - ethphy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - cpu-ctrl@dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xdd0000 0x10000>; - }; - - eth0: ethernet@e50000 { - compatible = "marvell,pxa168-eth"; - reg = <0xe50000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@0400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@0800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@0c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - interrupts = <8>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - interrupts = <9>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - interrupts = <10>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - interrupts = <11>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - interrupts = <12>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - interrupts = <13>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - interrupts = <14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - interrupts = <15>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - ahci: sata@e90000 { - compatible = "marvell,berlin2-ahci", "generic-ahci"; - reg = <0xe90000 0x1000>; - interrupts = ; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - status = "disabled"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - status = "disabled"; - }; - }; - - sata_phy: phy@e900a0 { - compatible = "marvell,berlin2-sata-phy"; - reg = <0xe900a0 0x200>; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - #phy-cells = <1>; - status = "disabled"; - - sata-phy@0 { - reg = <0>; - }; - - sata-phy@1 { - reg = <1>; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - chip_clk: clock { - compatible = "marvell,berlin2-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2-soc-pinctrl"; - - emmc_pmux: emmc-pmux { - groups = "G26"; - function = "emmc"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - }; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <11>; - }; - }; - - uart0: serial@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <8>; - clocks = <&refclk>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <9>; - clocks = <&refclk>; - pinctrl-0 = <&uart1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@b000 { - compatible = "snps,dw-apb-uart"; - reg = <0xb000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <10>; - clocks = <&refclk>; - pinctrl-0 = <&uart2_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2-system-pinctrl"; - uart0_pmux: uart0-pmux { - groups = "GSM4"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM5"; - function = "uart1"; - }; - uart2_pmux: uart2-pmux { - groups = "GSM3"; - function = "uart2"; - }; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/software/linux/kernel/arch/arm/boot/dts/berlin2cd-google-chromecast.dts deleted file mode 100644 index ca24def0c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/berlin2cd-google-chromecast.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Device Tree file for Google Chromecast - * - * Sebastian Hesselbarth - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "berlin2cd.dtsi" -#include - -/ { - model = "Google Chromecast"; - compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - leds { - compatible = "gpio-leds"; - - white { - label = "white"; - gpios = <&portc 1 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - red { - label = "red"; - gpios = <&portc 2 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; - -/* - * AzureWave AW-NH387 (Marvell 88W8787) - * 802.11b/g/n + Bluetooth 2.1 - */ -&sdhci0 { - non-removable; - status = "okay"; -}; - -&uart0 { status = "okay"; }; - -&usb_phy1 { status = "okay"; }; - -&usb1 { status = "okay"; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/berlin2cd.dtsi b/software/linux/kernel/arch/arm/boot/dts/berlin2cd.dtsi deleted file mode 100644 index 4fe1574d0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/berlin2cd.dtsi +++ /dev/null @@ -1,494 +0,0 @@ -/* - * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC - * - * Sebastian Hesselbarth - * - * based on GPL'ed 2.6 kernel sources - * (c) Marvell International Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - model = "Marvell Armada 1500-mini (BG2CD) SoC"; - compatible = "marvell,berlin2cd", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - operating-points = < - /* kHz uV */ - 800000 1200000 - 600000 1200000 - >; - }; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - ranges = <0 0xf7000000 0x1000000>; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - sdhci0: sdhci@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - l2: l2-cache-controller@ac0000 { - compatible = "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - interrupts = ; - clocks = <&chip_clk CLKID_TWD>; - }; - - usb_phy0: usb-phy@b74000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb74000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x178 23>; - status = "disabled"; - }; - - usb_phy1: usb-phy@b78000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb78000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x178 24>; - status = "disabled"; - }; - - eth1: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH1>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy1>; - status = "disabled"; - - ethphy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - eth0: ethernet@e50000 { - compatible = "marvell,pxa168-eth"; - reg = <0xe50000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@0400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@0800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@0c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - interrupts = <8>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - interrupts = <9>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "okay"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - interrupts = <10>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - interrupts = <11>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - interrupts = <12>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - interrupts = <13>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - interrupts = <14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - interrupts = <15>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - chip_clk: clock { - compatible = "marvell,berlin2-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2cd-soc-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "G6"; - function = "uart0"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - usb0: usb@ed0000 { - compatible = "chipidea,usb2"; - reg = <0xed0000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_USB0>; - phys = <&usb_phy0>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb1: usb@ee0000 { - compatible = "chipidea,usb2"; - reg = <0xee0000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_USB1>; - phys = <&usb_phy1>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - status = "disabled"; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - status = "disabled"; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - }; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - }; - }; - - uart0: serial@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <8>; - clocks = <&refclk>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - reg-shift = <2>; - reg-io-width = <1>; - interrupts = <9>; - clocks = <&refclk>; - status = "disabled"; - }; - - sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2cd-system-pinctrl"; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/software/linux/kernel/arch/arm/boot/dts/berlin2q-marvell-dmp.dts deleted file mode 100644 index f48530884..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (C) 2014 Antoine Ténart - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include "berlin2q.dtsi" - -/ { - model = "Marvell BG2-Q DMP"; - compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x80000000>; - }; - - choosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb2_vbus: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_sdio1_vmmc: regulator@3 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "sdio1_vmmc"; - enable-active-high; - regulator-boot-on; - gpio = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - - reg_sdio1_vqmmc: regulator@4 { - compatible = "regulator-gpio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "sdio1_vqmmc"; - regulator-type = "voltage"; - enable-active-high; - gpios = <&portb 16 GPIO_ACTIVE_HIGH>; - states = <3300000 0x1 - 1800000 0x0>; - }; - }; -}; - -&soc_pinctrl { - sd1gpio_pmux: sd1pwr-pmux { - groups = "G23", "G32"; - function = "gpio"; - }; -}; - -&sdhci1 { - vmmc-supply = <®_sdio1_vmmc>; - vqmmc-supply = <®_sdio1_vqmmc>; - cd-gpios = <&portc 30 GPIO_ACTIVE_LOW>; - wp-gpios = <&portd 0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&sd1gpio_pmux>, <&sd1_pmux>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_phy0 { - status = "okay"; -}; - -&usb_phy2 { - status = "okay"; -}; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; - -&usb2 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -ð0 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/berlin2q.dtsi b/software/linux/kernel/arch/arm/boot/dts/berlin2q.dtsi deleted file mode 100644 index e54822969..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/berlin2q.dtsi +++ /dev/null @@ -1,658 +0,0 @@ -/* - * Copyright (C) 2014 Antoine Ténart - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - model = "Marvell Armada 1500 pro (BG2-Q) SoC"; - compatible = "marvell,berlin2q", "marvell,berlin"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,berlin-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - - clocks = <&chip_clk CLKID_CPU>; - clock-latency = <100000>; - /* Can be modified by the bootloader */ - operating-points = < - /* kHz uV */ - 1200000 1200000 - 1000000 1200000 - 800000 1200000 - 600000 1200000 - >; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <3>; - }; - }; - - refclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xf7000000 0x1000000>; - interrupt-parent = <&gic>; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - }; - - sdhci0: sdhci@ab0000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci1: sdhci@ab0800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab0800 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - interrupts = ; - status = "disabled"; - }; - - sdhci2: sdhci@ab1000 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xab1000 0x200>; - interrupts = ; - clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>; - clock-names = "io", "core"; - status = "disabled"; - }; - - l2: l2-cache-controller@ac0000 { - compatible = "arm,pl310-cache"; - reg = <0xac0000 0x1000>; - cache-level = <2>; - arm,data-latency = <2 2 2>; - arm,tag-latency = <2 2 2>; - }; - - scu: snoop-control-unit@ad0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xad0000 0x58>; - }; - - local-timer@ad0600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xad0600 0x20>; - clocks = <&chip_clk CLKID_TWD>; - interrupts = ; - }; - - gic: interrupt-controller@ad1000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xad1000 0x1000>, <0xad0100 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - usb_phy2: phy@a2f400 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xa2f400 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 14>; - status = "disabled"; - }; - - usb2: usb@a30000 { - compatible = "chipidea,usb2"; - reg = <0xa30000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB2>; - phys = <&usb_phy2>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb_phy0: phy@b74000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb74000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 12>; - status = "disabled"; - }; - - usb_phy1: phy@b78000 { - compatible = "marvell,berlin2cd-usb-phy"; - reg = <0xb78000 0x128>; - #phy-cells = <0>; - resets = <&chip_rst 0x104 13>; - status = "disabled"; - }; - - eth0: ethernet@b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xb90000 0x10000>; - clocks = <&chip_clk CLKID_GETH0>; - interrupts = ; - /* set by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - #address-cells = <1>; - #size-cells = <0>; - phy-connection-type = "mii"; - phy-handle = <ðphy0>; - status = "disabled"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - cpu-ctrl@dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xdd0000 0x10000>; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@0400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@0800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@0c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - i2c0: i2c@1400 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1400 0x100>; - interrupts = <4>; - clocks = <&chip_clk CLKID_CFG>; - pinctrl-0 = <&twsi0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c1: i2c@1800 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1800 0x100>; - interrupts = <5>; - clocks = <&chip_clk CLKID_CFG>; - pinctrl-0 = <&twsi1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - timer0: timer@2c00 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c00 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - interrupts = <8>; - }; - - timer1: timer@2c14 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c14 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - }; - - timer2: timer@2c28 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c28 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer3: timer@2c3c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c3c 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer4: timer@2c50 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c50 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer5: timer@2c64 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c64 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer6: timer@2c78 { - compatible = "snps,dw-apb-timer"; - reg = <0x2c78 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - timer7: timer@2c8c { - compatible = "snps,dw-apb-timer"; - reg = <0x2c8c 0x14>; - clocks = <&chip_clk CLKID_CFG>; - clock-names = "timer"; - status = "disabled"; - }; - - aic: interrupt-controller@3800 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3800 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>, <0xdd0170 0x10>; - - chip_clk: clock { - compatible = "marvell,berlin2q-clk"; - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; - }; - - soc_pinctrl: pin-controller { - compatible = "marvell,berlin2q-soc-pinctrl"; - - sd1_pmux: sd1-pmux { - groups = "G31"; - function = "sd1"; - }; - - twsi0_pmux: twsi0-pmux { - groups = "G6"; - function = "twsi0"; - }; - - twsi1_pmux: twsi1-pmux { - groups = "G7"; - function = "twsi1"; - }; - }; - - chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; - }; - }; - - ahci: sata@e90000 { - compatible = "marvell,berlin2q-ahci", "generic-ahci"; - reg = <0xe90000 0x1000>; - interrupts = ; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - status = "disabled"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - status = "disabled"; - }; - }; - - sata_phy: phy@e900a0 { - compatible = "marvell,berlin2q-sata-phy"; - reg = <0xe900a0 0x200>; - clocks = <&chip_clk CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - #phy-cells = <1>; - status = "disabled"; - - sata-phy@0 { - reg = <0>; - }; - - sata-phy@1 { - reg = <1>; - }; - }; - - usb0: usb@ed0000 { - compatible = "chipidea,usb2"; - reg = <0xed0000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB0>; - phys = <&usb_phy0>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - usb1: usb@ee0000 { - compatible = "chipidea,usb2"; - reg = <0xee0000 0x10000>; - interrupts = ; - clocks = <&chip_clk CLKID_USB1>; - phys = <&usb_phy1>; - phy-names = "usb-phy"; - status = "disabled"; - }; - - pwm: pwm@f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - wdt0: watchdog@1000 { - compatible = "snps,dw-wdt"; - reg = <0x1000 0x100>; - clocks = <&refclk>; - interrupts = <0>; - }; - - wdt1: watchdog@2000 { - compatible = "snps,dw-wdt"; - reg = <0x2000 0x100>; - clocks = <&refclk>; - interrupts = <1>; - }; - - wdt2: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&refclk>; - interrupts = <2>; - }; - - sm_gpio1: gpio@5000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x5000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - i2c2: i2c@7000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7000 0x100>; - interrupts = <6>; - clocks = <&refclk>; - pinctrl-0 = <&twsi2_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c3: i2c@8000 { - compatible = "snps,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x8000 0x100>; - interrupts = <7>; - clocks = <&refclk>; - pinctrl-0 = <&twsi3_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart0: uart@9000 { - compatible = "snps,dw-apb-uart"; - reg = <0x9000 0x100>; - interrupts = <8>; - clocks = <&refclk>; - reg-shift = <2>; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: uart@a000 { - compatible = "snps,dw-apb-uart"; - reg = <0xa000 0x100>; - interrupts = <9>; - clocks = <&refclk>; - reg-shift = <2>; - pinctrl-0 = <&uart1_pmux>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sm_gpio0: gpio@c000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xc000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - sysctrl: pin-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - sys_pinctrl: pin-controller { - compatible = "marvell,berlin2q-system-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "GSM12"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM14"; - function = "uart1"; - }; - - twsi2_pmux: twsi2-pmux { - groups = "GSM13"; - function = "twsi2"; - }; - - twsi3_pmux: twsi3-pmux { - groups = "GSM14"; - function = "twsi3"; - }; - }; - - adc: adc { - compatible = "marvell,berlin2-adc"; - interrupts = <12>, <14>; - interrupt-names = "adc", "tsen"; - }; - }; - - sic: interrupt-controller@e000 { - compatible = "snps,dw-apb-ictl"; - reg = <0xe000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/compulab-sb-som.dtsi b/software/linux/kernel/arch/arm/boot/dts/compulab-sb-som.dtsi deleted file mode 100644 index 4af1adfee..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/compulab-sb-som.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - model = "CompuLab SB-SOM"; - compatible = "compulab,sb-som"; - - vsb_3v3: fixedregulator-v3_3 { - compatible = "regulator-fixed"; - regulator-name = "vsb_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - }; - - lcd0: display { - compatible = "startek,startek-kd050c", "panel-dpi"; - label = "lcd"; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <43>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - hdmi_conn: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/cros-adc-thermistors.dtsi b/software/linux/kernel/arch/arm/boot/dts/cros-adc-thermistors.dtsi deleted file mode 100644 index ce7fca76b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/cros-adc-thermistors.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Thermistor dts fragment for devices that use Thermistors as - * children of the IIO based ADC. - * - * Currently, used by Exynos5420 based Peach PIT and - * Exynos5800 based Peach PI. - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -&adc { - thermistor3 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 3>; - }; - thermistor4 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 4>; - }; - thermistor5 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 5>; - }; - thermistor6 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 6>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/cros-ec-keyboard.dtsi b/software/linux/kernel/arch/arm/boot/dts/cros-ec-keyboard.dtsi deleted file mode 100644 index c04510517..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/cros-ec-keyboard.dtsi +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Keyboard dts fragment for devices that use cros-ec-keyboard - * - * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -&cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,needs-ghost-filter; - - linux,keymap = < - MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) - MATRIX_KEY(0x00, 0x02, KEY_F1) - MATRIX_KEY(0x00, 0x03, KEY_B) - MATRIX_KEY(0x00, 0x04, KEY_F10) - MATRIX_KEY(0x00, 0x05, KEY_RO) - MATRIX_KEY(0x00, 0x06, KEY_N) - MATRIX_KEY(0x00, 0x08, KEY_EQUAL) - MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) - - MATRIX_KEY(0x01, 0x01, KEY_ESC) - MATRIX_KEY(0x01, 0x02, KEY_F4) - MATRIX_KEY(0x01, 0x03, KEY_G) - MATRIX_KEY(0x01, 0x04, KEY_F7) - MATRIX_KEY(0x01, 0x06, KEY_H) - MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) - MATRIX_KEY(0x01, 0x09, KEY_F9) - MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) - MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) - - MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) - MATRIX_KEY(0x02, 0x01, KEY_TAB) - MATRIX_KEY(0x02, 0x02, KEY_F3) - MATRIX_KEY(0x02, 0x03, KEY_T) - MATRIX_KEY(0x02, 0x04, KEY_F6) - MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) - MATRIX_KEY(0x02, 0x06, KEY_Y) - MATRIX_KEY(0x02, 0x07, KEY_102ND) - MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) - MATRIX_KEY(0x02, 0x09, KEY_F8) - MATRIX_KEY(0x02, 0x0a, KEY_YEN) - - MATRIX_KEY(0x03, 0x01, KEY_GRAVE) - MATRIX_KEY(0x03, 0x02, KEY_F2) - MATRIX_KEY(0x03, 0x03, KEY_5) - MATRIX_KEY(0x03, 0x04, KEY_F5) - MATRIX_KEY(0x03, 0x06, KEY_6) - MATRIX_KEY(0x03, 0x08, KEY_MINUS) - MATRIX_KEY(0x03, 0x09, KEY_F13) - MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) - MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) - - MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) - MATRIX_KEY(0x04, 0x01, KEY_A) - MATRIX_KEY(0x04, 0x02, KEY_D) - MATRIX_KEY(0x04, 0x03, KEY_F) - MATRIX_KEY(0x04, 0x04, KEY_S) - MATRIX_KEY(0x04, 0x05, KEY_K) - MATRIX_KEY(0x04, 0x06, KEY_J) - MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) - MATRIX_KEY(0x04, 0x09, KEY_L) - MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) - MATRIX_KEY(0x04, 0x0b, KEY_ENTER) - - MATRIX_KEY(0x05, 0x01, KEY_Z) - MATRIX_KEY(0x05, 0x02, KEY_C) - MATRIX_KEY(0x05, 0x03, KEY_V) - MATRIX_KEY(0x05, 0x04, KEY_X) - MATRIX_KEY(0x05, 0x05, KEY_COMMA) - MATRIX_KEY(0x05, 0x06, KEY_M) - MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) - MATRIX_KEY(0x05, 0x08, KEY_SLASH) - MATRIX_KEY(0x05, 0x09, KEY_DOT) - MATRIX_KEY(0x05, 0x0b, KEY_SPACE) - - MATRIX_KEY(0x06, 0x01, KEY_1) - MATRIX_KEY(0x06, 0x02, KEY_3) - MATRIX_KEY(0x06, 0x03, KEY_4) - MATRIX_KEY(0x06, 0x04, KEY_2) - MATRIX_KEY(0x06, 0x05, KEY_8) - MATRIX_KEY(0x06, 0x06, KEY_7) - MATRIX_KEY(0x06, 0x08, KEY_0) - MATRIX_KEY(0x06, 0x09, KEY_9) - MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) - MATRIX_KEY(0x06, 0x0b, KEY_DOWN) - MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) - - MATRIX_KEY(0x07, 0x01, KEY_Q) - MATRIX_KEY(0x07, 0x02, KEY_E) - MATRIX_KEY(0x07, 0x03, KEY_R) - MATRIX_KEY(0x07, 0x04, KEY_W) - MATRIX_KEY(0x07, 0x05, KEY_I) - MATRIX_KEY(0x07, 0x06, KEY_U) - MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) - MATRIX_KEY(0x07, 0x08, KEY_P) - MATRIX_KEY(0x07, 0x09, KEY_O) - MATRIX_KEY(0x07, 0x0b, KEY_UP) - MATRIX_KEY(0x07, 0x0c, KEY_LEFT) - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/cros-ec-sbs.dtsi b/software/linux/kernel/arch/arm/boot/dts/cros-ec-sbs.dtsi deleted file mode 100644 index 71f5c5ecc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/cros-ec-sbs.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Smart battery dts fragment for devices that use cros-ec-sbs - * - * Copyright (c) 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&i2c_tunnel { - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/cx92755.dtsi b/software/linux/kernel/arch/arm/boot/dts/cx92755.dtsi deleted file mode 100644 index a5a23c376..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/cx92755.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Device Tree Include file for the Conexant Digicolor CX92755 SoC - * - * Author: Baruch Siach - * - * Copyright (C) 2014 Paradox Innovation Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -/ { - compatible = "cnxt,cx92755"; - - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - - main_clk: main_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - intc: interrupt-controller@f0000040 { - compatible = "cnxt,cx92755-ic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf0000040 0x40>; - syscon = <&uc_regs>; - }; - - timer@f0000fc0 { - compatible = "cnxt,cx92755-timer"; - reg = <0xf0000fc0 0x40>; - interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; - clocks = <&main_clk>; - }; - - rtc@f0000c30 { - compatible = "cnxt,cx92755-rtc"; - reg = <0xf0000c30 0x18>; - interrupts = <25>; - }; - - watchdog@f0000fc0 { - compatible = "cnxt,cx92755-wdt"; - reg = <0xf0000fc0 0x8>; - clocks = <&main_clk>; - timeout-sec = <15>; - }; - - pinctrl: pinctrl@f0000e20 { - compatible = "cnxt,cx92755-pinctrl"; - reg = <0xf0000e20 0x100>; - gpio-controller; - #gpio-cells = <2>; - }; - - uc_regs: syscon@f00003a0 { - compatible = "cnxt,cx92755-uc", "syscon"; - reg = <0xf00003a0 0x10>; - }; - - uart0: uart@f0000740 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000740 0x20>; - clocks = <&main_clk>; - interrupts = <44>; - status = "disabled"; - }; - - uart1: uart@f0000760 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000760 0x20>; - clocks = <&main_clk>; - interrupts = <45>; - status = "disabled"; - }; - - uart2: uart@f0000780 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000780 0x20>; - clocks = <&main_clk>; - interrupts = <46>; - status = "disabled"; - }; - - i2c: i2c@f0000120 { - compatible = "cnxt,cx92755-i2c"; - reg = <0xf0000120 0x10>; - interrupts = <28>; - clocks = <&main_clk>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/cx92755_equinox.dts b/software/linux/kernel/arch/arm/boot/dts/cx92755_equinox.dts deleted file mode 100644 index 026f556c8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/cx92755_equinox.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Device Tree file for the Conexant Equinox CX92755 EVK - * - * Author: Baruch Siach - * - * Copyright (C) 2014 Paradox Innovation Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "cx92755.dtsi" - -/ { - model = "Conexant Equinox CX92755 EVK"; - compatible = "cnxt,equinox", "cnxt,cx92755"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - memory@0 { - reg = <0 0x8000000>; - device_type = "memory"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c { - status = "okay"; -}; - -&pinctrl { - uart0_default: uart0_active { - pins = "GP_O0", "GP_O1"; - function = "client_b"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/da850-enbw-cmc.dts b/software/linux/kernel/arch/arm/boot/dts/da850-enbw-cmc.dts deleted file mode 100644 index 14dff3e18..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/da850-enbw-cmc.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Device Tree for AM1808 EnBW CMC board - * - * Copyright 2012 DENX Software Engineering GmbH - * Heiko Schocher - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -/dts-v1/; -#include "da850.dtsi" - -/ { - compatible = "enbw,cmc", "ti,da850"; - model = "EnBW CMC"; - - soc@1c00000 { - serial0: serial@42000 { - status = "okay"; - }; - serial1: serial@10c000 { - status = "okay"; - }; - serial2: serial@10d000 { - status = "okay"; - }; - mdio: mdio@224000 { - status = "okay"; - }; - eth0: ethernet@220000 { - status = "okay"; - }; - }; -}; - -&edma0 { - ti,edma-reserved-slot-ranges = <32 50>; -}; - -&edma1 { - ti,edma-reserved-slot-ranges = <32 90>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/da850-evm.dts b/software/linux/kernel/arch/arm/boot/dts/da850-evm.dts deleted file mode 100644 index 78492a0bb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/da850-evm.dts +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Device Tree for DA850 EVM board - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation, version 2. - */ -/dts-v1/; -#include "da850.dtsi" - -/ { - compatible = "ti,da850-evm", "ti,da850"; - model = "DA850/AM1808/OMAP-L138 EVM"; - - soc@1c00000 { - pmx_core: pinmux@14120 { - status = "okay"; - - mcasp0_pins: pinmux_mcasp0_pins { - pinctrl-single,bits = < - /* - * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, - * AFSR, AMUTE - */ - 0x00 0x11111111 0xffffffff - /* AXR11, AXR12 */ - 0x04 0x00011000 0x000ff000 - >; - }; - nand_pins: nand_pins { - pinctrl-single,bits = < - /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ - 0x1c 0x10110110 0xf0ff0ff0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; - }; - serial0: serial@42000 { - status = "okay"; - }; - serial1: serial@10c000 { - status = "okay"; - }; - serial2: serial@10d000 { - status = "okay"; - }; - rtc0: rtc@23000 { - status = "okay"; - }; - i2c0: i2c@22000 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - tps: tps@48 { - reg = <0x48>; - }; - tlv320aic3106: tlv320aic3106@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x18>; - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&vdcdc2_reg>; - /* Derived from VBAT: Baseboard 3.3V / 1.8V */ - AVDD-supply = <&vbat>; - DRVDD-supply = <&vbat>; - DVDD-supply = <&vbat>; - }; - - }; - wdt: wdt@21000 { - status = "okay"; - }; - mmc0: mmc@40000 { - max-frequency = <50000000>; - bus-width = <4>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - }; - spi1: spi@30e000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64"; - spi-max-frequency = <30000000>; - m25p,fast-read; - reg = <0>; - partition@0 { - label = "U-Boot-SPL"; - reg = <0x00000000 0x00010000>; - read-only; - }; - partition@1 { - label = "U-Boot"; - reg = <0x00010000 0x00080000>; - read-only; - }; - partition@2 { - label = "U-Boot-Env"; - reg = <0x00090000 0x00010000>; - read-only; - }; - partition@3 { - label = "Kernel"; - reg = <0x000a0000 0x00280000>; - }; - partition@4 { - label = "Filesystem"; - reg = <0x00320000 0x00400000>; - }; - partition@5 { - label = "MAC-Address"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; - }; - mdio: mdio@224000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - bus_freq = <2200000>; - }; - eth0: ethernet@220000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mii_pins>; - }; - gpio: gpio@226000 { - status = "okay"; - }; - }; - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "DA850/OMAP-L138 EVM"; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out"; - simple-audio-card,routing = - "LINE1L", "Line In", - "LINE1R", "Line In", - "Line Out", "LLOUT", - "Line Out", "RLOUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - system-clock-frequency = <24576000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24576000>; - }; - }; -}; - -/include/ "tps6507x.dtsi" - -&tps { - vdcdc1_2-supply = <&vbat>; - vdcdc3-supply = <&vbat>; - vldo1_2-supply = <&vbat>; - - regulators { - vdcdc1_reg: regulator@0 { - regulator-name = "VDCDC1_3.3V"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - }; - - vdcdc2_reg: regulator@1 { - regulator-name = "VDCDC2_3.3V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - vdcdc3_reg: regulator@2 { - regulator-name = "VDCDC3_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - ldo1_reg: regulator@3 { - regulator-name = "LDO1_1.8V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "LDO2_1.2V"; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1320000>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 0 - 0 0 0 1 - 2 0 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&edma0 { - ti,edma-reserved-slot-ranges = <32 50>; -}; - -&edma1 { - ti,edma-reserved-slot-ranges = <32 90>; -}; - -&aemif { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - status = "ok"; - cs3 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <3>; - - nand@2000000,0 { - compatible = "ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x02000000 0x02000000 - 1 0x00000000 0x00008000>; - - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/da850-lcdk.dts b/software/linux/kernel/arch/arm/boot/dts/da850-lcdk.dts deleted file mode 100644 index 7b8ab21fe..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/da850-lcdk.dts +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2016 BayLibre, Inc. - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "da850.dtsi" -#include - -/ { - model = "DA850/AM1808/OMAP-L138 LCDK"; - compatible = "ti,da850-lcdk", "ti,da850"; - - aliases { - serial2 = &serial2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0xc0000000 0x08000000>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "DA850/OMAP-L138 LCDK"; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out"; - simple-audio-card,routing = - "LINE1L", "Line In", - "LINE1R", "Line In", - "Line Out", "LLOUT", - "Line Out", "RLOUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - system-clock-frequency = <24576000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24576000>; - }; - }; -}; - -&pmx_core { - status = "okay"; - - mcasp0_pins: pinmux_mcasp0_pins { - pinctrl-single,bits = < - /* AHCLKX AFSX ACLKX */ - 0x00 0x00101010 0x00f0f0f0 - /* ARX13 ARX14 */ - 0x04 0x00000110 0x00000ff0 - >; - }; - - nand_pins: nand_pins { - pinctrl-single,bits = < - /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ - 0x1c 0x10110010 0xf0ff00f0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* - * EMA_D[8], EMA_D[9], EMA_D[10], - * EMA_D[11], EMA_D[12], EMA_D[13], - * EMA_D[14], EMA_D[15] - */ - 0x20 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; -}; - -&serial2 { - pinctrl-names = "default"; - pinctrl-0 = <&serial2_rxtx_pins>; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&rtc0 { - status = "okay"; -}; - -&gpio { - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - bus_freq = <2200000>; - status = "okay"; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&mii_pins>; - status = "okay"; -}; - -&mmc0 { - max-frequency = <50000000>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - status = "okay"; - - tlv320aic3106: tlv320aic3106@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x18>; - status = "okay"; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - status = "okay"; - - op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 1 2 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&aemif { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - status = "okay"; - cs3 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <3>; - - nand@2000000,0 { - compatible = "ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x02000000 0x02000000 - 1 0x00000000 0x00008000>; - - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - - ti,davinci-nand-buswidth = <16>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; - - /* - * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: - * "To boot from NAND Flash, the AIS should be written - * to NAND block 1 (NAND block 0 is not used by default)". - * The same doc mentions that for ROM "Silicon Revision 2.1", - * "Updated NAND boot mode to offer boot from block 0 or block 1". - * However the limitaion is left here by default for compatibility - * with older silicon and because it needs new boot pin settings - * not possible in stock LCDK. - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot env"; - reg = <0 0x020000>; - }; - partition@0x020000 { - /* The LCDK defaults to booting from this partition */ - label = "u-boot"; - reg = <0x020000 0x080000>; - }; - partition@0x0a0000 { - label = "free space"; - reg = <0x0a0000 0>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/da850.dtsi b/software/linux/kernel/arch/arm/boot/dts/da850.dtsi deleted file mode 100644 index f79e1b91c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/da850.dtsi +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Copyright 2012 DENX Software Engineering GmbH - * Heiko Schocher - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include "skeleton.dtsi" -#include - -/ { - arm { - #address-cells = <1>; - #size-cells = <1>; - ranges; - intc: interrupt-controller@fffee000 { - compatible = "ti,cp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <101>; - reg = <0xfffee000 0x2000>; - }; - }; - soc@1c00000 { - compatible = "simple-bus"; - model = "da850"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x01c00000 0x400000>; - interrupt-parent = <&intc>; - - pmx_core: pinmux@14120 { - compatible = "pinctrl-single"; - reg = <0x14120 0x50>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xf>; - status = "disabled"; - - serial0_rtscts_pins: pinmux_serial0_rtscts_pins { - pinctrl-single,bits = < - /* UART0_RTS UART0_CTS */ - 0x0c 0x22000000 0xff000000 - >; - }; - serial0_rxtx_pins: pinmux_serial0_rxtx_pins { - pinctrl-single,bits = < - /* UART0_TXD UART0_RXD */ - 0x0c 0x00220000 0x00ff0000 - >; - }; - serial1_rtscts_pins: pinmux_serial1_rtscts_pins { - pinctrl-single,bits = < - /* UART1_CTS UART1_RTS */ - 0x00 0x00440000 0x00ff0000 - >; - }; - serial1_rxtx_pins: pinmux_serial1_rxtx_pins { - pinctrl-single,bits = < - /* UART1_TXD UART1_RXD */ - 0x10 0x22000000 0xff000000 - >; - }; - serial2_rtscts_pins: pinmux_serial2_rtscts_pins { - pinctrl-single,bits = < - /* UART2_CTS UART2_RTS */ - 0x00 0x44000000 0xff000000 - >; - }; - serial2_rxtx_pins: pinmux_serial2_rxtx_pins { - pinctrl-single,bits = < - /* UART2_TXD UART2_RXD */ - 0x10 0x00220000 0x00ff0000 - >; - }; - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,bits = < - /* I2C0_SDA,I2C0_SCL */ - 0x10 0x00002200 0x0000ff00 - >; - }; - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,bits = < - /* I2C1_SDA, I2C1_SCL */ - 0x10 0x00440000 0x00ff0000 - >; - }; - mmc0_pins: pinmux_mmc_pins { - pinctrl-single,bits = < - /* MMCSD0_DAT[3] MMCSD0_DAT[2] - * MMCSD0_DAT[1] MMCSD0_DAT[0] - * MMCSD0_CMD MMCSD0_CLK - */ - 0x28 0x00222222 0x00ffffff - >; - }; - ehrpwm0a_pins: pinmux_ehrpwm0a_pins { - pinctrl-single,bits = < - /* EPWM0A */ - 0xc 0x00000002 0x0000000f - >; - }; - ehrpwm0b_pins: pinmux_ehrpwm0b_pins { - pinctrl-single,bits = < - /* EPWM0B */ - 0xc 0x00000020 0x000000f0 - >; - }; - ehrpwm1a_pins: pinmux_ehrpwm1a_pins { - pinctrl-single,bits = < - /* EPWM1A */ - 0x14 0x00000002 0x0000000f - >; - }; - ehrpwm1b_pins: pinmux_ehrpwm1b_pins { - pinctrl-single,bits = < - /* EPWM1B */ - 0x14 0x00000020 0x000000f0 - >; - }; - ecap0_pins: pinmux_ecap0_pins { - pinctrl-single,bits = < - /* ECAP0_APWM0 */ - 0x8 0x20000000 0xf0000000 - >; - }; - ecap1_pins: pinmux_ecap1_pins { - pinctrl-single,bits = < - /* ECAP1_APWM1 */ - 0x4 0x40000000 0xf0000000 - >; - }; - ecap2_pins: pinmux_ecap2_pins { - pinctrl-single,bits = < - /* ECAP2_APWM2 */ - 0x4 0x00000004 0x0000000f - >; - }; - spi0_pins: pinmux_spi0_pins { - pinctrl-single,bits = < - /* SIMO, SOMI, CLK */ - 0xc 0x00001101 0x0000ff0f - >; - }; - spi0_cs0_pin: pinmux_spi0_cs0 { - pinctrl-single,bits = < - /* CS0 */ - 0x10 0x00000010 0x000000f0 - >; - }; - spi1_pins: pinmux_spi1_pins { - pinctrl-single,bits = < - /* SIMO, SOMI, CLK */ - 0x14 0x00110100 0x00ff0f00 - >; - }; - spi1_cs0_pin: pinmux_spi1_cs0 { - pinctrl-single,bits = < - /* CS0 */ - 0x14 0x00000010 0x000000f0 - >; - }; - mdio_pins: pinmux_mdio_pins { - pinctrl-single,bits = < - /* MDIO_CLK, MDIO_D */ - 0x10 0x00000088 0x000000ff - >; - }; - mii_pins: pinmux_mii_pins { - pinctrl-single,bits = < - /* - * MII_TXEN, MII_TXCLK, MII_COL - * MII_TXD_3, MII_TXD_2, MII_TXD_1 - * MII_TXD_0 - */ - 0x8 0x88888880 0xfffffff0 - /* - * MII_RXER, MII_CRS, MII_RXCLK - * MII_RXDV, MII_RXD_3, MII_RXD_2 - * MII_RXD_1, MII_RXD_0 - */ - 0xc 0x88888888 0xffffffff - >; - }; - - }; - edma0: edma@0 { - compatible = "ti,edma3-tpcc"; - /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ - reg = <0x0 0x8000>; - reg-names = "edma3_cc"; - interrupts = <11 12>; - interrupt-names = "edma3_ccint", "edma3_ccerrint"; - #dma-cells = <2>; - - ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; - }; - edma0_tptc0: tptc@8000 { - compatible = "ti,edma3-tptc"; - reg = <0x8000 0x400>; - interrupts = <13>; - interrupt-names = "edm3_tcerrint"; - }; - edma0_tptc1: tptc@8400 { - compatible = "ti,edma3-tptc"; - reg = <0x8400 0x400>; - interrupts = <32>; - interrupt-names = "edm3_tcerrint"; - }; - edma1: edma@230000 { - compatible = "ti,edma3-tpcc"; - /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ - reg = <0x230000 0x8000>; - reg-names = "edma3_cc"; - interrupts = <93 94>; - interrupt-names = "edma3_ccint", "edma3_ccerrint"; - #dma-cells = <2>; - - ti,tptcs = <&edma1_tptc0 7>; - }; - edma1_tptc0: tptc@238000 { - compatible = "ti,edma3-tptc"; - reg = <0x238000 0x400>; - interrupts = <95>; - interrupt-names = "edm3_tcerrint"; - }; - serial0: serial@42000 { - compatible = "ns16550a"; - reg = <0x42000 0x100>; - reg-shift = <2>; - interrupts = <25>; - status = "disabled"; - }; - serial1: serial@10c000 { - compatible = "ns16550a"; - reg = <0x10c000 0x100>; - reg-shift = <2>; - interrupts = <53>; - status = "disabled"; - }; - serial2: serial@10d000 { - compatible = "ns16550a"; - reg = <0x10d000 0x100>; - reg-shift = <2>; - interrupts = <61>; - status = "disabled"; - }; - rtc0: rtc@23000 { - compatible = "ti,da830-rtc"; - reg = <0x23000 0x1000>; - interrupts = <19 - 19>; - status = "disabled"; - }; - i2c0: i2c@22000 { - compatible = "ti,davinci-i2c"; - reg = <0x22000 0x1000>; - interrupts = <15>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - i2c1: i2c@228000 { - compatible = "ti,davinci-i2c"; - reg = <0x228000 0x1000>; - interrupts = <51>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - wdt: wdt@21000 { - compatible = "ti,davinci-wdt"; - reg = <0x21000 0x1000>; - status = "disabled"; - }; - mmc0: mmc@40000 { - compatible = "ti,da830-mmc"; - reg = <0x40000 0x1000>; - interrupts = <16>; - dmas = <&edma0 16 0>, <&edma0 17 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - mmc1: mmc@21b000 { - compatible = "ti,da830-mmc"; - reg = <0x21b000 0x1000>; - interrupts = <72>; - dmas = <&edma1 28 0>, <&edma1 29 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x300000 0x2000>; - status = "disabled"; - }; - ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x302000 0x2000>; - status = "disabled"; - }; - ecap0: ecap@306000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x306000 0x80>; - status = "disabled"; - }; - ecap1: ecap@307000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x307000 0x80>; - status = "disabled"; - }; - ecap2: ecap@308000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x308000 0x80>; - status = "disabled"; - }; - spi0: spi@41000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,da830-spi"; - reg = <0x41000 0x1000>; - num-cs = <6>; - ti,davinci-spi-intr-line = <1>; - interrupts = <20>; - status = "disabled"; - }; - spi1: spi@30e000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,da830-spi"; - reg = <0x30e000 0x1000>; - num-cs = <4>; - ti,davinci-spi-intr-line = <1>; - interrupts = <56>; - dmas = <&edma0 18 0>, <&edma0 19 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - mdio: mdio@224000 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x224000 0x1000>; - status = "disabled"; - }; - eth0: ethernet@220000 { - compatible = "ti,davinci-dm6467-emac"; - reg = <0x220000 0x4000>; - ti,davinci-ctrl-reg-offset = <0x3000>; - ti,davinci-ctrl-mod-reg-offset = <0x2000>; - ti,davinci-ctrl-ram-offset = <0>; - ti,davinci-ctrl-ram-size = <0x2000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <33 - 34 - 35 - 36 - >; - status = "disabled"; - }; - gpio: gpio@226000 { - compatible = "ti,dm6441-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x226000 0x1000>; - interrupts = <42 IRQ_TYPE_EDGE_BOTH - 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH - 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH - 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH - 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - status = "disabled"; - }; - - mcasp0: mcasp@100000 { - compatible = "ti,da830-mcasp-audio"; - reg = <0x100000 0x2000>, - <0x102000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <54>; - interrupt-names = "common"; - status = "disabled"; - dmas = <&edma0 1 1>, - <&edma0 0 1>; - dma-names = "tx", "rx"; - }; - }; - aemif: aemif@68000000 { - compatible = "ti,da850-aemif"; - #address-cells = <2>; - #size-cells = <1>; - - reg = <0x68000000 0x00008000>; - ranges = <0 0 0x60000000 0x08000000 - 1 0 0x68000000 0x00008000>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dm8148-evm.dts b/software/linux/kernel/arch/arm/boot/dts/dm8148-evm.dts deleted file mode 100644 index d6657b3ba..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dm8148-evm.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "dm814x.dtsi" -#include - -/ { - model = "DM8148 EVM"; - compatible = "ti,dm8148-evm", "ti,dm8148"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16aadwp"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@0x1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@0x280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@0x780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - status = "disabled"; -}; - -&pincntl { - sd1_pins: pinmux_sd1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ - DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ - DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ - DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ - DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ - DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ - DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ - DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ - >; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dm8148-t410.dts b/software/linux/kernel/arch/arm/boot/dts/dm8148-t410.dts deleted file mode 100644 index 63883b347..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dm8148-t410.dts +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "dm814x.dtsi" - -/ { - model = "HP t410 Smart Zero Client"; - compatible = "hp,t410", "ti,dm8148"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* gpio9 seems to control USB VBUS regulator and/or hub power */ - usb_power: regulator@9 { - compatible = "regulator-fixed"; - regulator-name = "usb_power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&sd2_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - dmas = <&edma_xbar 8 0 1 /* use SDTXEVT1 instead of MCASP0TX */ - &edma_xbar 9 0 2>; /* use SDRXEVT1 instead of MCASP0RX */ - dma-names = "tx", "rx"; - non-removable; -}; - -&pincntl { - sd2_pins: pinmux_sd2_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[7] */ - DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[6] */ - DM814X_IOPAD(0x09c8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[5] */ - DM814X_IOPAD(0x09cc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[4] */ - DM814X_IOPAD(0x09d0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[3] */ - DM814X_IOPAD(0x09d4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[2] */ - DM814X_IOPAD(0x09d8, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[1] */ - DM814X_IOPAD(0x09dc, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[0] */ - DM814X_IOPAD(0x09e0, PIN_INPUT | 0x1) /* SD2_CLK */ - DM814X_IOPAD(0x09f4, PIN_INPUT_PULLUP | 0x2) /* SD2_CMD */ - DM814X_IOPAD(0x0920, PIN_INPUT | 40) /* SD2_SDCD */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ - >; - }; -}; - -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "host"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - dr_mode = "host"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dm814x-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/dm814x-clocks.dtsi deleted file mode 100644 index c4671af0a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dm814x-clocks.dtsi +++ /dev/null @@ -1,339 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -&pllss { - /* - * See TRM "2.6.10 Connected outputso DPLLS" and - * "2.6.11 Connected Outputs of DPLLJ". Only clkout is - * connected except for hdmi and usb. - */ - adpll_mpu_ck: adpll@40 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-s-clock"; - reg = <0x40 0x40>; - clocks = <&devosc_ck &devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow", "clkinphif"; - clock-output-names = "481c5040.adpll.dcoclkldo", - "481c5040.adpll.clkout", - "481c5040.adpll.clkoutx2", - "481c5040.adpll.clkouthif"; - }; - - adpll_dsp_ck: adpll@80 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x80 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5080.adpll.dcoclkldo", - "481c5080.adpll.clkout", - "481c5080.adpll.clkoutldo"; - }; - - adpll_sgx_ck: adpll@b0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0xb0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c50b0.adpll.dcoclkldo", - "481c50b0.adpll.clkout", - "481c50b0.adpll.clkoutldo"; - }; - - adpll_hdvic_ck: adpll@e0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0xe0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c50e0.adpll.dcoclkldo", - "481c50e0.adpll.clkout", - "481c50e0.adpll.clkoutldo"; - }; - - adpll_l3_ck: adpll@110 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x110 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5110.adpll.dcoclkldo", - "481c5110.adpll.clkout", - "481c5110.adpll.clkoutldo"; - }; - - adpll_isp_ck: adpll@140 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x140 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5140.adpll.dcoclkldo", - "481c5140.adpll.clkout", - "481c5140.adpll.clkoutldo"; - }; - - adpll_dss_ck: adpll@170 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x170 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5170.adpll.dcoclkldo", - "481c5170.adpll.clkout", - "481c5170.adpll.clkoutldo"; - }; - - adpll_video0_ck: adpll@1a0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x1a0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c51a0.adpll.dcoclkldo", - "481c51a0.adpll.clkout", - "481c51a0.adpll.clkoutldo"; - }; - - adpll_video1_ck: adpll@1d0 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x1d0 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c51d0.adpll.dcoclkldo", - "481c51d0.adpll.clkout", - "481c51d0.adpll.clkoutldo"; - }; - - adpll_hdmi_ck: adpll@200 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x200 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5200.adpll.dcoclkldo", - "481c5200.adpll.clkout", - "481c5200.adpll.clkoutldo"; - }; - - adpll_audio_ck: adpll@230 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x230 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5230.adpll.dcoclkldo", - "481c5230.adpll.clkout", - "481c5230.adpll.clkoutldo"; - }; - - adpll_usb_ck: adpll@260 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x260 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5260.adpll.dcoclkldo", - "481c5260.adpll.clkout", - "481c5260.adpll.clkoutldo"; - }; - - adpll_ddr_ck: adpll@290 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x290 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5290.adpll.dcoclkldo", - "481c5290.adpll.clkout", - "481c5290.adpll.clkoutldo"; - }; -}; - -&pllss_clocks { - timer1_fck: timer1_fck@2e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <3>; - reg = <0x2e0>; - }; - - timer2_fck: timer2_fck@2e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <6>; - reg = <0x2e0>; - }; - - /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */ - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&adpll_video0_ck 1 - &adpll_video1_ck 1 - &adpll_audio_ck 1>; - ti,bit-shift = <1>; - reg = <0x2e8>; - }; - - /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */ - cpsw_125mhz_gclk: cpsw_125mhz_gclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - }; - - sysclk18_ck: sysclk18_ck@2f0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&rtcosc_ck>, <&rtcdivider_ck>; - ti,bit-shift = <0>; - reg = <0x02f0>; - }; -}; - -&scm_clocks { - devosc_ck: devosc_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_20000000_ck>, <&virt_19200000_ck>; - ti,bit-shift = <21>; - reg = <0x0040>; - }; - - /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */ - auxosc_ck: auxosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <22572900>; - }; - - /* Optional 32768Hz crystal or clock on RTCOSC pins */ - rtcosc_ck: rtcosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - /* Optional external clock on TCLKIN pin, set rate in baord dts file */ - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - virt_20000000_ck: virt_20000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - mpu_ck: mpu_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000000>; - }; -}; - -&prcm_clocks { - osc_src_ck: osc_src_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&devosc_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mpu_clksrc_ck: mpu_clksrc_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&devosc_ck>, <&rtcdivider_ck>; - ti,bit-shift = <0>; - reg = <0x0040>; - }; - - /* Fixed divider clock 0.0016384 * devosc */ - rtcdivider_ck: rtcdivider_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&devosc_ck>; - clock-mult = <128>; - clock-div = <78125>; - }; - - /* L4_HS 220 MHz*/ - sysclk4_ck: sysclk4_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - }; - - /* L4_FWCFG */ - sysclk5_ck: sysclk5_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <2>; - }; - - /* L4_LS 110 MHz */ - sysclk6_ck: sysclk6_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_l3_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <2>; - }; - - sysclk8_ck: sysclk8_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&adpll_usb_ck 1>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - }; - - sysclk10_ck: sysclk10_ck { - compatible = "ti,divider-clock"; - reg = <0x324>; - ti,max-div = <7>; - #clock-cells = <0>; - clocks = <&adpll_usb_ck 1>; - }; - - aud_clkin0_ck: aud_clkin0_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - aud_clkin1_ck: aud_clkin1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - aud_clkin2_ck: aud_clkin2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dm814x.dtsi b/software/linux/kernel/arch/arm/boot/dts/dm814x.dtsi deleted file mode 100644 index ff57a20af..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dm814x.dtsi +++ /dev/null @@ -1,578 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -/ { - compatible = "ti,dm814"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - usb0 = &usb0; - usb1 = &usb1; - phy0 = &usb0_phy; - phy1 = &usb1_phy; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - usb: usb@47400000 { - compatible = "ti,am33xx-usb"; - reg = <0x47400000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - usb0_phy: usb-phy@47401300 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401300 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&usb_ctrl_mod>; - }; - - usb0: usb@47401000 { - compatible = "ti,musb-am33xx"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb0_phy>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-am33xx"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "otg"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb1_phy>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - }; - }; - - /* - * See TRM "Table 1-317. L4LS Instance Summary" for hints. - * It shows the module target agent registers though, so the - * actual device is typically 0x1000 before the target agent - * except in cases where the module is larger than 0x1000. - */ - l4ls: l4ls@48000000 { - compatible = "ti,dm814-l4ls", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x2000000>; - - i2c1: i2c@28000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - reg = <0x28000 0x1000>; - interrupts = <70>; - }; - - elm: elm@80000 { - compatible = "ti,814-elm"; - ti,hwmods = "elm"; - reg = <0x80000 0x2000>; - interrupts = <4>; - }; - - gpio1: gpio@32000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - reg = <0x32000 0x2000>; - interrupts = <96>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - reg = <0x4c000 0x2000>; - interrupts = <98>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c2: i2c@2a000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - reg = <0x2a000 0x1000>; - interrupts = <71>; - }; - - mcspi1: spi@30000 { - compatible = "ti,omap4-mcspi"; - reg = <0x30000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <65>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi1"; - dmas = <&edma 16 0 &edma 17 0 - &edma 18 0 &edma 19 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - timer1: timer@2e000 { - compatible = "ti,dm814-timer"; - reg = <0x2e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - uart1: uart@20000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - reg = <0x20000 0x2000>; - clock-frequency = <48000000>; - interrupts = <72>; - dmas = <&edma 26 0 &edma 27 0>; - dma-names = "tx", "rx"; - }; - - uart2: uart@22000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - reg = <0x22000 0x2000>; - clock-frequency = <48000000>; - interrupts = <73>; - dmas = <&edma 28 0 &edma 29 0>; - dma-names = "tx", "rx"; - }; - - uart3: uart@24000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - reg = <0x24000 0x2000>; - clock-frequency = <48000000>; - interrupts = <74>; - dmas = <&edma 30 0 &edma 31 0>; - dma-names = "tx", "rx"; - }; - - timer2: timer@40000 { - compatible = "ti,dm814-timer"; - reg = <0x40000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - }; - - timer3: timer@42000 { - compatible = "ti,dm814-timer"; - reg = <0x42000 0x2000>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - mmc1: mmc@60000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc1"; - dmas = <&edma 24 0 - &edma 25 0>; - dma-names = "tx", "rx"; - interrupts = <64>; - interrupt-parent = <&intc>; - reg = <0x60000 0x1000>; - }; - - rtc: rtc@c0000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0xc0000 0x1000>; - interrupts = <75 76>; - ti,hwmods = "rtc"; - }; - - mmc2: mmc@1d8000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc2"; - dmas = <&edma 2 0 - &edma 3 0>; - dma-names = "tx", "rx"; - interrupts = <28>; - interrupt-parent = <&intc>; - reg = <0x1d8000 0x1000>; - }; - - control: control@140000 { - compatible = "ti,dm814-scm", "simple-bus"; - reg = <0x140000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x140000 0x20000>; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scm_clockdomains: clockdomains { - }; - }; - - usb_ctrl_mod: control@620 { - compatible = "ti,am335x-usb-ctrl-module"; - reg = <0x620 0x10 - 0x648 0x4>; - reg-names = "phy_ctrl", "wakeup"; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <32>; - dma-masters = <&edma>; - }; - - /* - * Note that silicon revision 2.1 and older - * require input enabled (bit 18 set) for all - * 3.3V I/Os to avoid cumulative hardware damage. - * For more info, see errata advisory 2.1.87. - * We leave bit 18 out of function-mask and rely - * on the bootloader for it. - */ - pincntl: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x438>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x307ff>; - }; - - usb1_phy: usb-phy@1b00 { - compatible = "ti,am335x-usb-phy"; - reg = <0x1b00 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&usb_ctrl_mod>; - }; - }; - - prcm: prcm@180000 { - compatible = "ti,dm814-prcm", "simple-bus"; - reg = <0x180000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x180000 0x2000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ - pllss: pllss@1c5000 { - compatible = "ti,dm814-pllss", "simple-bus"; - reg = <0x1c5000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1c5000 0x1000>; - - pllss_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - pllss_clockdomains: clockdomains { - }; - }; - - wdt1: wdt@1c7000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer"; - reg = <0x1c7000 0x1000>; - interrupts = <91>; - }; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,dm814-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - /* Board must configure evtmux with edma_xbar for EDMA */ - mmc3: mmc@47810000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc3"; - interrupts = <29>; - interrupt-parent = <&intc>; - reg = <0x47810000 0x1000>; - }; - - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 3>, <&edma_tptc3 0>; - - ti,edma-memcpy-channels = <20 21>; - }; - - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc3: tptc@49b00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc3"; - reg = <0x49b00000 0x100000>; - interrupts = <115>; - interrupt-names = "edma3_tcerrint"; - }; - - /* See TRM "Table 1-318. L4HS Instance Summary" */ - l4hs: l4hs@4a000000 { - compatible = "ti,dm814-l4hs", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x1b4040>; - }; - - /* REVISIT: Move to live under l4hs once driver is fixed */ - mac: ethernet@4a100000 { - compatible = "ti,cpsw"; - ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - no_bd_ram = <0>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - reg = <0x4a100000 0x800 - 0x4a100900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - /* - * c0_rx_thresh_pend - * c0_rx_pend - * c0_tx_pend - * c0_misc_pend - */ - interrupts = <40 41 42 43>; - ranges; - syscon = <&scm_conf>; - - davinci_mdio: mdio@4a100800 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - reg = <0x4a100800 0x100>; - }; - - cpsw_emac0: slave@4a100200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpsw_emac1: slave@4a100300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@48140650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x48140650 0x4>; - reg-names = "gmii-sel"; - }; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - ti,no-idle-on-init; - reg = <0x50000000 0x2000>; - interrupts = <100>; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; - -#include "dm814x-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/dm8168-evm.dts b/software/linux/kernel/arch/arm/boot/dts/dm8168-evm.dts deleted file mode 100644 index 0bf55fa72..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dm8168-evm.dts +++ /dev/null @@ -1,175 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "dm816x.dtsi" -#include - -/ { - model = "DM8168 EVM"; - compatible = "ti,dm8168-evm", "ti,dm8168"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000 /* 1 GB */ - 0xc0000000 0x40000000>; /* 1 GB */ - }; - - /* FDC6331L controlled by SD_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&dm816x_pinmux { - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ - DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ - DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ - DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ - >; - }; - - mmc_pins: pinmux_mmc_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ - DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ - DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ - DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ - DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ - DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ - DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ - >; - }; -}; - -&i2c1 { - extgpio0: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c2 { - extgpio1: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29f2g16aadwp"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@0x1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@0x280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@0x780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - m25p80@0 { - compatible = "w25x32"; - spi-max-frequency = <48000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -/* At least dm8168-evm rev c won't support multipoint, later may */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - mentor,multipoint = <0>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - mentor,multipoint = <0>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dm816x-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/dm816x-clocks.dtsi deleted file mode 100644 index 51865eb84..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dm816x-clocks.dtsi +++ /dev/null @@ -1,250 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -&scrm { - main_fapll: main_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x400 0x40>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>, - <6>, <7>; - clock-output-names = "main_pll_clk1", - "main_pll_clk2", - "main_pll_clk3", - "main_pll_clk4", - "main_pll_clk5", - "main_pll_clk6", - "main_pll_clk7"; - }; - - ddr_fapll: ddr_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x440 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>; - clock-output-names = "ddr_pll_clk1", - "ddr_pll_clk2", - "ddr_pll_clk3", - "ddr_pll_clk4"; - }; - - video_fapll: video_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x470 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>; - clock-output-names = "video_pll_clk1", - "video_pll_clk2", - "video_pll_clk3"; - }; - - audio_fapll: audio_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x4a0 0x30>; - clocks = <&main_fapll 7>, < &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>; - clock-output-names = "audio_pll_clk1", - "audio_pll_clk2", - "audio_pll_clk3", - "audio_pll_clk4", - "audio_pll_clk5"; - }; -}; - -&scrm_clocks { - secure_32k_ck: secure_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clkin_ck: sys_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; -}; - -/* 0x48180000 */ -&prcm_clocks { - clkout_pre_ck: clkout_pre_ck@100 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 - &audio_fapll 1>; - reg = <0x100>; - }; - - clkout_div_ck: clkout_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x100>; - }; - - clkout_ck: clkout_ck@100 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout_div_ck>; - ti,bit-shift = <7>; - reg = <0x100>; - }; - - /* CM_DPLL clocks p1795 */ - sysclk1_ck: sysclk1_ck@300 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 1>; - ti,max-div = <7>; - reg = <0x0300>; - }; - - sysclk2_ck: sysclk2_ck@304 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 2>; - ti,max-div = <7>; - reg = <0x0304>; - }; - - sysclk3_ck: sysclk3_ck@308 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 3>; - ti,max-div = <7>; - reg = <0x0308>; - }; - - sysclk4_ck: sysclk4_ck@30c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,max-div = <1>; - reg = <0x030c>; - }; - - sysclk5_ck: sysclk5_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclk4_ck>; - ti,max-div = <1>; - reg = <0x0310>; - }; - - sysclk6_ck: sysclk6_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,dividers = <2>, <4>; - reg = <0x0314>; - }; - - sysclk10_ck: sysclk10_ck@324 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&ddr_fapll 2>; - ti,max-div = <7>; - reg = <0x0324>; - }; - - sysclk24_ck: sysclk24_ck@3b4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 5>; - ti,max-div = <7>; - reg = <0x03b4>; - }; - - mpu_ck: mpu_ck@15dc { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sysclk2_ck>; - ti,bit-shift = <1>; - reg = <0x15dc>; - }; - - audio_pll_a_ck: audio_pll_a_ck@35c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&audio_fapll 1>; - ti,max-div = <7>; - reg = <0x035c>; - }; - - sysclk18_ck: sysclk18_ck@378 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; - reg = <0x0378>; - }; - - timer1_fck: timer1_fck@390 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0390>; - }; - - timer2_fck: timer2_fck@394 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0394>; - }; - - timer3_fck: timer3_fck@398 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0398>; - }; - - timer4_fck: timer4_fck@39c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x039c>; - }; - - timer5_fck: timer5_fck@3a0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a0>; - }; - - timer6_fck: timer6_fck@3a4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a4>; - }; - - timer7_fck: timer7_fck@3a8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a8>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dm816x.dtsi b/software/linux/kernel/arch/arm/boot/dts/dm816x.dtsi deleted file mode 100644 index 62c0a6155..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dm816x.dtsi +++ /dev/null @@ -1,516 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -/ { - compatible = "ti,dm816"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - ethernet0 = ð0; - ethernet1 = ð1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the dm816x interconnect. - * The real dm816x interconnect network is quite complex. Since - * it will not bring real advantage to represent that in DT - * for the moment, just use a fake OCP bus entry to represent - * the whole bus hierarchy. - */ - ocp { - compatible = "simple-bus"; - reg = <0x44000000 0x10000>; - interrupts = <9 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - prcm: prcm@48180000 { - compatible = "ti,dm816-prcm"; - reg = <0x48180000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@48140000 { - compatible = "ti,dm816-scrm", "simple-bus"; - reg = <0x48140000 0x21000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48140000 0x21000>; - - dm816x_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x50a>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xf>; - }; - - /* Device Configuration Registers */ - scm_conf: syscon@600 { - compatible = "syscon", "simple-bus"; - reg = <0x600 0x110>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x110>; - - usb_phy0: usb-phy@20 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x20 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - - usb_phy1: usb-phy@28 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x28 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - }; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; - interrupts = <12 13 14>; - #dma-cells = <1>; - }; - - elm: elm@48080000 { - compatible = "ti,816-elm"; - ti,hwmods = "elm"; - reg = <0x48080000 0x2000>; - interrupts = <4>; - }; - - gpio1: gpio@48032000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - reg = <0x48032000 0x1000>; - interrupts = <96>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4804c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - reg = <0x4804c000 0x1000>; - interrupts = <98>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <100>; - dmas = <&edma 52>; - dma-names = "rxtx"; - gpmc,num-cs = <6>; - gpmc,num-waitpins = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c1: i2c@48028000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48028000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <70>; - dmas = <&edma 58 &edma 59>; - dma-names = "tx", "rx"; - }; - - i2c2: i2c@4802a000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c2"; - reg = <0x4802a000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <71>; - dmas = <&edma 60 &edma 61>; - dma-names = "tx", "rx"; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,dm816-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - rtc: rtc@480c0000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x480c0000 0x1000>; - interrupts = <75 76>; - ti,hwmods = "rtc"; - }; - - mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480c8000 0x2000>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <0 0 0>; - }; - }; - - spinbox: spinbox@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x2000>; - ti,hwmods = "spinbox"; - #hwlock-cells = <1>; - }; - - mdio: mdio@4a100800 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4a100800 0x100>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - phy0: ethernet-phy@0 { - reg = <1>; - }; - phy1: ethernet-phy@1 { - reg = <2>; - }; - }; - - eth0: ethernet@4a100000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac0"; - reg = <0x4a100000 0x800 - 0x4a100900 0x3700>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <40 41 42 43>; - phy-handle = <&phy0>; - }; - - eth1: ethernet@4a120000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac1"; - reg = <0x4a120000 0x4000>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <44 45 46 47>; - phy-handle = <&phy1>; - }; - - mcspi1: spi@48030000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48030000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <65>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi1"; - dmas = <&edma 16 &edma 17 - &edma 18 &edma 19 - &edma 20 &edma 21 - &edma 22 &edma 23>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x48060000 0x11000>; - ti,hwmods = "mmc1"; - interrupts = <64>; - dmas = <&edma 24 &edma 25>; - dma-names = "tx", "rx"; - }; - - timer1: timer@4802e000 { - compatible = "ti,dm816-timer"; - reg = <0x4802e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@48040000 { - compatible = "ti,dm816-timer"; - reg = <0x48040000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48042000 { - compatible = "ti,dm816-timer"; - reg = <0x48042000 0x2000>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48044000 { - compatible = "ti,dm816-timer"; - reg = <0x48044000 0x2000>; - interrupts = <92>; - ti,hwmods = "timer4"; - ti,timer-pwm; - }; - - timer5: timer@48046000 { - compatible = "ti,dm816-timer"; - reg = <0x48046000 0x2000>; - interrupts = <93>; - ti,hwmods = "timer5"; - ti,timer-pwm; - }; - - timer6: timer@48048000 { - compatible = "ti,dm816-timer"; - reg = <0x48048000 0x2000>; - interrupts = <94>; - ti,hwmods = "timer6"; - ti,timer-pwm; - }; - - timer7: timer@4804a000 { - compatible = "ti,dm816-timer"; - reg = <0x4804a000 0x2000>; - interrupts = <95>; - ti,hwmods = "timer7"; - ti,timer-pwm; - }; - - uart1: uart@48020000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - reg = <0x48020000 0x2000>; - clock-frequency = <48000000>; - interrupts = <72>; - dmas = <&edma 26 &edma 27>; - dma-names = "tx", "rx"; - }; - - uart2: uart@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - reg = <0x48022000 0x2000>; - clock-frequency = <48000000>; - interrupts = <73>; - dmas = <&edma 28 &edma 29>; - dma-names = "tx", "rx"; - }; - - uart3: uart@48024000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - reg = <0x48024000 0x2000>; - clock-frequency = <48000000>; - interrupts = <74>; - dmas = <&edma 30 &edma 31>; - dma-names = "tx", "rx"; - }; - - /* NOTE: USB needs a transceiver driver for phys to work */ - usb: usb_otg_hs@47401000 { - compatible = "ti,am33xx-usb"; - reg = <0x47401000 0x400000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - usb0: usb@47401000 { - compatible = "ti,musb-dm816"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy0>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-dm816"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy1>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - }; - }; - - wd_timer2: wd_timer@480c2000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer"; - reg = <0x480c2000 0x1000>; - interrupts = <0>; - }; - }; -}; - -#include "dm816x-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/dove-cm-a510.dtsi b/software/linux/kernel/arch/arm/boot/dts/dove-cm-a510.dtsi deleted file mode 100644 index 59b4056b4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dove-cm-a510.dtsi +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Device Tree include for Compulab CM-A510 System-on-Module - * - * Copyright (C) 2015, Sebastian Hesselbarth - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The CM-A510 comes with several optional components: - * - * Memory options: - * D512: 512M - * D1024: 1G - * - * NAND options: - * N512: 512M NAND - * - * Ethernet options: - * E1: PHY RTL8211D on internal GbE (SMI address 0x03) - * E2: Additional ethernet NIC RTL8111D on PCIe1 - * - * Audio options: - * A: TI TLV320AIC23b audio codec (I2C address 0x1a) - * - * Touchscreen options: - * I: TI TSC2046 touchscreen controller (on SPI1) - * - * USB options: - * U2: 2 dual-role USB2.0 ports - * U4: 2 additional USB2.0 host ports (via USB1) - * - * WiFi options: - * W: Broadcom BCM4319 802.11b/g/n (USI WM-N-BM-01 on SDIO1) - * - * GPIOs used on CM-A510: - * 1 GbE PHY reset (active low) - * 3 WakeUp - * 8 PowerOff (active low) - * 13 Touchscreen pen irq (active low) - * 65 System LED (active high) - * 69 USB Hub reset (active low) - * 70 WLAN reset (active low) - * 71 WLAN regulator (active high) - */ - -#include "dove.dtsi" - -/ { - model = "Compulab CM-A510"; - compatible = "compulab,cm-a510", "marvell,dove"; - - /* - * Set the minimum memory size here and let the - * bootloader set the real size. - */ - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - /* Set upper NAND data bit to GPO */ - pinctrl-0 = <&pmx_nand_gpo>; - pinctrl-names = "default"; - - system { - label = "cm-a510:system:green"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - wifi_power: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "WiFi Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -/* Optional RTL8211D GbE PHY on SMI address 0x03 */ -ðphy { - reg = <3>; - status = "disabled"; -}; - -&i2c0 { - /* Optional TI TLV320AIC23b audio codec */ - opt_audio: audio@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - status = "disabled"; - }; -}; - -/* Optional RTL8111D GbE NIC on PCIe1 */ -&pcie { status = "disabled"; }; - -&pcie1 { - pinctrl-0 = <&pmx_pcie1_clkreq>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&pinctrl { - pmx_uart2: pmx-uart2 { - marvell,pins = "mpp14", "mpp15"; - marvell,function = "uart2"; - }; -}; - -/* Optional Broadcom BCM4319 802.11b/g/n WiFi module */ -&sdio1 { - non-removable; - vmmc-supply = <&wifi_power>; - reset-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&spi0 { - status = "okay"; - - /* 1M Flash Winbond W25Q80BL */ - flash@0 { - compatible = "winbond,w25q80"; - spi-max-frequency = <80000000>; - reg = <0>; - }; -}; - -&spi1 { - pinctrl-0 = <&pmx_spi1_20_23>; - pinctrl-names = "default"; - status = "disabled"; - - /* Optional TI TSC2046 touchscreen controller */ - opt_touch: touchscreen@0 { - compatible = "ti,tsc2046"; - spi-max-frequency = <2500000>; - reg = <0>; - pinctrl-0 = <&pmx_gpio_13>; - pinctrl-names = "default"; - interrupts-extended = <&gpio0 13 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&uart2 { - pinctrl-0 = <&pmx_uart2>; - pinctrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dove-cubox-es.dts b/software/linux/kernel/arch/arm/boot/dts/dove-cubox-es.dts deleted file mode 100644 index e28ef056d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dove-cubox-es.dts +++ /dev/null @@ -1,12 +0,0 @@ -#include "dove-cubox.dts" - -/ { - model = "SolidRun CuBox (Engineering Sample)"; - compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove"; -}; - -&sdio0 { - /* sdio0 card detect is connected to wrong pin on CuBox ES */ - cd-gpios = <&gpio0 12 1>; - pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dove-cubox.dts b/software/linux/kernel/arch/arm/boot/dts/dove-cubox.dts deleted file mode 100644 index af3cb6331..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dove-cubox.dts +++ /dev/null @@ -1,142 +0,0 @@ -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "SolidRun CuBox"; - compatible = "solidrun,cubox", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_18>; - pinctrl-names = "default"; - - power { - label = "Power"; - gpios = <&gpio0 18 1>; - default-state = "keep"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 1 0>; - pinctrl-0 = <&pmx_gpio_1>; - pinctrl-names = "default"; - }; - }; - - clocks { - /* 25MHz reference crystal */ - ref25: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 19 1>; - pinctrl-0 = <&pmx_gpio_19>; - pinctrl-names = "default"; - }; - - gpu-subsystem { - status = "okay"; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&mdio { status = "okay"; }; -ð { status = "okay"; }; - -ðphy { - compatible = "marvell,88e1310"; - reg = <1>; -}; - -&gpu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - si5351: clock-generator { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - }; - - clkout2 { - reg = <2>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - silabs,pll-master; - }; - }; -}; - -&sdio0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Winbond W25Q32BV */ - spi-flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&audio1 { - status = "okay"; - clocks = <&gate_clk 13>, <&si5351 2>; - clock-names = "internal", "extclk"; - pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>; - pinctrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dove-d2plug.dts b/software/linux/kernel/arch/arm/boot/dts/dove-d2plug.dts deleted file mode 100644 index c11d3636c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dove-d2plug.dts +++ /dev/null @@ -1,69 +0,0 @@ -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Globalscale D2Plug"; - compatible = "globalscale,d2plug", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; - pinctrl-names = "default"; - - wlan-ap { - label = "wlan-ap"; - gpios = <&gpio0 0 1>; - }; - - wlan-act { - label = "wlan-act"; - gpios = <&gpio0 1 1>; - }; - - bluetooth-act { - label = "bt-act"; - gpios = <&gpio0 2 1>; - }; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; -&mdio { status = "okay"; }; -ð { status = "okay"; }; - -/* Samsung M8G2F eMMC */ -&sdio0 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -/* Marvell SD8787 WLAN/BT */ -&sdio1 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Macronix MX25L3205D */ - spi-flash@0 { - compatible = "st,m25l3205d"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dove-d3plug.dts b/software/linux/kernel/arch/arm/boot/dts/dove-d3plug.dts deleted file mode 100644 index f5f59bb5a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dove-d3plug.dts +++ /dev/null @@ -1,103 +0,0 @@ -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Globalscale D3Plug"; - compatible = "globalscale,d3plug", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; - pinctrl-names = "default"; - - wlan-act { - label = "wlan-act"; - gpios = <&gpio0 0 1>; - }; - - wlan-ap { - label = "wlan-ap"; - gpios = <&gpio0 1 1>; - }; - - status { - label = "status"; - gpios = <&gpio0 2 1>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 8 0>; - pinctrl-0 = <&pmx_gpio_8>; - pinctrl-names = "default"; - }; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; - -/* Samsung M8G2F eMMC */ -&sdio0 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -/* Marvell SD8787 WLAN/BT */ -&sdio1 { - status = "okay"; - non-removable; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 2M Flash Macronix MX25L1605D */ - spi-flash@0 { - compatible = "st,m25l1605d"; - spi-max-frequency = <86000000>; - reg = <0>; - }; -}; - -&pcie { - status = "okay"; - /* Fresco Logic USB3.0 xHCI controller */ - pcie-port@0 { - status = "okay"; - reset-gpios = <&gpio0 26 1>; - reset-delay-us = <20000>; - pinctrl-0 = <&pmx_camera_gpio>; - pinctrl-names = "default"; - }; - /* Mini-PCIe slot */ - pcie-port@1 { - status = "okay"; - reset-gpios = <&gpio0 25 1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dove-dove-db.dts b/software/linux/kernel/arch/arm/boot/dts/dove-dove-db.dts deleted file mode 100644 index bb725dca3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dove-dove-db.dts +++ /dev/null @@ -1,38 +0,0 @@ -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Marvell DB-MV88AP510-BP Development Board"; - compatible = "marvell,dove-db", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; -}; - -&uart0 { status = "okay"; }; -&uart1 { status = "okay"; }; -&sdio0 { status = "okay"; }; -&sdio1 { status = "okay"; }; -&sata0 { status = "okay"; }; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash ST-M25P32-VMF6P */ - spi-flash@0 { - compatible = "st,m25p32"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dove-sbc-a510.dts b/software/linux/kernel/arch/arm/boot/dts/dove-sbc-a510.dts deleted file mode 100644 index 288e707de..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dove-sbc-a510.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Device Tree file for Compulab SBC-A510 Single Board Computer - * - * Copyright (C) 2015, Sebastian Hesselbarth - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * SBC-A510 comprises a PCA9555 I2C GPIO expander its GPIO lines connected to - * - * 0.0 USB0 VBUS_EN (active high) - * 0.1 USB0 VBUS_GOOD - * 0.2 DVI transmitter TI TFP410 MSEN - * 0.3 DVI transmitter TI TFP410 PD# (active low power down) - * 0.4 LVDS transmitter DS90C365 PD# (active low power down) - * 0.5 LCD nRST (active low reset) - * 0.6 PCIe0 nRST (active low reset) - * 0.7 mini-PCIe slot W_DISABLE# - * - * 1.0 MMC WP - * 1.1 Camera Input FPC FLASH_STB and P21.5 - * 1.2 Camera Input FPC WE and P21.22 - * 1.3 MMC VCC_EN (active high) and P21.7 - * 1.4 Camera Input FPC AFTR_RST and P21.17 - * 1.5 Camera Input FPC OE and P21.19 - * 1.6 Camera Input FPC SNPSHT and P21.6 - * 1.7 Camera Input FPC SHTR and P21.10 - */ - -/dts-v1/; - -#include "dove-cm-a510.dtsi" - -/ { - model = "Compulab SBC-A510"; - compatible = "compulab,sbc-a510", "compulab,cm-a510", "marvell,dove"; - - chosen { - stdout-path = &uart0; - }; - - regulators { - usb0_power: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>; - }; - - mmc_power: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "MMC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -/* Ethernet0 depends on CM-A510 option E1 */ -&mdio { status = "disabled"; }; -ð { status = "disabled"; }; -ðphy { status = "disabled"; }; - -/* - * USB port 0 can be powered and monitored by I2C GPIO expander: - * VBUS_ENABLE on GPIO0, VBUS_GOOD on GPIO1 - */ -&ehci0 { - status = "okay"; - vbus-supply = <&usb0_power>; -}; - -/* USB port 1 (and ports 2, 3 if CM-A510 has U4 option) */ -&ehci1 { status = "okay"; }; - -/* - * I2C bus layout: - * i2c0: - * - Audio Codec, 0x1a (option from CM-A510) - * - DVI transmitter TI TFP410, 0x39 - * - HDMI/DVI DDC channel - * i2c1: - * - GPIO expander, NXP PCA9555, 0x20 - * - VGA DDC channel - */ -&i2c { - pinctrl-0 = <&pmx_i2c1>; - pinctrl-names = "default"; -}; - -&i2c0 { - /* TI TFP410 DVI transmitter */ - dvi: video@39 { - compatible = "ti,tfp410"; - reg = <0x39>; - powerdown-gpio = <&gpio_ext 3 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - status = "okay"; - - /* NXP PCA9555 GPIO expander */ - gpio_ext: gpio@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - #gpio-cells = <2>; - }; -}; - -&pcie { status = "okay"; }; - -/* - * PCIe0 can be configured by Jumper E1 to be either connected to - * a mini-PCIe slot or a Pericom PI7C9X111 PCIe-to-PCI bridge. - */ -&pcie0 { - status = "okay"; - pinctrl-0 = <&pmx_pcie0_clkreq>; - pinctrl-names = "default"; - reset-gpios = <&gpio_ext 6 GPIO_ACTIVE_LOW>; -}; - -/* Ethernet1 depends on CM-A510 option E2 */ -&pcie1 { status = "disabled"; }; - -/* SATA connector */ -&sata0 { status = "okay"; }; - -/* - * SDIO0 is connected to a MMC/SD/SDIO socket, I2C GPIO expander has - * VCC_MMC_ENABLE on GPIO13, MMC_WP on GPIO10 - */ -&sdio0 { - vmmc-supply = <&mmc_power>; - wp-gpios = <&gpio_ext 10 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* UART0 on RS232 mini-connector */ -&uart0 { status = "okay"; }; -/* UART2 on pin headers */ -&uart2 { status = "okay"; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/dove.dtsi b/software/linux/kernel/arch/arm/boot/dts/dove.dtsi deleted file mode 100644 index 698d58cea..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dove.dtsi +++ /dev/null @@ -1,803 +0,0 @@ -/include/ "skeleton.dtsi" - -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - compatible = "marvell,dove"; - model = "Marvell Armada 88AP510 SoC"; - interrupt-parent = <&intc>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "marvell,pj4a", "marvell,sheeva-v7"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - }; - }; - - l2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0>; - }; - - gpu-subsystem { - compatible = "marvell,dove-gpu-subsystem"; - cores = <&gpu>; - status = "disabled"; - }; - - i2c-mux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c>; - - pinctrl-names = "i2c0", "i2c1", "i2c2"; - pinctrl-0 = <&pmx_i2cmux_0>; - pinctrl-1 = <&pmx_i2cmux_1>; - pinctrl-2 = <&pmx_i2cmux_2>; - - i2c0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - }; - - i2c1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - /* Requires pmx_i2c1 on i2c controller node */ - status = "disabled"; - }; - - i2c2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - /* Requires pmx_i2c2 on i2c controller node */ - status = "disabled"; - }; - }; - - mbus { - compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ - pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ - - ranges = ; /* PMU SRAM 1M */ - - pcie: pcie-controller { - compatible = "marvell,dove-pcie"; - status = "disabled"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&intc>; - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 - 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 - 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ - 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ - 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ - 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - - pcie0: pcie-port@0 { - device_type = "pci"; - status = "disabled"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - clocks = <&gate_clk 4>; - marvell,pcie-port = <0>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 16>; - }; - - pcie1: pcie-port@1 { - device_type = "pci"; - status = "disabled"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - clocks = <&gate_clk 5>; - marvell,pcie-port = <1>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 18>; - }; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ - 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ - 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ - 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ - - spi0: spi-ctrl@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <6>; - reg = <0x10600 0x28>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_spi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c: i2c-ctrl@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <11>; - clock-frequency = <400000>; - timeout-ms = <1000>; - clocks = <&core_clk 0>; - status = "okay"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <7>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@12200 { - compatible = "ns16550a"; - reg = <0x12200 0x100>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "ns16550a"; - reg = <0x12300 0x100>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - spi1: spi-ctrl@14600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <5>; - reg = <0x14600 0x28>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - mbusc: mbus-ctrl@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x800100 0x8>; - }; - - sysc: system-ctrl@20000 { - compatible = "marvell,orion-system-controller"; - reg = <0x20000 0x110>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <5>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - watchdog@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&core_clk 0>; - }; - - crypto: crypto-engine@30000 { - compatible = "marvell,dove-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <31>; - clocks = <&gate_clk 15>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - ehci0: usb-host@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <24>; - clocks = <&gate_clk 0>; - status = "okay"; - }; - - ehci1: usb-host@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x1000>; - interrupts = <25>; - clocks = <&gate_clk 1>; - status = "okay"; - }; - - xor0: dma-engine@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gate_clk 23>; - status = "okay"; - - channel0 { - interrupts = <39>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <40>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - xor1: dma-engine@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gate_clk 24>; - status = "okay"; - - channel0 { - interrupts = <42>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <43>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - sdio1: sdio-host@90000 { - compatible = "marvell,dove-sdhci"; - reg = <0x90000 0x100>; - interrupts = <36>, <38>; - clocks = <&gate_clk 9>; - pinctrl-0 = <&pmx_sdio1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - eth: ethernet-ctrl@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 2>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethernet-port@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <29>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-handle = <ðphy>; - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <30>; - clocks = <&gate_clk 2>; - status = "disabled"; - - ethphy: ethernet-phy { - /* set phy address in board file */ - }; - }; - - sdio0: sdio-host@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>, <37>; - clocks = <&gate_clk 8>; - pinctrl-0 = <&pmx_sdio0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata0: sata-host@a0000 { - compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; - interrupts = <62>; - clocks = <&gate_clk 3>; - phys = <&sata_phy0>; - phy-names = "port0"; - nr-ports = <1>; - status = "disabled"; - }; - - sata_phy0: sata-phy@a2000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0xa2000 0x0334>; - clocks = <&gate_clk 3>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - audio0: audio-controller@b0000 { - compatible = "marvell,dove-audio"; - reg = <0xb0000 0x2210>; - interrupts = <19>, <20>; - clocks = <&gate_clk 12>; - clock-names = "internal"; - status = "disabled"; - }; - - audio1: audio-controller@b4000 { - compatible = "marvell,dove-audio"; - reg = <0xb4000 0x2210>; - interrupts = <21>, <22>; - clocks = <&gate_clk 13>; - clock-names = "internal"; - status = "disabled"; - }; - - pmu: power-management@d0000 { - compatible = "marvell,dove-pmu", "simple-bus"; - reg = <0xd0000 0x8000>, <0xd8000 0x8000>; - ranges = <0x00000000 0x000d0000 0x8000 - 0x00008000 0x000d8000 0x8000>; - interrupts = <33>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - #reset-cells = <1>; - - domains { - vpu_domain: vpu-domain { - #power-domain-cells = <0>; - marvell,pmu_pwr_mask = <0x00000008>; - marvell,pmu_iso_mask = <0x00000001>; - resets = <&pmu 16>; - }; - - gpu_domain: gpu-domain { - #power-domain-cells = <0>; - marvell,pmu_pwr_mask = <0x00000004>; - marvell,pmu_iso_mask = <0x00000002>; - resets = <&pmu 18>; - }; - }; - - thermal: thermal-diode@001c { - compatible = "marvell,dove-thermal"; - reg = <0x001c 0x0c>, <0x005c 0x08>; - }; - - gate_clk: clock-gating-ctrl@0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0x0038 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - divider_clk: core-clock@0064 { - compatible = "marvell,dove-divider-clock"; - reg = <0x0064 0x8>; - #clock-cells = <1>; - }; - - pinctrl: pin-ctrl@0200 { - compatible = "marvell,dove-pinctrl"; - reg = <0x0200 0x14>, - <0x0440 0x04>; - clocks = <&gate_clk 22>; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; - - pmx_gpio_8: pmx-gpio-8 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_gpio_9: pmx-gpio-9 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_pcie1_clkreq: pmx-pcie1-clkreq { - marvell,pins = "mpp9"; - marvell,function = "pex1"; - }; - - pmx_gpio_10: pmx-gpio-10 { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_gpio_11: pmx-gpio-11 { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - - pmx_pcie0_clkreq: pmx-pcie0-clkreq { - marvell,pins = "mpp11"; - marvell,function = "pex0"; - }; - - pmx_gpio_12: pmx-gpio-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_gpio_13: pmx-gpio-13 { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_audio1_extclk: pmx-audio1-extclk { - marvell,pins = "mpp13"; - marvell,function = "audio1"; - }; - - pmx_gpio_14: pmx-gpio-14 { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_gpio_15: pmx-gpio-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_gpio_16: pmx-gpio-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_gpio_17: pmx-gpio-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_gpio_18: pmx-gpio-18 { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_gpio_19: pmx-gpio-19 { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_gpio_20: pmx-gpio-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_gpio_21: pmx-gpio-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_camera: pmx-camera { - marvell,pins = "mpp_camera"; - marvell,function = "camera"; - }; - - pmx_camera_gpio: pmx-camera-gpio { - marvell,pins = "mpp_camera"; - marvell,function = "gpio"; - }; - - pmx_sdio0: pmx-sdio0 { - marvell,pins = "mpp_sdio0"; - marvell,function = "sdio0"; - }; - - pmx_sdio0_gpio: pmx-sdio0-gpio { - marvell,pins = "mpp_sdio0"; - marvell,function = "gpio"; - }; - - pmx_sdio1: pmx-sdio1 { - marvell,pins = "mpp_sdio1"; - marvell,function = "sdio1"; - }; - - pmx_sdio1_gpio: pmx-sdio1-gpio { - marvell,pins = "mpp_sdio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_gpio: pmx-audio1-gpio { - marvell,pins = "mpp_audio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { - marvell,pins = "mpp_audio1"; - marvell,function = "i2s1/spdifo"; - }; - - pmx_spi0: pmx-spi0 { - marvell,pins = "mpp_spi0"; - marvell,function = "spi0"; - }; - - pmx_spi0_gpio: pmx-spi0-gpio { - marvell,pins = "mpp_spi0"; - marvell,function = "gpio"; - }; - - pmx_spi1_4_7: pmx-spi1-4-7 { - marvell,pins = "mpp4", "mpp5", - "mpp6", "mpp7"; - marvell,function = "spi1"; - }; - - pmx_spi1_20_23: pmx-spi1-20-23 { - marvell,pins = "mpp20", "mpp21", - "mpp22", "mpp23"; - marvell,function = "spi1"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp_uart1"; - marvell,function = "uart1"; - }; - - pmx_uart1_gpio: pmx-uart1-gpio { - marvell,pins = "mpp_uart1"; - marvell,function = "gpio"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp_nand"; - marvell,function = "nand"; - }; - - pmx_nand_gpo: pmx-nand-gpo { - marvell,pins = "mpp_nand"; - marvell,function = "gpo"; - }; - - pmx_i2c1: pmx-i2c1 { - marvell,pins = "mpp17", "mpp19"; - marvell,function = "twsi"; - }; - - pmx_i2c2: pmx-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "twsi"; - }; - - pmx_ssp_i2c2: pmx-ssp-i2c2 { - marvell,pins = "mpp_audio1"; - marvell,function = "ssp/twsi"; - }; - - pmx_i2cmux_0: pmx-i2cmux-0 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt1"; - }; - - pmx_i2cmux_1: pmx-i2cmux-1 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt2"; - }; - - pmx_i2cmux_2: pmx-i2cmux-2 { - marvell,pins = "twsi"; - marvell,function = "twsi-opt3"; - }; - }; - - core_clk: core-clocks@0214 { - compatible = "marvell,dove-core-clock"; - reg = <0x0214 0x4>; - #clock-cells = <1>; - }; - - gpio0: gpio-ctrl@0400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x0400 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <12>, <13>, <14>, <60>; - }; - - gpio1: gpio-ctrl@0420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x0420 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <61>; - }; - - rtc: real-time-clock@8500 { - compatible = "marvell,orion-rtc"; - reg = <0x8500 0x20>; - interrupts = <5>; - }; - }; - - gconf: global-config@e802c { - compatible = "marvell,dove-global-config", - "syscon"; - reg = <0xe802c 0x14>; - }; - - gpio2: gpio-ctrl@e8400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe8400 0x0c>; - ngpios = <8>; - }; - - lcd1: lcd-controller@810000 { - compatible = "marvell,dove-lcd"; - reg = <0x810000 0x1000>; - interrupts = <46>; - status = "disabled"; - }; - - lcd0: lcd-controller@820000 { - compatible = "marvell,dove-lcd"; - reg = <0x820000 0x1000>; - interrupts = <47>; - status = "disabled"; - }; - - crypto_sram: sa-sram@ffffe000 { - compatible = "mmio-sram"; - reg = <0xffffe000 0x800>; - clocks = <&gate_clk 15>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gpu: gpu@840000 { - clocks = <÷r_clk 1>; - clock-names = "core"; - compatible = "vivante,gc"; - interrupts = <48>; - power-domains = <&gpu_domain>; - reg = <0x840000 0x4000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra62x-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra62x-clocks.dtsi deleted file mode 100644 index 0e4974174..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra62x-clocks.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "dm814x-clocks.dtsi" - -/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */ -&adpll_hdvic_ck { - status = "disabled"; -}; - -&adpll_l3_ck { - status = "disabled"; -}; - -&adpll_dss_ck { - status = "disabled"; -}; - -/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */ -&sysclk4_ck { - clocks = <&adpll_isp_ck 1>; -}; - -&sysclk5_ck { - clocks = <&adpll_isp_ck 1>; -}; - -&sysclk6_ck { - clocks = <&adpll_isp_ck 1>; -}; - -/* - * Compared to dm814x, dra62x has different shifts and more mux options. - * Please add the extra options for ysclk_14 and 16 if really needed. - */ -&timer1_fck { - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <4>; -}; - -&timer2_fck { - clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck - &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; - ti,bit-shift = <8>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/software/linux/kernel/arch/arm/boot/dts/dra62x-j5eco-evm.dts deleted file mode 100644 index 155eb32ee..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "dra62x.dtsi" -#include - -/ { - model = "DRA62x J5 Eco EVM"; - compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16aadwp"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@0x1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@0x280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@0x780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; -}; - -&pincntl { - sd1_pins: pinmux_sd1_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ - DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ - DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ - DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ - DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ - DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ - DM814X_IOPAD(0x0924, PIN_OUTPUT | 0x40) /* SD1_POW */ - DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ - >; - }; -}; - -/* USB0_ID pin state: SW10[1] = 0 cable detection, SW10[1] = 1 ID grounded */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - dr_mode = "otg"; -}; - -&usb1_phy { - status = "disabled"; -}; - -&usb1 { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra62x.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra62x.dtsi deleted file mode 100644 index d3cbb4ea3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra62x.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "dm814x.dtsi" - -/ { - compatible = "ti,dra62x"; -}; - -/* Compared to dm814x, dra62x has different offsets for Ethernet */ -&mac { - reg = <0x4a100000 0x800 - 0x4a101200 0x100>; -}; - -&davinci_mdio { - reg = <0x4a101000 0x100>; -}; - -#include "dra62x-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi deleted file mode 100644 index 1c39a8459..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Device Tree Source for DRA7x SoC DSPEVE thermal - * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -dspeve_thermal: dspeve_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 3>; - - trips { - dspeve_crit: dspeve_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra7-evm.dts b/software/linux/kernel/arch/arm/boot/dts/dra7-evm.dts deleted file mode 100644 index 132f2be10..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra7-evm.dts +++ /dev/null @@ -1,939 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "dra74x.dtsi" -#include -#include -#include - -/ { - model = "TI DRA742"; - compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - evm_3v3_sw: fixedregulator-evm_3v3_sw { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sw"; - vin-supply = <&sysen1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3_sw>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - vtt_fixed: fixedregulator-vtt { - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - vin-supply = <&sysen2>; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; - }; - - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; - }; - }; - - leds { - compatible = "gpio-leds"; - led0 { - label = "dra7:usr1"; - gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "dra7:usr2"; - gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "dra7:usr3"; - gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "dra7:usr4"; - gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - USER1 { - label = "btnUser1"; - linux,code = ; - gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; - }; - - USER2 { - label = "btnUser2"; - linux,code = ; - gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&dra7_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&vtt_pin>; - - vtt_pin: pinmux_vtt_pin { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ - DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */ - DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */ - DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */ - DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ - DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */ - DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ - DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ - DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ - DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ - DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - nand_flash_x16: nand_flash_x16 { - /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch - * So NAND flash requires following switch settings: - * SW5.1 (NAND_BOOTn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ - DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ - DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ - DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ - DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ - DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ - DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ - DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15) - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; - - atl_pins: pinmux_atl_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ - DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ - >; - }; - - mcasp3_pins: pinmux_mcasp3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ - >; - }; - - mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps123_reg: smps123 { - /* VDD_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* CORE_VDD */ - regulator-name = "smps7"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_IVAHD */ - regulator-name = "smps8"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDS1V8 */ - regulator-name = "smps9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: ldo2 { - /* VDD_RTCIO */ - /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - /* REGEN1 is unused */ - - regen2: regen2 { - /* Needed for PMIC internal resources */ - regulator-name = "regen2"; - regulator-boot-on; - regulator-always-on; - }; - - /* REGEN3 is unused */ - - sysen1: sysen1 { - /* PMIC_REGEN_3V3 */ - regulator-name = "sysen1"; - regulator-boot-on; - regulator-always-on; - }; - - sysen2: sysen2 { - /* PMIC_REGEN_DDR */ - regulator-name = "sysen2"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - }; - - pcf_lcd: gpio@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&evm_3v3_sw>; - IOVDD-supply = <&evm_3v3_sw>; - DRVDD-supply = <&evm_3v3_sw>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; - - pcf_hdmi: gpio@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - p1 { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; -}; - -&mcspi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -&mcspi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3e0>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&evm_3v3_sd>; - vmmc_aux-supply = <&ldo1_reg>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is always hardwired. - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&evm_3v3_sw>; - bus-width = <8>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb1 { - dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&usb2 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x16>; - ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&gpio7 { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <2>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <3>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - -&dcan1 { - status = "ok"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&atl { - pinctrl-names = "default"; - pinctrl-0 = <&atl_pins>; - - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_gfclk_mux>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - - status = "okay"; - - atl2 { - bws = ; - aws = ; - }; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins>; - pinctrl-1 = <&mcasp3_sleep_pins>; - - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&atl_clkin2_ck>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra7-iva-thermal.dtsi deleted file mode 100644 index dd74a5337..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra7-iva-thermal.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Device Tree Source for DRA7x SoC IVA thermal - * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -iva_thermal: iva_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 4>; - - trips { - iva_crit: iva_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra7.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra7.dtsi deleted file mode 100644 index ce54a70b7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra7.dtsi +++ /dev/null @@ -1,1989 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * Based on "omap4.dtsi" - */ - -#include -#include - -#define MAX_SOURCES 400 - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "ti,dra7xx"; - interrupt-parent = <&crossbar_mpu>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - serial8 = &uart9; - serial9 = &uart10; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; - d_can0 = &dcan1; - d_can1 = &dcan2; - spi0 = &qspi; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x48211000 0x0 0x1000>, - <0x0 0x48212000 0x0 0x1000>, - <0x0 0x48214000 0x0 0x2000>, - <0x0 0x48216000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x48281000 0x0 0x1000>; - interrupt-parent = <&gic>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap5-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the SOC interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,dra7-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0xc0000000>; - ti,hwmods = "l3_main_1", "l3_main_2"; - reg = <0x0 0x44000000 0x0 0x1000000>, - <0x0 0x45000000 0x0 0x1000>; - interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - - l4_cfg: l4@4a000000 { - compatible = "ti,dra7-l4-cfg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x22c000>; - - scm: scm@2000 { - compatible = "ti,dra7-scm-core", "simple-bus"; - reg = <0x2000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x2000>; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x1400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x1400>; - - pbias_regulator: pbias_regulator@e00 { - compatible = "ti,pbias-dra7", "ti,pbias-omap"; - reg = <0xe00 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - scm_conf_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dra7_pmx_core: pinmux@1400 { - compatible = "ti,dra7-padconf", - "pinctrl-single"; - reg = <0x1400 0x0468>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - - scm_conf1: scm_conf@1c04 { - compatible = "syscon"; - reg = <0x1c04 0x0020>; - }; - - scm_conf_pcie: scm_conf@1c24 { - compatible = "syscon"; - reg = <0x1c24 0x0024>; - }; - - sdma_xbar: dma-router@b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0xb78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - dma-masters = <&sdma>; - }; - - edma_xbar: dma-router@c78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0xc78 0x7c>; - #dma-cells = <2>; - dma-requests = <204>; - ti,dma-safe-map = <0>; - dma-masters = <&edma>; - }; - }; - - cm_core_aon: cm_core_aon@5000 { - compatible = "ti,dra7-cm-core-aon"; - reg = <0x5000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core@8000 { - compatible = "ti,dra7-cm-core"; - reg = <0x8000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - }; - - l4_wkup: l4@4ae00000 { - compatible = "ti,dra7-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4ae00000 0x3f000>; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x40>; - ti,hwmods = "counter_32k"; - }; - - prm: prm@6000 { - compatible = "ti,dra7-prm"; - reg = <0x6000 0x3000>; - interrupts = ; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - scm_wkup: scm_conf@c000 { - compatible = "syscon"; - reg = <0xc000 0x1000>; - }; - }; - - axi@0 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51000000 0x51000000 0x3000 - 0x0 0x20000000 0x10000000>; - pcie1: pcie@51000000 { - compatible = "ti,dra7-pcie"; - reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 232 0x4>, <0 233 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x20013000 0x13000 0 0xffed000>; - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - num-lanes = <1>; - linux,pci-domain = <0>; - ti,hwmods = "pcie1"; - phys = <&pcie1_phy>; - phy-names = "pcie-phy0"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 1>, - <0 0 0 2 &pcie1_intc 2>, - <0 0 0 3 &pcie1_intc 3>, - <0 0 0 4 &pcie1_intc 4>; - pcie1_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - axi@1 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51800000 0x51800000 0x3000 - 0x0 0x30000000 0x10000000>; - status = "disabled"; - pcie@51800000 { - compatible = "ti,dra7-pcie"; - reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 355 0x4>, <0 356 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x30013000 0x13000 0 0xffed000>; - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - num-lanes = <1>; - linux,pci-domain = <1>; - ti,hwmods = "pcie2"; - phys = <&pcie2_phy>; - phy-names = "pcie-phy0"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 1>, - <0 0 0 2 &pcie2_intc 2>, - <0 0 0 3 &pcie2_intc 3>, - <0 0 0 4 &pcie2_intc 4>; - pcie2_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - ocmcram1: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x80000>; - ranges = <0x0 0x40300000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - /* - * This is a placeholder for an optional reserved - * region for use by secure software. The size - * of this region is not known until runtime so it - * is set as zero to either be updated to reserve - * space or left unchanged to leave all SRAM for use. - * On HS parts that that require the reserved region - * either the bootloader can update the size to - * the required amount or the node can be overridden - * from the board dts file for the secure platform. - */ - sram-hs@0 { - compatible = "ti,secure-ram"; - reg = <0x0 0x0>; - }; - }; - - /* - * NOTE: ocmcram2 and ocmcram3 are not available on all - * DRA7xx and AM57xx variants. Confirm availability in - * the data manual for the exact part number in use - * before enabling these nodes in the board dts file. - */ - ocmcram2: ocmcram@40400000 { - status = "disabled"; - compatible = "mmio-sram"; - reg = <0x40400000 0x100000>; - ranges = <0x0 0x40400000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - ocmcram3: ocmcram@40500000 { - status = "disabled"; - compatible = "mmio-sram"; - reg = <0x40500000 0x100000>; - ranges = <0x0 0x40500000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - bandgap: bandgap@4a0021e0 { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c - 0x4a002564 0x8 - 0x4a002574 0x50>; - compatible = "ti,dra752-bandgap"; - interrupts = ; - #thermal-sensor-cells = <1>; - }; - - dsp1_system: dsp_system@40d00000 { - compatible = "syscon"; - reg = <0x40d00000 0x100>; - }; - - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - - edma: edma@43300000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x43300000 0x100000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; - - /* - * memcpy is disabled, can be enabled with: - * ti,edma-memcpy-channels = <20 21>; - * for example. Note that these channels need to be - * masked in the xbar as well. - */ - }; - - edma_tptc0: tptc@43400000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x43400000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@43500000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x43500000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - gpio1: gpio@4ae10000 { - compatible = "ti,omap4-gpio"; - reg = <0x4ae10000 0x200>; - interrupts = ; - ti,hwmods = "gpio1"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - reg = <0x48055000 0x200>; - interrupts = ; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - reg = <0x48057000 0x200>; - interrupts = ; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - reg = <0x48059000 0x200>; - interrupts = ; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805b000 0x200>; - interrupts = ; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805d000 0x200>; - interrupts = ; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@48051000 { - compatible = "ti,omap4-gpio"; - reg = <0x48051000 0x200>; - interrupts = ; - ti,hwmods = "gpio7"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@48053000 { - compatible = "ti,omap4-gpio"; - reg = <0x48053000 0x200>; - interrupts = ; - ti,hwmods = "gpio8"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart1: serial@4806a000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; - dma-names = "tx", "rx"; - }; - - uart2: serial@4806c000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x4806c000 0x100>; - interrupts = ; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; - dma-names = "tx", "rx"; - }; - - uart3: serial@48020000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48020000 0x100>; - interrupts = ; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; - dma-names = "tx", "rx"; - }; - - uart4: serial@4806e000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x4806e000 0x100>; - interrupts = ; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; - dma-names = "tx", "rx"; - }; - - uart5: serial@48066000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48066000 0x100>; - interrupts = ; - ti,hwmods = "uart5"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; - dma-names = "tx", "rx"; - }; - - uart6: serial@48068000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48068000 0x100>; - interrupts = ; - ti,hwmods = "uart6"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; - dma-names = "tx", "rx"; - }; - - uart7: serial@48420000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48420000 0x100>; - interrupts = ; - ti,hwmods = "uart7"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart8: serial@48422000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48422000 0x100>; - interrupts = ; - ti,hwmods = "uart8"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart9: serial@48424000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48424000 0x100>; - interrupts = ; - ti,hwmods = "uart9"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart10: serial@4ae2b000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x4ae2b000 0x100>; - interrupts = ; - ti,hwmods = "uart10"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - mailbox1: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = , - , - ; - ti,hwmods = "mailbox1"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - status = "disabled"; - }; - - mailbox2: mailbox@4883a000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4883a000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox2"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox3: mailbox@4883c000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4883c000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox3"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox4: mailbox@4883e000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4883e000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox4"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox5: mailbox@48840000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48840000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox5"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox6: mailbox@48842000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48842000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox6"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox7: mailbox@48844000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48844000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox7"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox8: mailbox@48846000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48846000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox8"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox9: mailbox@4885e000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4885e000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox9"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox10: mailbox@48860000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48860000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox10"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox11: mailbox@48862000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48862000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox11"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox12: mailbox@48864000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48864000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox12"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox13: mailbox@48802000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48802000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox13"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - timer1: timer@4ae18000 { - compatible = "ti,omap5430-timer"; - reg = <0x4ae18000 0x80>; - interrupts = ; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@48032000 { - compatible = "ti,omap5430-timer"; - reg = <0x48032000 0x80>; - interrupts = ; - ti,hwmods = "timer2"; - }; - - timer3: timer@48034000 { - compatible = "ti,omap5430-timer"; - reg = <0x48034000 0x80>; - interrupts = ; - ti,hwmods = "timer3"; - }; - - timer4: timer@48036000 { - compatible = "ti,omap5430-timer"; - reg = <0x48036000 0x80>; - interrupts = ; - ti,hwmods = "timer4"; - }; - - timer5: timer@48820000 { - compatible = "ti,omap5430-timer"; - reg = <0x48820000 0x80>; - interrupts = ; - ti,hwmods = "timer5"; - }; - - timer6: timer@48822000 { - compatible = "ti,omap5430-timer"; - reg = <0x48822000 0x80>; - interrupts = ; - ti,hwmods = "timer6"; - }; - - timer7: timer@48824000 { - compatible = "ti,omap5430-timer"; - reg = <0x48824000 0x80>; - interrupts = ; - ti,hwmods = "timer7"; - }; - - timer8: timer@48826000 { - compatible = "ti,omap5430-timer"; - reg = <0x48826000 0x80>; - interrupts = ; - ti,hwmods = "timer8"; - }; - - timer9: timer@4803e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4803e000 0x80>; - interrupts = ; - ti,hwmods = "timer9"; - }; - - timer10: timer@48086000 { - compatible = "ti,omap5430-timer"; - reg = <0x48086000 0x80>; - interrupts = ; - ti,hwmods = "timer10"; - }; - - timer11: timer@48088000 { - compatible = "ti,omap5430-timer"; - reg = <0x48088000 0x80>; - interrupts = ; - ti,hwmods = "timer11"; - }; - - timer12: timer@4ae20000 { - compatible = "ti,omap5430-timer"; - reg = <0x4ae20000 0x80>; - interrupts = ; - ti,hwmods = "timer12"; - ti,timer-alwon; - ti,timer-secure; - }; - - timer13: timer@48828000 { - compatible = "ti,omap5430-timer"; - reg = <0x48828000 0x80>; - interrupts = ; - ti,hwmods = "timer13"; - }; - - timer14: timer@4882a000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882a000 0x80>; - interrupts = ; - ti,hwmods = "timer14"; - }; - - timer15: timer@4882c000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882c000 0x80>; - interrupts = ; - ti,hwmods = "timer15"; - }; - - timer16: timer@4882e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882e000 0x80>; - interrupts = ; - ti,hwmods = "timer16"; - }; - - wdt2: wdt@4ae14000 { - compatible = "ti,omap3-wdt"; - reg = <0x4ae14000 0x80>; - interrupts = ; - ti,hwmods = "wd_timer2"; - }; - - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - dmm@4e000000 { - compatible = "ti,omap5-dmm"; - reg = <0x4e000000 0x800>; - interrupts = ; - ti,hwmods = "dmm"; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - reg = <0x48070000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - status = "disabled"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - reg = <0x48072000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - status = "disabled"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - reg = <0x48060000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - status = "disabled"; - }; - - i2c4: i2c@4807a000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807a000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - status = "disabled"; - }; - - i2c5: i2c@4807c000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c5"; - status = "disabled"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - interrupts = ; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; - dma-names = "tx", "rx"; - status = "disabled"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480b4000 0x400>; - interrupts = ; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480ad000 0x400>; - interrupts = ; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d1000 0x400>; - interrupts = ; - ti,hwmods = "mmc4"; - ti,needs-special-reset; - dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmu0_dsp1: mmu@40d01000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x40d01000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp1"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x0>; - status = "disabled"; - }; - - mmu1_dsp1: mmu@40d02000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x40d02000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp1"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp1_system 0x1>; - status = "disabled"; - }; - - mmu_ipu1: mmu@58882000 { - compatible = "ti,dra7-iommu"; - reg = <0x58882000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu1"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - status = "disabled"; - }; - - mmu_ipu2: mmu@55082000 { - compatible = "ti,dra7-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu2"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - status = "disabled"; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v3"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, - <0x4ae06014 0x4>, <0x4a003b20 0xc>, - <0x4ae0c158 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x80>; - /* LDOVBBMPU_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMPU_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1160000 0 0x4 0 0x02000000 0x01F00000 - 1210000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_ivahd: regulator-abb-ivahd { - compatible = "ti,abb-v3"; - regulator-name = "abb_ivahd"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, - <0x4ae06010 0x4>, <0x4a0025cc 0xc>, - <0x4a002470 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x40000000>; - /* LDOVBBIVA_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBIVA_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1055000 0 0x0 0 0x02000000 0x01F00000 - 1150000 0 0x4 0 0x02000000 0x01F00000 - 1250000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_dspeve: regulator-abb-dspeve { - compatible = "ti,abb-v3"; - regulator-name = "abb_dspeve"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, - <0x4ae06010 0x4>, <0x4a0025e0 0xc>, - <0x4a00246c 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x20000000>; - /* LDOVBBDSPEVE_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBDSPEVE_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1055000 0 0x0 0 0x02000000 0x01F00000 - 1150000 0 0x4 0 0x02000000 0x01F00000 - 1250000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - abb_gpu: regulator-abb-gpu { - compatible = "ti,abb-v3"; - regulator-name = "abb_gpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin1>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, - <0x4ae06010 0x4>, <0x4a003b08 0xc>, - <0x4ae0c154 0x4>; - reg-names = "setup-address", "control-address", - "int-address", "efuse-address", - "ldo-address"; - ti,tranxdone-status-mask = <0x10000000>; - /* LDOVBBGPU_FBB_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBGPU_FBB_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1090000 0 0x0 0 0x02000000 0x01F00000 - 1210000 0 0x4 0 0x02000000 0x01F00000 - 1280000 0 0x8 0 0x02000000 0x01F00000 - >; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma_xbar 35>, - <&sdma_xbar 36>, - <&sdma_xbar 37>, - <&sdma_xbar 38>, - <&sdma_xbar 39>, - <&sdma_xbar 40>, - <&sdma_xbar 41>, - <&sdma_xbar 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - status = "disabled"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma_xbar 43>, - <&sdma_xbar 44>, - <&sdma_xbar 45>, - <&sdma_xbar 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - - qspi: qspi@4b300000 { - compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>, - <0x5c000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - syscon-chipselects = <&scm_conf 0x558>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "qspi"; - clocks = <&qspi_gfclk_div>; - clock-names = "fck"; - num-cs = <4>; - interrupts = ; - status = "disabled"; - }; - - /* OCP2SCP3 */ - ocp2scp@4a090000 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0x4a090000 0x20>; - ti,hwmods = "ocp2scp3"; - sata_phy: phy@4A096000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x4A096000 0x80>, /* phy_rx */ - <0x4A096400 0x64>, /* phy_tx */ - <0x4A096800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin1>, <&sata_ref_clk>; - clock-names = "sysclk", "refclk"; - syscon-pllreset = <&scm_conf 0x3fc>; - #phy-cells = <0>; - }; - - pcie1_phy: pciephy@4a094000 { - compatible = "ti,phy-pipe3-pcie"; - reg = <0x4a094000 0x80>, /* phy_rx */ - <0x4a094400 0x64>; /* phy_tx */ - reg-names = "phy_rx", "phy_tx"; - syscon-phy-power = <&scm_conf_pcie 0x1c>; - syscon-pcs = <&scm_conf_pcie 0x10>; - clocks = <&dpll_pcie_ref_ck>, - <&dpll_pcie_ref_m2ldo_ck>, - <&optfclk_pciephy1_32khz>, - <&optfclk_pciephy1_clk>, - <&optfclk_pciephy1_div_clk>, - <&optfclk_pciephy_div>, - <&sys_clkin1>; - clock-names = "dpll_ref", "dpll_ref_m2", - "wkupclk", "refclk", - "div-clk", "phy-div", "sysclk"; - #phy-cells = <0>; - }; - - pcie2_phy: pciephy@4a095000 { - compatible = "ti,phy-pipe3-pcie"; - reg = <0x4a095000 0x80>, /* phy_rx */ - <0x4a095400 0x64>; /* phy_tx */ - reg-names = "phy_rx", "phy_tx"; - syscon-phy-power = <&scm_conf_pcie 0x20>; - syscon-pcs = <&scm_conf_pcie 0x10>; - clocks = <&dpll_pcie_ref_ck>, - <&dpll_pcie_ref_m2ldo_ck>, - <&optfclk_pciephy2_32khz>, - <&optfclk_pciephy2_clk>, - <&optfclk_pciephy2_div_clk>, - <&optfclk_pciephy_div>, - <&sys_clkin1>; - clock-names = "dpll_ref", "dpll_ref_m2", - "wkupclk", "refclk", - "div-clk", "phy-div", "sysclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&sata_ref_clk>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; - }; - - rtc: rtc@48838000 { - compatible = "ti,am3352-rtc"; - reg = <0x48838000 0x100>; - interrupts = , - ; - ti,hwmods = "rtcss"; - clocks = <&sys_32k_ck>; - }; - - /* OCP2SCP1 */ - ocp2scp@4a080000 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0x4a080000 0x20>; - ti,hwmods = "ocp2scp1"; - - usb2_phy1: phy@4a084000 { - compatible = "ti,dra7x-usb2", "ti,omap-usb2"; - reg = <0x4a084000 0x400>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy1_always_on_clk32k>, - <&usb_otg_ss1_refclk960m>; - clock-names = "wkupclk", - "refclk"; - #phy-cells = <0>; - }; - - usb2_phy2: phy@4a085000 { - compatible = "ti,dra7x-usb2-phy2", - "ti,omap-usb2"; - reg = <0x4a085000 0x400>; - syscon-phy-power = <&scm_conf 0xe74>; - clocks = <&usb_phy2_always_on_clk32k>, - <&usb_otg_ss2_refclk960m>; - clock-names = "wkupclk", - "refclk"; - #phy-cells = <0>; - }; - - usb3_phy1: phy@4a084400 { - compatible = "ti,omap-usb3"; - reg = <0x4a084400 0x80>, - <0x4a084800 0x64>, - <0x4a084c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy3_always_on_clk32k>, - <&sys_clkin1>, - <&usb_otg_ss1_refclk960m>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - - omap_dwc3_1: omap_dwc3_1@48880000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss1"; - reg = <0x48880000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - usb1: usb@48890000 { - compatible = "snps,dwc3"; - reg = <0x48890000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - - omap_dwc3_2: omap_dwc3_2@488c0000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss2"; - reg = <0x488c0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - usb2: usb@488d0000 { - compatible = "snps,dwc3"; - reg = <0x488d0000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - - /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ - omap_dwc3_3: omap_dwc3_3@48900000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss3"; - reg = <0x48900000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb3: usb@48910000 { - compatible = "snps,dwc3"; - reg = <0x48910000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - - elm: elm@48078000 { - compatible = "ti,am3352-elm"; - reg = <0x48078000 0xfc0>; /* device IO registers */ - interrupts = ; - ti,hwmods = "elm"; - status = "disabled"; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x37c>; /* device IO registers */ - interrupts = ; - dmas = <&edma_xbar 4 0>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - atl: atl@4843c000 { - compatible = "ti,dra7-atl"; - reg = <0x4843c000 0x3ff>; - ti,hwmods = "atl"; - ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, - <&atl_clkin2_ck>, <&atl_clkin3_ck>; - clocks = <&atl_gfclk_mux>; - clock-names = "fck"; - status = "disabled"; - }; - - mcasp1: mcasp@48460000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x48460000 0x2000>, - <0x45800000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; - dma-names = "tx", "rx"; - clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, - <&mcasp1_ahclkr_mux>; - clock-names = "fck", "ahclkx", "ahclkr"; - status = "disabled"; - }; - - mcasp2: mcasp@48464000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp2"; - reg = <0x48464000 0x2000>, - <0x45c00000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; - dma-names = "tx", "rx"; - clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, - <&mcasp2_ahclkr_mux>; - clock-names = "fck", "ahclkx", "ahclkr"; - status = "disabled"; - }; - - mcasp3: mcasp@48468000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp3"; - reg = <0x48468000 0x2000>, - <0x46000000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; - dma-names = "tx", "rx"; - clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp4: mcasp@4846c000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp4"; - reg = <0x4846c000 0x2000>, - <0x48436000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; - dma-names = "tx", "rx"; - clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp5: mcasp@48470000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp5"; - reg = <0x48470000 0x2000>, - <0x4843a000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; - dma-names = "tx", "rx"; - clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp6: mcasp@48474000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp6"; - reg = <0x48474000 0x2000>, - <0x4844c000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; - dma-names = "tx", "rx"; - clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp7: mcasp@48478000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp7"; - reg = <0x48478000 0x2000>, - <0x48450000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; - dma-names = "tx", "rx"; - clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp8: mcasp@4847c000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp8"; - reg = <0x4847c000 0x2000>, - <0x48454000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; - dma-names = "tx", "rx"; - clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - crossbar_mpu: crossbar@4a002a48 { - compatible = "ti,irq-crossbar"; - reg = <0x4a002a48 0x130>; - interrupt-controller; - interrupt-parent = <&wakeupgen>; - #interrupt-cells = <3>; - ti,max-irqs = <160>; - ti,max-crossbar-sources = ; - ti,reg-size = <2>; - ti,irqs-reserved = <0 1 2 3 5 6 131 132>; - ti,irqs-skip = <10 133 139 140>; - ti,irqs-safe-map = <0>; - }; - - mac: ethernet@48484000 { - compatible = "ti,dra7-cpsw","ti,cpsw"; - ti,hwmods = "gmac"; - clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - no_bd_ram = <0>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x784CFE14>; - cpts_clock_shift = <29>; - reg = <0x48484000 0x1000 - 0x48485200 0x2E00>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * Do not allow gating of cpsw clock as workaround - * for errata i877. Keeping internal clock disabled - * causes the device switching characteristics - * to degrade over time and eventually fail to meet - * the data manual delay time/skew specs. - */ - ti,no-idle; - - /* - * rx_thresh_pend - * rx_pend - * tx_pend - * misc_pend - */ - interrupts = , - , - , - ; - ranges; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@48485000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - reg = <0x48485000 0x100>; - }; - - cpsw_emac0: slave@48480200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpsw_emac1: slave@48480300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@4a002554 { - compatible = "ti,dra7xx-cpsw-phy-sel"; - reg= <0x4a002554 0x4>; - reg-names = "gmii-sel"; - }; - }; - - dcan1: can@481cc000 { - compatible = "ti,dra7-d_can"; - ti,hwmods = "dcan1"; - reg = <0x4ae3c000 0x2000>; - syscon-raminit = <&scm_conf 0x558 0>; - interrupts = ; - clocks = <&dcan1_sys_clk_mux>; - status = "disabled"; - }; - - dcan2: can@481d0000 { - compatible = "ti,dra7-d_can"; - ti,hwmods = "dcan2"; - reg = <0x48480000 0x2000>; - syscon-raminit = <&scm_conf 0x558 1>; - interrupts = ; - clocks = <&sys_clkin1>; - status = "disabled"; - }; - - dss: dss@58000000 { - compatible = "ti,dra7-dss"; - /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ - /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ - status = "disabled"; - ti,hwmods = "dss_core"; - /* CTRL_CORE_DSS_PLL_CONTROL */ - syscon-pll-ctrl = <&scm_conf 0x538>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,dra7-dispc"; - reg = <0x58001000 0x1000>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&dss_dss_clk>; - clock-names = "fck"; - /* CTRL_CORE_SMA_SW_1 */ - syscon-pol = <&scm_conf 0x534>; - }; - - hdmi: encoder@58060000 { - compatible = "ti,dra7-hdmi"; - reg = <0x58040000 0x200>, - <0x58040200 0x80>, - <0x58040300 0x80>, - <0x58060000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; - clock-names = "fck", "sys_clk"; - }; - }; - - epwmss0: epwmss@4843e000 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x4843e000 0x30>; - ti,hwmods = "epwmss0"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; - - ehrpwm0: pwm@4843e200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x4843e200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - ecap0: ecap@4843e100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x4843e100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - epwmss1: epwmss@48440000 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x48440000 0x30>; - ti,hwmods = "epwmss1"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; - - ehrpwm1: pwm@48440200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48440200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - ecap1: ecap@48440100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x48440100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - epwmss2: epwmss@48442000 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x48442000 0x30>; - ti,hwmods = "epwmss2"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; - - ehrpwm2: pwm@48442200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48442200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - ecap2: ecap@48442100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x48442100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - aes1: aes@4b500000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes1"; - reg = <0x4b500000 0xa0>; - interrupts = ; - dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - - aes2: aes@4b700000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes2"; - reg = <0x4b700000 0xa0>; - interrupts = ; - dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - - des: des@480a5000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x480a5000 0xa0>; - interrupts = ; - dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - - sham: sham@53100000 { - compatible = "ti,omap5-sham"; - ti,hwmods = "sham"; - reg = <0x4b101000 0x300>; - interrupts = ; - dmas = <&edma_xbar 119 0>; - dma-names = "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - - rng: rng@48090000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48090000 0x2000>; - interrupts = ; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - }; - - thermal_zones: thermal-zones { - #include "omap4-cpu-thermal.dtsi" - #include "omap5-gpu-thermal.dtsi" - #include "omap5-core-thermal.dtsi" - #include "dra7-dspeve-thermal.dtsi" - #include "dra7-iva-thermal.dtsi" - }; - -}; - -&cpu_thermal { - polling-delay = <500>; /* milliseconds */ -}; - -/include/ "dra7xx-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/dra72-evm-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra72-evm-common.dtsi deleted file mode 100644 index c94d8d647..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra72-evm-common.dtsi +++ /dev/null @@ -1,817 +0,0 @@ -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "dra72x.dtsi" -#include -#include - -/ { - compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; - - aliases { - display0 = &hdmi0; - }; - - evm_3v3_sw: fixedregulator-evm_3v3 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3_sw>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ - <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; - }; - - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; - }; - }; -}; - -&dra7_pmx_core { - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - nand_default: nand_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ - DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ - DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - tps65917_pins_default: tps65917_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - >; - }; - - atl_pins: pinmux_atl_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ - DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ - >; - }; - - mcasp3_pins: pinmux_mcasp3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ - >; - }; - - mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps65917_pins_default>; - - interrupts = ; /* IRQ_SYS_1N */ - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - tps65917_regulators: regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - - pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&evm_3v3_sw>; - IOVDD-supply = <&evm_3v3_sw>; - DRVDD-supply = <&evm_3v3_sw>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - clock-frequency = <400000>; - - pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - /* - * initial state is used here to keep the mdio interface - * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and - * VIN2_S0 driven high otherwise Ethernet stops working - * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 - */ - lines-initial-states = <0x0f2b>; - - p1 { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; -}; - -&uart1 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3e0>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_default>; - ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - /* To use NAND, DIP switch SW5 must be set like so: - * SW5.1 (NAND_SELn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb1 { - dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&usb2 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - vmmc-supply = <&evm_3v3_sd>; - vmmc_aux-supply = <&ldo1_reg>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is a viable alternative - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - max-frequency = <192000000>; -}; - -&mmc2 { - /* SW5-3 in ON position */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&evm_3v3_sw>; - bus-width = <8>; - ti,non-removable; - max-frequency = <192000000>; -}; - -&dra7_pmx_core { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) - >; - }; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - -&dcan1 { - status = "ok"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldo5_reg>; -}; - -&hdmi { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&atl { - pinctrl-names = "default"; - pinctrl-0 = <&atl_pins>; - - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_gfclk_mux>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - - status = "okay"; - - atl2 { - bws = ; - aws = ; - }; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins>; - pinctrl-1 = <&mcasp3_sleep_pins>; - - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&atl_clkin2_ck>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra72-evm-revc.dts b/software/linux/kernel/arch/arm/boot/dts/dra72-evm-revc.dts deleted file mode 100644 index 064b322a7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra72-evm-revc.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include "dra72-evm-common.dtsi" -#include - -/ { - model = "TI DRA722 Rev C EVM"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ - }; -}; - -&tps65917_regulators { - ldo2_reg: ldo2 { - /* LDO2_OUT --> VDDA_1V8_PHY2 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&hdmi { - vdda-supply = <&ldo2_reg>; -}; - -&pcf_gpio_21 { - interrupt-parent = <&gpio3>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; -}; - -&mac { - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, - <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ - <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - dual_emac; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <2>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <3>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - dp83867_0: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - }; - - dp83867_1: ethernet-phy@3 { - reg = <3>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra72-evm.dts b/software/linux/kernel/arch/arm/boot/dts/dra72-evm.dts deleted file mode 100644 index e3a9b6985..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra72-evm.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include "dra72-evm-common.dtsi" -/ { - model = "TI DRA722"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ - }; -}; - -&tps65917_regulators { - ldo2_reg: ldo2 { - /* LDO2_OUT --> TP1017 (UNUSED) */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-allow-bypass; - }; -}; - -&hdmi { - vdda-supply = <&ldo3_reg>; -}; - -&pcf_gpio_21 { - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; -}; - -&mac { - slaves = <1>; - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <3>; - phy-mode = "rgmii"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra72x.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra72x.dtsi deleted file mode 100644 index 67107605f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra72x.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * Based on "omap4.dtsi" - */ - -#include "dra7.dtsi" - -/ { - compatible = "ti,dra722", "ti,dra72", "ti,dra7"; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&wakeupgen>; - interrupts = ; - }; -}; - -&dss { - reg = <0x58000000 0x80>, - <0x58004054 0x4>, - <0x58004300 0x20>; - reg-names = "dss", "pll1_clkctrl", "pll1"; - - clocks = <&dss_dss_clk>, - <&dss_video1_clk>; - clock-names = "fck", "video1_clk"; -}; - -&mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; - -&mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra74x.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra74x.dtsi deleted file mode 100644 index 0a78347e6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra74x.dtsi +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * Based on "omap4.dtsi" - */ - -#include "dra7.dtsi" - -/ { - compatible = "ti,dra742", "ti,dra74", "ti,dra7"; - - cpus { - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&wakeupgen>; - interrupts = , - ; - }; - - ocp { - dsp2_system: dsp_system@41500000 { - compatible = "syscon"; - reg = <0x41500000 0x100>; - }; - - omap_dwc3_4: omap_dwc3_4@48940000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss4"; - reg = <0x48940000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb4: usb@48950000 { - compatible = "snps,dwc3"; - reg = <0x48950000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - - mmu0_dsp2: mmu@41501000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41501000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - status = "disabled"; - }; - - mmu1_dsp2: mmu@41502000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41502000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - status = "disabled"; - }; - }; -}; - -&dss { - reg = <0x58000000 0x80>, - <0x58004054 0x4>, - <0x58004300 0x20>, - <0x58009054 0x4>, - <0x58009300 0x20>; - reg-names = "dss", "pll1_clkctrl", "pll1", - "pll2_clkctrl", "pll2"; - - clocks = <&dss_dss_clk>, - <&dss_video1_clk>, - <&dss_video2_clk>; - clock-names = "fck", "video1_clk", "video2_clk"; -}; - -&mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; - -&mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - ti,mbox-tx = <6 2 2>; - ti,mbox-rx = <4 2 2>; - status = "disabled"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - ti,mbox-tx = <5 2 2>; - ti,mbox-rx = <1 2 2>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/dra7xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/dra7xx-clocks.dtsi deleted file mode 100644 index 3330738e4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ /dev/null @@ -1,2196 +0,0 @@ -/* - * Device Tree Source for DRA7xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&cm_core_aon_clocks { - atl_clkin0_ck: atl_clkin0_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; - }; - - atl_clkin1_ck: atl_clkin1_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; - }; - - atl_clkin2_ck: atl_clkin2_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; - }; - - atl_clkin3_ck: atl_clkin3_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; - }; - - hdmi_clkin_ck: hdmi_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - mlb_clkin_ck: mlb_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - mlbp_clkin_ck: mlbp_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - pciesref_acs_clk_ck: pciesref_acs_clk_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - ref_clkin0_ck: ref_clkin0_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ref_clkin1_ck: ref_clkin1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ref_clkin2_ck: ref_clkin2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - ref_clkin3_ck: ref_clkin3_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - rmii_clk_ck: rmii_clk_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - sdvenc_clkin_ck: sdvenc_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clk32_crystal_ck: sys_clk32_crystal_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin1>; - clock-mult = <1>; - clock-div = <610>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_20000000_ck: virt_20000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <20000000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - sys_clkin2: sys_clkin2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <22579200>; - }; - - usb_otg_clkin_ck: usb_otg_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - video1_clkin_ck: video1_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - video1_m2_clkin_ck: video1_m2_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - video2_clkin_ck: video2_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - video2_m2_clkin_ck: video2_m2_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_abe_ck>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_byp_mux: dpll_core_byp_mux@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x013c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap5-mpu-dpll-clock"; - clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0170>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_dclk_div: mpu_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_mpu_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x0240>; - }; - - dpll_dsp_ck: dpll_dsp_ck@234 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; - reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; - }; - - dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_dsp_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0244>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - }; - - dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01b0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - iva_dclk: iva_dclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_iva_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02e4>; - }; - - dpll_gpu_ck: dpll_gpu_ck@2d8 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; - reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; - }; - - dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02e8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0130>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - core_dpll_out_dclk_div: core_dpll_out_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x021c>; - }; - - dpll_ddr_ck: dpll_ddr_ck@210 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; - reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; - }; - - dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0220>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02b4>; - }; - - dpll_gmac_ck: dpll_gmac_ck@2a8 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; - reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; - }; - - dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02b8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - video2_dclk_div: video2_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video2_m2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video1_dclk_div: video1_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video1_m2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - hdmi_dclk_div: hdmi_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - per_dpll_hs_clk_div: per_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_eve_byp_mux: dpll_eve_byp_mux@290 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x0290>; - }; - - dpll_eve_ck: dpll_eve_ck@284 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; - reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; - }; - - dpll_eve_m2_ck: dpll_eve_m2_ck@294 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_eve_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0294>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - eve_dclk_div: eve_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_eve_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0140>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0144>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0154>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_ddr_x2_ck: dpll_ddr_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_ddr_ck>; - }; - - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0228>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_dsp_x2_ck: dpll_dsp_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_dsp_ck>; - }; - - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_dsp_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0248>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_x2_ck: dpll_gmac_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_gmac_ck>; - }; - - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x02c8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x02bc>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - gmii_m_clk_div: gmii_m_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_gmac_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - hdmi_clk2_div: hdmi_clk2_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - hdmi_div_clk: hdmi_div_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hdmi_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3_iclk_div: l3_iclk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x0100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; - }; - - l4_root_clk_div: l4_root_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_iclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - video1_clk2_div: video1_clk2_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video1_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video1_div_clk: video1_div_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video1_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video2_clk2_div: video2_clk2_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - video2_div_clk: video2_div_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&video2_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - ipu1_gfclk_mux: ipu1_gfclk_mux@520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; - ti,bit-shift = <24>; - reg = <0x0520>; - }; - - mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <28>; - reg = <0x0550>; - }; - - mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x0550>; - }; - - mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x0550>; - }; - - timer5_gfclk_mux: timer5_gfclk_mux@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; - ti,bit-shift = <24>; - reg = <0x0558>; - }; - - timer6_gfclk_mux: timer6_gfclk_mux@560 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; - ti,bit-shift = <24>; - reg = <0x0560>; - }; - - timer7_gfclk_mux: timer7_gfclk_mux@568 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; - ti,bit-shift = <24>; - reg = <0x0568>; - }; - - timer8_gfclk_mux: timer8_gfclk_mux@570 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; - ti,bit-shift = <24>; - reg = <0x0570>; - }; - - uart6_gfclk_mux: uart6_gfclk_mux@580 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x0580>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin1: sys_clkin1@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0118>; - }; - - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; - reg = <0x0114>; - }; - - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - abe_24m_fclk: abe_24m_fclk@11c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - reg = <0x011c>; - ti,dividers = <8>, <16>; - }; - - aess_fclk: aess_fclk@178 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - reg = <0x0178>; - ti,max-div = <2>; - }; - - abe_giclk_div: abe_giclk_div@174 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&aess_fclk>; - reg = <0x0174>; - ti,max-div = <2>; - }; - - abe_lp_clk_div: abe_lp_clk_div@1d8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - reg = <0x01d8>; - ti,dividers = <16>, <32>; - }; - - abe_sys_clk_div: abe_sys_clk_div@120 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - reg = <0x0120>; - ti,max-div = <2>; - }; - - adc_gfclk_mux: adc_gfclk_mux@1dc { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; - reg = <0x01dc>; - }; - - sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x01c8>; - ti,index-power-of-two; - }; - - sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin2>; - ti,max-div = <64>; - reg = <0x01cc>; - ti,index-power-of-two; - }; - - per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2_ck>; - ti,max-div = <64>; - reg = <0x01bc>; - ti,index-power-of-two; - }; - - dsp_gclk_div: dsp_gclk_div@18c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_dsp_m2_ck>; - ti,max-div = <64>; - reg = <0x018c>; - ti,index-power-of-two; - }; - - gpu_dclk: gpu_dclk@1a0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gpu_m2_ck>; - ti,max-div = <64>; - reg = <0x01a0>; - ti,index-power-of-two; - }; - - emif_phy_dclk_div: emif_phy_dclk_div@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_m2_ck>; - ti,max-div = <64>; - reg = <0x0190>; - ti,index-power-of-two; - }; - - gmac_250m_dclk_div: gmac_250m_dclk_div@19c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_m2_ck>; - ti,max-div = <64>; - reg = <0x019c>; - ti,index-power-of-two; - }; - - gmac_main_clk: gmac_main_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&gmac_250m_dclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,max-div = <64>; - reg = <0x01ac>; - ti,index-power-of-two; - }; - - usb_otg_dclk_div: usb_otg_dclk_div@184 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&usb_otg_clkin_ck>; - ti,max-div = <64>; - reg = <0x0184>; - ti,index-power-of-two; - }; - - sata_dclk_div: sata_dclk_div@1c0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x01c0>; - ti,index-power-of-two; - }; - - pcie2_dclk_div: pcie2_dclk_div@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_pcie_ref_m2_ck>; - ti,max-div = <64>; - reg = <0x01b8>; - ti,index-power-of-two; - }; - - pcie_dclk_div: pcie_dclk_div@1b4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&apll_pcie_m2_ck>; - ti,max-div = <64>; - reg = <0x01b4>; - ti,index-power-of-two; - }; - - emu_dclk_div: emu_dclk_div@194 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - ti,max-div = <64>; - reg = <0x0194>; - ti,index-power-of-two; - }; - - secure_32k_dclk_div: secure_32k_dclk_div@1c4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&secure_32k_clk_src_ck>; - ti,max-div = <64>; - reg = <0x01c4>; - ti,index-power-of-two; - }; - - clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x0158>; - }; - - clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x015c>; - }; - - clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; - reg = <0x0160>; - }; - - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin1>; - clock-mult = <1>; - clock-div = <2>; - }; - - eve_clk: eve_clk@180 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; - reg = <0x0180>; - }; - - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0164>; - }; - - mlb_clk: mlb_clk@134 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mlb_clkin_ck>; - ti,max-div = <64>; - reg = <0x0134>; - ti,index-power-of-two; - }; - - mlbp_clk: mlbp_clk@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mlbp_clkin_ck>; - ti,max-div = <64>; - reg = <0x0130>; - ti,index-power-of-two; - }; - - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2_ck>; - ti,max-div = <64>; - reg = <0x0138>; - ti,index-power-of-two; - }; - - timer_sys_clk_div: timer_sys_clk_div@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin1>; - reg = <0x0144>; - ti,max-div = <2>; - }; - - video1_dpll_clk_mux: video1_dpll_clk_mux@168 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0168>; - }; - - video2_dpll_clk_mux: video2_dpll_clk_mux@16c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x016c>; - }; - - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&abe_lp_clk_div>; - reg = <0x0108>; - }; - - gpio1_dbclk: gpio1_dbclk@1838 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1838>; - }; - - dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - ti,bit-shift = <24>; - reg = <0x1888>; - }; - - timer1_gfclk_mux: timer1_gfclk_mux@1840 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1840>; - }; - - uart10_gfclk_mux: uart10_gfclk_mux@1880 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1880>; - }; -}; -&cm_core_clocks { - dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&sys_clkin1>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; - }; - - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_pcie_ref_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0210>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { - compatible = "ti,mux-clock"; - clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; - #clock-cells = <0>; - reg = <0x021c 0x4>; - ti,bit-shift = <7>; - }; - - apll_pcie_ck: apll_pcie_ck@21c { - #clock-cells = <0>; - compatible = "ti,dra7-apll-clock"; - clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; - reg = <0x021c>, <0x0220>; - }; - - optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - #clock-cells = <0>; - reg = <0x13b0>; - ti,bit-shift = <8>; - }; - - optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 { - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - #clock-cells = <0>; - reg = <0x13b8>; - ti,bit-shift = <8>; - }; - - optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { - compatible = "ti,divider-clock"; - clocks = <&apll_pcie_ck>; - #clock-cells = <0>; - reg = <0x021c>; - ti,dividers = <2>, <1>; - ti,bit-shift = <8>; - ti,max-div = <2>; - }; - - optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { - compatible = "ti,gate-clock"; - clocks = <&apll_pcie_ck>; - #clock-cells = <0>; - reg = <0x13b0>; - ti,bit-shift = <9>; - }; - - optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 { - compatible = "ti,gate-clock"; - clocks = <&apll_pcie_ck>; - #clock-cells = <0>; - reg = <0x13b8>; - ti,bit-shift = <9>; - }; - - optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { - compatible = "ti,gate-clock"; - clocks = <&optfclk_pciephy_div>; - #clock-cells = <0>; - reg = <0x13b0>; - ti,bit-shift = <10>; - }; - - optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 { - compatible = "ti,gate-clock"; - clocks = <&optfclk_pciephy_div>; - #clock-cells = <0>; - reg = <0x13b8>; - ti,bit-shift = <10>; - }; - - apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - apll_pcie_m2_ck: apll_pcie_m2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll_pcie_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_per_byp_mux: dpll_per_byp_mux@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - func_96m_aon_dclk_div: func_96m_aon_dclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0190>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_pcie_ref_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0210>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_x2_ck: dpll_per_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_per_ck>; - }; - - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0160>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - ti,autoidle-shift = <8>; - reg = <0x0164>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - func_128m_clk: func_128m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_48m_fclk: func_48m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_96m_fclk: func_96m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_60m_fclk: l3init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - clkout2_clk: clkout2_clk@6b0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkoutmux2_clk_mux>; - ti,bit-shift = <8>; - reg = <0x06b0>; - }; - - l3init_960m_gfclk: l3init_960m_gfclk@6c0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x06c0>; - }; - - dss_32khz_clk: dss_32khz_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <11>; - reg = <0x1120>; - }; - - dss_48mhz_clk: dss_48mhz_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48m_fclk>; - ti,bit-shift = <9>; - reg = <0x1120>; - }; - - dss_dss_clk: dss_dss_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_h12x2_ck>; - ti,bit-shift = <8>; - reg = <0x1120>; - ti,set-rate-parent; - }; - - dss_hdmi_clk: dss_hdmi_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&hdmi_dpll_clk_mux>; - ti,bit-shift = <10>; - reg = <0x1120>; - }; - - dss_video1_clk: dss_video1_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&video1_dpll_clk_mux>; - ti,bit-shift = <12>; - reg = <0x1120>; - }; - - dss_video2_clk: dss_video2_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&video2_dpll_clk_mux>; - ti,bit-shift = <13>; - reg = <0x1120>; - }; - - gpio2_dbclk: gpio2_dbclk@1760 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1760>; - }; - - gpio3_dbclk: gpio3_dbclk@1768 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1768>; - }; - - gpio4_dbclk: gpio4_dbclk@1770 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1770>; - }; - - gpio5_dbclk: gpio5_dbclk@1778 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1778>; - }; - - gpio6_dbclk: gpio6_dbclk@1780 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1780>; - }; - - gpio7_dbclk: gpio7_dbclk@1810 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1810>; - }; - - gpio8_dbclk: gpio8_dbclk@1818 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1818>; - }; - - mmc1_clk32k: mmc1_clk32k@1328 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1328>; - }; - - mmc2_clk32k: mmc2_clk32k@1330 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1330>; - }; - - mmc3_clk32k: mmc3_clk32k@1820 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1820>; - }; - - mmc4_clk32k: mmc4_clk32k@1828 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1828>; - }; - - sata_ref_clk: sata_ref_clk@1388 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin1>; - ti,bit-shift = <8>; - reg = <0x1388>; - }; - - usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_960m_gfclk>; - ti,bit-shift = <8>; - reg = <0x13f0>; - }; - - usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_960m_gfclk>; - ti,bit-shift = <8>; - reg = <0x1340>; - }; - - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0688>; - }; - - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0698>; - }; - - atl_dpll_clk_mux: atl_dpll_clk_mux@c00 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>; - ti,bit-shift = <24>; - reg = <0x0c00>; - }; - - atl_gfclk_mux: atl_gfclk_mux@c00 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>; - ti,bit-shift = <26>; - reg = <0x0c00>; - }; - - rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; - ti,bit-shift = <24>; - reg = <0x13d0>; - }; - - gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>; - ti,bit-shift = <25>; - reg = <0x13d0>; - }; - - gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; - ti,bit-shift = <24>; - reg = <0x1220>; - }; - - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; - ti,bit-shift = <26>; - reg = <0x1220>; - }; - - l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&wkupaon_iclk_mux>; - ti,bit-shift = <24>; - reg = <0x0e50>; - ti,dividers = <8>, <16>, <32>; - }; - - mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <28>; - reg = <0x1860>; - }; - - mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1860>; - }; - - mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1860>; - }; - - mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1868>; - }; - - mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1868>; - }; - - mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1898>; - }; - - mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1898>; - }; - - mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1878>; - }; - - mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1878>; - }; - - mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1904>; - }; - - mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1904>; - }; - - mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <24>; - reg = <0x1908>; - }; - - mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <22>; - reg = <0x1908>; - }; - - mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; - ti,bit-shift = <22>; - reg = <0x1890>; - }; - - mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; - ti,bit-shift = <24>; - reg = <0x1890>; - }; - - mmc1_fclk_mux: mmc1_fclk_mux@1328 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1328>; - }; - - mmc1_fclk_div: mmc1_fclk_div@1328 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc1_fclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1328>; - ti,index-power-of-two; - }; - - mmc2_fclk_mux: mmc2_fclk_mux@1330 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1330>; - }; - - mmc2_fclk_div: mmc2_fclk_div@1330 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc2_fclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1330>; - ti,index-power-of-two; - }; - - mmc3_gfclk_mux: mmc3_gfclk_mux@1820 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1820>; - }; - - mmc3_gfclk_div: mmc3_gfclk_div@1820 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc3_gfclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1820>; - ti,index-power-of-two; - }; - - mmc4_gfclk_mux: mmc4_gfclk_mux@1828 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1828>; - }; - - mmc4_gfclk_div: mmc4_gfclk_div@1828 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc4_gfclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1828>; - ti,index-power-of-two; - }; - - qspi_gfclk_mux: qspi_gfclk_mux@1838 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>; - ti,bit-shift = <24>; - reg = <0x1838>; - }; - - qspi_gfclk_div: qspi_gfclk_div@1838 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&qspi_gfclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <4>; - reg = <0x1838>; - ti,index-power-of-two; - }; - - timer10_gfclk_mux: timer10_gfclk_mux@1728 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1728>; - }; - - timer11_gfclk_mux: timer11_gfclk_mux@1730 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1730>; - }; - - timer13_gfclk_mux: timer13_gfclk_mux@17c8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x17c8>; - }; - - timer14_gfclk_mux: timer14_gfclk_mux@17d0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x17d0>; - }; - - timer15_gfclk_mux: timer15_gfclk_mux@17d8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x17d8>; - }; - - timer16_gfclk_mux: timer16_gfclk_mux@1830 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1830>; - }; - - timer2_gfclk_mux: timer2_gfclk_mux@1738 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1738>; - }; - - timer3_gfclk_mux: timer3_gfclk_mux@1740 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1740>; - }; - - timer4_gfclk_mux: timer4_gfclk_mux@1748 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1748>; - }; - - timer9_gfclk_mux: timer9_gfclk_mux@1750 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; - ti,bit-shift = <24>; - reg = <0x1750>; - }; - - uart1_gfclk_mux: uart1_gfclk_mux@1840 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1840>; - }; - - uart2_gfclk_mux: uart2_gfclk_mux@1848 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1848>; - }; - - uart3_gfclk_mux: uart3_gfclk_mux@1850 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1850>; - }; - - uart4_gfclk_mux: uart4_gfclk_mux@1858 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1858>; - }; - - uart5_gfclk_mux: uart5_gfclk_mux@1870 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1870>; - }; - - uart7_gfclk_mux: uart7_gfclk_mux@18d0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x18d0>; - }; - - uart8_gfclk_mux: uart8_gfclk_mux@18e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x18e0>; - }; - - uart9_gfclk_mux: uart9_gfclk_mux@18e8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x18e8>; - }; - - vip1_gclk_mux: vip1_gclk_mux@1020 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1020>; - }; - - vip2_gclk_mux: vip2_gclk_mux@1028 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1028>; - }; - - vip3_gclk_mux: vip3_gclk_mux@1030 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; - ti,bit-shift = <24>; - reg = <0x1030>; - }; -}; - -&cm_core_clockdomains { - coreaon_clkdm: coreaon_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scm_conf_clocks { - dss_deshdcp_clk: dss_deshdcp_clk@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_iclk_div>; - ti,bit-shift = <0>; - reg = <0x558>; - }; - - ehrpwm0_tbclk: ehrpwm0_tbclk@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <20>; - reg = <0x0558>; - }; - - ehrpwm1_tbclk: ehrpwm1_tbclk@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <21>; - reg = <0x0558>; - }; - - ehrpwm2_tbclk: ehrpwm2_tbclk@558 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_root_clk_div>; - ti,bit-shift = <22>; - reg = <0x0558>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; - ti,bit-shift = <8>; - reg = <0x6c4>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ecx-2000.dts b/software/linux/kernel/arch/arm/boot/dts/ecx-2000.dts deleted file mode 100644 index 2ccbb57fb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ecx-2000.dts +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2011-2012 Calxeda, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -/dts-v1/; - -/* First 4KB has pen for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; - -/ { - model = "Calxeda ECX-2000"; - compatible = "calxeda,ecx-2000"; - #address-cells = <2>; - #size-cells = <2>; - clock-ranges; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - }; - - memory@0 { - name = "memory"; - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0xff800000>; - }; - - memory@200000000 { - name = "memory"; - device_type = "memory"; - reg = <0x00000002 0x00000000 0x00000003 0x00000000>; - }; - - soc { - ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>; - - timer { - compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - memory-controller@fff00000 { - compatible = "calxeda,ecx-2000-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; - interrupt-controller; - interrupts = <1 9 0xf04>; - reg = <0xfff11000 0x1000>, - <0xfff12000 0x1000>, - <0xfff14000 0x2000>, - <0xfff16000 0x2000>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; - }; - }; -}; - -/include/ "ecx-common.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/ecx-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/ecx-common.dtsi deleted file mode 100644 index b90045a8f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ecx-common.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright 2011-2012 Calxeda, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -/ { - chosen { - bootargs = "console=ttyAMA0"; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000002>; - cpu_off = <0x84000004>; - cpu_on = <0x84000006>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - - sata@ffe08000 { - compatible = "calxeda,hb-ahci"; - reg = <0xffe08000 0x10000>; - interrupts = <0 83 4>; - dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 - &combophy0 1 &combophy0 2 - &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; - calxeda,led-order = <4 0 1 2 3>; - }; - - sdhci@ffe0e000 { - compatible = "calxeda,hb-sdhci"; - reg = <0xffe0e000 0x1000>; - interrupts = <0 90 4>; - clocks = <&eclk>; - status = "disabled"; - }; - - ipc@fff20000 { - compatible = "arm,pl320", "arm,primecell"; - reg = <0xfff20000 0x1000>; - interrupts = <0 7 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpioe: gpio@fff30000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff30000 0x1000>; - interrupts = <0 14 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpiof: gpio@fff31000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff31000 0x1000>; - interrupts = <0 15 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpiog: gpio@fff32000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff32000 0x1000>; - interrupts = <0 16 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpioh: gpio@fff33000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfff33000 0x1000>; - interrupts = <0 17 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer@fff34000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xfff34000 0x1000>; - interrupts = <0 18 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc@fff35000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0xfff35000 0x1000>; - interrupts = <0 19 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - serial@fff36000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xfff36000 0x1000>; - interrupts = <0 20 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - smic@fff3a000 { - compatible = "ipmi-smic"; - device_type = "ipmi"; - reg = <0xfff3a000 0x1000>; - interrupts = <0 24 4>; - reg-size = <4>; - reg-spacing = <4>; - }; - - sregs@fff3c000 { - compatible = "calxeda,hb-sregs"; - reg = <0xfff3c000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333000>; - }; - - ddrpll: ddrpll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x108>; - }; - - a9pll: a9pll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x100>; - }; - - a9periphclk: a9periphclk { - #clock-cells = <0>; - compatible = "calxeda,hb-a9periph-clock"; - clocks = <&a9pll>; - reg = <0x104>; - }; - - a9bclk: a9bclk { - #clock-cells = <0>; - compatible = "calxeda,hb-a9bus-clock"; - clocks = <&a9pll>; - reg = <0x104>; - }; - - emmcpll: emmcpll { - #clock-cells = <0>; - compatible = "calxeda,hb-pll-clock"; - clocks = <&osc>; - reg = <0x10C>; - }; - - eclk: eclk { - #clock-cells = <0>; - compatible = "calxeda,hb-emmc-clock"; - clocks = <&emmcpll>; - reg = <0x114>; - }; - - pclk: pclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <150000000>; - }; - }; - }; - - dma@fff3d000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xfff3d000 0x1000>; - interrupts = <0 92 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - ethernet@fff50000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff50000 0x1000>; - interrupts = <0 77 4 0 78 4 0 79 4>; - dma-coherent; - }; - - ethernet@fff51000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff51000 0x1000>; - interrupts = <0 80 4 0 81 4 0 82 4>; - dma-coherent; - }; - - combophy0: combo-phy@fff58000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff58000 0x1000>; - phydev = <5>; - }; - - combophy5: combo-phy@fff5d000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff5d000 0x1000>; - phydev = <31>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/efm32gg-dk3750.dts b/software/linux/kernel/arch/arm/boot/dts/efm32gg-dk3750.dts deleted file mode 100644 index 98fc667d2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/efm32gg-dk3750.dts +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Device tree for EFM32GG-DK3750 development board. - * - * Documentation available from - * http://www.silabs.com/Support%20Documents/TechnicalDocs/efm32gg-dk3750-ug.pdf - */ - -/dts-v1/; -#include "efm32gg.dtsi" - -/ { - model = "Energy Micro Giant Gecko Development Kit"; - compatible = "efm32,dk3750"; - - chosen { - bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0"; - }; - - memory@88000000 { - device_type = "memory"; - reg = <0x88000000 0x400000>; - }; - - soc { - adc@40002000 { - status = "ok"; - }; - - i2c@4000a000 { - energymicro,location = <3>; - status = "ok"; - - temp@48 { - compatible = "st,stds75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "microchip,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - spi0: spi@4000c000 { /* USART0 */ - cs-gpios = <&gpio 68 1>; // E4 - energymicro,location = <1>; - status = "ok"; - - microsd@0 { - compatible = "mmc-spi-slot"; - spi-max-frequency = <100000>; - voltage-ranges = <3200 3400>; - broken-cd; - reg = <0>; - }; - }; - - spi1: spi@4000c400 { /* USART1 */ - cs-gpios = <&gpio 51 1>; // D3 - energymicro,location = <1>; - status = "ok"; - - ks8851@0 { - compatible = "ks8851"; - spi-max-frequency = <6000000>; - reg = <0>; - interrupt-parent = <&boardfpga>; - interrupts = <4>; - }; - }; - - uart4: uart@4000e400 { /* UART1 */ - energymicro,location = <2>; - status = "ok"; - }; - - boardfpga: boardfpga@80000000 { - compatible = "efm32board"; - reg = <0x80000000 0x400>; - irq-gpios = <&gpio 64 1>; - interrupt-controller; - #interrupt-cells = <1>; - status = "ok"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/efm32gg.dtsi b/software/linux/kernel/arch/arm/boot/dts/efm32gg.dtsi deleted file mode 100644 index b78c57e51..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/efm32gg.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Device tree for Energy Micro EFM32 Giant Gecko SoC. - * - * Documentation available from - * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf - */ - -#include "armv7-m.dtsi" -#include "dt-bindings/clock/efm32-cmu.h" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - soc { - adc: adc@40002000 { - compatible = "energymicro,efm32-adc"; - reg = <0x40002000 0x400>; - interrupts = <7>; - clocks = <&cmu clk_HFPERCLKADC0>; - status = "disabled"; - }; - - gpio: gpio@40006000 { - compatible = "energymicro,efm32-gpio"; - reg = <0x40006000 0x1000>; - interrupts = <1 11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - clocks = <&cmu clk_HFPERCLKGPIO>; - status = "ok"; - }; - - i2c0: i2c@4000a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-i2c"; - reg = <0x4000a000 0x400>; - interrupts = <9>; - clocks = <&cmu clk_HFPERCLKI2C0>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c1: i2c@4000a400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-i2c"; - reg = <0x4000a400 0x400>; - interrupts = <10>; - clocks = <&cmu clk_HFPERCLKI2C1>; - clock-frequency = <100000>; - status = "disabled"; - }; - - spi0: spi@4000c000 { /* USART0 */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-spi"; - reg = <0x4000c000 0x400>; - interrupts = <3 4>; - clocks = <&cmu clk_HFPERCLKUSART0>; - status = "disabled"; - }; - - spi1: spi@4000c400 { /* USART1 */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-spi"; - reg = <0x4000c400 0x400>; - interrupts = <15 16>; - clocks = <&cmu clk_HFPERCLKUSART1>; - status = "disabled"; - }; - - spi2: spi@4000c800 { /* USART2 */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-spi"; - reg = <0x4000c800 0x400>; - interrupts = <18 19>; - clocks = <&cmu clk_HFPERCLKUSART2>; - status = "disabled"; - }; - - uart0: uart@4000c000 { /* USART0 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000c000 0x400>; - interrupts = <3 4>; - clocks = <&cmu clk_HFPERCLKUSART0>; - status = "disabled"; - }; - - uart1: uart@4000c400 { /* USART1 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000c400 0x400>; - interrupts = <15 16>; - clocks = <&cmu clk_HFPERCLKUSART1>; - status = "disabled"; - }; - - uart2: uart@4000c800 { /* USART2 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000c800 0x400>; - interrupts = <18 19>; - clocks = <&cmu clk_HFPERCLKUSART2>; - status = "disabled"; - }; - - uart3: uart@4000e000 { /* UART0 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000e000 0x400>; - interrupts = <20 21>; - clocks = <&cmu clk_HFPERCLKUART0>; - status = "disabled"; - }; - - uart4: uart@4000e400 { /* UART1 */ - compatible = "energymicro,efm32-uart"; - reg = <0x4000e400 0x400>; - interrupts = <22 23>; - clocks = <&cmu clk_HFPERCLKUART1>; - status = "disabled"; - }; - - timer0: timer@40010000 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010000 0x400>; - interrupts = <2>; - clocks = <&cmu clk_HFPERCLKTIMER0>; - }; - - timer1: timer@40010400 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010400 0x400>; - interrupts = <12>; - clocks = <&cmu clk_HFPERCLKTIMER1>; - }; - - timer2: timer@40010800 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010800 0x400>; - interrupts = <13>; - clocks = <&cmu clk_HFPERCLKTIMER2>; - }; - - timer3: timer@40010c00 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010c00 0x400>; - interrupts = <14>; - clocks = <&cmu clk_HFPERCLKTIMER3>; - }; - - cmu: cmu@400c8000 { - compatible = "efm32gg,cmu"; - reg = <0x400c8000 0x400>; - interrupts = <32>; - #clock-cells = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/software/linux/kernel/arch/arm/boot/dts/elpida_ecb240abacn.dtsi deleted file mode 100644 index f97f70f83..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/elpida_ecb240abacn.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Common devices used in different OMAP boards - */ - -/ { - elpida_ECB240ABACN: lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; - density = <2048>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - - timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <200000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <10000>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/emev2-kzm9d.dts b/software/linux/kernel/arch/arm/boot/dts/emev2-kzm9d.dts deleted file mode 100644 index 60d0a7328..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/emev2-kzm9d.dts +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Device Tree Source for the KZM9D board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ -/dts-v1/; - -#include "emev2.dtsi" -#include -#include -#include - -/ { - model = "EMEV2 KZM9D Board"; - compatible = "renesas,kzm9d", "renesas,emev2"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x8000000>; - }; - - aliases { - serial1 = &uart1; - }; - - chosen { - bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp"; - stdout-path = "serial1:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - one { - debounce_interval = <50>; - wakeup-source; - label = "DSW2-1"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - two { - debounce_interval = <50>; - wakeup-source; - label = "DSW2-2"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - three { - debounce_interval = <50>; - wakeup-source; - label = "DSW2-3"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - four { - debounce_interval = <50>; - wakeup-source; - label = "DSW2-4"; - linux,code = ; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ethernet@20000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x20000000 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpio0>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; -}; - -&iic0 { - status = "okay"; -}; - -&iic1 { - status = "okay"; -}; - -&pfc { - uart1_pins: uart1 { - groups = "uart1_ctrl", "uart1_data"; - function = "uart1"; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/emev2.dtsi b/software/linux/kernel/arch/arm/boot/dts/emev2.dtsi deleted file mode 100644 index cd119400f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/emev2.dtsi +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Device Tree Source for the EMEV2 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "skeleton.dtsi" -#include -#include - -/ { - compatible = "renesas,emev2"; - interrupt-parent = <&gic>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &iic0; - i2c1 = &iic1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <533000000>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <533000000>; - }; - }; - - gic: interrupt-controller@e0020000 { - compatible = "arm,pl390"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xe0028000 0x1000>, - <0xe0020000 0x0100>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - }; - - clocks@e0110000 { - compatible = "renesas,emev2-smu"; - reg = <0xe0110000 0x10000>; - #address-cells = <2>; - #size-cells = <0>; - - c32ki: c32ki { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - iic0_sclkdiv: iic0_sclkdiv@624,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x624 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - iic0_sclk: iic0_sclk@48c,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x48c 1>; - clocks = <&iic0_sclkdiv>; - #clock-cells = <0>; - }; - iic1_sclkdiv: iic1_sclkdiv@624,16 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x624 16>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - iic1_sclk: iic1_sclk@490,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x490 1>; - clocks = <&iic1_sclkdiv>; - #clock-cells = <0>; - }; - pll3_fo: pll3_fo { - compatible = "fixed-factor-clock"; - clocks = <&c32ki>; - clock-div = <1>; - clock-mult = <7000>; - #clock-cells = <0>; - }; - usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x65c 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x65c 16>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x660 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usia_u0_sclk: usia_u0_sclk@4a0,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; - }; - usib_u1_sclk: usib_u1_sclk@4b8,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4b8 1>; - clocks = <&usib_u1_sclkdiv>; - #clock-cells = <0>; - }; - usib_u2_sclk: usib_u2_sclk@4bc,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4bc 1>; - clocks = <&usib_u2_sclkdiv>; - #clock-cells = <0>; - }; - usib_u3_sclk: usib_u3_sclk@4c0,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4c0 1>; - clocks = <&usib_u3_sclkdiv>; - #clock-cells = <0>; - }; - sti_sclk: sti_sclk@528,1 { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x528 1>; - clocks = <&c32ki>; - #clock-cells = <0>; - }; - }; - - timer@e0180000 { - compatible = "renesas,em-sti"; - reg = <0xe0180000 0x54>; - interrupts = ; - clocks = <&sti_sclk>; - clock-names = "sclk"; - }; - - uart0: serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = ; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; - }; - - uart1: serial@e1030000 { - compatible = "renesas,em-uart"; - reg = <0xe1030000 0x38>; - interrupts = ; - clocks = <&usib_u1_sclk>; - clock-names = "sclk"; - }; - - uart2: serial@e1040000 { - compatible = "renesas,em-uart"; - reg = <0xe1040000 0x38>; - interrupts = ; - clocks = <&usib_u2_sclk>; - clock-names = "sclk"; - }; - - uart3: serial@e1050000 { - compatible = "renesas,em-uart"; - reg = <0xe1050000 0x38>; - interrupts = ; - clocks = <&usib_u3_sclk>; - clock-names = "sclk"; - }; - - pfc: pfc@e0140200 { - compatible = "renesas,pfc-emev2"; - reg = <0xe0140200 0x100>; - }; - - gpio0: gpio@e0050000 { - compatible = "renesas,em-gio"; - reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - gpio1: gpio@e0050080 { - compatible = "renesas,em-gio"; - reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - gpio2: gpio@e0050100 { - compatible = "renesas,em-gio"; - reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - gpio3: gpio@e0050180 { - compatible = "renesas,em-gio"; - reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #gpio-cells = <2>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - gpio4: gpio@e0050200 { - compatible = "renesas,em-gio"; - reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; - interrupts = , - ; - gpio-controller; - gpio-ranges = <&pfc 0 128 31>; - #gpio-cells = <2>; - ngpios = <31>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - iic0: i2c@e0070000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-emev2"; - reg = <0xe0070000 0x28>; - interrupts = ; - clocks = <&iic0_sclk>; - clock-names = "sclk"; - status = "disabled"; - }; - - iic1: i2c@e10a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-emev2"; - reg = <0xe10a0000 0x28>; - interrupts = ; - clocks = <&iic1_sclk>; - clock-names = "sclk"; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ep7209.dtsi b/software/linux/kernel/arch/arm/boot/dts/ep7209.dtsi deleted file mode 100644 index aaf1261d2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ep7209.dtsi +++ /dev/null @@ -1,191 +0,0 @@ -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - */ - -/dts-v1/; - -#include "skeleton.dtsi" - -#include - -/ { - model = "Cirrus Logic EP7209"; - compatible = "cirrus,ep7209"; - - aliases { - gpio0 = &porta; - gpio1 = &portb; - gpio3 = &portd; - gpio4 = &porte; - serial0 = &uart1; - serial1 = &uart2; - spi0 = &spi; - timer0 = &timer1; - timer1 = &timer2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm720t"; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - clks: clks@80000000 { - #clock-cells = <1>; - compatible = "cirrus,ep7209-clk"; - reg = <0x80000000 0xc000>; - startup-frequency = <73728000>; - }; - - intc: intc@80000000 { - compatible = "cirrus,ep7209-intc"; - reg = <0x80000000 0x4000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - porta: gpio@80000000 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000000 0x1 0x80000040 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - portb: gpio@80000001 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000001 0x1 0x80000041 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - portd: gpio@80000003 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000003 0x1 0x80000043 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - porte: gpio@80000083 { - compatible = "cirrus,ep7209-gpio"; - reg = <0x80000083 0x1 0x800000c3 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; - - syscon1: syscon@80000100 { - compatible = "cirrus,ep7209-syscon1", "syscon"; - reg = <0x80000100 0x80>; - }; - - bus: bus@80000180 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "cirrus,ep7209-bus", "simple-bus"; - clocks = <&clks CLPS711X_CLK_BUS>; - reg = <0x80000180 0x80>; - ranges = < - 0 0 0x00000000 0x10000000 - 1 0 0x10000000 0x10000000 - 2 0 0x20000000 0x10000000 - 3 0 0x30000000 0x10000000 - 4 0 0x40000000 0x10000000 - 5 0 0x50000000 0x10000000 - 6 0 0x60000000 0x0000c000 - 7 0 0x70000000 0x00000080 - >; - }; - - fb: fb@800002c0 { - compatible = "cirrus,ep7209-fb"; - reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; - clocks = <&clks CLPS711X_CLK_BUS>; - status = "disabled"; - }; - - timer1: timer@80000300 { - compatible = "cirrus,ep7209-timer"; - reg = <0x80000300 0x4>; - clocks = <&clks CLPS711X_CLK_TIMER1>; - interrupts = <8>; - }; - - timer2: timer@80000340 { - compatible = "cirrus,ep7209-timer"; - reg = <0x80000340 0x4>; - clocks = <&clks CLPS711X_CLK_TIMER2>; - interrupts = <9>; - }; - - pwm: pwm@80000400 { - compatible = "cirrus,ep7209-pwm"; - reg = <0x80000400 0x4>; - clocks = <&clks CLPS711X_CLK_PWM>; - #pwm-cells = <1>; - }; - - uart1: uart@80000480 { - compatible = "cirrus,ep7209-uart"; - reg = <0x80000480 0x80>; - interrupts = <12 13>; - clocks = <&clks CLPS711X_CLK_UART>; - syscon = <&syscon1>; - }; - - spi: spi@80000500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cirrus,ep7209-spi"; - reg = <0x80000500 0x4>; - interrupts = <15>; - clocks = <&clks CLPS711X_CLK_SPI>; - status = "disabled"; - }; - - syscon2: syscon@80001100 { - compatible = "cirrus,ep7209-syscon2", "syscon"; - reg = <0x80001100 0x80>; - }; - - uart2: uart@80001480 { - compatible = "cirrus,ep7209-uart"; - reg = <0x80001480 0x80>; - interrupts = <28 29>; - clocks = <&clks CLPS711X_CLK_UART>; - syscon = <&syscon2>; - }; - - dai: dai@80002000 { - #sound-dai-cells = <0>; - compatible = "cirrus,ep7209-dai"; - reg = <0x80002000 0x604>; - clocks = <&clks CLPS711X_CLK_PLL>; - clock-names = "pll"; - interrupts = <32>; - status = "disabled"; - }; - - syscon3: syscon@80002200 { - compatible = "cirrus,ep7209-syscon3", "syscon"; - reg = <0x80002200 0x40>; - }; - }; - - mctrl: mctrl { - compatible = "cirrus,ep7209-mctrl-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ep7211-edb7211.dts b/software/linux/kernel/arch/arm/boot/dts/ep7211-edb7211.dts deleted file mode 100644 index 9a134ed27..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ep7211-edb7211.dts +++ /dev/null @@ -1,100 +0,0 @@ -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - */ - -#include "ep7211.dtsi" -#include - -/ { - model = "Cirrus Logic EP7211 Development Board"; - compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209"; - - memory { - reg = <0xc0000000 0x02000000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0>; - brightness-levels = < - 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 - 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf - >; - default-brightness-level = <0x0>; - power-supply = <&blen>; - }; - - display: display { - model = "320x240x4"; - native-mode = <&timing0>; - bits-per-pixel = <4>; - ac-prescale = <17>; - - display-timings { - timing0: 320x240 { - hactive = <320>; - hback-porch = <0>; - hfront-porch = <0>; - hsync-len = <0>; - vactive = <240>; - vback-porch = <0>; - vfront-porch = <0>; - vsync-len = <0>; - clock-frequency = <6500000>; - }; - }; - }; - - i2c: i2c { - compatible = "i2c-gpio"; - gpios = <&portd 4 GPIO_ACTIVE_HIGH>, - <&portd 5 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - i2c-gpio,scl-output-only; - #address-cells = <1>; - #size-cells = <0>; - }; - - lcddc: lcddc { - compatible = "regulator-fixed"; - regulator-name = "BACKLIGHT ENABLE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&portd 1 GPIO_ACTIVE_HIGH>; - }; - - blen: blen { - compatible = "regulator-fixed"; - regulator-name = "BACKLIGHT ENABLE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&portd 3 GPIO_ACTIVE_HIGH>; - }; -}; - -&bus { - flash: nor@00000000 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&fb { - display = <&display>; - lcd-supply = <&lcddc>; - status = "okay"; -}; - -&portd { - lcden { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LCD ENABLE"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ep7211.dtsi b/software/linux/kernel/arch/arm/boot/dts/ep7211.dtsi deleted file mode 100644 index e438f6db0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ep7211.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - */ - -#include "ep7209.dtsi" - -/ { - model = "Cirrus Logic EP7211"; - compatible = "cirrus,ep7211", "cirrus,ep7209"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ethernut5.dts b/software/linux/kernel/arch/arm/boot/dts/ethernut5.dts deleted file mode 100644 index 4687229a3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ethernut5.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * ethernut5.dts - Device Tree file for Ethernut 5 board - * - * Copyright (C) 2012 egnite GmbH - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9xe.dtsi" - -/ { - model = "Ethernut 5"; - compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; - }; - - memory { - reg = <0x20000000 0x08000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - gpios = <0 - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - - root@0 { - label = "root"; - reg = <0x0 0x08000000>; - }; - - data@20000 { - label = "data"; - reg = <0x08000000 0x38000000>; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - - pcf8563@50 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/evk-pro3.dts b/software/linux/kernel/arch/arm/boot/dts/evk-pro3.dts deleted file mode 100644 index 20a4481b6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/evk-pro3.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3 - * - * Copyright (C) 2012 Telit, - * 2012 Fabio Porcedda - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; - -#include "ge863-pro3.dtsi" - -/ { - model = "Telit EVK-PRO3 for Telit GE863-PRO3"; - compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - }; - - ahb { - apb { - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart2: serial@fffb8000 { - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - watchdog@fffffd40 { - status = "okay"; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi deleted file mode 100644 index f78c14c82..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition. - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region_mfc_left { - compatible = "shared-dma-pool"; - no-map; - size = <0x1000000>; - alignment = <0x100000>; - }; - - mfc_right: region_mfc_right { - compatible = "shared-dma-pool"; - no-map; - size = <0x800000>; - alignment = <0x100000>; - }; - }; -}; - -&mfc { - memory-region = <&mfc_left>, <&mfc_right>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos-syscon-restart.dtsi deleted file mode 100644 index 09a204005..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos-syscon-restart.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - soc { - compatible = "simple-bus"; - - poweroff: syscon-poweroff { - compatible = "syscon-poweroff"; - regmap = <&pmu_system_controller>; - offset = <0x330C>; /* PS_HOLD_CONTROL */ - mask = <0x5200>; /* reset value */ - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x0400>; /* SWRESET */ - mask = <0x1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/software/linux/kernel/arch/arm/boot/dts/exynos3250-artik5-eval.dts deleted file mode 100644 index be4d6aa37..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's ARTIK5 evaluation board - * which is based on Samsung Exynos3250 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "exynos3250-artik5.dtsi" - -/ { - model = "Samsung ARTIK5 evaluation board"; - compatible = "samsung,artik5-eval", "samsung,artik5", - "samsung,exynos3250", "samsung,exynos3"; -}; - -&mshc_2 { - num-slots = <1>; - cap-sd-highspeed; - disable-wp; - vqmmc-supply = <&ldo3_reg>; - card-detect-delay = <200>; - clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos3250-artik5.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos3250-artik5.dtsi deleted file mode 100644 index a70819b1b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Samsung's Exynos3250 based ARTIK5 module device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's ARTIK5 module which is based on - * Samsung Exynos3250 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "exynos3250.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3"; - - chosen { - stdout-path = &serial_2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1ff00000>; - }; - - firmware@0205f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205f000 0x1000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 500MHz */ - cooling-device = <&cpu0 5 5>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo7_reg>; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - s2mps14_pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx3>; - interrupts = <5 IRQ_TYPE_NONE>; - reg = <0x66>; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - /* VDD_ALIVE15x */ - regulator-name = "VLDO1_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - /* VDDQM176 ~ VDDQM185 */ - regulator-name = "VLDO2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - /* - * VDD1_E106 ~ VDD1_E111 - * DVDD_RTC_AP, DVDD_MMC2_AP - */ - regulator-name = "VLDO3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - /* AVDD_PLL1120 ~ AVDD_PLL11201 */ - regulator-name = "VLDO4_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - /* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */ - regulator-name = "VLDO5_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - /* VDD_USB, VDD10_HSIC */ - regulator-name = "VLDO6_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - /* - * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2, - * AVDD_ADC, AVDD_ABB_0, M4S_VDD18 - */ - regulator-name = "VLDO7_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - /* AVDD33_UOTG */ - regulator-name = "VLDO8_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - /* VDDQ_E86 ~ VDDQ_E105*/ - regulator-name = "VLDO9_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VLDO10_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo11_reg: LDO11 { - /* VDD74 ~ VDD75 */ - regulator-name = "VLDO11_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - /* VDD72 ~ VDD73 */ - regulator-name = "VLDO12_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VLDO13_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VLDO14_2.7V"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VLDO_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VLDO16_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VLDO17_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo18_reg: LDO18 { - /* DVDD_MMC2_AP */ - regulator-name = "VLDO18_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VLDO19_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "VLDO20_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "VLDO21_1.25V"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "VLDO22_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo23_reg: LDO23 { - /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */ - regulator-name = "VLDO23_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "VLDO24_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "VLDO25_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - /* VDD_MIF */ - regulator-name = "VBUCK1_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - /* VDD_CPU */ - regulator-name = "VBUCK2_1.2V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - /* VDD_G3D */ - regulator-name = "VBUCK3_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VBUCK4_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "VBUCK5_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&mshc_0 { - num-slots = <1>; - non-removable; - cap-mmc-highspeed; - card-detect-delay = <200>; - vmmc-supply = <&ldo12_reg>; - clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&tmu { - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos3250-monk.dts b/software/linux/kernel/arch/arm/boot/dts/exynos3250-monk.dts deleted file mode 100644 index 66f04f6ba..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos3250-monk.dts +++ /dev/null @@ -1,635 +0,0 @@ -/* - * Samsung's Exynos3250 based Monk board device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Monk board which is based on - * Samsung Exynos3250 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "exynos3250.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include - -/ { - model = "Samsung Monk board"; - compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3"; - - aliases { - i2c7 = &i2c_max77836; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1ff00000>; - }; - - firmware@0205F000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205F000 0x1000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - power_key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - vemmc_reg: voltage-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "V_EMMC_2.8V-fixed"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - i2c_max77836: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - max77836: subpmic@25 { - compatible = "maxim,max77836"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - reg = <0x25>; - wakeup-source; - - muic: max77836-muic { - compatible = "maxim,max77836-muic"; - }; - - regulators { - compatible = "maxim,max77836-regulator"; - safeout_reg: SAFEOUT { - regulator-name = "SAFEOUT"; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <45000>; - regulator-max-microamp = <475000>; - regulator-boot-on; - }; - - motor_reg: LDO1 { - regulator-name = "MOT_2.7V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <2700000>; - }; - - LDO2 { - regulator-name = "UNUSED_LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - }; - - charger { - compatible = "maxim,max77836-charger"; - - maxim,constant-uvolt = <4350000>; - maxim,fast-charge-uamp = <225000>; - maxim,eoc-uamp = <7500>; - maxim,ovp-uvolt = <6500000>; - }; - }; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <&motor_reg>; - min-microvolt = <1100000>; - max-microvolt = <2700000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Correspond to 500MHz at freq_table */ - cooling-device = <&cpu0 5 5>; - }; - map1 { - /* Correspond to 200MHz at freq_table */ - cooling-device = <&cpu0 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; - - thermistor-ap { - compatible = "ntc,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 0>; - }; - - thermistor-battery { - compatible = "ntc,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 1>; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&exynos_usbphy { - vbus-supply = <&safeout_reg>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - s2mps14_pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx0>; - interrupts = <7 0>; - reg = <0x66>; - wakeup-source; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VAP_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VAP_M1_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_AP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VAP_AVDD_PLL1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VAP_PLL_ISO_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VAP_MIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VAP_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VAP_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "V_LPDDR_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "UNUSED_LDO10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo11_reg: LDO11 { - regulator-name = "V_EMMC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - regulator-name = "V_EMMC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VSENSOR_2.85V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "UNUSED_LDO14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "LCD_VDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "UNUSED_LDO17"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "UNUSED_LDO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "LCD_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "UNUSED_LDO21"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "UNUSED_LDO22"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "UNUSED_LDO23"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "UNUSED_LDO24"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "UNUSED_LDO25"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VAP_MIF_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VAP_ARM_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VAP_INT3D_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VCC_SUB_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c_1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - fuelgauge@36 { - compatible = "maxim,max77836-battery"; - interrupt-parent = <&gpx1>; - interrupts = <2 8>; - reg = <0x36>; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&mshc_0 { - #address-cells = <1>; - #size-cells = <0>; - num-slots = <1>; - broken-cd; - non-removable; - cap-mmc-highspeed; - desc-num = <4>; - mmc-hs200-1_8v; - card-detect-delay = <200>; - vmmc-supply = <&vemmc_reg>; - clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&serial_0 { - assigned-clocks = <&cmu CLK_SCLK_UART0>; - assigned-clock-rates = <100000000>; - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo7_reg>; - status = "okay"; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - sleep0: sleep-state { - PIN_SLP(gpa0-0, INPUT, DOWN); - PIN_SLP(gpa0-1, INPUT, DOWN); - PIN_SLP(gpa0-2, INPUT, DOWN); - PIN_SLP(gpa0-3, INPUT, DOWN); - PIN_SLP(gpa0-4, INPUT, DOWN); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, DOWN); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, PREV, NONE); - PIN_SLP(gpb-1, PREV, NONE); - PIN_SLP(gpb-2, PREV, NONE); - PIN_SLP(gpb-3, PREV, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, DOWN); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, DOWN); - PIN_SLP(gpc1-1, INPUT, DOWN); - PIN_SLP(gpc1-2, INPUT, DOWN); - PIN_SLP(gpc1-3, INPUT, DOWN); - PIN_SLP(gpc1-4, INPUT, DOWN); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, NONE); - PIN_SLP(gpd1-1, INPUT, NONE); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&initial1 &sleep1>; - - initial1: initial-state { - PIN_IN(gpk2-0, DOWN, LV1); - PIN_IN(gpk2-1, DOWN, LV1); - PIN_IN(gpk2-2, DOWN, LV1); - PIN_IN(gpk2-3, DOWN, LV1); - PIN_IN(gpk2-4, DOWN, LV1); - PIN_IN(gpk2-5, DOWN, LV1); - PIN_IN(gpk2-6, DOWN, LV1); - }; - - sleep1: sleep-state { - PIN_SLP(gpe0-0, PREV, NONE); - PIN_SLP(gpe0-1, PREV, NONE); - PIN_SLP(gpe0-2, INPUT, DOWN); - PIN_SLP(gpe0-3, INPUT, DOWN); - PIN_SLP(gpe0-4, PREV, NONE); - PIN_SLP(gpe0-5, INPUT, DOWN); - PIN_SLP(gpe0-6, INPUT, DOWN); - PIN_SLP(gpe0-7, INPUT, DOWN); - - PIN_SLP(gpe1-0, INPUT, DOWN); - PIN_SLP(gpe1-1, PREV, NONE); - PIN_SLP(gpe1-2, INPUT, DOWN); - PIN_SLP(gpe1-3, INPUT, DOWN); - PIN_SLP(gpe1-4, INPUT, DOWN); - PIN_SLP(gpe1-5, INPUT, DOWN); - PIN_SLP(gpe1-6, INPUT, DOWN); - PIN_SLP(gpe1-7, INPUT, NONE); - - PIN_SLP(gpe2-0, INPUT, NONE); - PIN_SLP(gpe2-1, INPUT, NONE); - PIN_SLP(gpe2-2, INPUT, NONE); - - PIN_SLP(gpk0-0, INPUT, DOWN); - PIN_SLP(gpk0-1, INPUT, DOWN); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, INPUT, DOWN); - PIN_SLP(gpk0-4, INPUT, DOWN); - PIN_SLP(gpk0-5, INPUT, DOWN); - PIN_SLP(gpk0-6, INPUT, DOWN); - PIN_SLP(gpk0-7, INPUT, DOWN); - - PIN_SLP(gpk1-0, PREV, NONE); - PIN_SLP(gpk1-1, PREV, NONE); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, PREV, NONE); - PIN_SLP(gpk1-4, PREV, NONE); - PIN_SLP(gpk1-5, PREV, NONE); - PIN_SLP(gpk1-6, PREV, NONE); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, DOWN); - PIN_SLP(gpm1-3, INPUT, DOWN); - PIN_SLP(gpm1-4, INPUT, DOWN); - PIN_SLP(gpm1-5, INPUT, DOWN); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, DOWN); - PIN_SLP(gpm2-1, INPUT, DOWN); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, INPUT, DOWN); - PIN_SLP(gpm3-1, INPUT, DOWN); - PIN_SLP(gpm3-2, INPUT, DOWN); - PIN_SLP(gpm3-3, INPUT, DOWN); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos3250-pinctrl.dtsi deleted file mode 100644 index ec331169c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ /dev/null @@ -1,559 +0,0 @@ -/* - * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -#define PIN_IN(_pin, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -#define PIN_OUT(_pin, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -#define PIN_OUT_SET(_pin, _val, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - samsung,pin-val = <_val>; \ - } - -#define PIN_CFG(_pin, _sel, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <_sel>; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ - } - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi0_clk: mipi0-clk { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe2: gpe2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, - <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, - <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpk0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos3250-rinato.dts b/software/linux/kernel/arch/arm/boot/dts/exynos3250-rinato.dts deleted file mode 100644 index 3967ee5f7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos3250-rinato.dts +++ /dev/null @@ -1,906 +0,0 @@ -/* - * Samsung's Exynos3250 based Rinato board device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Rinato board which is based on - * Samsung Exynos3250 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "exynos3250.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include - -/ { - model = "Samsung Rinato board"; - compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3"; - - aliases { - i2c7 = &i2c_max77836; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x1ff00000>; - }; - - firmware@0205F000 { - compatible = "samsung,secure-firmware"; - reg = <0x0205F000 0x1000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - power_key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - i2c_max77836: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - max77836: subpmic@25 { - compatible = "maxim,max77836"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - reg = <0x25>; - wakeup-source; - - muic: max77836-muic { - compatible = "maxim,max77836-muic"; - }; - - regulators { - compatible = "maxim,max77836-regulator"; - safeout_reg: SAFEOUT { - regulator-name = "SAFEOUT"; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <45000>; - regulator-max-microamp = <475000>; - regulator-boot-on; - }; - - motor_reg: LDO1 { - regulator-name = "MOT_2.7V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <2700000>; - }; - - LDO2 { - regulator-name = "UNUSED_LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - }; - - charger { - compatible = "maxim,max77836-charger"; - - maxim,constant-uvolt = <4350000>; - maxim,fast-charge-uamp = <225000>; - maxim,eoc-uamp = <7500>; - maxim,ovp-uvolt = <6500000>; - }; - }; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <&motor_reg>; - min-microvolt = <1100000>; - max-microvolt = <2700000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 500MHz */ - cooling-device = <&cpu0 5 5>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 8 8>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; - assigned-clocks = <&cmu CLK_SCLK_TSADC>; - assigned-clock-rates = <6000000>; - - thermistor-ap { - compatible = "ntc,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 0>; - }; - - thermistor-battery { - compatible = "ntc,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <100000>; - io-channels = <&adc 1>; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_lcd0 { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mcuisp { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_isp { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peril { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safeout_reg>; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&dsi_0 { - vddcore-supply = <&ldo6_reg>; - vddio-supply = <&ldo6_reg>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi_out: endpoint { - remote-endpoint = <&dsi_in>; - samsung,burst-clock-frequency = <250000000>; - samsung,esc-clock-frequency = <20000000>; - }; - }; - }; - - panel@0 { - compatible = "samsung,s6e63j0x03"; - reg = <0>; - vdd3-supply = <&ldo16_reg>; - vci-supply = <&ldo20_reg>; - reset-gpios = <&gpe0 1 GPIO_ACTIVE_HIGH>; - te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - power-on-delay= <30>; - power-off-delay= <120>; - reset-delay = <5>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <29>; - panel-height-mm = <29>; - - display-timings { - timing-0 { - clock-frequency = <4600000>; - hactive = <320>; - vactive = <320>; - hfront-porch = <1>; - hback-porch = <1>; - hsync-len = <1>; - vfront-porch = <150>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - - port { - dsi_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&fimd { - status = "okay"; - - i80-if-timings { - cs-setup = <0>; - wr-setup = <0>; - wr-act = <1>; - wr-hold = <0>; - }; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - s2mps14_pmic@66 { - compatible = "samsung,s2mps14-pmic"; - interrupt-parent = <&gpx0>; - interrupts = <7 0>; - reg = <0x66>; - wakeup-source; - - s2mps14_osc: clocks { - compatible = "samsung,s2mps14-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps14_ap", "unused", - "s2mps14_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VAP_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "VAP_M1_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_AP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo4_reg: LDO4 { - regulator-name = "VAP_AVDD_PLL1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "VAP_PLL_ISO_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "VAP_VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VAP_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VAP_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "V_LPDDR_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "UNUSED_LDO10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "V_EMMC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo12_reg: LDO12 { - regulator-name = "V_EMMC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_AVDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "UNUSED_LDO14"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "LCD_VDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "V_IRLED_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "CAM_AF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo19_reg: LDO19 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo20_reg: LDO20 { - regulator-name = "LCD_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo21_reg: LDO21 { - regulator-name = "CAM_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo22_reg: LDO22 { - regulator-name = "CAM_DVDD_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo23_reg: LDO23 { - regulator-name = "HRM_VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "HRM_VCC_3.3V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo25_reg: LDO25 { - regulator-name = "UNUSED_LDO25"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck1_reg: BUCK1 { - regulator-name = "VAP_MIF_1.0V"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "VAP_ARM_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VAP_INT3D_1.0V"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "VCC_SUB_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c_1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - fuelgauge@36 { - compatible = "maxim,max77836-battery"; - interrupt-parent = <&gpx1>; - interrupts = <2 8>; - reg = <0x36>; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&jpeg { - status = "okay"; -}; - -&mshc_0 { - #address-cells = <1>; - #size-cells = <0>; - num-slots = <1>; - broken-cd; - non-removable; - cap-mmc-highspeed; - desc-num = <4>; - mmc-hs200-1_8v; - card-detect-delay = <200>; - vmmc-supply = <&ldo12_reg>; - clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - status = "okay"; -}; - -&serial_0 { - assigned-clocks = <&cmu CLK_SCLK_UART0>; - assigned-clock-rates = <100000000>; - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo7_reg>; - status = "okay"; -}; - -&rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - status = "okay"; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&initial0 &sleep0>; - - initial0: initial-state { - PIN_IN(gpa1-4, DOWN, LV1); - PIN_IN(gpa1-5, DOWN, LV1); - - PIN_IN(gpc0-0, DOWN, LV1); - PIN_IN(gpc0-1, DOWN, LV1); - PIN_IN(gpc0-2, DOWN, LV1); - PIN_IN(gpc0-3, DOWN, LV1); - PIN_IN(gpc0-4, DOWN, LV1); - - PIN_IN(gpd0-0, DOWN, LV1); - PIN_IN(gpd0-1, DOWN, LV1); - }; - - sleep0: sleep-state { - PIN_SLP(gpa0-0, INPUT, DOWN); - PIN_SLP(gpa0-1, INPUT, DOWN); - PIN_SLP(gpa0-2, INPUT, DOWN); - PIN_SLP(gpa0-3, INPUT, DOWN); - PIN_SLP(gpa0-4, INPUT, DOWN); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, DOWN); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, PREV, NONE); - PIN_SLP(gpb-1, PREV, NONE); - PIN_SLP(gpb-2, PREV, NONE); - PIN_SLP(gpb-3, PREV, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, DOWN); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, DOWN); - PIN_SLP(gpc1-1, INPUT, DOWN); - PIN_SLP(gpc1-2, INPUT, DOWN); - PIN_SLP(gpc1-3, INPUT, DOWN); - PIN_SLP(gpc1-4, INPUT, DOWN); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, NONE); - PIN_SLP(gpd1-1, INPUT, NONE); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&initial1 &sleep1>; - - initial1: initial-state { - PIN_IN(gpe0-6, DOWN, LV1); - PIN_IN(gpe0-7, DOWN, LV1); - - PIN_IN(gpe1-0, DOWN, LV1); - PIN_IN(gpe1-3, DOWN, LV1); - PIN_IN(gpe1-4, DOWN, LV1); - PIN_IN(gpe1-5, DOWN, LV1); - PIN_IN(gpe1-6, DOWN, LV1); - - PIN_IN(gpk2-0, DOWN, LV1); - PIN_IN(gpk2-1, DOWN, LV1); - PIN_IN(gpk2-2, DOWN, LV1); - PIN_IN(gpk2-3, DOWN, LV1); - PIN_IN(gpk2-4, DOWN, LV1); - PIN_IN(gpk2-5, DOWN, LV1); - PIN_IN(gpk2-6, DOWN, LV1); - - PIN_IN(gpm0-0, DOWN, LV1); - PIN_IN(gpm0-1, DOWN, LV1); - PIN_IN(gpm0-2, DOWN, LV1); - PIN_IN(gpm0-3, DOWN, LV1); - PIN_IN(gpm0-4, DOWN, LV1); - PIN_IN(gpm0-5, DOWN, LV1); - PIN_IN(gpm0-6, DOWN, LV1); - PIN_IN(gpm0-7, DOWN, LV1); - - PIN_IN(gpm1-0, DOWN, LV1); - PIN_IN(gpm1-1, DOWN, LV1); - PIN_IN(gpm1-2, DOWN, LV1); - PIN_IN(gpm1-3, DOWN, LV1); - PIN_IN(gpm1-4, DOWN, LV1); - PIN_IN(gpm1-5, DOWN, LV1); - PIN_IN(gpm1-6, DOWN, LV1); - - PIN_IN(gpm2-0, DOWN, LV1); - PIN_IN(gpm2-1, DOWN, LV1); - - PIN_IN(gpm3-0, DOWN, LV1); - PIN_IN(gpm3-1, DOWN, LV1); - PIN_IN(gpm3-2, DOWN, LV1); - PIN_IN(gpm3-3, DOWN, LV1); - PIN_IN(gpm3-4, DOWN, LV1); - - PIN_IN(gpm4-1, DOWN, LV1); - PIN_IN(gpm4-2, DOWN, LV1); - PIN_IN(gpm4-3, DOWN, LV1); - PIN_IN(gpm4-4, DOWN, LV1); - PIN_IN(gpm4-5, DOWN, LV1); - PIN_IN(gpm4-6, DOWN, LV1); - PIN_IN(gpm4-7, DOWN, LV1); - }; - - sleep1: sleep-state { - PIN_SLP(gpe0-0, PREV, NONE); - PIN_SLP(gpe0-1, PREV, NONE); - PIN_SLP(gpe0-2, INPUT, DOWN); - PIN_SLP(gpe0-3, INPUT, UP); - PIN_SLP(gpe0-4, INPUT, DOWN); - PIN_SLP(gpe0-5, INPUT, DOWN); - PIN_SLP(gpe0-6, INPUT, DOWN); - PIN_SLP(gpe0-7, INPUT, DOWN); - - PIN_SLP(gpe1-0, INPUT, DOWN); - PIN_SLP(gpe1-1, PREV, NONE); - PIN_SLP(gpe1-2, INPUT, DOWN); - PIN_SLP(gpe1-3, INPUT, DOWN); - PIN_SLP(gpe1-4, INPUT, DOWN); - PIN_SLP(gpe1-5, INPUT, DOWN); - PIN_SLP(gpe1-6, INPUT, DOWN); - PIN_SLP(gpe1-7, INPUT, NONE); - - PIN_SLP(gpe2-0, INPUT, NONE); - PIN_SLP(gpe2-1, INPUT, NONE); - PIN_SLP(gpe2-2, INPUT, NONE); - - PIN_SLP(gpk0-0, INPUT, DOWN); - PIN_SLP(gpk0-1, INPUT, DOWN); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, INPUT, DOWN); - PIN_SLP(gpk0-4, INPUT, DOWN); - PIN_SLP(gpk0-5, INPUT, DOWN); - PIN_SLP(gpk0-6, INPUT, DOWN); - PIN_SLP(gpk0-7, INPUT, DOWN); - - PIN_SLP(gpk1-0, INPUT, DOWN); - PIN_SLP(gpk1-1, INPUT, DOWN); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, INPUT, DOWN); - PIN_SLP(gpk1-4, INPUT, DOWN); - PIN_SLP(gpk1-5, INPUT, DOWN); - PIN_SLP(gpk1-6, INPUT, DOWN); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, DOWN); - PIN_SLP(gpm1-3, INPUT, DOWN); - PIN_SLP(gpm1-4, INPUT, DOWN); - PIN_SLP(gpm1-5, INPUT, DOWN); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, DOWN); - PIN_SLP(gpm2-1, INPUT, DOWN); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, INPUT, DOWN); - PIN_SLP(gpm3-1, INPUT, DOWN); - PIN_SLP(gpm3-2, INPUT, DOWN); - PIN_SLP(gpm3-3, INPUT, DOWN); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos3250.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos3250.dtsi deleted file mode 100644 index e9d2556c0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos3250.dtsi +++ /dev/null @@ -1,900 +0,0 @@ -/* - * Samsung's Exynos3250 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "exynos4-cpu-thermal.dtsi" -#include "exynos-syscon-restart.dtsi" -#include - -/ { - compatible = "samsung,exynos3250"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - mshc0 = &mshc_0; - mshc1 = &mshc_1; - mshc2 = &mshc_2; - spi0 = &spi_0; - spi1 = &spi_1; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cmu CLK_ARM_CLK>; - clock-names = "cpu"; - #cooling-cells = <2>; - - operating-points = < - 1000000 1150000 - 900000 1112500 - 800000 1075000 - 700000 1037500 - 600000 1000000 - 500000 962500 - 400000 925000 - 300000 887500 - 200000 850000 - 100000 850000 - >; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fixed-rate-clocks { - #address-cells = <1>; - #size-cells = <0>; - - xusbxti: clock@0 { - compatible = "fixed-clock"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xusbxti"; - }; - - xxti: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xxti"; - }; - - xtcxo: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xtcxo"; - }; - }; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@3f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x3f000 0x1000>; - }; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sys_reg: syscon@10010000 { - compatible = "samsung,exynos3-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos3250-pmu", "syscon"; - reg = <0x10020000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - mipi_phy: video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - pd_cam: cam-power-domain@10023C00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; - #power-domain-cells = <0>; - }; - - pd_mfc: mfc-power-domain@10023C40 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; - #power-domain-cells = <0>; - }; - - pd_g3d: g3d-power-domain@10023C60 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; - #power-domain-cells = <0>; - }; - - pd_lcd0: lcd0-power-domain@10023C80 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp: isp-power-domain@10023CA0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - }; - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos3250-cmu"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, - <&cmu CLK_MOUT_ACLK_266_SUB>; - assigned-clock-parents = <&cmu CLK_FIN_PLL>, - <&cmu CLK_FIN_PLL>; - }; - - cmu_dmc: clock-controller@105C0000 { - compatible = "samsung,exynos3250-cmu-dmc"; - reg = <0x105C0000 0x2000>; - #clock-cells = <1>; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = <0 73 0>, <0 74 0>; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; - }; - - tmu: tmu@100C0000 { - compatible = "samsung,exynos3250-tmu"; - reg = <0x100C0000 0x100>; - interrupts = <0 216 0>; - clocks = <&cmu CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - status = "disabled"; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, - <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; - clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos3250-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 225 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupts = <0 48 0>; - }; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos3250-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 240 0>; - }; - - jpeg: codec@11830000 { - compatible = "samsung,exynos3250-jpeg"; - reg = <0x11830000 0x1000>; - interrupts = <0 171 0>; - clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; - clock-names = "jpeg", "sclk"; - power-domains = <&pd_cam>; - assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; - assigned-clock-rates = <0>, <150000000>; - assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; - iommus = <&sysmmu_jpeg>; - status = "disabled"; - }; - - sysmmu_jpeg: sysmmu@11A60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11a60000 0x1000>; - interrupts = <0 156 0>, <0 161 0>; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - fimd: fimd@11c00000 { - compatible = "samsung,exynos3250-fimd"; - reg = <0x11c00000 0x30000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0 84 0>, <0 85 0>, <0 86 0>; - clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sys_reg>; - status = "disabled"; - }; - - dsi_0: dsi@11C80000 { - compatible = "samsung,exynos3250-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = <0 83 0>; - samsung,phy-type = <0>; - power-domains = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sysmmu_fimd0: sysmmu@11E20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11e20000 0x1000>; - interrupts = <0 80 0>, <0 81 0>; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - hsotg: hsotg@12480000 { - compatible = "snps,dwc2"; - reg = <0x12480000 0x20000>; - interrupts = <0 141 0>; - clocks = <&cmu CLK_USBOTG>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - mshc_0: mshc@12510000 { - compatible = "samsung,exynos5420-dw-mshc"; - reg = <0x12510000 0x1000>; - interrupts = <0 142 0>; - clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_1: mshc@12520000 { - compatible = "samsung,exynos5420-dw-mshc"; - reg = <0x12520000 0x1000>; - interrupts = <0 143 0>; - clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_2: mshc@12530000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12530000 0x1000>; - interrupts = <0 144 0>; - clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - exynos_usbphy: exynos-usbphy@125B0000 { - compatible = "samsung,exynos3250-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <0 138 0>; - clocks = <&cmu CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <0 139 0>; - clocks = <&cmu CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - adc: adc@126C0000 { - compatible = "samsung,exynos3250-adc", - "samsung,exynos-adc-v2"; - reg = <0x126C0000 0x100>; - interrupts = <0 137 0>; - clock-names = "adc", "sclk"; - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - mfc: codec@13400000 { - compatible = "samsung,mfc-v7"; - reg = <0x13400000 0x10000>; - interrupts = <0 102 0>; - clock-names = "mfc", "sclk_mfc"; - clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; - power-domains = <&pd_mfc>; - iommus = <&sysmmu_mfc>; - }; - - sysmmu_mfc: sysmmu@13620000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13620000 0x1000>; - interrupts = <0 96 0>, <0 98 0>; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 109 0>; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data &uart0_fctl>; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = <0 110 0>; - clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 111 0>; - clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = <0 113 0>; - clocks = <&cmu CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = <0 114 0>; - clocks = <&cmu CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = <0 115 0>; - clocks = <&cmu CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = <0 116 0>; - clocks = <&cmu CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138A0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = <0 117 0>; - clocks = <&cmu CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138B0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = <0 118 0>; - clocks = <&cmu CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138C0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = <0 119 0>; - clocks = <&cmu CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138D0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = <0 120 0>; - clocks = <&cmu CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = <0 121 0>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = <0 122 0>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - i2s2: i2s@13970000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13970000 0x100>; - interrupts = <0 126 0>; - clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0"; - dmas = <&pdma0 14>, <&pdma0 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&i2s2_bus>; - pinctrl-names = "default"; - status = "disabled"; - }; - - pwm: pwm@139D0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 108 0>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 18 0>, <0 19 0>; - }; - - ppmu_dmc0: ppmu_dmc0@106a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106a0000 0x2000>; - status = "disabled"; - }; - - ppmu_dmc1: ppmu_dmc1@106b0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106b0000 0x2000>; - status = "disabled"; - }; - - ppmu_cpu: ppmu_cpu@106c0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106c0000 0x2000>; - status = "disabled"; - }; - - ppmu_rightbus: ppmu_rightbus@112a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x112a0000 0x2000>; - clocks = <&cmu CLK_PPMURIGHT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_leftbus: ppmu_leftbus0@116a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x116a0000 0x2000>; - clocks = <&cmu CLK_PPMULEFT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_camif: ppmu_camif@11ac0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11ac0000 0x2000>; - clocks = <&cmu CLK_PPMUCAMIF>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_lcd0: ppmu_lcd0@11e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11e40000 0x2000>; - clocks = <&cmu CLK_PPMULCD0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_fsys: ppmu_fsys@12630000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12630000 0x2000>; - clocks = <&cmu CLK_PPMUFILE>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_g3d: ppmu_g3d@13220000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13220000 0x2000>; - clocks = <&cmu CLK_PPMUG3D>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc: ppmu_mfc@13660000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13660000 0x2000>; - clocks = <&cmu CLK_PPMUMFC_L>; - clock-names = "ppmu"; - status = "disabled"; - }; - - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_dmc CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp@50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <800000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <800000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <800000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <875000>; - }; - }; - - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus_lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_160>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mcuisp: bus_mcuisp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; - clock-names = "bus"; - operating-points-v2 = <&bus_mcuisp_opp_table>; - status = "disabled"; - }; - - bus_isp: bus_isp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_266>; - clock-names = "bus"; - operating-points-v2 = <&bus_isp_opp_table>; - status = "disabled"; - }; - - bus_peril: bus_peril { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peril_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp@50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <900000>; - }; - opp@80000000 { - opp-hz = /bits/ 64 <80000000>; - opp-microvolt = <900000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1000000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1000000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - }; - }; - - bus_mcuisp_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp@50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp@80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - }; - - bus_isp_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp@50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp@80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp@300000000 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_peril_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp@50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp@80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - }; -}; - -#include "exynos3250-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi deleted file mode 100644 index 735cb2f10..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Device tree sources for Exynos4 thermal zone - * - * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -/ { -thermal-zones { - cpu_thermal: cpu-thermal { - thermal-sensors = <&tmu 0>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - cpu_alert0: cpu-alert-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <95000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - }; - map1 { - trip = <&cpu_alert1>; - }; - }; - }; -}; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4.dtsi deleted file mode 100644 index 5f034eb5a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4.dtsi +++ /dev/null @@ -1,998 +0,0 @@ -/* - * Samsung's Exynos4 SoC series common device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular - * SoCs from Exynos4 series can include this file and provide values for SoCs - * specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include "exynos-syscon-restart.dtsi" - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - i2c8 = &i2c_8; - csis0 = &csis_0; - csis1 = &csis_1; - fimc0 = &fimc_0; - fimc1 = &fimc_1; - fimc2 = &fimc_2; - fimc3 = &fimc_3; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - serial3 = &serial_3; - }; - - clock_audss: clock-controller@03810000 { - compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - }; - - i2s0: i2s@03830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - clocks = <&clock_audss EXYNOS_I2S_BUS>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; - dma-names = "tx", "rx", "tx-sec"; - samsung,idma-addr = <0x03000000>; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - memory-controller@12570000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - }; - - mipi_phy: video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - pd_mfc: mfc-power-domain@10023C40 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; - #power-domain-cells = <0>; - }; - - pd_g3d: g3d-power-domain@10023C60 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; - #power-domain-cells = <0>; - }; - - pd_lcd0: lcd0-power-domain@10023C80 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; - #power-domain-cells = <0>; - }; - - pd_tv: tv-power-domain@10023C20 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C20 0x20>; - #power-domain-cells = <0>; - power-domains = <&pd_lcd0>; - }; - - pd_cam: cam-power-domain@10023C00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; - #power-domain-cells = <0>; - }; - - pd_gps: gps-power-domain@10023CE0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CE0 0x20>; - #power-domain-cells = <0>; - }; - - pd_gps_alive: gps-alive-power-domain@10023D00 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023D00 0x20>; - #power-domain-cells = <0>; - }; - - gic: interrupt-controller@10490000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10490000 0x10000>, <0x10480000 0x10000>; - }; - - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x10440000 0x1000>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&combiner>; - interrupts = <2 2>, <3 2>; - }; - - sys_reg: syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4210-pmu", "syscon"; - reg = <0x10020000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - dsi_0: dsi@11C80000 { - compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = <0 79 0>; - power-domains = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "sclk_mipi"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - camera { - compatible = "samsung,fimc", "simple-bus"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - #clock-cells = <1>; - clock-output-names = "cam_a_clkout", "cam_b_clkout"; - ranges; - - fimc_0: fimc@11800000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11800000 0x1000>; - interrupts = <0 84 0>; - clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc0>; - status = "disabled"; - }; - - fimc_1: fimc@11810000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11810000 0x1000>; - interrupts = <0 85 0>; - clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc1>; - status = "disabled"; - }; - - fimc_2: fimc@11820000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11820000 0x1000>; - interrupts = <0 86 0>; - clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc2>; - status = "disabled"; - }; - - fimc_3: fimc@11830000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11830000 0x1000>; - interrupts = <0 87 0>; - clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; - clock-names = "fimc", "sclk_fimc"; - power-domains = <&pd_cam>; - samsung,sysreg = <&sys_reg>; - iommus = <&sysmmu_fimc3>; - status = "disabled"; - }; - - csis_0: csis@11880000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11880000 0x4000>; - interrupts = <0 78 0>; - clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; - clock-names = "csis", "sclk_csis"; - bus-width = <4>; - power-domains = <&pd_cam>; - phys = <&mipi_phy 0>; - phy-names = "csis"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - csis_1: csis@11890000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11890000 0x4000>; - interrupts = <0 80 0>; - clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; - clock-names = "csis", "sclk_csis"; - bus-width = <2>; - power-domains = <&pd_cam>; - phys = <&mipi_phy 2>; - phy-names = "csis"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - watchdog: watchdog@10060000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x10060000 0x100>; - interrupts = <0 43 0>; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - status = "disabled"; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupt-parent = <&pmu_system_controller>; - interrupts = <0 44 0>, <0 45 0>; - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - keypad: keypad@100A0000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; - interrupts = <0 109 0>; - clocks = <&clock CLK_KEYIF>; - clock-names = "keypad"; - status = "disabled"; - }; - - sdhci_0: sdhci@12510000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12510000 0x100>; - interrupts = <0 73 0>; - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_1: sdhci@12520000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12520000 0x100>; - interrupts = <0 74 0>; - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_2: sdhci@12530000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12530000 0x100>; - interrupts = <0 75 0>; - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - sdhci_3: sdhci@12540000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12540000 0x100>; - interrupts = <0 76 0>; - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - exynos_usbphy: exynos-usbphy@125B0000 { - compatible = "samsung,exynos4210-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = <0 71 0>; - clocks = <&clock CLK_USB_DEVICE>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - ehci: ehci@12580000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12580000 0x100>; - interrupts = <0 70 0>; - clocks = <&clock CLK_USB_HOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - port@1 { - reg = <1>; - phys = <&exynos_usbphy 2>; - status = "disabled"; - }; - port@2 { - reg = <2>; - phys = <&exynos_usbphy 3>; - status = "disabled"; - }; - }; - - ohci: ohci@12590000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12590000 0x100>; - interrupts = <0 70 0>; - clocks = <&clock CLK_USB_HOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - }; - - i2s1: i2s@13960000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13960000 0x100>; - clocks = <&clock CLK_I2S1>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - dmas = <&pdma1 12>, <&pdma1 11>; - dma-names = "tx", "rx"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - i2s2: i2s@13970000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0x13970000 0x100>; - clocks = <&clock CLK_I2S2>; - clock-names = "iis"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - dmas = <&pdma0 14>, <&pdma0 13>; - dma-names = "tx", "rx"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; - power-domains = <&pd_mfc>; - clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; - clock-names = "mfc", "sclk_mfc"; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 52 0>; - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 15>, <&pdma0 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = <0 53 0>; - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 15>, <&pdma1 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma0 17>, <&pdma0 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - serial_3: serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = <0 55 0>; - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - dmas = <&pdma1 17>, <&pdma1 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = <0 58 0>; - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = <0 59 0>; - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = <0 60 0>; - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = <0 61 0>; - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138A0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = <0 62 0>; - clocks = <&clock CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138B0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = <0 63 0>; - clocks = <&clock CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138C0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = <0 64 0>; - clocks = <&clock CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138D0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = <0 65 0>; - clocks = <&clock CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - i2c_8: i2c@138E0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x138E0000 0x100>; - interrupts = <0 93 0>; - clocks = <&clock CLK_I2C_HDMI>; - clock-names = "i2c"; - status = "disabled"; - - hdmi_i2c_phy: hdmiphy@38 { - compatible = "exynos4210-hdmiphy"; - reg = <0x38>; - }; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = <0 66 0>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = <0 67 0>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = <0 68 0>; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - status = "disabled"; - }; - - pwm: pwm@139D0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; - clocks = <&clock CLK_PWM>; - clock-names = "timers"; - #pwm-cells = <3>; - status = "disabled"; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <0 35 0>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <0 36 0>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma1: mdma@12850000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12850000 0x1000>; - interrupts = <0 34 0>; - clocks = <&clock CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - }; - - fimd: fimd@11c00000 { - compatible = "samsung,exynos4210-fimd"; - interrupt-parent = <&combiner>; - reg = <0x11c00000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <11 0>, <11 1>, <11 2>; - clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sys_reg>; - status = "disabled"; - }; - - tmu: tmu@100C0000 { - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - jpeg_codec: jpeg-codec@11840000 { - compatible = "samsung,exynos4210-jpeg"; - reg = <0x11840000 0x1000>; - interrupts = <0 88 0>; - clocks = <&clock CLK_JPEG>; - clock-names = "jpeg"; - power-domains = <&pd_cam>; - iommus = <&sysmmu_jpeg>; - }; - - rotator: rotator@12810000 { - compatible = "samsung,exynos4210-rotator"; - reg = <0x12810000 0x64>; - interrupts = <0 83 0>; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - hdmi: hdmi@12D00000 { - compatible = "samsung,exynos4210-hdmi"; - reg = <0x12D00000 0x70000>; - interrupts = <0 92 0>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", - "mout_hdmi"; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - phy = <&hdmi_i2c_phy>; - power-domains = <&pd_tv>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - hdmicec: cec@100B0000 { - compatible = "samsung,s5p-cec"; - reg = <0x100B0000 0x200>; - interrupts = <0 114 0>; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "disabled"; - }; - - mixer: mixer@12C10000 { - compatible = "samsung,exynos4210-mixer"; - interrupts = <0 91 0>; - reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; - power-domains = <&pd_tv>; - iommus = <&sysmmu_tv>; - status = "disabled"; - }; - - ppmu_dmc0: ppmu_dmc0@106a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106a0000 0x2000>; - clocks = <&clock CLK_PPMUDMC0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_dmc1: ppmu_dmc1@106b0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106b0000 0x2000>; - clocks = <&clock CLK_PPMUDMC1>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_cpu: ppmu_cpu@106c0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106c0000 0x2000>; - clocks = <&clock CLK_PPMUCPU>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_acp: ppmu_acp@10ae0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106e0000 0x2000>; - status = "disabled"; - }; - - ppmu_rightbus: ppmu_rightbus@112a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x112a0000 0x2000>; - clocks = <&clock CLK_PPMURIGHT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_leftbus: ppmu_leftbus0@116a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x116a0000 0x2000>; - clocks = <&clock CLK_PPMULEFT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_camif: ppmu_camif@11ac0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11ac0000 0x2000>; - clocks = <&clock CLK_PPMUCAMIF>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_lcd0: ppmu_lcd0@11e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x11e40000 0x2000>; - clocks = <&clock CLK_PPMULCD0>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_fsys: ppmu_g3d@12630000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12630000 0x2000>; - status = "disabled"; - }; - - ppmu_image: ppmu_image@12aa0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12aa0000 0x2000>; - clocks = <&clock CLK_PPMUIMAGE>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_tv: ppmu_tv@12e40000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12e40000 0x2000>; - clocks = <&clock CLK_PPMUTV>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_g3d: ppmu_g3d@13220000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13220000 0x2000>; - clocks = <&clock CLK_PPMUG3D>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc_left: ppmu_mfc_left@13660000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13660000 0x2000>; - clocks = <&clock CLK_PPMUMFC_L>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_mfc_right: ppmu_mfc_right@13670000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x13670000 0x2000>; - clocks = <&clock CLK_PPMUMFC_R>; - clock-names = "ppmu"; - status = "disabled"; - }; - - sysmmu_mfc_l: sysmmu@13620000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13620000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@13630000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13630000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&pd_mfc>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@12E20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12E20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; - power-domains = <&pd_tv>; - #iommu-cells = <0>; - }; - - sysmmu_fimc0: sysmmu@11A20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc1: sysmmu@11A30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A30000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 3>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc2: sysmmu@11A40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_fimc3: sysmmu@11A50000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A50000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg: sysmmu@11A60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - power-domains = <&pd_cam>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@12A30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12A30000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_fimd0: sysmmu@11E20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11E20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <0 112 0>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - - prng: rng@10830400 { - compatible = "samsung,exynos4-rng"; - reg = <0x10830400 0x200>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4210-origen.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4210-origen.dts deleted file mode 100644 index a2c6a13fe..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4210-origen.dts +++ /dev/null @@ -1,334 +0,0 @@ -/* - * Samsung's Exynos4210 based Origen board device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Device tree source file for Insignal's Origen board which is based on - * Samsung's Exynos4210 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4210.dtsi" -#include -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Insignal Origen evaluation board based on Exynos4210"; - compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000 - 0x60000000 0x10000000 - 0x70000000 0x10000000>; - }; - - chosen { - bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; - stdout-path = &serial_2; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - mmc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - up { - label = "Up"; - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - down { - label = "Down"; - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - back { - label = "Back"; - gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - home { - label = "Home"; - gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - status { - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <47500000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <64>; - hback-porch = <16>; - hsync-len = <48>; - vback-porch = <64>; - vfront-porch = <16>; - vsync-len = <3>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck1_reg>; -}; - -&fimd { - pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - - max8997_pmic@66 { - compatible = "maxim,max8997-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <4 0>, <3 0>; - - max8997,pmic-buck1-dvs-voltage = <1350000>; - max8997,pmic-buck2-dvs-voltage = <1100000>; - max8997,pmic-buck5-dvs-voltage = <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VMIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_RTC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_AUD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "DVDD_SWB_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_PLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_AUD_3V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "AVDD18_SWB_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDD_SWB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD_MIF_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - /* - * HACK: The real name is VDD_ARM_1.2V, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_INT_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_G3D_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VDD_LCD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&sdhci_0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&tmu { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4210-pinctrl.dtsi deleted file mode 100644 index d9b6d25e4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ /dev/null @@ -1,856 +0,0 @@ -/* - * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2011-2012 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -/ { - pinctrl@11400000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe2: gpe2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe3: gpe3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe4: gpe4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_sync: lcd-sync { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_en: lcd-en { - samsung,pins = "gpe3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl@11000000 { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl@03860000 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4210-smdkv310.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4210-smdkv310.dts deleted file mode 100644 index 9c98a3724..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Samsung's Exynos4210 based SMDKV310 board device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Device tree source file for Samsung's SMDKV310 board which is based on - * Samsung's Exynos4210 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4210.dtsi" -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Samsung smdkv310 evaluation board based on Exynos4210"; - compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; - stdout-path = &serial_1; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <12000000>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - eeprom@50 { - compatible = "samsung,24ad0xd1"; - reg = <0x50>; - }; - - eeprom@52 { - compatible = "samsung,24ad0xd1"; - reg = <0x52>; - }; -}; - -&keypad { - samsung,keypad-num-rows = <2>; - samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_rows &keypad_cols>; - status = "okay"; - - key_1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = <2>; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = <3>; - }; - - key_3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <4>; - }; - - key_4 { - keypad,row = <0>; - keypad,column = <6>; - linux,code = <5>; - }; - - key_5 { - keypad,row = <0>; - keypad,column = <7>; - linux,code = <6>; - }; - - key_a { - keypad,row = <1>; - keypad,column = <3>; - linux,code = <30>; - }; - - key_b { - keypad,row = <1>; - keypad,column = <4>; - linux,code = <48>; - }; - - key_c { - keypad,row = <1>; - keypad,column = <5>; - linux,code = <46>; - }; - - key_d { - keypad,row = <1>; - keypad,column = <6>; - linux,code = <32>; - }; - - key_e { - keypad,row = <1>; - keypad,column = <7>; - linux,code = <18>; - }; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&spi_2 { - cs-gpios = <&gpc1 2 GPIO_ACTIVE_HIGH>; - status = "okay"; - - w25x80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25x80"; - reg = <0>; - spi-max-frequency = <1000000>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4210-trats.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4210-trats.dts deleted file mode 100644 index 0ca1b4d35..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4210-trats.dts +++ /dev/null @@ -1,493 +0,0 @@ -/* - * Samsung's Exynos4210 based Trats board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Trats board which is based on - * Samsung's Exynos4210 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4210.dtsi" -#include - -/ { - model = "Samsung Trats based on Exynos4210"; - compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000 - 0x60000000 0x10000000 - 0x70000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; - stdout-path = &serial_2; - }; - - regulators { - compatible = "simple-bus"; - - vemmc_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - tsp_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "TSP_FIXED_VOLTAGES"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_af_28v_reg: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "8M_AF_2.8V_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_io_en_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "CAM_IO_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_io_12v_reg: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "8M_1.2V_EN"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vt_core_15v_reg: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "VT_CORE_1.5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - vol-down-key { - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <10>; - }; - - vol-up-key { - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <10>; - }; - - power-key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - - ok-key { - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,code = <352>; - label = "ok"; - debounce-interval = <10>; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 2 2>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 4 4>; - }; - }; - }; - }; - - camera { - pinctrl-names = "default"; - pinctrl-0 = <>; - status = "okay"; - - fimc_0: fimc@11800000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_1: fimc@11810000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_2: fimc@11820000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_3: fimc@11830000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&varm_breg>; -}; - -&dsi_0 { - vddcore-supply = <&vusb_reg>; - vddio-supply = <&vmipi_reg>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi_out: endpoint { - remote-endpoint = <&dsi_in>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - }; - }; - }; - - panel@0 { - reg = <0>; - compatible = "samsung,s6e8aa0"; - vdd3-supply = <&vcclcd_reg>; - vci-supply = <&vlcd_reg>; - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - - port { - dsi_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safe1_sreg>; -}; - -&fimd { - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&vusb_reg>; - vusb_a-supply = <&vusbdac_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - mms114-touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpx0>; - interrupts = <4 2>; - x-size = <720>; - y-size = <1280>; - avdd-supply = <&tsp_reg>; - vdd-supply = <&tsp_reg>; - }; -}; - -&i2c_5 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - status = "okay"; - - max8997_pmic@66 { - compatible = "maxim,max8997-pmic"; - - reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <7 0>; - - max8997,pmic-buck1-uses-gpio-dvs; - max8997,pmic-buck2-uses-gpio-dvs; - max8997,pmic-buck5-uses-gpio-dvs; - - max8997,pmic-ignore-gpiodvs-side-effect; - max8997,pmic-buck125-default-dvs-idx = <0>; - - max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, - <&gpx0 6 GPIO_ACTIVE_HIGH>, - <&gpl0 0 GPIO_ACTIVE_HIGH>; - - max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, - <950000>, <900000>, - <1100000>, <1000000>, - <950000>, <900000>; - - max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - valive_reg: LDO2 { - regulator-name = "VALIVE_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vusb_reg: LDO3 { - regulator-name = "VUSB_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vmipi_reg: LDO4 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vpda_reg: LDO6 { - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcam_reg: LDO7 { - regulator-name = "CAM_ISP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vusbdac_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V_C210"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccpda_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vpll_reg: LDO10 { - regulator-name = "VPLL_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vtcam_reg: LDO12 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcclcd_reg: LDO13 { - regulator-name = "VCC_3.3V_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vlcd_reg: LDO15 { - regulator-name = "VLCD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - }; - - camsensor_reg: LDO16 { - regulator-name = "CAM_SENSOR_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddq_reg: LDO21 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - varm_breg: BUCK1 { - /* - * HACK: The real name is VARM_1.2V_C210, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vint_breg: BUCK2 { - regulator-name = "VINT_1.1V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - camisp_breg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vmem_breg: BUCK5 { - regulator-name = "VMEM_1.2V_C210"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vccsub_breg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; -}; - -&sdhci_0 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&vemmc_reg>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4210-universal_c210.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4210-universal_c210.dts deleted file mode 100644 index 0c89ea99d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ /dev/null @@ -1,584 +0,0 @@ -/* - * Samsung's Exynos4210 based Universal C210 board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Universal C210 board which is based on - * Samsung's Exynos4210 rev0 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4210.dtsi" -#include - -/ { - model = "Samsung Universal C210 based on Exynos4210 rev0"; - compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; - stdout-path = &serial_2; - }; - - sysram@02020000 { - smp-sysram@0 { - status = "disabled"; - }; - - smp-sysram@5000 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x5000 0x1000>; - }; - - smp-sysram@1f000 { - status = "disabled"; - }; - }; - - mct@10050000 { - compatible = "none"; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - vemmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2_8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe1 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - - vol-up-key { - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <1>; - }; - - vol-down-key { - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <1>; - }; - - config-key { - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = <171>; - label = "config"; - debounce-interval = <1>; - wakeup-source; - }; - - camera-key { - gpios = <&gpx2 3 GPIO_ACTIVE_LOW>; - linux,code = <212>; - label = "camera"; - debounce-interval = <1>; - }; - - power-key { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - - ok-key { - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,code = <352>; - label = "ok"; - debounce-interval = <1>; - }; - }; - - tsp_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "TSP_2_8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe2 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - spi-lcd { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - cs-gpios = <&gpy4 3 GPIO_ACTIVE_HIGH>; - - lcd@0 { - compatible = "samsung,ld9040"; - reg = <0>; - vdd3-supply = <&ldo7_reg>; - vci-supply = <&ldo17_reg>; - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <1200000>; - spi-cpol; - spi-cpha; - power-on-delay = <10>; - reset-delay = <10>; - panel-width-mm = <90>; - panel-height-mm = <154>; - display-timings { - timing { - clock-frequency = <23492370>; - hactive = <480>; - vactive = <800>; - hback-porch = <16>; - hfront-porch = <16>; - vback-porch = <2>; - vfront-porch = <28>; - hsync-len = <2>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_dpi_ep>; - }; - }; - }; - }; - - camera { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <>; - - fimc_0: fimc@11800000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_1: fimc@11810000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_2: fimc@11820000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - - fimc_3: fimc@11830000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_SCLK_MPLL>; - assigned-clock-rates = <0>, <160000000>; - }; - }; - - hdmi_en: voltage-regulator-hdmi-5v { - compatible = "regulator-fixed"; - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpe0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi_ddc: i2c-ddc { - compatible = "i2c-gpio"; - gpios = <&gpe4 2 GPIO_ACTIVE_HIGH &gpe4 3 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <100>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&i2c_ddc_bus>; - pinctrl-names = "default"; - status = "okay"; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm_reg>; -}; - -&ehci { - status = "okay"; - port@0 { - status = "okay"; - }; -}; - -&exynos_usbphy { - status = "okay"; - vbus-supply = <&safeout1_reg>; -}; - -&fimd { - pinctrl-0 = <&lcd_clk>, <&lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - samsung,invert-vden; - samsung,invert-vclk; - #address-cells = <1>; - #size-cells = <0>; - port@3 { - reg = <3>; - fimd_dpi_ep: endpoint { - remote-endpoint = <&lcd_ep>; - }; - }; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - hdmi-en-supply = <&hdmi_en>; - vdd-supply = <&ldo3_reg>; - vdd_osc-supply = <&ldo4_reg>; - vdd_pll-supply = <&ldo3_reg>; - ddc = <&hdmi_ddc>; - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo3_reg>; - vusb_a-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - tsp@4a { - /* TBD: Atmel maXtouch touchscreen */ - reg = <0x4a>; - }; -}; - -&i2c_5 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - status = "okay"; - - vdd_arm_reg: pmic@60 { - compatible = "maxim,max8952"; - reg = <0x60>; - - max8952,vid-gpios = <&gpx0 3 GPIO_ACTIVE_HIGH>, - <&gpx0 4 GPIO_ACTIVE_HIGH>; - max8952,default-mode = <0>; - max8952,dvs-mode-microvolt = <1250000>, <1200000>, - <1050000>, <950000>; - max8952,sync-freq = <0>; - max8952,ramp-speed = <0>; - - regulator-name = "vdd_arm"; - regulator-min-microvolt = <770000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - pmic@66 { - compatible = "national,lp3974"; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, - <&gpx0 6 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>, - <1100000>, <1000000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gpe2 0 GPIO_ACTIVE_HIGH>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "LDO6"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD+VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "PS_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VHIC_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_I_HOST_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_S_DIG+FM33_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "CAM_S_ANA_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VCC_3.0V_LCD"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VINT_1.1V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VG3D_1.1V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "VMEM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ap32khz_reg: EN32KHz-AP { - regulator-name = "32KHz AP"; - regulator-always-on; - }; - - cp32khz_reg: EN32KHz-CP { - regulator-name = "32KHz CP"; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - }; - - safeout1_reg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - }; - - safeout2_reg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; -}; - -&mdma1 { - reg = <0x12840000 0x1000>; -}; - -&mixer { - status = "okay"; -}; - -&ohci { - status = "okay"; - port@0 { - status = "okay"; - }; -}; - -&pinctrl_1 { - hdmi_hpd: hdmi-hpd { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; -}; - -&pinctrl_0 { - i2c_ddc_bus: i2c-ddc-bus { - samsung,pins = "gpe4-2", "gpe4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - compatible = "samsung,s5p6440-pwm"; - status = "okay"; -}; - -&sdhci_0 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&vemmc_reg>; - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo5_reg>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; - cd-inverted; - status = "okay"; -}; - -&serial_0 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&serial_1 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&serial_2 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&serial_3 { - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4210.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4210.dtsi deleted file mode 100644 index 2d9b02967..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4210.dtsi +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Samsung's Exynos4210 SoC device tree source - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2010-2011 Linaro Ltd. - * www.linaro.org - * - * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "exynos4.dtsi" -#include "exynos4210-pinctrl.dtsi" -#include "exynos4-cpu-thermal.dtsi" - -/ { - compatible = "samsung,exynos4210", "samsung,exynos4"; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@900 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x900>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - clock-latency = <160000>; - - operating-points = < - 1200000 1250000 - 1000000 1150000 - 800000 1075000 - 500000 975000 - 400000 975000 - 200000 950000 - >; - cooling-min-level = <4>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu@901 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x901>; - }; - }; - - sysram: sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x20000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@1f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x1f000 0x1000>; - }; - }; - - pd_lcd1: lcd1-power-domain@10023CA0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <2 2 1>; - }; - - mct: mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &gic 0 57 0>, - <1 &gic 0 69 0>, - <2 &combiner 12 6>, - <3 &combiner 12 7>, - <4 &gic 0 42 0>, - <5 &gic 0 48 0>; - }; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4210-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 46 0>; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - - pinctrl_2: pinctrl@03860000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x03860000 0x1000>; - }; - - tmu: tmu@100C0000 { - compatible = "samsung,exynos4210-tmu"; - interrupt-parent = <&combiner>; - reg = <0x100C0000 0x100>; - interrupts = <2 4>; - clocks = <&clock CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - samsung,tmu_gain = <15>; - samsung,tmu_reference_voltage = <7>; - status = "disabled"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert0: cpu-alert-0 { - temperature = <85000>; /* millicelsius */ - }; - cpu_alert1: cpu-alert-1 { - temperature = <100000>; /* millicelsius */ - }; - cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - }; - }; - }; - }; - - g2d: g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = <0 89 0>; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - power-domains = <&pd_lcd0>; - iommus = <&sysmmu_g2d>; - }; - - camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - - fimc_0: fimc@11800000 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; - }; - - fimc_1: fimc@11810000 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; - }; - - fimc_2: fimc@11820000 { - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; - }; - - fimc_3: fimc@11830000 { - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,lcd-wb; - }; - }; - - mixer: mixer@12C10000 { - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", - "sclk_mixer"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, - <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; - }; - - ppmu_lcd1: ppmu_lcd1@12240000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x12240000 0x2000>; - clocks = <&clock CLK_PPMULCD1>; - clock-names = "ppmu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@12A20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12A20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1: sysmmu@12220000 { - compatible = "samsung,exynos-sysmmu"; - interrupt-parent = <&combiner>; - reg = <0x12220000 0x1000>; - interrupts = <5 3>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; - power-domains = <&pd_lcd1>; - #iommu-cells = <0>; - }; - - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_acp: bus_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_display: bus_display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus_lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1025000>; - }; - opp@267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1050000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1150000>; - }; - }; - - bus_acp_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_peri_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp@5000000 { - opp-hz = /bits/ 64 <5000000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_fsys_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp@10000000 { - opp-hz = /bits/ 64 <10000000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_display_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - }; - - bus_leftbus_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; -}; - -&gic { - cpu-offset = <0x8000>; -}; - -&combiner { - samsung,combiner-nr = <16>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; -}; - -&mdma1 { - power-domains = <&pd_lcd0>; -}; - -&pmu_system_controller { - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; -}; - -&rotator { - power-domains = <&pd_lcd0>; -}; - -&sysmmu_rotator { - power-domains = <&pd_lcd0>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4212.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4212.dtsi deleted file mode 100644 index 538901123..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4212.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Samsung's Exynos4212 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "exynos4x12.dtsi" - -/ { - compatible = "samsung,exynos4212", "samsung,exynos4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@A00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA00>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - cooling-min-level = <13>; - cooling-max-level = <7>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu@A01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA01>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp01 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp02 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <925000>; - clock-latency-ns = <200000>; - }; - opp03 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - clock-latency-ns = <200000>; - }; - opp04 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <200000>; - }; - opp05 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <987500>; - clock-latency-ns = <200000>; - }; - opp06 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <200000>; - }; - opp07 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <200000>; - }; - opp08 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1087500>; - clock-latency-ns = <200000>; - }; - opp09 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <200000>; - }; - opp10 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1187500>; - clock-latency-ns = <200000>; - }; - opp11 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <200000>; - }; - opp12 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1287500>; - clock-latency-ns = <200000>; - }; - opp13 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - turbo-mode; - }; - }; -}; - -&combiner { - samsung,combiner-nr = <18>; -}; - -&gic { - cpu-offset = <0x8000>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroid-common.dtsi deleted file mode 100644 index 5282d69e5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ /dev/null @@ -1,565 +0,0 @@ -/* - * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards - * device tree source - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - chosen { - stdout-path = &serial_1; - }; - - firmware@0204F000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_power_key>; - - power_key { - interrupt-parent = <&gpx1>; - interrupts = <3 0>; - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <192000000>, - <19200000>; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - - simple-audio-card,cpu { - sound-dai = <&i2s0 0>; - system-clock-frequency = <19200000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&max98090>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - }; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&sd1_cd>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; - }; - - camera { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - cooling_map0: map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>; - }; - cooling_map1: map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>; - }; - }; - }; - }; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_display { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -/* RSTN signal for eMMC */ -&sd1_cd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - -&pinctrl_1 { - gpio_power_key: power_key { - samsung,pins = "gpx1-3"; - samsung,pin-pud = ; - }; - - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd: hdmi-hpd { - samsung,pins = "gpx3-7"; - samsung,pin-pud = ; - }; -}; - -&ehci { - status = "okay"; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - ddc = <&i2c_2>; - status = "okay"; -}; - -&hdmicec { - status = "okay"; -}; - -&hsotg { - dr_mode = "peripheral"; - status = "okay"; - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; -}; - -&i2c_0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - usb3503: usb3503@08 { - compatible = "smsc,usb3503"; - reg = <0x08>; - - intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; - connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; - initial-mode = <1>; - }; - - max77686: pmic@09 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 0>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M1_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDQ_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_MMC2_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDDQ_MMC1_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_HDMI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDDQ_MIPIHSI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_USB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_HSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo20_reg: LDO20 { - regulator-name = "LDO20_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "TFLASH_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo22_reg: LDO22 { - /* - * Only U3 uses it, so let it define the - * constraints - */ - regulator-name = "LDO22"; - regulator-boot-on; - }; - - ldo25_reg: LDO25 { - regulator-name = "VDDQ_LCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-microvolt-offset = <50000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDDQ_CKEM1_2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "BUCK6_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "BUCK7_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - /* - * Constraints set by specific board: X, - * X2 and U3. - */ - regulator-name = "BUCK8_2.8V"; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpx0>; - interrupts = <0 0>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2c_2 { - status = "okay"; -}; - -&i2c_8 { - status = "okay"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; -}; - -&mixer { - status = "okay"; -}; - -&mshc_0 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&ldo20_reg>; - mmc-pwrseq = <&emmc_pwrseq>; - status = "okay"; - - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - vqmmc-supply = <&ldo4_reg>; - cd-gpios = <&gpk2 2 GPIO_ACTIVE_HIGH>; - cd-inverted; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&tmu { - vtmu-supply = <&ldo10_reg>; - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidu3.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidu3.dts deleted file mode 100644 index 7504a5aa5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Hardkernel's Exynos4412 based ODROID-U3 board device tree source - * - * Copyright (c) 2014 Marek Szyprowski - * - * Device tree source file for Hardkernel's ODROID-U3 board which is based - * on Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4412-odroid-common.dtsi" -#include "exynos4412-prime.dtsi" - -/ { - model = "Hardkernel ODROID-U3 board based on Exynos4412"; - compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7FF00000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "led1:heart"; - gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 10000 0>; - cooling-min-state = <0>; - cooling-max-state = <3>; - #cooling-cells = <2>; - cooling-levels = <0 102 170 230>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 9 9>; - }; - map1 { - trip = <&cpu_alert2>; - cooling-device = <&cpu0 15 15>; - }; - map2 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map3 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map4 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - }; - }; - }; -}; - -/* Supply for LAN9730/SMSC95xx */ -&buck8_reg { - regulator-name = "BUCK8_P3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -/* VDDQ for MSHC (eMMC card) */ -&ldo22_reg { - regulator-name = "LDO22_VDDQ_MMC4_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&mshc_0 { - vqmmc-supply = <&ldo22_reg>; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; - status = "okay"; -}; - -&usb3503 { - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - refclk-frequency = <24000000>; -}; - -&ehci { - port@1 { - status = "okay"; - }; - port@2 { - status = "okay"; - }; -}; - -&sound { - simple-audio-card,name = "Odroid-U3"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Speakers", "Speakers"; - simple-audio-card,routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN1", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR"; -}; - -&spi_1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidx.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidx.dts deleted file mode 100644 index 61906b35e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidx.dts +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Hardkernel's Exynos4412 based ODROID-X board device tree source - * - * Copyright (c) 2012 Dongjin Kim - * - * Device tree source file for Hardkernel's ODROID-X board which is based - * on Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4412-odroid-common.dtsi" - -/ { - model = "Hardkernel ODROID-X board based on Exynos4412"; - compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x3FF00000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "led1:heart"; - gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led2 { - label = "led2:mmc0"; - gpios = <&gpc1 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "mmc0"; - }; - }; - - gpio_keys { - pinctrl-0 = <&gpio_power_key &gpio_home_key>; - - home_key { - interrupt-parent = <&gpx2>; - interrupts = <2 0>; - gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - label = "home key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - - regulator_p3v3 { - compatible = "regulator-fixed"; - regulator-name = "p3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpa1 1 GPIO_ACTIVE_LOW>; - enable-active-high; - regulator-always-on; - }; -}; - -/* VDDQ for MSHC (eMMC card) */ -&buck8_reg { - regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&ehci { - port@1 { - status = "okay"; - }; -}; - -&mshc_0 { - vqmmc-supply = <&buck8_reg>; -}; - -&pinctrl_1 { - gpio_home_key: home_key { - samsung,pins = "gpx2-2"; - samsung,pin-pud = ; - }; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidx2.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidx2.dts deleted file mode 100644 index d6e92ebc3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Hardkernel's Exynos4412 based ODROID-X2 board device tree source - * - * Copyright (c) 2012 Dongjin Kim - * - * Device tree source file for Hardkernel's ODROID-X2 board which is based - * on Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "exynos4412-odroidx.dts" -#include "exynos4412-prime.dtsi" - -/ { - model = "Hardkernel ODROID-X2 board based on Exynos4412"; - compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7FF00000>; - }; -}; - -/* VDDQ for MSHC (eMMC card) */ -&buck8_reg { - regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&mshc_0 { - vqmmc-supply = <&buck8_reg>; -}; - -&sound { - simple-audio-card,name = "Odroid-X2"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Microphone", "Mic Jack", - "Microphone", "DMIC"; - simple-audio-card,routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "IN1", "Mic Jack", - "Mic Jack", "MICBIAS"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-origen.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4412-origen.dts deleted file mode 100644 index a1ab6f94b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-origen.dts +++ /dev/null @@ -1,547 +0,0 @@ -/* - * Insignal's Exynos4412 based Origen board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Insignal's Origen board which is based on - * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4412.dtsi" -#include -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Insignal Origen evaluation board based on Exynos4412"; - compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - chosen { - bootargs ="console=ttySAC2,115200"; - stdout-path = &serial_2; - }; - - firmware@0203F000 { - compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - mmc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <47500000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <64>; - hback-porch = <16>; - hsync-len = <48>; - vback-porch = <64>; - vfront-porch = <16>; - vsync-len = <3>; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&exynos_usbphy { - status = "okay"; -}; - -&ehci { - samsung,vbus-gpio = <&gpx3 5 1>; - status = "okay"; - - port@1{ - status = "okay"; - }; - port@2 { - status = "okay"; - }; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_0 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck-default-dvs-idx = <3>; - - s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, - <&gpx2 4 GPIO_ACTIVE_HIGH>, - <&gpx2 5 GPIO_ACTIVE_HIGH>; - - s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>, - <&gpm3 6 GPIO_ACTIVE_HIGH>, - <&gpm3 7 GPIO_ACTIVE_HIGH>; - - s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDIOAP_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_PRE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD18_2M"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_MIPI"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD33_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD18_MIPI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_UOTG"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDIOPERI_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB02"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_USH"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDIOAP_MMC012_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo18_reg: LDO18 { - regulator-name = "VDDIOPERI_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo19_reg: LDO19 { - regulator-name = "DVDD25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD28_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD28_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo22_reg: LDO22 { - regulator-name = "VDDA28_2M"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD28_TF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD33_A31"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo25_reg: LDO25 { - regulator-name = "VDD18_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD18_A31"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo27_reg: LDO27 { - regulator-name = "GPS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo28_reg: LDO28 { - regulator-name = "DVDD12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - }; - }; -}; - -&keypad { - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <2>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-0 = <&keypad_rows &keypad_cols>; - pinctrl-names = "default"; - status = "okay"; - - key_home { - keypad,row = <0>; - keypad,column = <0>; - linux,code = ; - }; - - key_down { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key_up { - keypad,row = <1>; - keypad,column = <0>; - linux,code = ; - }; - - key_menu { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key_back { - keypad,row = <2>; - keypad,column = <0>; - linux,code = ; - }; - - key_enter { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; -}; - -&mshc_0 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi deleted file mode 100644 index 16e4b77d8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Device tree sources for Exynos4412 PPMU common device tree - * - * Copyright (C) 2015 Samsung Electronics - * Author: Chanwoo Choi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -&ppmu_dmc0 { - status = "okay"; - - events { - ppmu_dmc0_3: ppmu-event3-dmc0 { - event-name = "ppmu-event3-dmc0"; - }; - }; -}; - -&ppmu_dmc1 { - status = "okay"; - - events { - ppmu_dmc1_3: ppmu-event3-dmc1 { - event-name = "ppmu-event3-dmc1"; - }; - }; -}; - -&ppmu_leftbus { - status = "okay"; - - events { - ppmu_leftbus_3: ppmu-event3-leftbus { - event-name = "ppmu-event3-leftbus"; - }; - }; -}; - -&ppmu_rightbus { - status = "okay"; - - events { - ppmu_rightbus_3: ppmu-event3-rightbus { - event-name = "ppmu-event3-rightbus"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-prime.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4412-prime.dtsi deleted file mode 100644 index e75bc170c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-prime.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Samsung's Exynos4412 Prime SoC device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Exynos4412 Prime SoC revision supports higher CPU frequencies than - * non-Prime version. Therefore we need to update OPPs table and - * thermal maps accordingly. - */ - -&cpu0_opp_1500 { - /delete-property/turbo-mode; -}; - -&cpu0_opp_table { - opp@1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - }; - opp@1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - }; -}; - -&cooling_map0 { - cooling-device = <&cpu0 9 9>; -}; - -&cooling_map1 { - cooling-device = <&cpu0 15 15>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-smdk4412.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4412-smdk4412.dts deleted file mode 100644 index 7fcb43431..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Samsung's Exynos4412 based SMDK board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's SMDK4412 board which is based on - * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4412.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Samsung SMDK evaluation board based on Exynos4412"; - compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - chosen { - bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; - stdout-path = &serial_1; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&keypad { - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; - wakeup-source; - pinctrl-0 = <&keypad_rows &keypad_cols>; - pinctrl-names = "default"; - status = "okay"; - - key_1 { - keypad,row = <1>; - keypad,column = <3>; - linux,code = <2>; - }; - - key_2 { - keypad,row = <1>; - keypad,column = <4>; - linux,code = <3>; - }; - - key_3 { - keypad,row = <1>; - keypad,column = <5>; - linux,code = <4>; - }; - - key_4 { - keypad,row = <1>; - keypad,column = <6>; - linux,code = <5>; - }; - - key_5 { - keypad,row = <1>; - keypad,column = <7>; - linux,code = <6>; - }; - - key_A { - keypad,row = <2>; - keypad,column = <6>; - linux,code = <30>; - }; - - key_B { - keypad,row = <2>; - keypad,column = <7>; - linux,code = <48>; - }; - - key_C { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <46>; - }; - - key_D { - keypad,row = <2>; - keypad,column = <5>; - linux,code = <32>; - }; - - key_E { - keypad,row = <0>; - keypad,column = <7>; - linux,code = <18>; - }; -}; - -&pinctrl_1 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-tiny4412.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4412-tiny4412.dts deleted file mode 100644 index 5504398e6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* - * FriendlyARM's Exynos4412 based TINY4412 board device tree source - * - * Copyright (c) 2013 Alex Ling - * - * Device tree source file for FriendlyARM's TINY4412 board which is based on - * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4412.dtsi" -#include - -/ { - model = "FriendlyARM TINY4412 board based on Exynos4412"; - compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4"; - - chosen { - stdout-path = &serial_0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "led1"; - gpios = <&gpm4 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "led2"; - gpios = <&gpm4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "led3"; - gpios = <&gpm4 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led4 { - label = "led4"; - gpios = <&gpm4 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdhci_2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi deleted file mode 100644 index e3f7934d1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Device tree sources for Exynos4412 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <55>; -samsung,tmu_min_efuse_value = <40>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = ; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412-trats2.dts b/software/linux/kernel/arch/arm/boot/dts/exynos4412-trats2.dts deleted file mode 100644 index 41ecd6d46..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412-trats2.dts +++ /dev/null @@ -1,1297 +0,0 @@ -/* - * Samsung's Exynos4412 based Trats 2 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Samsung's Trats 2 board which is based on - * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos4412.dtsi" -#include "exynos4412-ppmu-common.dtsi" -#include -#include -#include - -/ { - model = "Samsung Trats 2 based on Exynos4412"; - compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; - - aliases { - i2c9 = &i2c_ak8975; - i2c10 = &i2c_cm36651; - i2c11 = &i2c_max77693; - i2c12 = &i2c_max77693_fuel; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; - stdout-path = &serial_2; - }; - - firmware@0204F000 { - compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti", "fixed-clock"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti", "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - cam_io_reg: voltage-regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "CAM_SENSOR_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lcd_vdd3_reg: voltage-regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "LCD_VDD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - cam_af_reg: voltage-regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ps_als_reg: voltage-regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "LED_A_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-down { - gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; - linux,code = <114>; - label = "volume down"; - debounce-interval = <10>; - }; - - key-up { - gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = <115>; - label = "volume up"; - debounce-interval = <10>; - }; - - key-power { - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - debounce-interval = <10>; - wakeup-source; - }; - - key-ok { - gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; - linux,code = <139>; - label = "ok"; - debounce-inteval = <10>; - wakeup-source; - }; - }; - - i2c_max77693: i2c-gpio-1 { - compatible = "i2c-gpio"; - gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max77693@66 { - compatible = "maxim,max77693"; - interrupt-parent = <&gpx1>; - interrupts = <5 2>; - reg = <0x66>; - - regulators { - esafeout1_reg: ESAFEOUT1 { - regulator-name = "ESAFEOUT1"; - }; - esafeout2_reg: ESAFEOUT2 { - regulator-name = "ESAFEOUT2"; - }; - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <60000>; - regulator-max-microamp = <2580000>; - }; - }; - - max77693_haptic { - compatible = "maxim,max77693-haptic"; - haptic-supply = <&ldo26_reg>; - pwms = <&pwm 0 38022 0>; - }; - - charger { - compatible = "maxim,max77693-charger"; - - maxim,constant-microvolt = <4350000>; - maxim,min-system-microvolt = <3600000>; - maxim,thermal-regulation-celsius = <100>; - maxim,battery-overcurrent-microamp = <3500000>; - maxim,charge-input-threshold-microvolt = <4300000>; - }; - }; - }; - - i2c_max77693_fuel: i2c-gpio-3 { - compatible = "i2c-gpio"; - gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max77693-fuel-gauge@36 { - compatible = "maxim,max17047"; - interrupt-parent = <&gpx2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg = <0x36>; - - maxim,over-heat-temp = <700>; - maxim,over-volt = <4500>; - }; - }; - - i2c_ak8975: i2c-gpio-0 { - compatible = "i2c-gpio"; - gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ak8975@0c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c_cm36651: i2c-gpio-2 { - compatible = "i2c-gpio"; - gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - cm36651@18 { - compatible = "capella,cm36651"; - reg = <0x18>; - interrupt-parent = <&gpx0>; - interrupts = <2 2>; - vled-supply = <&ps_als_reg>; - }; - }; - - camera: camera { - pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; - pinctrl-names = "default"; - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_CAM0>, - <&clock CLK_MOUT_CAM1>; - assigned-clock-parents = <&clock CLK_XUSBXTI>, - <&clock CLK_XUSBXTI>; - - - }; - - sound { - compatible = "samsung,trats2-audio"; - samsung,i2s-controller = <&i2s0>; - samsung,model = "Trats2"; - samsung,audio-codec = <&wm1811>; - samsung,audio-routing = - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - "SPK", "SPKOUTRN", - "SPK", "SPKOUTRP"; - }; - - thermistor-ap { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; /* VCC_1.8V_AP */ - pullup-ohm = <100000>; /* 100K */ - pulldown-ohm = <100000>; /* 100K */ - io-channels = <&adc 1>; /* AP temperature */ - }; - - thermistor-battery { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; /* VCC_1.8V_AP */ - pullup-ohm = <100000>; /* 100K */ - pulldown-ohm = <100000>; /* 100K */ - io-channels = <&adc 2>; /* Battery temperature */ - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>; - }; - }; - }; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; -}; - -&bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; - status = "okay"; -}; - -&bus_acp { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_c2c { - devfreq = <&bus_dmc>; - status = "okay"; -}; - -&bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; -}; - -&bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_display { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&csis_0 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS0>, - <&clock CLK_SCLK_CSIS0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera C (3) MIPI CSI-2 (CSIS0) */ - port@3 { - reg = <3>; - csis0_ep: endpoint { - remote-endpoint = <&s5c73m3_ep>; - data-lanes = <1 2 3 4>; - samsung,csis-hs-settle = <12>; - }; - }; -}; - -&csis_1 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS1>, - <&clock CLK_SCLK_CSIS1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera D (4) MIPI CSI-2 (CSIS1) */ - port@4 { - reg = <4>; - csis1_ep: endpoint { - remote-endpoint = <&is_s5k6a3_ep>; - data-lanes = <1>; - samsung,csis-hs-settle = <18>; - samsung,csis-wclk; - }; - }; -}; - -&dsi_0 { - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi_out: endpoint { - remote-endpoint = <&dsi_in>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - }; - }; - }; - - panel@0 { - compatible = "samsung,s6e8aa0"; - reg = <0>; - vdd3-supply = <&lcd_vdd3_reg>; - vci-supply = <&ldo25_reg>; - reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - - port { - dsi_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&exynos_usbphy { - vbus-supply = <&esafeout1_reg>; - status = "okay"; -}; - -&fimc_0 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_1 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_2 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_3 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; -}; - -&fimc_is { - pinctrl-0 = <&fimc_is_uart>; - pinctrl-names = "default"; - status = "okay"; - - i2c1_isp: i2c-isp@12140000 { - pinctrl-0 = <&fimc_is_i2c1>; - pinctrl-names = "default"; - - s5k6a3@10 { - compatible = "samsung,s5k6a3"; - reg = <0x10>; - svdda-supply = <&cam_io_reg>; - svddio-supply = <&ldo19_reg>; - afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; - /* CAM_B_CLKOUT */ - clocks = <&camera 1>; - clock-names = "extclk"; - samsung,camclk-out = <1>; - gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; - - port { - is_s5k6a3_ep: endpoint { - remote-endpoint = <&csis1_ep>; - data-lanes = <1>; - }; - }; - }; - }; -}; - -&fimc_lite_0 { - status = "okay"; -}; - -&fimc_lite_1 { - status = "okay"; -}; - -&fimd { - status = "okay"; -}; - -&hsotg { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&i2c_0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5c73m3@3c { - compatible = "samsung,s5c73m3"; - reg = <0x3c>; - standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */ - xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ - vdd-int-supply = <&buck9_reg>; - vddio-cis-supply = <&ldo9_reg>; - vdda-supply = <&ldo17_reg>; - vddio-host-supply = <&ldo18_reg>; - vdd-af-supply = <&cam_af_reg>; - vdd-reg-supply = <&cam_io_reg>; - clock-frequency = <24000000>; - /* CAM_A_CLKOUT */ - clocks = <&camera 0>; - clock-names = "cis_extclk"; - port { - s5c73m3_ep: endpoint { - remote-endpoint = <&csis0_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&i2c_3 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - mms114-touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpm2>; - interrupts = <3 2>; - x-size = <720>; - y-size = <1280>; - avdd-supply = <&ldo23_reg>; - vdd-supply = <&ldo24_reg>; - }; -}; - -&i2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - status = "okay"; - - wm1811: wm1811@1a { - compatible = "wlf,wm1811"; - reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; - DCVDD-supply = <&ldo3_reg>; - DBVDD1-supply = <&ldo3_reg>; - wlf,ldo1ena = <&gpj0 4 0>; - }; -}; - -&i2c_7 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c7_bus>; - pinctrl-names = "default"; - status = "okay"; - - max77686: max77686_pmic@09 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx0>; - interrupts = <7 0>; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VALIVE_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VM1M2_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VCC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VCC_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "VCC_1.8V_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VMPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "CAM_ISP_MIPI_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VABB1_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "VUOTG_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "NFC_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VABB2_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "VHSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VHSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "CAM_ISP_SEN_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "VDDQ_PRE_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; - }; - - ldo22_reg: LDO22 { - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo23_reg: LDO23 { - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "LCD_VCC_3.3V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "MOTOR_VCC_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VMEM_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VMEM_VDDF_3.0V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - buck9_reg: BUCK9 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mshc_0 { - num-slots = <1>; - broken-cd; - non-removable; - card-detect-delay = <200>; - vmmc-supply = <&ldo22_reg>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <0>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; -}; - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; - - sleep0: sleep-states { - PIN_SLP(gpa0-0, INPUT, NONE); - PIN_SLP(gpa0-1, OUT0, NONE); - PIN_SLP(gpa0-2, INPUT, NONE); - PIN_SLP(gpa0-3, INPUT, UP); - PIN_SLP(gpa0-4, INPUT, NONE); - PIN_SLP(gpa0-5, INPUT, DOWN); - PIN_SLP(gpa0-6, INPUT, DOWN); - PIN_SLP(gpa0-7, INPUT, UP); - - PIN_SLP(gpa1-0, INPUT, DOWN); - PIN_SLP(gpa1-1, INPUT, DOWN); - PIN_SLP(gpa1-2, INPUT, DOWN); - PIN_SLP(gpa1-3, INPUT, DOWN); - PIN_SLP(gpa1-4, INPUT, DOWN); - PIN_SLP(gpa1-5, INPUT, DOWN); - - PIN_SLP(gpb-0, INPUT, NONE); - PIN_SLP(gpb-1, INPUT, NONE); - PIN_SLP(gpb-2, INPUT, NONE); - PIN_SLP(gpb-3, INPUT, NONE); - PIN_SLP(gpb-4, INPUT, DOWN); - PIN_SLP(gpb-5, INPUT, UP); - PIN_SLP(gpb-6, INPUT, DOWN); - PIN_SLP(gpb-7, INPUT, DOWN); - - PIN_SLP(gpc0-0, INPUT, DOWN); - PIN_SLP(gpc0-1, INPUT, DOWN); - PIN_SLP(gpc0-2, INPUT, DOWN); - PIN_SLP(gpc0-3, INPUT, DOWN); - PIN_SLP(gpc0-4, INPUT, DOWN); - - PIN_SLP(gpc1-0, INPUT, NONE); - PIN_SLP(gpc1-1, PREV, NONE); - PIN_SLP(gpc1-2, INPUT, NONE); - PIN_SLP(gpc1-3, INPUT, NONE); - PIN_SLP(gpc1-4, INPUT, NONE); - - PIN_SLP(gpd0-0, INPUT, DOWN); - PIN_SLP(gpd0-1, INPUT, DOWN); - PIN_SLP(gpd0-2, INPUT, NONE); - PIN_SLP(gpd0-3, INPUT, NONE); - - PIN_SLP(gpd1-0, INPUT, DOWN); - PIN_SLP(gpd1-1, INPUT, DOWN); - PIN_SLP(gpd1-2, INPUT, NONE); - PIN_SLP(gpd1-3, INPUT, NONE); - - PIN_SLP(gpf0-0, INPUT, NONE); - PIN_SLP(gpf0-1, INPUT, NONE); - PIN_SLP(gpf0-2, INPUT, DOWN); - PIN_SLP(gpf0-3, INPUT, DOWN); - PIN_SLP(gpf0-4, INPUT, NONE); - PIN_SLP(gpf0-5, INPUT, DOWN); - PIN_SLP(gpf0-6, INPUT, NONE); - PIN_SLP(gpf0-7, INPUT, DOWN); - - PIN_SLP(gpf1-0, INPUT, DOWN); - PIN_SLP(gpf1-1, INPUT, DOWN); - PIN_SLP(gpf1-2, INPUT, DOWN); - PIN_SLP(gpf1-3, INPUT, DOWN); - PIN_SLP(gpf1-4, INPUT, NONE); - PIN_SLP(gpf1-5, INPUT, NONE); - PIN_SLP(gpf1-6, INPUT, DOWN); - PIN_SLP(gpf1-7, PREV, NONE); - - PIN_SLP(gpf2-0, PREV, NONE); - PIN_SLP(gpf2-1, INPUT, DOWN); - PIN_SLP(gpf2-2, INPUT, DOWN); - PIN_SLP(gpf2-3, INPUT, DOWN); - PIN_SLP(gpf2-4, INPUT, DOWN); - PIN_SLP(gpf2-5, INPUT, DOWN); - PIN_SLP(gpf2-6, INPUT, NONE); - PIN_SLP(gpf2-7, INPUT, NONE); - - PIN_SLP(gpf3-0, INPUT, NONE); - PIN_SLP(gpf3-1, PREV, NONE); - PIN_SLP(gpf3-2, PREV, NONE); - PIN_SLP(gpf3-3, PREV, NONE); - PIN_SLP(gpf3-4, OUT1, NONE); - PIN_SLP(gpf3-5, INPUT, DOWN); - - PIN_SLP(gpj0-0, PREV, NONE); - PIN_SLP(gpj0-1, PREV, NONE); - PIN_SLP(gpj0-2, PREV, NONE); - PIN_SLP(gpj0-3, INPUT, DOWN); - PIN_SLP(gpj0-4, PREV, NONE); - PIN_SLP(gpj0-5, PREV, NONE); - PIN_SLP(gpj0-6, INPUT, DOWN); - PIN_SLP(gpj0-7, INPUT, DOWN); - - PIN_SLP(gpj1-0, INPUT, DOWN); - PIN_SLP(gpj1-1, PREV, NONE); - PIN_SLP(gpj1-2, PREV, NONE); - PIN_SLP(gpj1-3, INPUT, DOWN); - PIN_SLP(gpj1-4, INPUT, DOWN); - }; -}; - -&pinctrl_1 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep1>; - - sleep1: sleep-states { - PIN_SLP(gpk0-0, PREV, NONE); - PIN_SLP(gpk0-1, PREV, NONE); - PIN_SLP(gpk0-2, OUT0, NONE); - PIN_SLP(gpk0-3, PREV, NONE); - PIN_SLP(gpk0-4, PREV, NONE); - PIN_SLP(gpk0-5, PREV, NONE); - PIN_SLP(gpk0-6, PREV, NONE); - - PIN_SLP(gpk1-0, INPUT, DOWN); - PIN_SLP(gpk1-1, INPUT, DOWN); - PIN_SLP(gpk1-2, INPUT, DOWN); - PIN_SLP(gpk1-3, PREV, NONE); - PIN_SLP(gpk1-4, PREV, NONE); - PIN_SLP(gpk1-5, PREV, NONE); - PIN_SLP(gpk1-6, PREV, NONE); - - PIN_SLP(gpk2-0, INPUT, DOWN); - PIN_SLP(gpk2-1, INPUT, DOWN); - PIN_SLP(gpk2-2, INPUT, DOWN); - PIN_SLP(gpk2-3, INPUT, DOWN); - PIN_SLP(gpk2-4, INPUT, DOWN); - PIN_SLP(gpk2-5, INPUT, DOWN); - PIN_SLP(gpk2-6, INPUT, DOWN); - - PIN_SLP(gpk3-0, OUT0, NONE); - PIN_SLP(gpk3-1, INPUT, NONE); - PIN_SLP(gpk3-2, INPUT, DOWN); - PIN_SLP(gpk3-3, INPUT, NONE); - PIN_SLP(gpk3-4, INPUT, NONE); - PIN_SLP(gpk3-5, INPUT, NONE); - PIN_SLP(gpk3-6, INPUT, NONE); - - PIN_SLP(gpl0-0, INPUT, DOWN); - PIN_SLP(gpl0-1, INPUT, DOWN); - PIN_SLP(gpl0-2, INPUT, DOWN); - PIN_SLP(gpl0-3, INPUT, DOWN); - PIN_SLP(gpl0-4, PREV, NONE); - PIN_SLP(gpl0-6, PREV, NONE); - - PIN_SLP(gpl1-0, INPUT, DOWN); - PIN_SLP(gpl1-1, INPUT, DOWN); - PIN_SLP(gpl2-0, INPUT, DOWN); - PIN_SLP(gpl2-1, INPUT, DOWN); - PIN_SLP(gpl2-2, INPUT, DOWN); - PIN_SLP(gpl2-3, INPUT, DOWN); - PIN_SLP(gpl2-4, INPUT, DOWN); - PIN_SLP(gpl2-5, INPUT, DOWN); - PIN_SLP(gpl2-6, PREV, NONE); - PIN_SLP(gpl2-7, INPUT, DOWN); - - PIN_SLP(gpm0-0, INPUT, DOWN); - PIN_SLP(gpm0-1, INPUT, DOWN); - PIN_SLP(gpm0-2, INPUT, DOWN); - PIN_SLP(gpm0-3, INPUT, DOWN); - PIN_SLP(gpm0-4, INPUT, DOWN); - PIN_SLP(gpm0-5, INPUT, DOWN); - PIN_SLP(gpm0-6, INPUT, DOWN); - PIN_SLP(gpm0-7, INPUT, DOWN); - - PIN_SLP(gpm1-0, INPUT, DOWN); - PIN_SLP(gpm1-1, INPUT, DOWN); - PIN_SLP(gpm1-2, INPUT, NONE); - PIN_SLP(gpm1-3, INPUT, NONE); - PIN_SLP(gpm1-4, INPUT, NONE); - PIN_SLP(gpm1-5, INPUT, NONE); - PIN_SLP(gpm1-6, INPUT, DOWN); - - PIN_SLP(gpm2-0, INPUT, NONE); - PIN_SLP(gpm2-1, INPUT, NONE); - PIN_SLP(gpm2-2, INPUT, DOWN); - PIN_SLP(gpm2-3, INPUT, DOWN); - PIN_SLP(gpm2-4, INPUT, DOWN); - - PIN_SLP(gpm3-0, PREV, NONE); - PIN_SLP(gpm3-1, PREV, NONE); - PIN_SLP(gpm3-2, PREV, NONE); - PIN_SLP(gpm3-3, OUT1, NONE); - PIN_SLP(gpm3-4, INPUT, DOWN); - PIN_SLP(gpm3-5, INPUT, DOWN); - PIN_SLP(gpm3-6, INPUT, DOWN); - PIN_SLP(gpm3-7, INPUT, DOWN); - - PIN_SLP(gpm4-0, INPUT, DOWN); - PIN_SLP(gpm4-1, INPUT, DOWN); - PIN_SLP(gpm4-2, INPUT, DOWN); - PIN_SLP(gpm4-3, INPUT, DOWN); - PIN_SLP(gpm4-4, INPUT, DOWN); - PIN_SLP(gpm4-5, INPUT, DOWN); - PIN_SLP(gpm4-6, INPUT, DOWN); - PIN_SLP(gpm4-7, INPUT, DOWN); - - PIN_SLP(gpy0-0, INPUT, DOWN); - PIN_SLP(gpy0-1, INPUT, DOWN); - PIN_SLP(gpy0-2, INPUT, DOWN); - PIN_SLP(gpy0-3, INPUT, DOWN); - PIN_SLP(gpy0-4, INPUT, DOWN); - PIN_SLP(gpy0-5, INPUT, DOWN); - - PIN_SLP(gpy1-0, INPUT, DOWN); - PIN_SLP(gpy1-1, INPUT, DOWN); - PIN_SLP(gpy1-2, INPUT, DOWN); - PIN_SLP(gpy1-3, INPUT, DOWN); - - PIN_SLP(gpy2-0, PREV, NONE); - PIN_SLP(gpy2-1, INPUT, DOWN); - PIN_SLP(gpy2-2, INPUT, NONE); - PIN_SLP(gpy2-3, INPUT, NONE); - PIN_SLP(gpy2-4, INPUT, NONE); - PIN_SLP(gpy2-5, INPUT, NONE); - - PIN_SLP(gpy3-0, INPUT, DOWN); - PIN_SLP(gpy3-1, INPUT, DOWN); - PIN_SLP(gpy3-2, INPUT, DOWN); - PIN_SLP(gpy3-3, INPUT, DOWN); - PIN_SLP(gpy3-4, INPUT, DOWN); - PIN_SLP(gpy3-5, INPUT, DOWN); - PIN_SLP(gpy3-6, INPUT, DOWN); - PIN_SLP(gpy3-7, INPUT, DOWN); - - PIN_SLP(gpy4-0, INPUT, DOWN); - PIN_SLP(gpy4-1, INPUT, DOWN); - PIN_SLP(gpy4-2, INPUT, DOWN); - PIN_SLP(gpy4-3, INPUT, DOWN); - PIN_SLP(gpy4-4, INPUT, DOWN); - PIN_SLP(gpy4-5, INPUT, DOWN); - PIN_SLP(gpy4-6, INPUT, DOWN); - PIN_SLP(gpy4-7, INPUT, DOWN); - - PIN_SLP(gpy5-0, INPUT, DOWN); - PIN_SLP(gpy5-1, INPUT, DOWN); - PIN_SLP(gpy5-2, INPUT, DOWN); - PIN_SLP(gpy5-3, INPUT, DOWN); - PIN_SLP(gpy5-4, INPUT, DOWN); - PIN_SLP(gpy5-5, INPUT, DOWN); - PIN_SLP(gpy5-6, INPUT, DOWN); - PIN_SLP(gpy5-7, INPUT, DOWN); - - PIN_SLP(gpy6-0, INPUT, DOWN); - PIN_SLP(gpy6-1, INPUT, DOWN); - PIN_SLP(gpy6-2, INPUT, DOWN); - PIN_SLP(gpy6-3, INPUT, DOWN); - PIN_SLP(gpy6-4, INPUT, DOWN); - PIN_SLP(gpy6-5, INPUT, DOWN); - PIN_SLP(gpy6-6, INPUT, DOWN); - PIN_SLP(gpy6-7, INPUT, DOWN); - }; -}; - -&pinctrl_2 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep2>; - - sleep2: sleep-states { - PIN_SLP(gpz-0, INPUT, DOWN); - PIN_SLP(gpz-1, INPUT, DOWN); - PIN_SLP(gpz-2, INPUT, DOWN); - PIN_SLP(gpz-3, INPUT, DOWN); - PIN_SLP(gpz-4, INPUT, DOWN); - PIN_SLP(gpz-5, INPUT, DOWN); - PIN_SLP(gpz-6, INPUT, DOWN); - }; -}; - -&pinctrl_3 { - pinctrl-names = "default"; - pinctrl-0 = <&sleep3>; - - sleep3: sleep-states { - PIN_SLP(gpv0-0, INPUT, DOWN); - PIN_SLP(gpv0-1, INPUT, DOWN); - PIN_SLP(gpv0-2, INPUT, DOWN); - PIN_SLP(gpv0-3, INPUT, DOWN); - PIN_SLP(gpv0-4, INPUT, DOWN); - PIN_SLP(gpv0-5, INPUT, DOWN); - PIN_SLP(gpv0-6, INPUT, DOWN); - PIN_SLP(gpv0-7, INPUT, DOWN); - - PIN_SLP(gpv1-0, INPUT, DOWN); - PIN_SLP(gpv1-1, INPUT, DOWN); - PIN_SLP(gpv1-2, INPUT, DOWN); - PIN_SLP(gpv1-3, INPUT, DOWN); - PIN_SLP(gpv1-4, INPUT, DOWN); - PIN_SLP(gpv1-5, INPUT, DOWN); - PIN_SLP(gpv1-6, INPUT, DOWN); - PIN_SLP(gpv1-7, INPUT, DOWN); - - PIN_SLP(gpv2-0, INPUT, DOWN); - PIN_SLP(gpv2-1, INPUT, DOWN); - PIN_SLP(gpv2-2, INPUT, DOWN); - PIN_SLP(gpv2-3, INPUT, DOWN); - PIN_SLP(gpv2-4, INPUT, DOWN); - PIN_SLP(gpv2-5, INPUT, DOWN); - PIN_SLP(gpv2-6, INPUT, DOWN); - PIN_SLP(gpv2-7, INPUT, DOWN); - - PIN_SLP(gpv3-0, INPUT, DOWN); - PIN_SLP(gpv3-1, INPUT, DOWN); - PIN_SLP(gpv3-2, INPUT, DOWN); - PIN_SLP(gpv3-3, INPUT, DOWN); - PIN_SLP(gpv3-4, INPUT, DOWN); - PIN_SLP(gpv3-5, INPUT, DOWN); - PIN_SLP(gpv3-6, INPUT, DOWN); - PIN_SLP(gpv3-7, INPUT, DOWN); - - PIN_SLP(gpv4-0, INPUT, DOWN); - }; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sdhci_2 { - bus-width = <4>; - cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - status = "okay"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&spi_1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - - s5c73m3_spi: s5c73m3@0 { - compatible = "samsung,s5c73m3"; - spi-max-frequency = <50000000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <2>; - }; - }; -}; - -&tmu { - vtmu-supply = <&ldo10_reg>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4412.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4412.dtsi deleted file mode 100644 index 3ebdf01d8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4412.dtsi +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Samsung's Exynos4412 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "exynos4x12.dtsi" - -/ { - compatible = "samsung,exynos4412", "samsung,exynos4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@A00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA00>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; - cooling-min-level = <13>; - cooling-max-level = <7>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu@A01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA01>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@A02 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA02>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@A03 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xA03>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <200000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <925000>; - clock-latency-ns = <200000>; - }; - opp@500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - clock-latency-ns = <200000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - clock-latency-ns = <200000>; - }; - opp@700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <987500>; - clock-latency-ns = <200000>; - }; - opp@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <200000>; - opp-suspend; - }; - opp@900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <200000>; - }; - opp@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1087500>; - clock-latency-ns = <200000>; - }; - opp@1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <200000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1187500>; - clock-latency-ns = <200000>; - }; - opp@1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <200000>; - }; - opp@1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1287500>; - clock-latency-ns = <200000>; - }; - cpu0_opp_1500: opp@1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1350000>; - clock-latency-ns = <200000>; - turbo-mode; - }; - }; - - pmu { - interrupts = <2 2>, <3 2>, <18 2>, <19 2>; - }; -}; - -&pmu_system_controller { - compatible = "samsung,exynos4412-pmu", "syscon"; -}; - -&combiner { - samsung,combiner-nr = <20>; -}; - -&gic { - cpu-offset = <0x4000>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4415-pinctrl.dtsi deleted file mode 100644 index 76cfd872e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4415-pinctrl.dtsi +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, - <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, - <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpk0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4415.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4415.dtsi deleted file mode 100644 index 3c40f8a95..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4415.dtsi +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Samsung's Exynos4415 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 - * based board files can include this file and provide values for board - * specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - -/ { - compatible = "samsung,exynos4415"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - mshc0 = &mshc_0; - mshc1 = &mshc_1; - mshc2 = &mshc_2; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@a00 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa00>; - clock-frequency = <1600000000>; - }; - - cpu1: cpu@a01 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa01>; - clock-frequency = <1600000000>; - }; - - cpu2: cpu@a02 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa02>; - clock-frequency = <1600000000>; - }; - - cpu3: cpu@a03 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0xa03>; - clock-frequency = <1600000000>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x50000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x50000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@4f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x4f000 0x1000>; - }; - }; - - pinctrl_2: pinctrl@03860000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 242 0>; - }; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sysreg_system_controller: syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4415-pmu", "syscon"; - reg = <0x10020000 0x4000>; - }; - - mipi_phy: video-phy@10020710 { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - - pd_cam: cam-power-domain@10024000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024000 0x20>; - #power-domain-cells = <0>; - }; - - pd_tv: tv-power-domain@10024020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024020 0x20>; - #power-domain-cells = <0>; - }; - - pd_mfc: mfc-power-domain@10024040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024040 0x20>; - #power-domain-cells = <0>; - }; - - pd_g3d: g3d-power-domain@10024060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024060 0x20>; - #power-domain-cells = <0>; - }; - - pd_lcd0: lcd0-power-domain@10024080 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10024080 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp0: isp0-power-domain@100240A0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100240A0 0x20>; - #power-domain-cells = <0>; - }; - - pd_isp1: isp1-power-domain@100240E0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100240E0 0x20>; - #power-domain-cells = <0>; - }; - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos4415-cmu"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = <0 73 0>, <0 74 0>; - status = "disabled"; - }; - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, - <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; - clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - cmu_dmc: clock-controller@105C0000 { - compatible = "samsung,exynos4415-cmu-dmc"; - reg = <0x105C0000 0x3000>; - #clock-cells = <1>; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 225 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 48 0>; - }; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4415-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 240 0>; - }; - - fimd: fimd@11C00000 { - compatible = "samsung,exynos4415-fimd"; - reg = <0x11C00000 0x30000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0 84 0>, <0 85 0>, <0 86 0>; - clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; - clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; - iommus = <&sysmmu_fimd0>; - samsung,sysreg = <&sysreg_system_controller>; - status = "disabled"; - }; - - dsi_0: dsi@11C80000 { - compatible = "samsung,exynos4415-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = <0 83 0>; - samsung,phy-type = <0>; - samsung,power-domain = <&pd_lcd0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sysmmu_fimd0: sysmmu@11E20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11e20000 0x1000>; - interrupts = <0 80 0>, <0 81 0>; - clock-names = "sysmmu", "master"; - clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; - power-domains = <&pd_lcd0>; - #iommu-cells = <0>; - }; - - hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = <0 141 0>; - clocks = <&cmu CLK_USBDEVICE>; - clock-names = "otg"; - phys = <&exynos_usbphy 0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - mshc_0: mshc@12510000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12510000 0x1000>; - interrupts = <0 142 0>; - clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_1: mshc@12520000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12520000 0x1000>; - interrupts = <0 143 0>; - clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mshc_2: mshc@12530000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12530000 0x1000>; - interrupts = <0 144 0>; - clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ehci: ehci@12580000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12580000 0x100>; - interrupts = <0 140 0>; - clocks = <&cmu CLK_USBHOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - port@1 { - reg = <1>; - phys = <&exynos_usbphy 2>; - status = "disabled"; - }; - port@2 { - reg = <2>; - phys = <&exynos_usbphy 3>; - status = "disabled"; - }; - }; - - ohci: ohci@12590000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12590000 0x100>; - interrupts = <0 140 0>; - clocks = <&cmu CLK_USBHOST>; - clock-names = "usbhost"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&exynos_usbphy 1>; - status = "disabled"; - }; - }; - - exynos_usbphy: exynos-usbphy@125B0000 { - compatible = "samsung,exynos4x12-usb2-phy"; - reg = <0x125B0000 0x100>; - samsung,pmureg-phandle = <&pmu_system_controller>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <0 138 0>; - clocks = <&cmu CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <0 139 0>; - clocks = <&cmu CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - adc: adc@126C0000 { - compatible = "samsung,exynos3250-adc", - "samsung,exynos-adc-v2"; - reg = <0x126C0000 0x100>, <0x10020718 0x4>; - interrupts = <0 137 0>; - clock-names = "adc", "sclk"; - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - serial_0: serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 109 0>; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_1: serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = <0 110 0>; - clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_2: serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 111 0>; - clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_3: serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = <0 112 0>; - clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - i2c_0: i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = <0 113 0>; - clocks = <&cmu CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@13870000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = <0 114 0>; - clocks = <&cmu CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@13880000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = <0 115 0>; - clocks = <&cmu CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@13890000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = <0 116 0>; - clocks = <&cmu CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - i2c_4: i2c@138A0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = <0 117 0>; - clocks = <&cmu CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@138B0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = <0 118 0>; - clocks = <&cmu CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@138C0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = <0 119 0>; - clocks = <&cmu CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@138D0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = <0 120 0>; - clocks = <&cmu CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = <0 121 0>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - status = "disabled"; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = <0 122 0>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - status = "disabled"; - }; - - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = <0 123 0>; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - status = "disabled"; - }; - - clock_audss: clock-controller@03810000 { - compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - }; - - i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - interrupts = <0 124 0>; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0"; - dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; - dma-names = "tx", "rx", "tx-sec"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - samsung,idma-addr = <0x03000000>; - status = "disabled"; - }; - - pwm: pwm@139D0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 108 0>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; - }; - }; -}; - -#include "exynos4415-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi deleted file mode 100644 index a56bf9b1a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ - } - -/ { - pinctrl_0: pinctrl@11400000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_a: uart-audio-a { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio_b: uart-audio-b { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi0_clk: mipi0-clk { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - mipi1_clk: mipi1-clk { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", - "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", - "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", - "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", - "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ldi: lcd-ldi { - samsung,pins = "gpf3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_1: pinctrl@11000000 { - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl1: gpl1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpl2: gpl2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm0: gpm0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm1: gpm1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm2: gpm2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm3: gpm3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm4: gpm4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_clk: sd4-clk { - samsung,pins = "gpk0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cmd: sd4-cmd { - samsung,pins = "gpk0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_cd: sd4-cd { - samsung,pins = "gpk0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus1: sd4-bus-width1 { - samsung,pins = "gpk0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus4: sd4-bus-width4 { - samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpk1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpk1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpk1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpk1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpk2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpk2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpk2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpk2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpk3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpk3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpk3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpk3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", - "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpm2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gpx2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c0: fimc-is-i2c0 { - samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_i2c1: fimc-is-i2c1 { - samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_cec: hdmi-cec { - samsung,pins = "gpx3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_2: pinctrl@03860000 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - - pinctrl_3: pinctrl@106E0000 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_bus: c2c-bus { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7", - "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", - "gpv4-0", "gpv4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos4x12.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos4x12.dtsi deleted file mode 100644 index 3394bdcf1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos4x12.dtsi +++ /dev/null @@ -1,578 +0,0 @@ -/* - * Samsung's Exynos4x12 SoCs device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "exynos4.dtsi" -#include "exynos4x12-pinctrl.dtsi" -#include "exynos4-cpu-thermal.dtsi" - -/ { - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - fimc-lite0 = &fimc_lite_0; - fimc-lite1 = &fimc_lite_1; - mshc0 = &mshc_0; - }; - - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_isp: isp-power-domain@10023CA0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; - #power-domain-cells = <0>; - }; - - l2c: l2-cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &gic 0 57 0>, - <1 &combiner 12 5>, - <2 &combiner 12 6>, - <3 &combiner 12 7>, - <4 &gic 1 12 0>; - }; - }; - - adc: adc@126C0000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x126C0000 0x100>; - interrupt-parent = <&combiner>; - interrupts = <10 3>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - g2d: g2d@10800000 { - compatible = "samsung,exynos4212-g2d"; - reg = <0x10800000 0x1000>; - interrupts = <0 89 0>; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - - camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - - /* fimc_[0-3] are configured outside, under phandles */ - fimc_lite_0: fimc-lite@12390000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x12390000 0x1000>; - interrupts = <0 105 0>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite0>; - status = "disabled"; - }; - - fimc_lite_1: fimc-lite@123A0000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123A0000 0x1000>; - interrupts = <0 106 0>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE1>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite1>; - status = "disabled"; - }; - - fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is", "simple-bus"; - reg = <0x12000000 0x260000>; - interrupts = <0 90 0>, <0 95 0>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>, - <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, - <&clock CLK_PPMUISPMX>, - <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, - <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, - <&clock CLK_PWM_ISP>, - <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, - <&clock CLK_DIV_MCUISP0>, - <&clock CLK_DIV_MCUISP1>, - <&clock CLK_UART_ISP_SCLK>, - <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, - <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK400_MCUISP>; - clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "mpll", "isp", - "drc", "fd", "mcuisp", - "gicisp", "mcuctl_isp", "pwm_isp", - "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "uart", "aclk200", - "div_aclk200", "aclk400mcuisp", - "div_aclk400mcuisp"; - iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, - <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; - iommu-names = "isp", "drc", "fd", "mcuctl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - pmu@10020000 { - reg = <0x10020000 0x3000>; - }; - - i2c1_isp: i2c-isp@12140000 { - compatible = "samsung,exynos4212-i2c-isp"; - reg = <0x12140000 0x100>; - clocks = <&clock CLK_I2C1_ISP>; - clock-names = "i2c_isp"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - mshc_0: mmc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - fifo-depth = <0x80>; - clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10A40000{ - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@12260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 2>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@12270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 3>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@122A0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122A0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 4>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@122B0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 5>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISPCX>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@123B0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@123C0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 1>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; - #iommu-cells = <0>; - }; - - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_acp: bus_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_c2c: bus_c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; - }; - opp@267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - }; - }; - - bus_acp_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp@267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_display: bus_display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - }; - }; - - bus_display_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_fsys_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp@134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_peri_opp_table: opp_table6 { - compatible = "operating-points-v2"; - opp-shared; - - opp@50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; -}; - -&combiner { - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; -}; - -&exynos_usbphy { - compatible = "samsung,exynos4x12-usb2-phy"; - samsung,sysreg-phandle = <&sys_reg>; -}; - -&fimc_0 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_1 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_2 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; - samsung,cam-if; -}; - -&fimc_3 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; -}; - -&hdmi { - compatible = "samsung,exynos4212-hdmi"; -}; - -&jpeg_codec { - compatible = "samsung,exynos4212-jpeg"; -}; - -&rotator { - compatible = "samsung,exynos4212-rotator"; -}; - -&mixer { - compatible = "samsung,exynos4212-mixer"; - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; -}; - -&pinctrl_0 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; -}; - -&pinctrl_1 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 46 0>; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; -}; - -&pinctrl_2 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x03860000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 0>; -}; - -&pinctrl_3 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106E0000 0x1000>; - interrupts = <0 72 0>; -}; - -&pmu_system_controller { - compatible = "samsung,exynos4212-pmu", "syscon"; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; -}; - -&tmu { - compatible = "samsung,exynos4412-tmu"; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - reg = <0x100C0000 0x100>; - clocks = <&clock 383>; - clock-names = "tmu_apbif"; - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5.dtsi deleted file mode 100644 index 8f0660987..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Samsung's Exynos5 SoC series common device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular - * SoCs from Exynos5 series can include this file and provide values for SoCs - * specfic bindings. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "exynos-syscon-restart.dtsi" - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - serial3 = &serial_3; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - sromc: memory-controller@12250000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12250000 0x14>; - }; - - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - samsung,combiner-nr = <32>; - reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - sysreg_system_controller: syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; - - serial_0: serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - }; - - serial_1: serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; - }; - - serial_2: serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; - }; - - serial_3: serial@12C30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; - }; - - i2c_0: i2c@12C60000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_1: i2c@12C70000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_2: i2c@12C80000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - i2c_3: i2c@12C90000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - status = "disabled"; - }; - - pwm: pwm@12DD0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x12DD0000 0x100>; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - }; - - rtc: rtc@101E0000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x101E0000 0x100>; - interrupts = <0 43 0>, <0 44 0>; - status = "disabled"; - }; - - fimd: fimd@14400000 { - compatible = "samsung,exynos5250-fimd"; - interrupt-parent = <&combiner>; - reg = <0x14400000 0x40000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <18 4>, <18 5>, <18 6>; - samsung,sysreg = <&sysreg_system_controller>; - status = "disabled"; - }; - - dp: dp-controller@145B0000 { - compatible = "samsung,exynos5-dp"; - reg = <0x145B0000 0x1000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5250-arndale.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5250-arndale.dts deleted file mode 100644 index 6098dacd0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5250-arndale.dts +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Samsung's Exynos5250 based Arndale board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include -#include -#include "exynos5250.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Insignal Arndale evaluation board based on EXYNOS5250"; - compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttySAC2,115200"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - menu { - label = "SW-TACT2"; - gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - home { - label = "SW-TACT3"; - gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - up { - label = "SW-TACT4"; - gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - down { - label = "SW-TACT5"; - gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - back { - label = "SW-TACT6"; - gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - wakeup { - label = "SW-TACT7"; - gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - main_dc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "MAIN_DC"; - }; - - mmc_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_LOW>; - enable-active-high; - }; - - reg_hdmi_en: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdmi-en"; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; - - // SMSC USB3503 connected in hardware only mode as a PHY - usb_hub: usb-hub { - compatible = "smsc,usb3503a"; - - reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - status = "okay"; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing { - /* 2560x1600 DP panel */ - clock-frequency = <50000>; - hactive = <2560>; - vactive = <1600>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - vback-porch = <16>; - vfront-porch = <8>; - vsync-len = <6>; - }; - }; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_LOW>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - samsung,i2c-slave-addr = <0x66>; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - vinb1-supply = <&main_dc_reg>; - vinb2-supply = <&main_dc_reg>; - vinb3-supply = <&main_dc_reg>; - vinb4-supply = <&main_dc_reg>; - vinb5-supply = <&main_dc_reg>; - vinb6-supply = <&main_dc_reg>; - vinb7-supply = <&main_dc_reg>; - vinb8-supply = <&main_dc_reg>; - vinb9-supply = <&main_dc_reg>; - - vinl1-supply = <&buck7_reg>; - vinl2-supply = <&buck7_reg>; - vinl3-supply = <&buck7_reg>; - vinl4-supply = <&main_dc_reg>; - vinl5-supply = <&main_dc_reg>; - vinl6-supply = <&main_dc_reg>; - vinl7-supply = <&main_dc_reg>; - vinl8-supply = <&buck8_reg>; - vinl9-supply = <&buck8_reg>; - - s5m8767,pmic-buck2-dvs-voltage = <1300000>; - s5m8767,pmic-buck3-dvs-voltage = <1100000>; - s5m8767,pmic-buck4-dvs-voltage = <1200000>; - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, - <&gpd1 1 GPIO_ACTIVE_HIGH>, - <&gpd1 2 GPIO_ACTIVE_HIGH>; - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, - <&gpx2 4 GPIO_ACTIVE_HIGH>, - <&gpx2 5 GPIO_ACTIVE_HIGH>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_28IO_DP_1.35V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD_COMMON1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_IOPERI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD_MPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_XPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD_COMMON2_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD_33ON_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_COMMON3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_ABB2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_COMMON4_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDQ_MMC2_3_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo18_reg: LDO18 { - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo22_reg: LDO22 { - regulator-name = "EXT_33_OFF"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; - }; - - ldo23_reg: LDO23 { - regulator-name = "EXT_28_OFF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo25_reg: LDO25 { - regulator-name = "PVDD_LDO25"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - op_mode = <1>; - }; - - ldo26_reg: LDO26 { - regulator-name = "EXT_18_OFF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_MEM_1.35V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1355000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck7_reg: BUCK7 { - regulator-name = "PVDD_BUCK7"; - regulator-always-on; - op_mode = <1>; - }; - - buck8_reg: BUCK8 { - regulator-name = "PVDD_BUCK8"; - regulator-always-on; - op_mode = <1>; - }; - - buck9_reg: BUCK9 { - regulator-name = "VDD_33_OFF_EXT1"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - }; - }; -}; - -&i2c_2 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; -}; - -&i2c_3 { - status = "okay"; - - wm1811a@1a { - compatible = "wlf,wm1811"; - reg = <0x1a>; - - AVDD2-supply = <&main_dc_reg>; - CPVDD-supply = <&main_dc_reg>; - DBVDD1-supply = <&main_dc_reg>; - DBVDD2-supply = <&main_dc_reg>; - DBVDD3-supply = <&main_dc_reg>; - LDO1VDD-supply = <&main_dc_reg>; - SPKVDD1-supply = <&main_dc_reg>; - SPKVDD2-supply = <&main_dc_reg>; - - wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>; - wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c_8 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x38>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; -}; - -&i2c_9 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - - sata_phy_i2c:sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sata_phy { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5250-pinctrl.dtsi deleted file mode 100644 index 2f6ab32b5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ /dev/null @@ -1,818 +0,0 @@ -/* - * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_hs_bus: i2c2-hs-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_hs_bus: i2c3-hs-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_hs_bus: i2c0-hs-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_hs_bus: i2c1-hs-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpc4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpc4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpc4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpc4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd: dp_hpd { - samsung,pins = "gpx0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c2_bus: cam-i2c2-bus { - samsung,pins = "gpe0-6", "gpe1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_bayrgb_bus: cam-bayrgb-bus { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0", "gpg2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a: cam-port-a { - samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", - "gph1-0", "gph1-1", "gph1-2", "gph1-3", - "gph1-4", "gph1-5", "gph1-6", "gph1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_rxd: c2c-rxd { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - c2c_txd: c2c-txd { - samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5250-smdk5250.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5250-smdk5250.dts deleted file mode 100644 index a97a785cc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ /dev/null @@ -1,424 +0,0 @@ -/* - * SAMSUNG SMDK5250 board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include -#include "exynos5250.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; - compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5"; - - aliases { - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; - }; - - vdd: fixed-regulator-vdd { - compatible = "regulator-fixed"; - regulator-name = "vdd-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - dbvdd: fixed-regulator-dbvdd { - compatible = "regulator-fixed"; - regulator-name = "dbvdd-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - spkvdd: fixed-regulator-spkvdd { - compatible = "regulator-fixed"; - regulator-name = "spkvdd-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound { - compatible = "samsung,smdk-wm8994"; - - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&wm8994>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - - codec_mclk: codec-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16934000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - - timing0: timing { - /* 1280x800 */ - clock-frequency = <50000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <4>; - hback-porch = <4>; - hsync-len = <4>; - vback-porch = <4>; - vfront-porch = <4>; - vsync-len = <4>; - }; - }; -}; - -&ehci { - samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - - eeprom@50 { - compatible = "samsung,s524ad0xd1"; - reg = <0x50>; - }; - - max77686@09 { - compatible = "maxim,max77686"; - reg = <0x09>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.2V_LDO_OUT2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "P2.8V_LDO_OUT4"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "P1.8V_LDO_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "P1.1V_LDO_OUT6"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "P1.8V_LDO_OUT11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "P1.8V_LDO_OUT13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - - eeprom@51 { - compatible = "samsung,s524ad0xd1"; - reg = <0x51>; - }; - - wm8994: wm8994@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; - - clocks = <&codec_mclk>; - clock-names = "MCLK1"; - - AVDD2-supply = <&vdd>; - CPVDD-supply = <&vdd>; - DBVDD-supply = <&dbvdd>; - SPKVDD1-supply = <&spkvdd>; - SPKVDD2-supply = <&spkvdd>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; -}; - -&i2c_8 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; -}; - -&i2c_9 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - - sata_phy_i2c: sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sata_phy { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; -}; - -&spi_1 { - status = "okay"; - cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; - - w25q80bw@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25x80"; - reg = <0>; - spi-max-frequency = <1000000>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; - }; - }; -}; - -&pinctrl_0 { - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow-common.dtsi deleted file mode 100644 index d5d51916b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ /dev/null @@ -1,688 +0,0 @@ -/* - * Google Snow board device tree source - * - * Copyright (c) 2012 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - aliases { - i2c104 = &i2c_104; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=tty1"; - stdout-path = "serial3:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - vbat: vbat-fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - }; - - i2c-arbitrator { - compatible = "i2c-arb-gpio-challenge"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c_4>; - - our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; - their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; - slew-delay-us = <10>; - wait-retry-us = <3000>; - wait-free-us = <50000>; - - pinctrl-names = "default"; - pinctrl-0 = <&arb_our_claim &arb_their_claim>; - - /* Use ID 104 as a hint that we're on physical bus 4 */ - i2c_104: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - }; - - cros_ec: embedded-controller@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_irq>; - wakeup-source; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&vbat>; - infet3-supply = <&vbat>; - infet4-supply = <&vbat>; - infet5-supply = <&vbat>; - infet6-supply = <&vbat>; - infet7-supply = <&vbat>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - dcdc1 { - ti,enable-ext-control; - }; - dcdc2 { - ti,enable-ext-control; - }; - dcdc3 { - ti,enable-ext-control; - }; - fet1: fet1 { - regulator-name = "vcd_led"; - ti,overcurrent-wait = <3>; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet4 { - regulator-name = "sdcard"; - ti,overcurrent-wait = <3>; - }; - fet5 { - regulator-name = "camout"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet6: fet6 { - regulator-name = "lcd_vdd"; - ti,overcurrent-wait = <3>; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - ldo1 { - }; - ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; - - sound { - samsung,i2s-controller = <&i2s0>; - }; - - usb3_vbus_reg: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_en>; - enable-active-high; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; - power-supply = <&fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ - <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77686 MAX77686_CLK_PMIC>; - clock-names = "ext_clock"; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&ehci { - samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; - ddc = <&i2c_2>; - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - max77686: max77686@09 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.8V_LDO_OUT2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.35V_BUCK_OUT6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "P2.0V_BUCK_OUT7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "P2.85V_BUCK_OUT8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - trackpad@67 { - reg = <0x67>; - compatible = "cypress,cyapa"; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - wakeup-source; - }; -}; - -/* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ -&i2c2_bus { - samsung,pin-pud = ; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; -}; - -&i2c_3 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_4 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_5 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_7 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - ptn3460: lvds-bridge@20 { - compatible = "nxp,ptn3460"; - reg = <0x20>; - powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; - edid-emulation = <5>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - }; -}; - -&i2c_8 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - non-removable; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; - cap-sd-highspeed; -}; - -/* - * On Snow we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - */ -&mmc_3 { - status = "okay"; - num-slots = <1>; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4 &wifi_en &wifi_rst>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc3_pwrseq>; -}; - -&pinctrl_0 { - wifi_en: wifi-en { - samsung,pins = "gpx0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - wifi_rst: wifi-rst { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_vbus_en: usb3-vbus-en { - samsung,pins = "gpx2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - arb_their_claim: arb-their-claim { - samsung,pins = "gpe0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - arb_our_claim: arb-our-claim { - samsung,pins = "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sd3_bus4 { - samsung,pin-drv = ; -}; - -&sd3_clk { - samsung,pin-drv = ; -}; - -&sd3_cmd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - -&spi_1 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; - cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; -}; - -&usbdrd_dwc3 { - dr_mode = "host"; -}; - -&usbdrd_phy { - vbus-supply = <&usb3_vbus_reg>; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow-rev5.dts deleted file mode 100644 index 90560c316..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Google Snow Rev 5+ board device tree source - * - * Copyright (c) 2012 Google, Inc - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "exynos5250-snow-common.dtsi" - -/ { - model = "Google Snow Rev 5+"; - compatible = "google,snow-rev5", "samsung,exynos5250", - "samsung,exynos5"; - - sound { - compatible = "google,snow-audio-max98090"; - - samsung,model = "Snow-I2S-MAX98090"; - samsung,audio-codec = <&max98090>; - }; -}; - -&i2c_7 { - max98090: codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupts = <4 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98090_irq>; - }; -}; - -&pinctrl_0 { - max98090_irq: max98090-irq { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow.dts deleted file mode 100644 index df48f2cc9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5250-snow.dts +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Google Snow board device tree source - * - * Copyright (c) 2012 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "exynos5250-snow-common.dtsi" - -/ { - model = "Google Snow"; - compatible = "google,snow-rev4", "google,snow", "samsung,exynos5250", - "samsung,exynos5"; - - sound { - compatible = "google,snow-audio-max98095"; - - samsung,model = "Snow-I2S-MAX98095"; - samsung,audio-codec = <&max98095>; - }; -}; - -&i2c_7 { - max98095: codec@11 { - compatible = "maxim,max98095"; - reg = <0x11>; - pinctrl-names = "default"; - pinctrl-0 = <&max98095_en>; - }; -}; - -&pinctrl_0 { - max98095_en: max98095-en { - samsung,pins = "gpx1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5250-spring.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5250-spring.dts deleted file mode 100644 index 4d7bdb735..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5250-spring.dts +++ /dev/null @@ -1,558 +0,0 @@ -/* - * Google Spring board device tree source - * - * Copyright (c) 2013 Google, Inc - * Copyright (c) 2014 SUSE LINUX Products GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include -#include -#include "exynos5250.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Google Spring"; - compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=tty1"; - stdout-path = "serial3:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq>, <&lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - usb-hub { - compatible = "smsc,usb3503a"; - reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hsic_reset>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; -}; - -&cpu0 { - cpu0-supply = <&buck2_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <1>; - hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>; -}; - -&ehci { - samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; - ddc = <&i2c_2>; - hdmi-en-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - s5m8767-pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; - wakeup-source; - - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ - <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ - <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ - - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ - <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ - <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ - - /* - * The following arrays of DVS voltages are not used, since we are - * not using GPIOs to control PMIC bucks, but they must be defined - * to please the driver. - */ - s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - clocks { - compatible = "samsung,s5m8767-clk"; - #clock-cells = <1>; - clock-output-names = "en32khz_ap", - "en32khz_cp", - "en32khz_bt"; - }; - - regulators { - ldo4_reg: LDO4 { - regulator-name = "P1.0V_LDO_OUT4"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo5_reg: LDO5 { - regulator-name = "P1.0V_LDO_OUT5"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_mydp"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo11_reg: LDO11 { - regulator-name = "P1.8V_LDO_OUT11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo13_reg: LDO13 { - regulator-name = "P1.8V_LDO_OUT13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <3>; - }; - - ldo17_reg: LDO17 { - regulator-name = "P2.8V_LDO_OUT17"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <0>; - }; - - ldo25_reg: LDO25 { - regulator-name = "vdd_bridge"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - op_mode = <3>; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.2V_BUCK_OUT6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <0>; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_ummc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <3>; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; - wakeup-source; - }; -}; - -/* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ -&i2c2_bus { - samsung,pin-pud = ; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; -}; - -&i2c_3 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_4 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - cros_ec: embedded-controller@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&ec_irq>; - }; -}; - -&i2c_5 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_7 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - temperature-sensor@4c { - compatible = "gmt,g781"; - reg = <0x4c>; - }; -}; - -&i2c_8 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -/* - * On Spring we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - */ -&mmc_1 { - status = "okay"; - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - s5m8767_dvs: s5m8767-dvs { - samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp-hpd-gpio { - samsung,pins = "gpc3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - s5m8767_ds: s5m8767-ds { - samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - s5m8767_irq: s5m8767-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - hsic_reset: hsic-reset { - samsung,pins = "gpe1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sd1_bus4 { - samsung,pin-drv = ; -}; - -&sd1_cd { - samsung,pin-drv = ; -}; - -&sd1_clk { - samsung,pin-drv = ; -}; - -&sd1_cmd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - -&spi_1 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5250.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5250.dtsi deleted file mode 100644 index f7357d99b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5250.dtsi +++ /dev/null @@ -1,1063 +0,0 @@ -/* - * SAMSUNG EXYNOS5250 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. - * EXYNOS5250 based board files can include this file and provide - * values for board specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, - * additional nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include "exynos5.dtsi" -#include "exynos4-cpu-thermal.dtsi" -#include - -/ { - compatible = "samsung,exynos5250", "samsung,exynos5"; - - aliases { - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - gsc0 = &gsc_0; - gsc1 = &gsc_1; - gsc2 = &gsc_2; - gsc3 = &gsc_3; - mshc0 = &mmc_0; - mshc1 = &mmc_1; - mshc2 = &mmc_2; - mshc3 = &mmc_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - i2c8 = &i2c_8; - i2c9 = &i2c_9; - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1700000000>; - clocks = <&clock CLK_ARM_CLK>; - clock-names = "cpu"; - clock-latency = <140000>; - - operating-points = < - 1700000 1300000 - 1600000 1250000 - 1500000 1225000 - 1400000 1200000 - 1300000 1150000 - 1200000 1125000 - 1100000 1100000 - 1000000 1075000 - 900000 1050000 - 800000 1025000 - 700000 1012500 - 600000 1000000 - 500000 975000 - 400000 950000 - 300000 937500 - 200000 925000 - >; - cooling-min-level = <15>; - cooling-max-level = <9>; - #cooling-cells = <2>; /* min followed by max */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1700000000>; - }; - }; - - soc: soc { - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x30000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x30000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_gsc: gsc-power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - }; - - pd_mfc: mfc-power-domain@10044040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044040 0x20>; - #power-domain-cells = <0>; - }; - - pd_disp1: disp1-power-domain@100440A0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440A0 0x20>; - #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_ACLK200_DISP1_SUB>, - <&clock CLK_MOUT_ACLK300_DISP1_SUB>; - clock-names = "oscclk", "clk0", "clk1"; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5250-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, - <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - /* - * Unfortunately we need this since some versions - * of U-Boot on Exynos don't set the CNTFRQ register, - * so we need the value from DT. - */ - clock-frequency = <24000000>; - }; - - mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &combiner 23 3>, - <0x1 0 &combiner 23 4>, - <0x2 0 &combiner 25 2>, - <0x3 0 &combiner 25 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; - }; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, <22 4>; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 46 0>; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - - pinctrl_1: pinctrl@13400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; - }; - - pinctrl_2: pinctrl@10d10000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; - }; - - pinctrl_3: pinctrl@03860000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; - }; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - watchdog@101D0000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - g2d@10850000 { - compatible = "samsung,exynos5250-g2d"; - reg = <0x10850000 0x1000>; - interrupts = <0 91 0>; - clocks = <&clock CLK_G2D>; - clock-names = "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - - mfc: codec@11000000 { - compatible = "samsung,mfc-v6"; - reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; - power-domains = <&pd_mfc>; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - rotator: rotator@11C00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - tmu: tmu@10060000 { - compatible = "samsung,exynos5250-tmu"; - reg = <0x10060000 0x100>; - interrupts = <0 65 0>; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - sata: sata@122F0000 { - compatible = "snps,dwc-ahci"; - samsung,sata-freq = <66>; - reg = <0x122F0000 0x1ff>; - interrupts = <0 115 0>; - clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; - clock-names = "sata", "sclk_sata"; - phys = <&sata_phy>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - sata_phy: sata-phy@12170000 { - compatible = "samsung,exynos5250-sata-phy"; - reg = <0x12170000 0x1ff>; - clocks = <&clock CLK_SATA_PHYCTRL>; - clock-names = "sata_phyctrl"; - #phy-cells = <0>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - /* i2c_0-3 are defined in exynos5.dtsi */ - i2c_4: i2c@12CA0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CA0000 0x100>; - interrupts = <0 60 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C4>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; - status = "disabled"; - }; - - i2c_5: i2c@12CB0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CB0000 0x100>; - interrupts = <0 61 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C5>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; - status = "disabled"; - }; - - i2c_6: i2c@12CC0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CC0000 0x100>; - interrupts = <0 62 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C6>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; - status = "disabled"; - }; - - i2c_7: i2c@12CD0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12CD0000 0x100>; - interrupts = <0 63 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C7>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; - status = "disabled"; - }; - - i2c_8: i2c@12CE0000 { - compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x12CE0000 0x1000>; - interrupts = <0 64 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_I2C_HDMI>; - clock-names = "i2c"; - status = "disabled"; - }; - - i2c_9: i2c@121D0000 { - compatible = "samsung,exynos5-sata-phy-i2c"; - reg = <0x121D0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SATA_PHYI2C>; - clock-names = "i2c"; - status = "disabled"; - }; - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d20000 0x100>; - interrupts = <0 66 0>; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - }; - - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d30000 0x100>; - interrupts = <0 67 0>; - dmas = <&pdma1 5 - &pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - }; - - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - status = "disabled"; - reg = <0x12d40000 0x100>; - interrupts = <0 68 0>; - dmas = <&pdma0 7 - &pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x1000>; - clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x1000>; - clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_3: mmc@12230000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12230000 0x1000>; - interrupts = <0 78 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - i2s0: i2s@03830000 { - compatible = "samsung,s5pv210-i2s"; - status = "disabled"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10 - &pdma0 9 - &pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - }; - - i2s1: i2s@12D60000 { - compatible = "samsung,s3c6410-i2s"; - status = "disabled"; - reg = <0x12D60000 0x100>; - dmas = <&pdma1 12 - &pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; - clock-names = "iis", "i2s_opclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - }; - - i2s2: i2s@12D70000 { - compatible = "samsung,s3c6410-i2s"; - status = "disabled"; - reg = <0x12D70000 0x100>; - dmas = <&pdma0 12 - &pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; - clock-names = "iis", "i2s_opclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - }; - - usb_dwc3 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock CLK_USB3>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3: dwc3@12000000 { - compatible = "synopsys,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy: phy@12100000 { - compatible = "samsung,exynos5250-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - ehci: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock CLK_USB2>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy_gen 1>; - }; - }; - - ohci: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock CLK_USB2>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy_gen 1>; - }; - }; - - usb2_phy_gen: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@121A0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121B0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - mdma1: mdma@11C10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - }; - - gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - iommu = <&sysmmu_gsc0>; - }; - - gsc_1: gsc@13e10000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - iommu = <&sysmmu_gsc1>; - }; - - gsc_2: gsc@13e20000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e20000 0x1000>; - interrupts = <0 87 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL2>; - clock-names = "gscl"; - iommu = <&sysmmu_gsc2>; - }; - - gsc_3: gsc@13e30000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e30000 0x1000>; - interrupts = <0 88 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL3>; - clock-names = "gscl"; - iommu = <&sysmmu_gsc3>; - }; - - hdmi: hdmi@14530000 { - compatible = "samsung,exynos4212-hdmi"; - reg = <0x14530000 0x70000>; - power-domains = <&pd_disp1>; - interrupts = <0 95 0>; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - mixer@14450000 { - compatible = "samsung,exynos5250-mixer"; - reg = <0x14450000 0x10000>; - power-domains = <&pd_disp1>; - interrupts = <0 94 0>; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - iommus = <&sysmmu_tv>; - }; - - dp_phy: video-phy { - compatible = "samsung,exynos5250-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; - - adc: adc@12D10000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; - clocks = <&clock CLK_ADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <0 112 0>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; - - sysmmu_g2d: sysmmu@10A60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - power-domains = <&pd_mfc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_l: sysmmu@11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - power-domains = <&pd_mfc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@11D40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg: sysmmu@11F20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@13260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@13270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <11 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@132A0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132A0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 0>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_scc: sysmmu@13280000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13280000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 2>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_SCC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_scp: sysmmu@13290000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13290000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_SCP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@132B0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132B0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_MCU>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_odc: sysmmu@132C0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <11 0>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_ODC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_dis0: sysmmu@132D0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132D0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DIS0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_dis1: sysmmu@132E0000{ - compatible = "samsung,exynos-sysmmu"; - reg = <0x132E0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <9 4>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_DIS1>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_3dnr: sysmmu@132F0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x132F0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <5 6>; - clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FIMC_3DNR>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@13C40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 4>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@13C50000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C50000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 1>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; - #iommu-cells = <0>; - }; - - sysmmu_gsc0: sysmmu@13E80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_gsc1: sysmmu@13E90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_gsc2: sysmmu@13EA0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13EA0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_gsc3: sysmmu@13EB0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13EB0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 6>; - power-domains = <&pd_gsc>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1: sysmmu@14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - power-domains = <&pd_disp1>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - power-domains = <&pd_disp1>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; - #iommu-cells = <0>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; - - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 9 9>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 15 15>; - }; - }; - }; - }; -}; - -&dp { - power-domains = <&pd_disp1>; - clocks = <&clock CLK_DP>; - clock-names = "dp"; - phys = <&dp_phy>; - phy-names = "dp"; -}; - -&fimd { - power-domains = <&pd_disp1>; - clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; - clock-names = "sclk_fimd", "fimd"; - iommus = <&sysmmu_fimd1>; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; -}; - -#include "exynos5250-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5260-pinctrl.dtsi deleted file mode 100644 index 1b911a219..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ /dev/null @@ -1,572 +0,0 @@ -/* - * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb4: gpb4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb5: gpb5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd2: gpd2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3_vbus0_en: usb3-vbus0-en { - samsung,pins = "gpa2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif1_bus: spdif1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_hs_bus: i2c0-hs-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_hs_bus: i2c1-hs-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_hs_bus: i2c2-hs-bus { - samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_hs_bus: i2c3-hs-bus { - samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpb4-2", "gpb4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpb4-4", "gpb4-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpb4-6", "gpb4-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c8_bus: i2c8-bus { - samsung,pins = "gpb5-0", "gpb5-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c9_bus: i2c9-bus { - samsung,pins = "gpb5-2", "gpb5-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c10_bus: i2c10-bus { - samsung,pins = "gpb5-4", "gpb5-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c11_bus: i2c11-bus { - samsung,pins = "gpb5-6", "gpb5-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpz0: gpz0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpz1: gpz1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5260-xyref5260.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5260-xyref5260.dts deleted file mode 100644 index d0cc300cf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * SAMSUNG XYREF5260 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5260.dtsi" - -/ { - model = "SAMSUNG XYREF5260 board based on EXYNOS5260"; - compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttySAC2,115200"; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xrtcxti: xrtcxti { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xrtcxti"; - #clock-cells = <0>; - }; -}; - -&pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - broken-cd; - bypass-smu; - cap-mmc-highspeed; - supports-hs200-mode; /* 200 MHz */ - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - cap-sd-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - disable-wp; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5260.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5260.dtsi deleted file mode 100644 index a86a4898d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5260.dtsi +++ /dev/null @@ -1,313 +0,0 @@ -/* - * SAMSUNG EXYNOS5260 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -/ { - compatible = "samsung,exynos5260", "samsung,exynos5"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - cci-control-port = <&cci_control1>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - cci-control-port = <&cci_control1>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cci-control-port = <&cci_control0>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cci-control-port = <&cci_control0>; - }; - - cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cci-control-port = <&cci_control0>; - }; - - cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - cci-control-port = <&cci_control0>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock_top: clock-controller@10010000 { - compatible = "samsung,exynos5260-clock-top"; - reg = <0x10010000 0x10000>; - #clock-cells = <1>; - }; - - clock_peri: clock-controller@10200000 { - compatible = "samsung,exynos5260-clock-peri"; - reg = <0x10200000 0x10000>; - #clock-cells = <1>; - }; - - clock_egl: clock-controller@10600000 { - compatible = "samsung,exynos5260-clock-egl"; - reg = <0x10600000 0x10000>; - #clock-cells = <1>; - }; - - clock_kfc: clock-controller@10700000 { - compatible = "samsung,exynos5260-clock-kfc"; - reg = <0x10700000 0x10000>; - #clock-cells = <1>; - }; - - clock_g2d: clock-controller@10A00000 { - compatible = "samsung,exynos5260-clock-g2d"; - reg = <0x10A00000 0x10000>; - #clock-cells = <1>; - }; - - clock_mif: clock-controller@10CE0000 { - compatible = "samsung,exynos5260-clock-mif"; - reg = <0x10CE0000 0x10000>; - #clock-cells = <1>; - }; - - clock_mfc: clock-controller@11090000 { - compatible = "samsung,exynos5260-clock-mfc"; - reg = <0x11090000 0x10000>; - #clock-cells = <1>; - }; - - clock_g3d: clock-controller@11830000 { - compatible = "samsung,exynos5260-clock-g3d"; - reg = <0x11830000 0x10000>; - #clock-cells = <1>; - }; - - clock_fsys: clock-controller@122E0000 { - compatible = "samsung,exynos5260-clock-fsys"; - reg = <0x122E0000 0x10000>; - #clock-cells = <1>; - }; - - clock_aud: clock-controller@128C0000 { - compatible = "samsung,exynos5260-clock-aud"; - reg = <0x128C0000 0x10000>; - #clock-cells = <1>; - }; - - clock_isp: clock-controller@133C0000 { - compatible = "samsung,exynos5260-clock-isp"; - reg = <0x133C0000 0x10000>; - #clock-cells = <1>; - }; - - clock_gscl: clock-controller@13F00000 { - compatible = "samsung,exynos5260-clock-gscl"; - reg = <0x13F00000 0x10000>; - #clock-cells = <1>; - }; - - clock_disp: clock-controller@14550000 { - compatible = "samsung,exynos5260-clock-disp"; - reg = <0x14550000 0x10000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - chipid: chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - mct: mct@100B0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x100B0000 0x1000>; - clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, - <0 107 0>, <0 122 0>, <0 123 0>, - <0 124 0>, <0 125 0>, <0 126 0>, - <0 127 0>, <0 128 0>, <0 129 0>; - }; - - cci: cci@10F00000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10F00000 0x1000>; - ranges = <0x0 0x10F00000 0x6000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - }; - - pinctrl_0: pinctrl@11600000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x11600000 0x1000>; - interrupts = <0 79 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - - pinctrl_1: pinctrl@12290000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x12290000 0x1000>; - interrupts = <0 157 0>; - }; - - pinctrl_2: pinctrl@128B0000 { - compatible = "samsung,exynos5260-pinctrl"; - reg = <0x128B0000 0x1000>; - interrupts = <0 243 0>; - }; - - pmu_system_controller: system-controller@10D50000 { - compatible = "samsung,exynos5260-pmu", "syscon"; - reg = <0x10D50000 0x10000>; - }; - - uart0: serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 146 0>; - clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart1: serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 147 0>; - clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart2: serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 148 0>; - clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - uart3: serial@12860000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12860000 0x100>; - interrupts = <0 145 0>; - clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - mmc_0: mmc@12140000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12140000 0x2000>; - interrupts = <0 156 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <64>; - status = "disabled"; - }; - - mmc_1: mmc@12150000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12150000 0x2000>; - interrupts = <0 158 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <64>; - status = "disabled"; - }; - - mmc_2: mmc@12160000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12160000 0x2000>; - interrupts = <0 159 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <64>; - status = "disabled"; - }; - }; -}; - -#include "exynos5260-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5410-odroidxu.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5410-odroidxu.dts deleted file mode 100644 index 3c271cb4b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ /dev/null @@ -1,578 +0,0 @@ -/* - * Hardkernel Odroid XU board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2016 Krzysztof Kozlowski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "exynos5410.dtsi" -#include -#include -#include -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU"; - compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7ea00000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_nrst_pin>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 20972 0>; - cooling-min-state = <0>; - cooling-max-state = <3>; - #cooling-cells = <2>; - cooling-levels = <0 130 170 230>; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - firmware@02073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; -}; - -&cpu0_thermal { - thermal-sensors = <&tmu_cpu0 0>; - polling-delay-passive = <0>; - polling-delay = <0>; - - trips { - cpu_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - }; -}; - -&hsi2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; - - usb3503: usb-hub@08 { - compatible = "smsc,usb3503"; - reg = <0x08>; - - intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; - connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx1 4 GPIO_ACTIVE_HIGH>; - initial-mode = <1>; - - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - refclk-frequency = <24000000>; - }; - - max77802: pmic@09 { - compatible = "maxim,max77802"; - reg = <0x9>; - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, - <&pmic_dvs_3>; - #clock-cells = <1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&buck10_reg>; - inl7-supply = <&buck9_reg>; - /* inl9 supply is BOOST, not configured here */ - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - /* vdd_mmc0 */ - regulator-name = "vddf_2v85"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "buck9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "buck10"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_alive"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "vddq_m1_m2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vddq_gpio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - /* Having it off prevents reboot */ - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd18_hsic"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd18_bpll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vddq_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd10_hdmi"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "ldo9"; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd18_mipi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vddq_mmc01"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - /* - * Having it off prevents accessing MMC after - * reboot with error: - * MMC Device 1: Clock OFF has been failed. - */ - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd33_usb3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vddq_abbg0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "vddq_abbg1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd10_usb3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "ldo16"; - }; - - ldo17_reg: LDO17 { - regulator-name = "cam_sensor_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo19"; - }; - - ldo20_reg: LDO20 { - regulator-name = "vdd_mmc0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - /* vdd_mmc2 */ - regulator-name = "vddf_2v8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "ldo22"; - }; - - ldo23_reg: LDO23 { - regulator-name = "dp_p3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "cam_af"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "eth_p3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo26_reg: LDO26 { - regulator-name = "usb30_extclk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo27"; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo28"; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo29"; - }; - - ldo30_reg: LDO30 { - regulator-name = "vddq_e1_e2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo31_reg: LDO31 { - regulator-name = "ldo31"; - }; - - /* On revisions with ti,ina231 this is sensor VS */ - ldo32_reg: LDO32 { - regulator-name = "vs_power_meter"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo33"; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo34"; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo35"; - }; - }; - }; -}; - -&mmc_0 { - status = "okay"; - mmc-pwrseq = <&emmc_pwrseq>; - cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - vmmc-supply = <&ldo20_reg>; - vqmmc-supply = <&ldo11_reg>; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; - vmmc-supply = <&ldo21_reg>; - vqmmc-supply = <&ldo4_reg>; -}; - -&pinctrl_0 { - emmc_nrst_pin: emmc-nrst { - samsung,pins = "gpd1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpx0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1 { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <1>; - }; - - max77802_irq: max77802-irq { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; - -&usbdrd3_0 { - vdd33-supply = <&ldo12_reg>; - vdd10-supply = <&ldo15_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo12_reg>; - vdd10-supply = <&ldo15_reg>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5410-pinctrl.dtsi deleted file mode 100644 index a083d23fd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ /dev/null @@ -1,618 +0,0 @@ -/* - * Exynos5410 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Hardkernel Co., Ltd. - * http://www.hardkernel.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -&pinctrl_0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm5: gpm5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm7: gpm7 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy7: gpy7 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, - <24 0>, - <25 0>, - <25 1>, - <26 0>, - <26 1>, - <27 0>, - <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, - <28 1>, - <29 0>, - <29 1>, - <30 0>, - <30 1>, - <31 0>, - <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_hs_bus: i2c4-hs-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_hs_bus: i2c5-hs-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_hs_bus: i2c6-hs-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_hs_bus: i2c7-hs-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj2: gpj2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj3: gpj3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_2 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_3 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5410-smdk5410.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5410-smdk5410.dts deleted file mode 100644 index 6cc74d97d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * SAMSUNG SMDK5410 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5410.dtsi" -#include -/ { - model = "Samsung SMDK5410 board based on EXYNOS5410"; - compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttySAC2,115200"; - }; - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - firmware@02037000 { - compatible = "samsung,secure-firmware"; - reg = <0x02037000 0x1000>; - }; - -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - cap-mmc-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - cap-sd-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <4>; - disable-wp; -}; - -&pinctrl_0 { - srom_ctl: srom-ctl { - samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", - "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; - samsung,pin-function = ; - samsung,pin-drv = ; - }; - - srom_ebi: srom-ebi { - samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", - "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7", - "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", - "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", - "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", - "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&sromc { - pinctrl-names = "default"; - pinctrl-0 = <&srom_ctl>, <&srom_ebi>; - - ethernet@3,0 { - compatible = "smsc,lan9115"; - reg = <3 0 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpx0>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reg-io-width = <2>; - smsc,irq-push-pull; - smsc,force-internal-phy; - - samsung,srom-page-mode; - samsung,srom-timing = <9 12 1 9 1 1>; - }; -}; - -&serial_0 { - status = "okay"; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5410.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5410.dtsi deleted file mode 100644 index bb59fee07..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5410.dtsi +++ /dev/null @@ -1,363 +0,0 @@ -/* - * SAMSUNG EXYNOS5410 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. - * EXYNOS5410 based board files can include this file and provide - * values for board specfic bindings. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "exynos54xx.dtsi" -#include "exynos-syscon-restart.dtsi" -#include -#include - -/ { - compatible = "samsung,exynos5410", "samsung,exynos5"; - interrupt-parent = <&gic>; - - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - clock-frequency = <1600000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clock-frequency = <1600000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clock-frequency = <1600000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clock-frequency = <1600000000>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5410-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&fin_pll>; - #clock-cells = <1>; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5410-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - tmu_cpu0: tmu@10060000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu1: tmu@10064000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10064000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10068000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x1006c000 0x100>; - interrupts = ; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x80>; - status = "disabled"; - }; - - pinctrl_0: pinctrl@13400000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - - pinctrl_1: pinctrl@14000000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; - }; - - pinctrl_2: pinctrl@10d10000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; - }; - - pinctrl_3: pinctrl@03860000 { - compatible = "samsung,exynos5410-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - #include "exynos5420-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" - }; - }; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&hsi2c_4 { - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; -}; - -&hsi2c_5 { - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; -}; - -&hsi2c_6 { - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; -}; - -&hsi2c_7 { - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; -}; - -&mct { - clocks = <&fin_pll>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&sss { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&sromc { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 - 1 0 0x05000000 0x20000 - 2 0 0x06000000 0x20000 - 3 0 0x07000000 0x20000>; -}; - -&usbdrd3_0 { - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; -}; - -&usbdrd_phy0 { - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbdrd3_1 { - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; -}; - -&usbdrd_dwc3_1 { - interrupts = ; -}; - -&usbdrd_phy1 { - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbhost1 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usbhost2 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usb2_phy { - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; -}; - -&watchdog { - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -#include "exynos5410-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5420-arndale-octa.dts deleted file mode 100644 index 9cc83c51c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ /dev/null @@ -1,405 +0,0 @@ -/* - * Samsung's Exynos5420 based Arndale Octa board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" -#include -#include -#include -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; - compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttySAC3,115200"; - }; - - firmware@02073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - wakeup { - label = "SW-TACT1"; - gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&cci { - status = "disabled"; -}; - -&hdmi { - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - vdd-supply = <&ldo6_reg>; - ddc = <&i2c_2>; - status = "okay"; -}; - -&hsi2c_4 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - - s2mps11_osc: clocks { - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "PVDD_ALIVE_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "PVDD_APIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "PVDD_APIO_MMCON_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "PVDD_ADC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "PVDD_PLL_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "PVDD_ANAIP_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "PVDD_ANAIP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "PVDD_ABB_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "PVDD_USB_3V3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "PVDD_PRE_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "PVDD_USB_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "PVDD_HSIC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "PVDD_APIO_MMCOFF_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "PVDD_PERI_2V8"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "PVDD_PERI_3V3"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "PVDD_EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "PVDD_TFLASH_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "PVDD_BTWIFI_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "PVDD_CAM1IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "PVDD_MIFS_1V1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "PVDD_CAM1_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "PVDD_CAM0_AF_2V8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "PVDD_G3DS_1V0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "PVDD_TSP_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "PVDD_AUDIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo31_reg: LDO31 { - regulator-name = "PVDD_PERI_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo32_reg: LDO32 { - regulator-name = "PVDD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "PVDD_CAM0IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "PVDD_CAM0_DVDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo38_reg: LDO38 { - regulator-name = "PVDD_CAM0_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "PVDD_MIF_1V1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "PVDD_INT_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "PVDD_G3D_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "PVDD_LPDDR3_1V2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "PVDD_KFC_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VIN_LLDO_1V4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VIN_MLDO_2V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "VIN_HLDO_3V5"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "PVDD_EMMCF_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - }; - }; -}; - -&i2c_2 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - vmmc-supply = <&ldo10_reg>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - s2mps11_irq: s2mps11-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5420-cpus.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5420-cpus.dtsi deleted file mode 100644 index 5c052d7ff..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -/* - * SAMSUNG EXYNOS5420 SoC cpu device tree source - * - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This file provides desired ordering for Exynos5420 and Exynos5800 - * boards: CPU[0123] being the A15. - * - * The Exynos5420, 5422 and 5800 actually share the same CPU configuration - * but particular boards choose different booting order. - * - * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 - * booting cluster (big or LITTLE) is chosen by IROM code by reading - * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting - * from the LITTLE: Cortex-A7. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - clocks = <&clock CLK_ARM_CLK>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <7>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <7>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <7>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <7>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5420-peach-pit.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5420-peach-pit.dts deleted file mode 100644 index ec4a00f1c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ /dev/null @@ -1,1093 +0,0 @@ -/* - * Google Peach Pit Rev 6+ board device tree source - * - * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Google Peach Pit Rev 6+"; - - compatible = "google,pit-rev16", - "google,pit-rev15", "google,pit-rev14", - "google,pit-rev13", "google,pit-rev12", - "google,pit-rev11", "google,pit-rev10", - "google,pit-rev9", "google,pit-rev8", - "google,pit-rev7", "google,pit-rev6", - "google,pit", "google,peach","samsung,exynos5420", - "samsung,exynos5"; - - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - power-supply = <&tps65090_fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - sound { - compatible = "google,snow-audio-max98090"; - - samsung,model = "Peach-Pit-I2S-MAX98090"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98090>; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - - vbat: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - regulator-always-on; - }; - - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&tps65090_fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - mmc1_pwrseq: mmc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77802 MAX77802_CLK_32K_CP>; - clock-names = "ext_clock"; - }; -}; - -&adc { - status = "okay"; - vdd-supply = <&ldo9_reg>; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x06>; - samsung,lane-count = <2>; - hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hsi2c_4 { - status = "okay"; - clock-frequency = <400000>; - - max77802: max77802-pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&gpx3>; - interrupts = <1 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; - wakeup-source; - reg = <0x9>; - #clock-cells = <1>; - - inb1-supply = <&tps65090_dcdc2>; - inb2-supply = <&tps65090_dcdc1>; - inb3-supply = <&tps65090_dcdc2>; - inb4-supply = <&tps65090_dcdc2>; - inb5-supply = <&tps65090_dcdc1>; - inb6-supply = <&tps65090_dcdc2>; - inb7-supply = <&tps65090_dcdc1>; - inb8-supply = <&tps65090_dcdc1>; - inb9-supply = <&tps65090_dcdc1>; - inb10-supply = <&tps65090_dcdc1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&tps65090_dcdc2>; - inl7-supply = <&buck9_reg>; - inl9-supply = <&tps65090_dcdc2>; - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2v"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_1v2_2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_1v8_3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - vqmmc_sdcard: ldo4_reg: LDO4 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_1v8_5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_1v8_6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_1v8_7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo_19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "ldo_20"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "ldo_21"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "ldo_23"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - ldo24_reg: LDO24 { - regulator-name = "ldo_24"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "ldo_25"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "ldo_26"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo_27"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo_28"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo_29"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "ldo_32"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo_33"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo_34"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo_35"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <400000>; - - max98090: codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupts = <2 0>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98090_irq>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - }; - - light-sensor@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - vcc-supply = <&tps65090_fet5>; - }; - - ps8625: lvds-bridge@48 { - compatible = "parade,ps8625"; - reg = <0x48>; - sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; - lane-count = <2>; - use-external-pwm; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - - }; -}; - -&hsi2c_8 { - status = "okay"; - clock-frequency = <333000>; - - /* Atmel mXT336S */ - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; /* GPIO3 */ - }; -}; - -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - mmc-hs200-1_8v; - cap-mmc-highspeed; - non-removable; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; - bus-width = <8>; -}; - -&mmc_1 { - status = "okay"; - num-slots = <1>; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, - <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc1_pwrseq>; - vqmmc-supply = <&buck10_reg>; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; -}; - - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&mask_tpm_reset>; - - wifi_en: wifi-en { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max98090_irq: max98090-irq { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { - samsung,pins = "gpx0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - tpm_irq: tpm-irq { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq { - samsung,pins = "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp_hpd_gpio { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77802_irq: max77802-irq { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1 { - samsung,pins = "gpy7-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - /* Adjust WiFi drive strengths lower for EMI */ - sd1_clk: sd1-clk { - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = ; - }; - - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { - samsung,pins = "gpb1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gph0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_selb: pmic-selb { - samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", - "gph0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_FIN_PLL>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&spi_2 { - status = "okay"; - num-cs = <1>; - samsung,spi-src-clk = <0>; - cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_spi_cs &ec_irq>; - reg = <0>; - spi-max-frequency = <3125000>; - google,has-vbc-nvram; - - controller-data { - samsung,spi-feedback-delay = <1>; - }; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - sbs,i2c-retry-count = <2>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&tps65090_dcdc1>; - infet3-supply = <&tps65090_dcdc2>; - infet4-supply = <&tps65090_dcdc2>; - infet5-supply = <&tps65090_dcdc2>; - infet6-supply = <&tps65090_dcdc2>; - infet7-supply = <&tps65090_dcdc1>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - tps65090_dcdc1: dcdc1 { - ti,enable-ext-control; - }; - tps65090_dcdc2: dcdc2 { - ti,enable-ext-control; - }; - tps65090_dcdc3: dcdc3 { - ti,enable-ext-control; - }; - tps65090_fet1: fet1 { - regulator-name = "vcd_led"; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - }; - tps65090_fet3: fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - }; - tps65090_fet4: fet4 { - regulator-name = "sdcard"; - regulator-always-on; - }; - tps65090_fet5: fet5 { - regulator-name = "camout"; - regulator-always-on; - }; - tps65090_fet6: fet6 { - regulator-name = "lcd_vdd"; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - }; - tps65090_ldo1: ldo1 { - }; - tps65090_ldo2: ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; - -/* - * Use longest HW watchdog in SoC (32 seconds) since the hardware - * watchdog provides no debugging information (compared to soft/hard - * lockup detectors) and so should be last resort. - */ -&watchdog { - timeout-sec = <32>; -}; - -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5420-pinctrl.dtsi deleted file mode 100644 index 3924b4faf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ /dev/null @@ -1,723 +0,0 @@ -/* - * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -&pinctrl_0 { - gpy7: gpy7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - dp_hpd: dp_hpd { - samsung,pins = "gpx0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rclk: sd0-rclk { - samsung,pins = "gpc0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpc1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_int: sd1-int { - samsung,pins = "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c2_bus: cam-i2c2-bus { - samsung,pins = "gpf0-4", "gpf0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_bayrgb_bus: cam-bayrgb-bus { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb4: gpb4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c4_hs_bus: i2c4-hs-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c5_hs_bus: i2c5-hs-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c6_hs_bus: i2c6-hs-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpb2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpb2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpb2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c7_hs_bus: i2c7-hs-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c8_hs_bus: i2c8-hs-bus { - samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c9_hs_bus: i2c9-hs-bus { - samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c10_hs_bus: i2c10-hs-bus { - samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_4 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5420-smdk5420.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5420-smdk5420.dts deleted file mode 100644 index aaccd0da4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ /dev/null @@ -1,422 +0,0 @@ -/* - * SAMSUNG SMDK5420 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5420.dtsi" -#include "exynos5420-cpus.dtsi" -#include -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Samsung SMDK5420 board based on EXYNOS5420"; - compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttySAC2,115200 init=/linuxrc"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd: fixed-regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - dbvdd: fixed-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "dbvdd-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - spkvdd: fixed-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "spkvdd-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "VBUS0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpg0 5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "VBUS1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpg1 4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <50000>; - hactive = <2560>; - vactive = <1600>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - vback-porch = <16>; - vfront-porch = <8>; - vsync-len = <6>; - }; - }; -}; - -&fimd { - status = "okay"; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; -}; - -&hsi2c_4 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - s2mps11_osc: clocks { - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "tsp_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "tsp_io"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; -}; - -&mmc_0 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 - &sd0_rclk>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gpg0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gpg1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&rtc { - status = "okay"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5420-trip-points.dtsi deleted file mode 100644 index 2180a0152..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5420-trip-points.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Device tree sources for default Exynos5420 thermal zone definition - * - * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -polling-delay-passive = <0>; -polling-delay = <0>; -trips { - cpu-alert-0 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-alert-1 { - temperature = <103000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "active"; - }; - cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5420.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5420.dtsi deleted file mode 100644 index 00c4cfa54..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5420.dtsi +++ /dev/null @@ -1,1480 +0,0 @@ -/* - * SAMSUNG EXYNOS5420 SoC device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. - * EXYNOS5420 based board files can include this file and provide - * values for board specfic bindings. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "exynos54xx.dtsi" -#include -#include -#include - -/ { - compatible = "samsung,exynos5420", "samsung,exynos5"; - - aliases { - mshc0 = &mmc_0; - mshc1 = &mmc_1; - mshc2 = &mmc_2; - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - pinctrl4 = &pinctrl_4; - i2c8 = &hsi2c_8; - i2c9 = &hsi2c_9; - i2c10 = &hsi2c_10; - gsc0 = &gsc_0; - gsc1 = &gsc_1; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - }; - - /* - * The 'cpus' node is not present here but instead it is provided - * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. - */ - - soc: soc { - cluster_a15_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp@1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000>; - clock-latency-ns = <140000>; - }; - opp@1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp@1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1175000>; - clock-latency-ns = <140000>; - }; - opp@1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1137500>; - clock-latency-ns = <140000>; - }; - opp@1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp@1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500>; - clock-latency-ns = <140000>; - }; - opp@1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500>; - clock-latency-ns = <140000>; - }; - opp@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = < 987500>; - clock-latency-ns = <140000>; - }; - opp@900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = < 962500>; - clock-latency-ns = <140000>; - }; - opp@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = < 937500>; - clock-latency-ns = <140000>; - }; - opp@700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = < 912500>; - clock-latency-ns = <140000>; - }; - }; - - cluster_a7_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - opp@1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1275000>; - clock-latency-ns = <140000>; - }; - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1212500>; - clock-latency-ns = <140000>; - }; - opp@1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1162500>; - clock-latency-ns = <140000>; - }; - opp@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1112500>; - clock-latency-ns = <140000>; - }; - opp@900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <140000>; - }; - opp@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <140000>; - }; - opp@700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <975000>; - clock-latency-ns = <140000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <937500>; - clock-latency-ns = <140000>; - }; - }; - - cci: cci@10d20000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10d20000 0x1000>; - ranges = <0x0 0x10d20000 0x6000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - - clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5420-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, - <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; - }; - - mfc: codec@11000000 { - compatible = "samsung,mfc-v7"; - reg = <0x11000000 0x10000>; - interrupts = <0 96 0>; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; - power-domains = <&mfc_pd>; - iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; - iommu-names = "left", "right"; - }; - - mmc_0: mmc@12200000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12200000 0x2000>; - clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_1: mmc@12210000 { - compatible = "samsung,exynos5420-dw-mshc-smu"; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12210000 0x2000>; - clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_2: mmc@12220000 { - compatible = "samsung,exynos5420-dw-mshc"; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x12220000 0x1000>; - clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - nocp_mem0_0: nocp@10CA1000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1000 0x200>; - status = "disabled"; - }; - - nocp_mem0_1: nocp@10CA1400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1400 0x200>; - status = "disabled"; - }; - - nocp_mem1_0: nocp@10CA1800 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1800 0x200>; - status = "disabled"; - }; - - nocp_mem1_1: nocp@10CA1C00 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1C00 0x200>; - status = "disabled"; - }; - - nocp_g3d_0: nocp@11A51000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51000 0x200>; - status = "disabled"; - }; - - nocp_g3d_1: nocp@11A51400 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51400 0x200>; - status = "disabled"; - }; - - gsc_pd: power-domain@10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK300_GSCL>, - <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "oscclk", "clk0", "asb0", "asb1"; - }; - - isp_pd: power-domain@10044020 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044020 0x20>; - #power-domain-cells = <0>; - }; - - mfc_pd: power-domain@10044060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK333>, - <&clock CLK_ACLK333>; - clock-names = "oscclk", "clk0","asb0"; - #power-domain-cells = <0>; - }; - - msc_pd: power-domain@10044120 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044120 0x20>; - #power-domain-cells = <0>; - }; - - disp_pd: power-domain@100440C0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; - #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK200_DISP1>, - <&clock CLK_MOUT_USER_ACLK300_DISP1>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>, - <&clock CLK_FIMD1>, <&clock CLK_MIXER>; - clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; - }; - - pinctrl_0: pinctrl@13400000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - - pinctrl_1: pinctrl@13410000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x13410000 0x1000>; - interrupts = <0 78 0>; - }; - - pinctrl_2: pinctrl@14000000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14000000 0x1000>; - interrupts = <0 46 0>; - }; - - pinctrl_3: pinctrl@14010000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x14010000 0x1000>; - interrupts = <0 50 0>; - }; - - pinctrl_4: pinctrl@03860000 { - compatible = "samsung,exynos5420-pinctrl"; - reg = <0x03860000 0x1000>; - interrupts = <0 47 0>; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - adma: adma@03880000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x03880000 0x1000>; - interrupts = <0 110 0>; - clocks = <&clock_audss EXYNOS_ADMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <6>; - #dma-requests = <16>; - }; - - pdma0: pdma@121A0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = <0 34 0>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121B0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = <0 35 0>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = <0 33 0>; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - mdma1: mdma@11C10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = <0 124 0>; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - /* - * MDMA1 can support both secure and non-secure - * AXI transactions. When this is enabled in - * the kernel for boards that run in secure - * mode, we are getting imprecise external - * aborts causing the kernel to oops. - */ - status = "disabled"; - }; - }; - - i2s0: i2s@03830000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x03830000 0x100>; - dmas = <&adma 0 - &adma 2 - &adma 1>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk0"; - #sound-dai-cells = <1>; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - status = "disabled"; - }; - - i2s1: i2s@12D60000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12D60000 0x100>; - dmas = <&pdma1 12 - &pdma1 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk1"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s2: i2s@12D70000 { - compatible = "samsung,exynos5420-i2s"; - reg = <0x12D70000 0x100>; - dmas = <&pdma0 12 - &pdma0 11>; - dma-names = "tx", "rx"; - clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; - clock-names = "iis", "i2s_opclk0"; - #clock-cells = <1>; - clock-output-names = "i2s_cdclk2"; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - status = "disabled"; - }; - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d20000 0x100>; - interrupts = <0 68 0>; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_1: spi@12d30000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d30000 0x100>; - interrupts = <0 69 0>; - dmas = <&pdma1 5 - &pdma1 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - spi_2: spi@12d40000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d40000 0x100>; - interrupts = <0 70 0>; - dmas = <&pdma0 7 - &pdma0 6>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; - clock-names = "spi", "spi_busclk0"; - status = "disabled"; - }; - - dp_phy: dp-video-phy { - compatible = "samsung,exynos5420-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; - - mipi_phy: mipi-video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - dsi@14500000 { - compatible = "samsung,exynos5410-mipi-dsi"; - reg = <0x14500000 0x10000>; - interrupts = <0 82 0>; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; - clock-names = "bus_clk", "pll_clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - adc: adc@12D10000 { - compatible = "samsung,exynos-adc-v2"; - reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - hsi2c_8: i2c@12E00000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E00000 0x1000>; - interrupts = <0 87 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock CLK_USI4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: i2c@12E10000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E10000 0x1000>; - interrupts = <0 88 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock CLK_USI5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: i2c@12E20000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E20000 0x1000>; - interrupts = <0 203 0>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock CLK_USI6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hdmi: hdmi@14530000 { - compatible = "samsung,exynos5420-hdmi"; - reg = <0x14530000 0x70000>; - interrupts = <0 95 0>; - clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, - <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, - <&clock CLK_MOUT_HDMI>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - phy = <&hdmiphy>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - power-domains = <&disp_pd>; - }; - - hdmiphy: hdmiphy@145D0000 { - reg = <0x145D0000 0x20>; - }; - - mixer: mixer@14450000 { - compatible = "samsung,exynos5420-mixer"; - reg = <0x14450000 0x10000>; - interrupts = <0 94 0>; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>; - clock-names = "mixer", "hdmi", "sclk_hdmi"; - power-domains = <&disp_pd>; - iommus = <&sysmmu_tv>; - }; - - rotator: rotator@11C00000 { - compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; - interrupts = <0 84 0>; - clocks = <&clock CLK_ROTATOR>; - clock-names = "rotator"; - iommus = <&sysmmu_rotator>; - }; - - gsc_0: video-scaler@13e00000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl0>; - }; - - gsc_1: video-scaler@13e10000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e10000 0x1000>; - interrupts = <0 86 0>; - clocks = <&clock CLK_GSCL1>; - clock-names = "gscl"; - power-domains = <&gsc_pd>; - iommus = <&sysmmu_gscl1>; - }; - - jpeg_0: jpeg@11F50000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F50000 0x1000>; - interrupts = <0 89 0>; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG>; - iommus = <&sysmmu_jpeg0>; - }; - - jpeg_1: jpeg@11F60000 { - compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F60000 0x1000>; - interrupts = <0 168 0>; - clock-names = "jpeg"; - clocks = <&clock CLK_JPEG2>; - iommus = <&sysmmu_jpeg1>; - }; - - pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5420-pmu", "syscon"; - reg = <0x10040000 0x5000>; - clock-names = "clkout16"; - clocks = <&clock CLK_FIN_PLL>; - #clock-cells = <1>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - tmu_cpu0: tmu@10060000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10060000 0x100>; - interrupts = <0 65 0>; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu1: tmu@10064000 { - compatible = "samsung,exynos5420-tmu"; - reg = <0x10064000 0x100>; - interrupts = <0 183 0>; - clocks = <&clock CLK_TMU>; - clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = <0 184 0>; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = <0 185 0>; - clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - tmu_gpu: tmu@100a0000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = <0 215 0>; - clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" - }; - - sysmmu_g2dr: sysmmu@0x10A60000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <24 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_g2dw: sysmmu@0x10A70000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10A70000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_tv: sysmmu@0x14650000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14650000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <7 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl0: sysmmu@0x13E80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_gscl1: sysmmu@0x13E90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; - power-domains = <&gsc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0r: sysmmu@0x12880000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12880000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 4>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1r: sysmmu@0x12890000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12890000 0x1000>; - interrupts = <0 186 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2r: sysmmu@0x128A0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128A0000 0x1000>; - interrupts = <0 188 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_scaler0w: sysmmu@0x128C0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128C0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <27 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; - #iommu-cells = <0>; - }; - - sysmmu_scaler1w: sysmmu@0x128D0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128D0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <22 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; - #iommu-cells = <0>; - }; - - sysmmu_scaler2w: sysmmu@0x128E0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x128E0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <19 6>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; - #iommu-cells = <0>; - }; - - sysmmu_rotator: sysmmu@0x11D40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg0: sysmmu@0x11F10000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F10000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; - #iommu-cells = <0>; - }; - - sysmmu_jpeg1: sysmmu@0x11F20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; - interrupts = <0 169 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_l: sysmmu@0x11200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11200000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <6 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_mfc_r: sysmmu@0x11210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x11210000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <8 5>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; - power-domains = <&mfc_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_0: sysmmu@0x14640000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14640000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 2>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - sysmmu_fimd1_1: sysmmu@0x14680000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x14680000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <3 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; - power-domains = <&disp_pd>; - #iommu-cells = <0>; - }; - - bus_wcore: bus_wcore { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_WCORE>; - clock-names = "bus"; - operating-points-v2 = <&bus_wcore_opp_table>; - status = "disabled"; - }; - - bus_noc: bus_noc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK100_NOC>; - clock-names = "bus"; - operating-points-v2 = <&bus_noc_opp_table>; - status = "disabled"; - }; - - bus_fsys_apb: bus_fsys_apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_PCLK200_FSYS>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_apb_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_apb_opp_table>; - status = "disabled"; - }; - - bus_fsys2: bus_fsys2 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys2_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333>; - clock-names = "bus"; - operating-points-v2 = <&bus_mfc_opp_table>; - status = "disabled"; - }; - - bus_gen: bus_gen { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266>; - clock-names = "bus"; - operating-points-v2 = <&bus_gen_opp_table>; - status = "disabled"; - }; - - bus_peri: bus_peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK66>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_g2d: bus_g2d { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333_G2D>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_opp_table>; - status = "disabled"; - }; - - bus_g2d_acp: bus_g2d_acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266_G2D>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_acp_opp_table>; - status = "disabled"; - }; - - bus_jpeg: bus_jpeg { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_JPEG>; - clock-names = "bus"; - operating-points-v2 = <&bus_jpeg_opp_table>; - status = "disabled"; - }; - - bus_jpeg_apb: bus_jpeg_apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK166>; - clock-names = "bus"; - operating-points-v2 = <&bus_jpeg_apb_opp_table>; - status = "disabled"; - }; - - bus_disp1_fimd: bus_disp1_fimd { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_DISP1>; - clock-names = "bus"; - operating-points-v2 = <&bus_disp1_fimd_opp_table>; - status = "disabled"; - }; - - bus_disp1: bus_disp1 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_DISP1>; - clock-names = "bus"; - operating-points-v2 = <&bus_disp1_opp_table>; - status = "disabled"; - }; - - bus_gscl_scaler: bus_gscl_scaler { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_GSCL>; - clock-names = "bus"; - operating-points-v2 = <&bus_gscl_opp_table>; - status = "disabled"; - }; - - bus_mscl: bus_mscl { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_MSCL>; - clock-names = "bus"; - operating-points-v2 = <&bus_mscl_opp_table>; - status = "disabled"; - }; - - bus_wcore_opp_table: opp_table2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <84000000>; - opp-microvolt = <925000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - opp-microvolt = <950000>; - }; - opp02 { - opp-hz = /bits/ 64 <222000000>; - opp-microvolt = <950000>; - }; - opp03 { - opp-hz = /bits/ 64 <333000000>; - opp-microvolt = <950000>; - }; - opp04 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <987500>; - }; - }; - - bus_noc_opp_table: opp_table3 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <67000000>; - }; - opp01 { - opp-hz = /bits/ 64 <75000000>; - }; - opp02 { - opp-hz = /bits/ 64 <86000000>; - }; - opp03 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_fsys_apb_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <100000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_fsys2_opp_table: opp_table5 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <100000000>; - }; - opp02 { - opp-hz = /bits/ 64 <150000000>; - }; - }; - - bus_mfc_opp_table: opp_table6 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <96000000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - }; - opp02 { - opp-hz = /bits/ 64 <167000000>; - }; - opp03 { - opp-hz = /bits/ 64 <222000000>; - }; - opp04 { - opp-hz = /bits/ 64 <333000000>; - }; - }; - - bus_gen_opp_table: opp_table7 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <89000000>; - }; - opp01 { - opp-hz = /bits/ 64 <133000000>; - }; - opp02 { - opp-hz = /bits/ 64 <178000000>; - }; - opp03 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - - bus_peri_opp_table: opp_table8 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <67000000>; - }; - }; - - bus_g2d_opp_table: opp_table9 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <84000000>; - }; - opp01 { - opp-hz = /bits/ 64 <167000000>; - }; - opp02 { - opp-hz = /bits/ 64 <222000000>; - }; - opp03 { - opp-hz = /bits/ 64 <300000000>; - }; - opp04 { - opp-hz = /bits/ 64 <333000000>; - }; - }; - - bus_g2d_acp_opp_table: opp_table10 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <67000000>; - }; - opp01 { - opp-hz = /bits/ 64 <133000000>; - }; - opp02 { - opp-hz = /bits/ 64 <178000000>; - }; - opp03 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - - bus_jpeg_opp_table: opp_table11 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <75000000>; - }; - opp01 { - opp-hz = /bits/ 64 <150000000>; - }; - opp02 { - opp-hz = /bits/ 64 <200000000>; - }; - opp03 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_jpeg_apb_opp_table: opp_table12 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <84000000>; - }; - opp01 { - opp-hz = /bits/ 64 <111000000>; - }; - opp02 { - opp-hz = /bits/ 64 <134000000>; - }; - opp03 { - opp-hz = /bits/ 64 <167000000>; - }; - }; - - bus_disp1_fimd_opp_table: opp_table13 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <120000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_disp1_opp_table: opp_table14 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <120000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - opp02 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_gscl_opp_table: opp_table15 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <150000000>; - }; - opp01 { - opp-hz = /bits/ 64 <200000000>; - }; - opp02 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_mscl_opp_table: opp_table16 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <84000000>; - }; - opp01 { - opp-hz = /bits/ 64 <167000000>; - }; - opp02 { - opp-hz = /bits/ 64 <222000000>; - }; - opp03 { - opp-hz = /bits/ 64 <333000000>; - }; - opp04 { - opp-hz = /bits/ 64 <400000000>; - }; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0>; - #include "exynos5420-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" - }; - cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" - }; - gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - #include "exynos5420-trip-points.dtsi" - }; - }; -}; - -&dp { - clocks = <&clock CLK_DP1>; - clock-names = "dp"; - phys = <&dp_phy>; - phy-names = "dp"; - power-domains = <&disp_pd>; -}; - -&fimd { - compatible = "samsung,exynos5420-fimd"; - clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&disp_pd>; - iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; - iommu-names = "m0", "m1"; -}; - -&i2c_0 { - clocks = <&clock CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; -}; - -&i2c_1 { - clocks = <&clock CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; -}; - -&i2c_2 { - clocks = <&clock CLK_I2C2>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; -}; - -&i2c_3 { - clocks = <&clock CLK_I2C3>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; -}; - -&hsi2c_4 { - clocks = <&clock CLK_USI0>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_hs_bus>; -}; - -&hsi2c_5 { - clocks = <&clock CLK_USI1>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hs_bus>; -}; - -&hsi2c_6 { - clocks = <&clock CLK_USI2>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hs_bus>; -}; - -&hsi2c_7 { - clocks = <&clock CLK_USI3>; - clock-names = "hsi2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_hs_bus>; -}; - -&mct { - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; -}; - -&pwm { - clocks = <&clock CLK_PWM>; - clock-names = "timers"; -}; - -&rtc { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; -}; - -&serial_0 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_1 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_2 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&serial_3 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; -}; - -&sss { - clocks = <&clock CLK_SSS>; - clock-names = "secss"; -}; - -&usbdrd3_0 { - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; -}; - -&usbdrd_phy0 { - clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbdrd3_1 { - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; -}; - -&usbdrd_dwc3_1 { - interrupts = ; -}; - -&usbdrd_phy1 { - clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; -}; - -&usbhost1 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usbhost2 { - clocks = <&clock CLK_USBH20>; - clock-names = "usbhost"; -}; - -&usb2_phy { - clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; - clock-names = "phy", "ref"; - samsung,sysreg-phandle = <&sysreg_system_controller>; - samsung,pmureg-phandle = <&pmu_system_controller>; -}; - -&watchdog { - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -#include "exynos5420-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5422-cpus.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5422-cpus.dtsi deleted file mode 100644 index bf3c6f1ec..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -/* - * SAMSUNG EXYNOS5422 SoC cpu device tree source - * - * Copyright (c) 2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This file provides desired ordering for Exynos5422: CPU[0123] being the A7. - * - * The Exynos5420, 5422 and 5800 actually share the same CPU configuration - * but particular boards choose different booting order. - * - * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 - * booting cluster (big or LITTLE) is chosen by IROM code by reading - * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting - * from the LITTLE: Cortex-A7. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clocks = <&clock CLK_KFC_CLK>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clock-frequency = <1000000000>; - cci-control-port = <&cci_control0>; - operating-points-v2 = <&cluster_a7_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <11>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu4: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - clocks = <&clock CLK_ARM_CLK>; - reg = <0x0>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <15>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu5: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <15>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu6: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <15>; - #cooling-cells = <2>; /* min followed by max */ - }; - - cpu7: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - clock-frequency = <1800000000>; - cci-control-port = <&cci_control1>; - operating-points-v2 = <&cluster_a15_opp_table>; - cooling-min-level = <0>; - cooling-max-level = <15>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi deleted file mode 100644 index 9493923ec..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Hardkernel Odroid XU3 Audio Codec device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/ { - sound: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "Odroid-XU3"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Speakers", "Speakers"; - simple-audio-card,routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN1", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR"; - - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - - simple-audio-card,cpu { - sound-dai = <&i2s0 0>; - system-clock-frequency = <19200000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&max98090>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - }; - }; -}; - -&hsi2c_5 { - status = "okay"; - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpx3>; - interrupts = <2 0>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi deleted file mode 100644 index 246d29855..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ /dev/null @@ -1,614 +0,0 @@ -/* - * Hardkernel Odroid XU3 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2015 Lukasz Majewski - * Anand Moon - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include "exynos5800.dtsi" -#include "exynos5422-cpus.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x7EA00000>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - firmware@02073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_nrst_pin>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 0 20972 0>; - cooling-min-state = <0>; - cooling-max-state = <3>; - #cooling-cells = <2>; - cooling-levels = <0 130 170 230>; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - /* - * Exynos542x supports only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu_alert2 - */ - cpu_alert3: cpu-alert-3 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert4: cpu-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - /* - * When reaching cpu_alert3, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * be: 1600 MHz and 1100 MHz. - */ - map3 { - trip = <&cpu_alert3>; - cooling-device = <&cpu0 0 2>; - }; - map4 { - trip = <&cpu_alert3>; - cooling-device = <&cpu4 0 2>; - }; - - /* - * When reaching cpu_alert4, reduce CPU - * further, down to 600 MHz (11 steps for big, - * 7 steps for LITTLE). - */ - map5 { - trip = <&cpu_alert4>; - cooling-device = <&cpu0 3 7>; - }; - map6 { - trip = <&cpu_alert4>; - cooling-device = <&cpu4 3 11>; - }; - }; - }; - }; -}; - -&bus_wcore { - devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, - <&nocp_mem1_0>, <&nocp_mem1_1>; - vdd-supply = <&buck3_reg>; - exynos,saturation-ratio = <100>; - status = "okay"; -}; - -&bus_noc { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys_apb { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_fsys2 { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gen { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_peri { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_g2d_acp { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_jpeg_apb { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1_fimd { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_disp1 { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_gscl_scaler { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&bus_mscl { - devfreq = <&bus_wcore>; - status = "okay"; -}; - -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FIN_PLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <19200000>; -}; - -&cpu0 { - cpu-supply = <&buck6_reg>; -}; - -&cpu4 { - cpu-supply = <&buck2_reg>; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - vdd-supply = <&ldo6_reg>; -}; - -&hsi2c_4 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - samsung,s2mps11-acokb-ground; - - interrupt-parent = <&gpx0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&s2mps11_irq>; - - s2mps11_osc: clocks { - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vddq_mmc0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "tsp_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo18_reg: LDO18 { - regulator-name = "vdd_emmc_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "tsp_io"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo26_reg: LDO26 { - regulator-name = "vdd_ldo26"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c_2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; -}; - -&mmc_0 { - status = "okay"; - mmc-pwrseq = <&emmc_pwrseq>; - cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - vmmc-supply = <&ldo18_reg>; - vqmmc-supply = <&ldo3_reg>; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; -}; - -&nocp_mem0_0 { - status = "okay"; -}; - -&nocp_mem0_1 { - status = "okay"; -}; - -&nocp_mem1_0 { - status = "okay"; -}; - -&nocp_mem1_1 { - status = "okay"; -}; - -&pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - s2mps11_irq: s2mps11-irq { - samsung,pins = "gpx0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - emmc_nrst_pin: emmc-nrst { - samsung,pins = "gpd1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo7_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo7_reg>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -/* usbdrd_dwc3_1 mode customized in each board */ - -&usbdrd3_0 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; - -&usbdrd3_1 { - vdd33-supply = <&ldo9_reg>; - vdd10-supply = <&ldo11_reg>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts deleted file mode 100644 index 03fa88c45..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Hardkernel Odroid XU3-Lite board device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5422-odroidxu3-common.dtsi" -#include "exynos5422-odroidxu3-audio.dtsi" -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU3 Lite"; - compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3.dts deleted file mode 100644 index 9ed6564ac..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Hardkernel Odroid XU3 board device tree source - * - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5422-odroidxu3-common.dtsi" -#include "exynos5422-odroidxu3-audio.dtsi" -#include "exynos54xx-odroidxu-leds.dtsi" - -/ { - model = "Hardkernel Odroid XU3"; - compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; -}; - -&i2c_0 { - status = "okay"; - - /* A15 cluster: VDD_ARM */ - ina231@40 { - compatible = "ti,ina231"; - reg = <0x40>; - shunt-resistor = <10000>; - }; - - /* memory: VDD_MEM */ - ina231@41 { - compatible = "ti,ina231"; - reg = <0x41>; - shunt-resistor = <10000>; - }; - - /* GPU: VDD_G3D */ - ina231@44 { - compatible = "ti,ina231"; - reg = <0x44>; - shunt-resistor = <10000>; - }; - - /* A7 cluster: VDD_KFC */ - ina231@45 { - compatible = "ti,ina231"; - reg = <0x45>; - shunt-resistor = <10000>; - }; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 1 -- Green LED - * PWM 2 -- Blue LED - * PWM 3 -- on MIPI connector for backlight - */ - pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "peripheral"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu4.dts deleted file mode 100644 index 2faf88627..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Hardkernel Odroid XU4 board device tree source - * - * Copyright (c) 2015 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5422-odroidxu3-common.dtsi" - -/ { - model = "Hardkernel Odroid XU4"; - compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \ - "samsung,exynos5"; - - pwmleds { - compatible = "pwm-leds"; - - blueled { - label = "blue:heartbeat"; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max_brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&pwm { - /* - * PWM 0 -- fan - * PWM 2 -- Blue LED - */ - pinctrl-0 = <&pwm0_out &pwm2_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>, <2>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5440-sd5v1.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5440-sd5v1.dts deleted file mode 100644 index ad6f533b3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * SAMSUNG SD5v1 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5440.dtsi" - -/ { - model = "SAMSUNG SD5v1 board based on EXYNOS5440"; - compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5"; - - chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; - }; - - /* FIXME: set reg property with correct start address and size */ - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; - }; - }; - - spi { - status = "disabled"; - }; - -}; - -&gmac { - fixed_phy; - phy_addr = <1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5440-ssdk5440.dts deleted file mode 100644 index 92bd2c6f7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ /dev/null @@ -1,84 +0,0 @@ -/* - * SAMSUNG SSDK5440 board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -#include "exynos5440.dtsi" -#include - -/ { - model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; - compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5"; - - chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; - }; - - /* FIXME: set reg property with correct start address and size */ - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; - }; - }; -}; - -&pcie_0 { - reset-gpio = <&pin_ctrl 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie_1 { - reset-gpio = <&pin_ctrl 22 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi_0 { - flash: w25q128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128"; - spi-max-frequency = <15625000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@00000 { - label = "BootLoader"; - reg = <0x60000 0x80000>; - read-only; - }; - - partition@e0000 { - label = "Recovery-Kernel"; - reg = <0xe0000 0x300000>; - read-only; - }; - - partition@3e0000 { - label = "CRAM-FS"; - reg = <0x3e0000 0x700000>; - read-only; - }; - - partition@ae0000 { - label = "User-Data"; - reg = <0xae0000 0x520000>; - }; - - }; - -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi deleted file mode 100644 index 7b2fba0ae..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Device tree sources for Exynos5440 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <5>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <0x5d2d>; -samsung,tmu_min_efuse_value = <16>; -samsung,tmu_max_efuse_value = <76>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <70>; -samsung,tmu_default_temp_offset = <25>; -samsung,tmu_cal_type = ; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5440-trip-points.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5440-trip-points.dtsi deleted file mode 100644 index 356e963ed..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5440-trip-points.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Device tree sources for default Exynos5440 thermal zone definition - * - * Copyright (c) 2014 Lukasz Majewski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -polling-delay-passive = <0>; -polling-delay = <0>; -trips { - cpu-alert-0 { - temperature = <100000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "active"; - }; - cpu-crit-0 { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5440.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5440.dtsi deleted file mode 100644 index e6bffd13c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5440.dtsi +++ /dev/null @@ -1,324 +0,0 @@ -/* - * SAMSUNG EXYNOS5440 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -/ { - compatible = "samsung,exynos5440", "samsung,exynos5"; - - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &serial_0; - serial1 = &serial_1; - spi0 = &spi_0; - tmuctrl0 = &tmuctrl_0; - tmuctrl1 = &tmuctrl_1; - tmuctrl2 = &tmuctrl_2; - }; - - clock: clock-controller@160000 { - compatible = "samsung,exynos5440-clock"; - reg = <0x160000 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@2E0000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2E1000 0x1000>, - <0x2E2000 0x1000>, - <0x2E4000 0x2000>, - <0x2E6000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 52 4>, - <0 53 4>, - <0 54 4>, - <0 55 4>; - }; - - timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - clock-frequency = <50000000>; - }; - - cpufreq@160000 { - compatible = "samsung,exynos5440-cpufreq"; - reg = <0x160000 0x1000>; - interrupts = <0 57 0>; - operating-points = < - /* KHz uV */ - 1500000 1100000 - 1400000 1075000 - 1300000 1050000 - 1200000 1025000 - 1100000 1000000 - 1000000 975000 - 900000 950000 - 800000 925000 - >; - }; - - serial_0: serial@B0000 { - compatible = "samsung,exynos4210-uart"; - reg = <0xB0000 0x1000>; - interrupts = <0 2 0>; - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; - clock-names = "uart", "clk_uart_baud0"; - }; - - serial_1: serial@C0000 { - compatible = "samsung,exynos4210-uart"; - reg = <0xC0000 0x1000>; - interrupts = <0 3 0>; - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; - clock-names = "uart", "clk_uart_baud0"; - }; - - spi_0: spi@D0000 { - compatible = "samsung,exynos5440-spi"; - reg = <0xD0000 0x100>; - interrupts = <0 4 0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,spi-src-clk = <0>; - num-cs = <1>; - clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; - clock-names = "spi", "spi_busclk0"; - }; - - pin_ctrl: pinctrl@E0000 { - compatible = "samsung,exynos5440-pinctrl"; - reg = <0xE0000 0x1000>; - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, - <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>; - interrupt-controller; - #interrupt-cells = <2>; - #gpio-cells = <2>; - - fan: fan { - samsung,exynos5440-pin-function = <1>; - }; - - hdd_led0: hdd_led0 { - samsung,exynos5440-pin-function = <2>; - }; - - hdd_led1: hdd_led1 { - samsung,exynos5440-pin-function = <3>; - }; - - uart1: uart1 { - samsung,exynos5440-pin-function = <4>; - }; - }; - - i2c@F0000 { - compatible = "samsung,exynos5440-i2c"; - reg = <0xF0000 0x1000>; - interrupts = <0 5 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_B_125>; - clock-names = "i2c"; - }; - - i2c@100000 { - compatible = "samsung,exynos5440-i2c"; - reg = <0x100000 0x1000>; - interrupts = <0 6 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_B_125>; - clock-names = "i2c"; - }; - - watchdog@110000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x110000 0x1000>; - interrupts = <0 1 0>; - clocks = <&clock CLK_B_125>; - clock-names = "watchdog"; - }; - - gmac: ethernet@00230000 { - compatible = "snps,dwmac-3.70a"; - reg = <0x00230000 0x8000>; - interrupt-parent = <&gic>; - interrupts = <0 31 4>; - interrupt-names = "macirq"; - phy-mode = "sgmii"; - clocks = <&clock CLK_GMAC0>; - clock-names = "stmmaceth"; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - }; - - rtc@130000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x130000 0x1000>; - interrupts = <0 17 0>, <0 16 0>; - clocks = <&clock CLK_B_125>; - clock-names = "rtc"; - }; - - tmuctrl_0: tmuctrl@160118 { - compatible = "samsung,exynos5440-tmu"; - reg = <0x160118 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - tmuctrl_1: tmuctrl@16011C { - compatible = "samsung,exynos5440-tmu"; - reg = <0x16011C 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - tmuctrl_2: tmuctrl@160120 { - compatible = "samsung,exynos5440-tmu"; - reg = <0x160120 0x230>, <0x160368 0x10>; - interrupts = <0 58 0>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmuctrl_0>; - #include "exynos5440-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmuctrl_1>; - #include "exynos5440-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmuctrl_2>; - #include "exynos5440-trip-points.dtsi" - }; - }; - - sata@210000 { - compatible = "snps,exynos5440-ahci"; - reg = <0x210000 0x10000>; - interrupts = <0 30 0>; - clocks = <&clock CLK_SATA>; - clock-names = "sata"; - }; - - ohci@220000 { - compatible = "samsung,exynos5440-ohci"; - reg = <0x220000 0x1000>; - interrupts = <0 29 0>; - clocks = <&clock CLK_USB>; - clock-names = "usbhost"; - }; - - ehci@221000 { - compatible = "samsung,exynos5440-ehci"; - reg = <0x221000 0x1000>; - interrupts = <0 29 0>; - clocks = <&clock CLK_USB>; - clock-names = "usbhost"; - }; - - pcie_0: pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000 - 0x270000 0x1000 - 0x271000 0x40>; - interrupts = <0 20 0>, <0 21 0>, <0 22 0>; - clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 53>; - num-lanes = <4>; - status = "disabled"; - }; - - pcie_1: pcie@2a0000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x2a0000 0x1000 - 0x272000 0x1000 - 0x271040 0x40>; - interrupts = <0 23 0>, <0 24 0>, <0 25 0>; - clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 56>; - num-lanes = <4>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi deleted file mode 100644 index 0ed302066..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Hardkernel Odroid XU/XU3 LED device tree source - * - * Copyright (c) 2015,2016 Krzysztof Kozlowski - * Copyright (c) 2014 Collabora Ltd. - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include - -/ { - pwmleds { - compatible = "pwm-leds"; - - greenled { - label = "green:mmc0"; - pwms = <&pwm 1 2000000 0>; - pwm-names = "pwm1"; - /* - * Green LED is much brighter than the others - * so limit its max brightness - */ - max_brightness = <127>; - linux,default-trigger = "mmc0"; - }; - - blueled { - label = "blue:heartbeat"; - pwms = <&pwm 2 2000000 0>; - pwm-names = "pwm2"; - max_brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpioleds { - compatible = "gpio-leds"; - redled { - label = "red:microSD"; - gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc1"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos54xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos54xx.dtsi deleted file mode 100644 index 9d31cdce1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos54xx.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Samsung's Exynos54xx SoC series common device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2016 Krzysztof Kozlowski - * - * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific - * Exynos 54xx SoCs should include this file and customize it further - * (e.g. with clocks). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "exynos5.dtsi" - -/ { - compatible = "samsung,exynos5"; - - aliases { - i2c4 = &hsi2c_4; - i2c5 = &hsi2c_5; - i2c6 = &hsi2c_6; - i2c7 = &hsi2c_7; - usbdrdphy0 = &usbdrd_phy0; - usbdrdphy1 = &usbdrd_phy1; - }; - - soc: soc { - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; - - mct: mct@101c0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101c0000 0xb00>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, - <8>, <9>, <10>, <11>; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &combiner 23 3>, - <1 &combiner 23 4>, - <2 &combiner 25 2>, - <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; - }; - }; - - watchdog: watchdog@101d0000 { - compatible = "samsung,exynos5420-wdt"; - reg = <0x101d0000 0x100>; - interrupts = <0 42 0>; - }; - - sss: sss@10830000 { - compatible = "samsung,exynos4210-secss"; - reg = <0x10830000 0x300>; - interrupts = <0 112 0>; - }; - - /* i2c_0-3 are defined in exynos5.dtsi */ - hsi2c_4: i2c@12ca0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12ca0000 0x1000>; - interrupts = <0 60 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_5: i2c@12cb0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cb0000 0x1000>; - interrupts = <0 61 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_6: i2c@12cc0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cc0000 0x1000>; - interrupts = <0 62 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsi2c_7: i2c@12cd0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12cd0000 0x1000>; - interrupts = <0 63 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usbdrd3_0: usb3-0 { - compatible = "samsung,exynos5250-dwusb3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_0: dwc3@12000000 { - compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy0: phy@12100000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12100000 0x100>; - #phy-cells = <1>; - }; - - usbdrd3_1: usb3-1 { - compatible = "samsung,exynos5250-dwusb3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbdrd_dwc3_1: dwc3@12400000 { - compatible = "snps,dwc3"; - reg = <0x12400000 0x10000>; - phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd_phy1: phy@12500000 { - compatible = "samsung,exynos5420-usbdrd-phy"; - reg = <0x12500000 0x100>; - #phy-cells = <1>; - }; - - usbhost2: usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; - }; - }; - - usbhost1: usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2_phy 1>; - }; - }; - - usb2_phy: phy@12130000 { - compatible = "samsung,exynos5250-usb2-phy"; - reg = <0x12130000 0x100>; - #phy-cells = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5800-peach-pi.dts b/software/linux/kernel/arch/arm/boot/dts/exynos5800-peach-pi.dts deleted file mode 100644 index 01f466816..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ /dev/null @@ -1,1062 +0,0 @@ -/* - * Google Peach Pi Rev 10+ board device tree source - * - * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "exynos5800.dtsi" -#include "exynos5420-cpus.dtsi" -#include "exynos-mfc-reserved-memory.dtsi" - -/ { - model = "Google Peach Pi Rev 10+"; - - compatible = "google,pi-rev16", - "google,pi-rev15", "google,pi-rev14", - "google,pi-rev13", "google,pi-rev12", - "google,pi-rev11", "google,pi-rev10", - "google,pi", "google,peach", "samsung,exynos5800", - "samsung,exynos5"; - - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - power-supply = <&tps65090_fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x80000000>; - }; - - sound { - compatible = "google,snow-audio-max98091"; - - samsung,model = "Peach-Pi-I2S-MAX98091"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98091>; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - - vbat: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - regulator-always-on; - }; - - panel: panel { - compatible = "auo,b133htn01"; - power-supply = <&tps65090_fet6>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - - mmc1_pwrseq: mmc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - clocks = <&max77802 MAX77802_CLK_32K_CP>; - clock-names = "ext_clock"; - }; -}; - -&adc { - status = "okay"; - vdd-supply = <&ldo9_reg>; -}; - -&cpu0 { - cpu-supply = <&buck2_reg>; -}; - -&cpu4 { - cpu-supply = <&buck6_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; - - ports { - port { - dp_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hsi2c_4 { - status = "okay"; - clock-frequency = <400000>; - - max77802: max77802-pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&gpx3>; - interrupts = <1 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; - wakeup-source; - reg = <0x9>; - #clock-cells = <1>; - - inb1-supply = <&tps65090_dcdc2>; - inb2-supply = <&tps65090_dcdc1>; - inb3-supply = <&tps65090_dcdc2>; - inb4-supply = <&tps65090_dcdc2>; - inb5-supply = <&tps65090_dcdc1>; - inb6-supply = <&tps65090_dcdc2>; - inb7-supply = <&tps65090_dcdc1>; - inb8-supply = <&tps65090_dcdc1>; - inb9-supply = <&tps65090_dcdc1>; - inb10-supply = <&tps65090_dcdc1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&tps65090_dcdc2>; - inl7-supply = <&buck9_reg>; - inl9-supply = <&tps65090_dcdc2>; - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2v"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_1v2_2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_1v8_3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - vqmmc_sdcard: ldo4_reg: LDO4 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_1v8_5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_1v8_6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_1v8_7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo_19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "ldo_20"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "ldo_21"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "ldo_23"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - ldo24_reg: LDO24 { - regulator-name = "ldo_24"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "ldo_25"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "ldo_26"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo_27"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo_28"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo_29"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "ldo_32"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo_33"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo_34"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo_35"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <400000>; - - max98091: codec@10 { - compatible = "maxim,max98091"; - reg = <0x10>; - interrupts = <2 0>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98091_irq>; - clocks = <&pmu_system_controller 0>; - clock-names = "mclk"; - }; - - light-sensor@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - vcc-supply = <&tps65090_fet5>; - }; -}; - -&hsi2c_8 { - status = "okay"; - clock-frequency = <333000>; - /* Atmel mXT540S */ - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; /* GPIO 3 */ - }; -}; - -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-highspeed; - non-removable; - clock-frequency = <800000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; - bus-width = <8>; -}; - -&mmc_1 { - status = "okay"; - num-slots = <1>; - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <1>; - samsung,dw-mshc-sdr-timing = <0 1>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, - <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>; - bus-width = <4>; - cap-sd-highspeed; - mmc-pwrseq = <&mmc1_pwrseq>; - vqmmc-supply = <&buck10_reg>; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; -}; - - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&mask_tpm_reset>; - - wifi_en: wifi-en { - samsung,pins = "gpx0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max98091_irq: max98091-irq { - samsung,pins = "gpx0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { - samsung,pins = "gpx0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - samsung,pin-val = <0>; - }; - - tpm_irq: tpm-irq { - samsung,pins = "gpx1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - trackpad_irq: trackpad-irq { - samsung,pins = "gpx1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - dp_hpd_gpio: dp_hpd_gpio { - samsung,pins = "gpx2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - max77802_irq: max77802-irq { - samsung,pins = "gpx3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1 { - samsung,pins = "gpy7-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_1 { - /* Adjust WiFi drive strengths lower for EMI */ - sd1_clk: sd1-clk { - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = ; - }; -}; - -&pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = ; - }; - - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { - samsung,pins = "gpb1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gph0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_selb: pmic-selb { - samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", - "gph0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_FIN_PLL>; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&spi_2 { - status = "okay"; - num-cs = <1>; - samsung,spi-src-clk = <0>; - cs-gpios = <&gpb1 2 GPIO_ACTIVE_HIGH>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_spi_cs &ec_irq>; - reg = <0>; - spi-max-frequency = <3125000>; - google,has-vbc-nvram; - - controller-data { - samsung,spi-feedback-delay = <1>; - }; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - sbs,i2c-retry-count = <2>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&tps65090_dcdc1>; - infet3-supply = <&tps65090_dcdc2>; - infet4-supply = <&tps65090_dcdc2>; - infet5-supply = <&tps65090_dcdc2>; - infet6-supply = <&tps65090_dcdc2>; - infet7-supply = <&tps65090_dcdc1>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - tps65090_dcdc1: dcdc1 { - ti,enable-ext-control; - }; - tps65090_dcdc2: dcdc2 { - ti,enable-ext-control; - }; - tps65090_dcdc3: dcdc3 { - ti,enable-ext-control; - }; - tps65090_fet1: fet1 { - regulator-name = "vcd_led"; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - }; - tps65090_fet3: fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - }; - tps65090_fet4: fet4 { - regulator-name = "sdcard"; - regulator-always-on; - }; - tps65090_fet5: fet5 { - regulator-name = "camout"; - regulator-always-on; - }; - tps65090_fet6: fet6 { - regulator-name = "lcd_vdd"; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - }; - tps65090_ldo1: ldo1 { - }; - tps65090_ldo2: ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; -}; - -&serial_3 { - status = "okay"; -}; - -&tmu_cpu0 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu1 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu2 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_cpu3 { - vtmu-supply = <&ldo10_reg>; -}; - -&tmu_gpu { - vtmu-supply = <&ldo10_reg>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; - -/* - * Use longest HW watchdog in SoC (32 seconds) since the hardware - * watchdog provides no debugging information (compared to soft/hard - * lockup detectors) and so should be last resort. - */ -&watchdog { - timeout-sec = <32>; -}; - -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/exynos5800.dtsi b/software/linux/kernel/arch/arm/boot/dts/exynos5800.dtsi deleted file mode 100644 index 821301680..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/exynos5800.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -/* - * SAMSUNG EXYNOS5800 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file. - * EXYNOS5800 based board files can include this file and provide - * values for board specfic bindings. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "exynos5420.dtsi" - -/ { - compatible = "samsung,exynos5800", "samsung,exynos5"; -}; - -&clock { - compatible = "samsung,exynos5800-clock"; -}; - -&cluster_a15_opp_table { - opp@1700000000 { - opp-microvolt = <1250000>; - }; - opp@1600000000 { - opp-microvolt = <1250000>; - }; - opp@1500000000 { - opp-microvolt = <1100000>; - }; - opp@1400000000 { - opp-microvolt = <1100000>; - }; - opp@1300000000 { - opp-microvolt = <1100000>; - }; - opp@1200000000 { - opp-microvolt = <1000000>; - }; - opp@1100000000 { - opp-microvolt = <1000000>; - }; - opp@1000000000 { - opp-microvolt = <1000000>; - }; - opp@900000000 { - opp-microvolt = <1000000>; - }; - opp@800000000 { - opp-microvolt = <900000>; - }; - opp@700000000 { - opp-microvolt = <900000>; - }; - opp@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; - opp@500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; - opp@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; -}; - -&cluster_a7_opp_table { - opp@1300000000 { - opp-microvolt = <1250000>; - }; - opp@1200000000 { - opp-microvolt = <1250000>; - }; - opp@1100000000 { - opp-microvolt = <1250000>; - }; - opp@1000000000 { - opp-microvolt = <1100000>; - }; - opp@900000000 { - opp-microvolt = <1100000>; - }; - opp@800000000 { - opp-microvolt = <1100000>; - }; - opp@700000000 { - opp-microvolt = <1000000>; - }; - opp@600000000 { - opp-microvolt = <1000000>; - }; - opp@500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <140000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <140000>; - }; - opp@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; - opp@200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; - clock-latency-ns = <140000>; - }; -}; - -&mfc { - compatible = "samsung,mfc-v8"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/fusionx.infinity2m-spinand-ssc011a-s01a-fusionx.dts b/software/linux/kernel/arch/arm/boot/dts/fusionx.infinity2m-spinand-ssc011a-s01a-fusionx.dts new file mode 100644 index 000000000..e69de29bb diff --git a/software/linux/kernel/arch/arm/boot/dts/ge863-pro3.dtsi b/software/linux/kernel/arch/arm/boot/dts/ge863-pro3.dtsi deleted file mode 100644 index 4aee5cc75..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ge863-pro3.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3 - * - * Copyright (C) 2012 Telit, - * 2012 Fabio Porcedda - * - * Licensed under GPLv2 or later. - */ - -#include "at91sam9260.dtsi" - -/ { - clocks { - main_xtal { - clock-frequency = <6000000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - boot@0 { - label = "boot"; - reg = <0x0 0x7c0000>; - }; - - root@07c0000 { - label = "root"; - reg = <0x7c0000 0x7840000>; - }; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hi3519-demb.dts b/software/linux/kernel/arch/arm/boot/dts/hi3519-demb.dts deleted file mode 100644 index 6991ab694..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hi3519-demb.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - */ - -/dts-v1/; -#include "hi3519.dtsi" - -/ { - model = "HiSilicon HI3519 DEMO Board"; - compatible = "hisilicon,hi3519"; - - aliases { - serial0 = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&dual_timer0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hi3519.dtsi b/software/linux/kernel/arch/arm/boot/dts/hi3519.dtsi deleted file mode 100644 index 5729ecfcd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hi3519.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - */ - -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - }; - }; - - gic: interrupt-controller@10300000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10301000 0x1000>, <0x10302000 0x1000>; - }; - - clk_3m: clk_3m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3000000>; - }; - - crg: clock-reset-controller@12010000 { - compatible = "hisilicon,hi3519-crg"; - #clock-cells = <1>; - #reset-cells = <2>; - reg = <0x12010000 0x10000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - uart0: serial@12100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12100000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART0_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - uart1: serial@12101000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12101000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART1_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - uart2: serial@12102000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12102000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART2_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - uart3: serial@12103000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12103000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART3_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - uart4: serial@12104000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12104000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_UART4_CLK>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - dual_timer0: timer@12000000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12000000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - dual_timer1: timer@12001000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12001000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - dual_timer2: timer@12002000 { - compatible = "arm,sp804", "arm,primecell"; - interrupts = , - ; - reg = <0x12002000 0x1000>; - clocks = <&clk_3m>; - clock-names = "apb_pclk"; - status = "disable"; - }; - - spi_bus0: spi@12120000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12120000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI0_CLK>; - clock-names = "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - spi_bus1: spi@12121000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12121000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI1_CLK>; - clock-names = "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - spi_bus2: spi@12122000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x12122000 0x1000>; - interrupts = ; - clocks = <&crg HI3519_SPI2_CLK>; - clock-names = "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - - sysctrl: system-controller@12020000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12020000 0x1000>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&sysctrl>; - offset = <0x4>; - mask = <0xdeadbeef>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hi3620-hi4511.dts b/software/linux/kernel/arch/arm/boot/dts/hi3620-hi4511.dts deleted file mode 100644 index a579fbf13..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hi3620-hi4511.dts +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Copyright (C) 2012-2013 Linaro Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; - -#include "hi3620.dtsi" - -/ { - model = "Hisilicon Hi4511 Development Board"; - compatible = "hisilicon,hi3620-hi4511"; - - chosen { - bootargs = "root=/dev/ram0"; - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - amba { - dual_timer0: dual_timer@800000 { - status = "ok"; - }; - - uart0: uart@b00000 { /* console */ - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; - pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; - status = "ok"; - }; - - uart1: uart@b01000 { /* modem */ - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; - pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; - status = "ok"; - }; - - uart2: uart@b02000 { /* audience */ - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; - status = "ok"; - }; - - uart3: uart@b03000 { - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; - status = "ok"; - }; - - uart4: uart@b04000 { - pinctrl-names = "default", "idle"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; - status = "ok"; - }; - - pmx0: pinmux@803000 { - pinctrl-names = "default"; - pinctrl-0 = <&board_pmx_pins>; - - board_pmx_pins: board_pmx_pins { - pinctrl-single,pins = < - 0x008 0x0 /* GPIO -- eFUSE_DOUT */ - 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ - >; - }; - uart0_pmx_func: uart0_pmx_func { - pinctrl-single,pins = < - 0x0f0 0x0 - 0x0f4 0x0 /* UART0_RX & UART0_TX */ - >; - }; - uart0_pmx_idle: uart0_pmx_idle { - pinctrl-single,pins = < - /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ - 0x0f4 0x1 /* UART0_RX & UART0_TX */ - >; - }; - uart1_pmx_func: uart1_pmx_func { - pinctrl-single,pins = < - 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ - 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ - >; - }; - uart1_pmx_idle: uart1_pmx_idle { - pinctrl-single,pins = < - 0x0f8 0x1 /* GPIO (IOMG61) */ - 0x0fc 0x1 /* GPIO (IOMG62) */ - >; - }; - uart2_pmx_func: uart2_pmx_func { - pinctrl-single,pins = < - 0x104 0x2 /* UART2_RXD (IOMG96) */ - 0x108 0x2 /* UART2_TXD (IOMG64) */ - >; - }; - uart2_pmx_idle: uart2_pmx_idle { - pinctrl-single,pins = < - 0x104 0x1 /* GPIO (IOMG96) */ - 0x108 0x1 /* GPIO (IOMG64) */ - >; - }; - uart3_pmx_func: uart3_pmx_func { - pinctrl-single,pins = < - 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ - 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ - >; - }; - uart3_pmx_idle: uart3_pmx_idle { - pinctrl-single,pins = < - 0x160 0x1 /* GPIO (IOMG85) */ - 0x164 0x1 /* GPIO (IOMG86) */ - >; - }; - uart4_pmx_func: uart4_pmx_func { - pinctrl-single,pins = < - 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ - 0x16c 0x0 /* UART4_RXD (IOMG88) */ - 0x170 0x0 /* UART4_TXD (IOMG93) */ - >; - }; - uart4_pmx_idle: uart4_pmx_idle { - pinctrl-single,pins = < - 0x168 0x1 /* GPIO (IOMG87) */ - 0x16c 0x1 /* GPIO (IOMG88) */ - 0x170 0x1 /* GPIO (IOMG93) */ - >; - }; - i2c0_pmx_func: i2c0_pmx_func { - pinctrl-single,pins = < - 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ - >; - }; - i2c0_pmx_idle: i2c0_pmx_idle { - pinctrl-single,pins = < - 0x0b4 0x1 /* GPIO (IOMG45) */ - >; - }; - i2c1_pmx_func: i2c1_pmx_func { - pinctrl-single,pins = < - 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ - >; - }; - i2c1_pmx_idle: i2c1_pmx_idle { - pinctrl-single,pins = < - 0x0b8 0x1 /* GPIO (IOMG46) */ - >; - }; - i2c2_pmx_func: i2c2_pmx_func { - pinctrl-single,pins = < - 0x068 0x0 /* I2C2_SCL (IOMG26) */ - 0x06c 0x0 /* I2C2_SDA (IOMG27) */ - >; - }; - i2c2_pmx_idle: i2c2_pmx_idle { - pinctrl-single,pins = < - 0x068 0x1 /* GPIO (IOMG26) */ - 0x06c 0x1 /* GPIO (IOMG27) */ - >; - }; - i2c3_pmx_func: i2c3_pmx_func { - pinctrl-single,pins = < - 0x050 0x2 /* I2C3_SCL (IOMG20) */ - 0x054 0x2 /* I2C3_SDA (IOMG21) */ - >; - }; - i2c3_pmx_idle: i2c3_pmx_idle { - pinctrl-single,pins = < - 0x050 0x1 /* GPIO (IOMG20) */ - 0x054 0x1 /* GPIO (IOMG21) */ - >; - }; - spi0_pmx_func: spi0_pmx_func { - pinctrl-single,pins = < - 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ - 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ - 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */ - 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */ - 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ - >; - }; - spi0_pmx_idle: spi0_pmx_idle { - pinctrl-single,pins = < - 0x0d4 0x1 /* GPIO (IOMG53) */ - 0x0d8 0x1 /* GPIO (IOMG54) */ - 0x0dc 0x1 /* GPIO (IOMG55) */ - 0x0e0 0x1 /* GPIO (IOMG56) */ - 0x0e4 0x1 /* GPIO (IOMG57) */ - >; - }; - spi1_pmx_func: spi1_pmx_func { - pinctrl-single,pins = < - 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ - 0x0e8 0x0 /* SPI1_DO (IOMG58) */ - 0x0ec 0x0 /* SPI1_CS (IOMG95) */ - >; - }; - spi1_pmx_idle: spi1_pmx_idle { - pinctrl-single,pins = < - 0x184 0x1 /* GPIO (IOMG98) */ - 0x0e8 0x1 /* GPIO (IOMG58) */ - 0x0ec 0x1 /* GPIO (IOMG95) */ - >; - }; - kpc_pmx_func: kpc_pmx_func { - pinctrl-single,pins = < - 0x12c 0x0 /* KEY_IN0 (IOMG73) */ - 0x130 0x0 /* KEY_IN1 (IOMG74) */ - 0x134 0x0 /* KEY_IN2 (IOMG75) */ - 0x10c 0x0 /* KEY_OUT0 (IOMG65) */ - 0x110 0x0 /* KEY_OUT1 (IOMG66) */ - 0x114 0x0 /* KEY_OUT2 (IOMG67) */ - >; - }; - kpc_pmx_idle: kpc_pmx_idle { - pinctrl-single,pins = < - 0x12c 0x1 /* GPIO (IOMG73) */ - 0x130 0x1 /* GPIO (IOMG74) */ - 0x134 0x1 /* GPIO (IOMG75) */ - 0x10c 0x1 /* GPIO (IOMG65) */ - 0x110 0x1 /* GPIO (IOMG66) */ - 0x114 0x1 /* GPIO (IOMG67) */ - >; - }; - gpio_key_func: gpio_key_func { - pinctrl-single,pins = < - 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ - 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ - >; - }; - emmc_pmx_func: emmc_pmx_func { - pinctrl-single,pins = < - 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ - 0x018 0x0 /* NAND_CS3_N (IOMG6) */ - 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ - 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ - 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ - >; - }; - emmc_pmx_idle: emmc_pmx_idle { - pinctrl-single,pins = < - 0x030 0x0 /* GPIO (IOMG12) */ - 0x018 0x1 /* GPIO (IOMG6) */ - 0x024 0x1 /* GPIO (IOMG8) */ - 0x028 0x1 /* GPIO (IOMG9) */ - 0x02c 0x1 /* GPIO (IOMG10) */ - >; - }; - sd_pmx_func: sd_pmx_func { - pinctrl-single,pins = < - 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ - 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ - >; - }; - sd_pmx_idle: sd_pmx_idle { - pinctrl-single,pins = < - 0x0bc 0x1 /* GPIO (IOMG47) */ - 0x0c0 0x1 /* GPIO (IOMG48) */ - >; - }; - nand_pmx_func: nand_pmx_func { - pinctrl-single,pins = < - 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ - 0x010 0x0 /* NAND_CS1_N (IOMG4) */ - 0x014 0x0 /* NAND_CS2_N (IOMG5) */ - 0x018 0x0 /* NAND_CS3_N (IOMG6) */ - 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */ - 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */ - 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ - 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ - 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ - >; - }; - nand_pmx_idle: nand_pmx_idle { - pinctrl-single,pins = < - 0x00c 0x1 /* GPIO (IOMG3) */ - 0x010 0x1 /* GPIO (IOMG4) */ - 0x014 0x1 /* GPIO (IOMG5) */ - 0x018 0x1 /* GPIO (IOMG6) */ - 0x01c 0x1 /* GPIO (IOMG94) */ - 0x020 0x1 /* GPIO (IOMG7) */ - 0x024 0x1 /* GPIO (IOMG8) */ - 0x028 0x1 /* GPIO (IOMG9) */ - 0x02c 0x1 /* GPIO (IOMG10) */ - >; - }; - sdio_pmx_func: sdio_pmx_func { - pinctrl-single,pins = < - 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ - >; - }; - sdio_pmx_idle: sdio_pmx_idle { - pinctrl-single,pins = < - 0x0c4 0x1 /* GPIO (IOMG49) */ - >; - }; - audio_out_pmx_func: audio_out_pmx_func { - pinctrl-single,pins = < - 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ - >; - }; - }; - - pmx1: pinmux@803800 { - pinctrl-names = "default"; - pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins - &board_np_pins &board_ps_pins &kpc_cfg_func - &audio_out_cfg_func>; - board_pu_pins: board_pu_pins { - pinctrl-single,pins = < - 0x014 0 /* GPIO_158 (IOCFG2) */ - 0x018 0 /* GPIO_159 (IOCFG3) */ - 0x01c 0 /* BOOT_MODE0 (IOCFG4) */ - 0x020 0 /* BOOT_MODE1 (IOCFG5) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - }; - board_pd_pins: board_pd_pins { - pinctrl-single,pins = < - 0x038 0 /* eFUSE_DOUT (IOCFG11) */ - 0x150 0 /* ISP_GPIO8 (IOCFG93) */ - 0x154 0 /* ISP_GPIO9 (IOCFG94) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - board_pd_ps_pins: board_pd_ps_pins { - pinctrl-single,pins = < - 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ - 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - board_np_pins: board_np_pins { - pinctrl-single,pins = < - 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - board_ps_pins: board_ps_pins { - pinctrl-single,pins = < - 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ - 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ - >; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - uart0_cfg_func: uart0_cfg_func { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart0_cfg_idle: uart0_cfg_idle { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart1_cfg_func: uart1_cfg_func { - pinctrl-single,pins = < - 0x210 0 /* UART1_CTS (IOCFG140) */ - 0x214 0 /* UART1_RTS (IOCFG141) */ - 0x218 0 /* UART1_RXD (IOCFG142) */ - 0x21c 0 /* UART1_TXD (IOCFG143) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart1_cfg_idle: uart1_cfg_idle { - pinctrl-single,pins = < - 0x210 0 /* UART1_CTS (IOCFG140) */ - 0x214 0 /* UART1_RTS (IOCFG141) */ - 0x218 0 /* UART1_RXD (IOCFG142) */ - 0x21c 0 /* UART1_TXD (IOCFG143) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart2_cfg_func: uart2_cfg_func { - pinctrl-single,pins = < - 0x220 0 /* UART2_CTS (IOCFG144) */ - 0x224 0 /* UART2_RTS (IOCFG145) */ - 0x228 0 /* UART2_RXD (IOCFG146) */ - 0x22c 0 /* UART2_TXD (IOCFG147) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart2_cfg_idle: uart2_cfg_idle { - pinctrl-single,pins = < - 0x220 0 /* GPIO (IOCFG144) */ - 0x224 0 /* GPIO (IOCFG145) */ - 0x228 0 /* GPIO (IOCFG146) */ - 0x22c 0 /* GPIO (IOCFG147) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart3_cfg_func: uart3_cfg_func { - pinctrl-single,pins = < - 0x294 0 /* UART3_CTS (IOCFG173) */ - 0x298 0 /* UART3_RTS (IOCFG174) */ - 0x29c 0 /* UART3_RXD (IOCFG175) */ - 0x2a0 0 /* UART3_TXD (IOCFG176) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart3_cfg_idle: uart3_cfg_idle { - pinctrl-single,pins = < - 0x294 0 /* UART3_CTS (IOCFG173) */ - 0x298 0 /* UART3_RTS (IOCFG174) */ - 0x29c 0 /* UART3_RXD (IOCFG175) */ - 0x2a0 0 /* UART3_TXD (IOCFG176) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - uart4_cfg_func: uart4_cfg_func { - pinctrl-single,pins = < - 0x2a4 0 /* UART4_CTS (IOCFG177) */ - 0x2a8 0 /* UART4_RTS (IOCFG178) */ - 0x2ac 0 /* UART4_RXD (IOCFG179) */ - 0x2b0 0 /* UART4_TXD (IOCFG180) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - i2c0_cfg_func: i2c0_cfg_func { - pinctrl-single,pins = < - 0x17c 0 /* I2C0_SCL (IOCFG103) */ - 0x180 0 /* I2C0_SDA (IOCFG104) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c1_cfg_func: i2c1_cfg_func { - pinctrl-single,pins = < - 0x184 0 /* I2C1_SCL (IOCFG105) */ - 0x188 0 /* I2C1_SDA (IOCFG106) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c2_cfg_func: i2c2_cfg_func { - pinctrl-single,pins = < - 0x118 0 /* I2C2_SCL (IOCFG79) */ - 0x11c 0 /* I2C2_SDA (IOCFG80) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - i2c3_cfg_func: i2c3_cfg_func { - pinctrl-single,pins = < - 0x100 0 /* I2C3_SCL (IOCFG73) */ - 0x104 0 /* I2C3_SDA (IOCFG74) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi0_cfg_func1: spi0_cfg_func1 { - pinctrl-single,pins = < - 0x1d4 0 /* SPI0_CLK (IOCFG125) */ - 0x1d8 0 /* SPI0_DI (IOCFG126) */ - 0x1dc 0 /* SPI0_DO (IOCFG127) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi0_cfg_func2: spi0_cfg_func2 { - pinctrl-single,pins = < - 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ - 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ - 0x1e8 0 /* SPI0_CS2 (IOCFG130 */ - 0x1ec 0 /* SPI0_CS3 (IOCFG131) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi1_cfg_func1: spi1_cfg_func1 { - pinctrl-single,pins = < - 0x1f0 0 /* SPI1_CLK (IOCFG132) */ - 0x1f4 0 /* SPI1_DI (IOCFG133) */ - 0x1f8 0 /* SPI1_DO (IOCFG134) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - spi1_cfg_func2: spi1_cfg_func2 { - pinctrl-single,pins = < - 0x1fc 0 /* SPI1_CS (IOCFG135) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - kpc_cfg_func: kpc_cfg_func { - pinctrl-single,pins = < - 0x250 0 /* KEY_IN0 (IOCFG156) */ - 0x254 0 /* KEY_IN1 (IOCFG157) */ - 0x258 0 /* KEY_IN2 (IOCFG158) */ - 0x230 0 /* KEY_OUT0 (IOCFG148) */ - 0x234 0 /* KEY_OUT1 (IOCFG149) */ - 0x238 0 /* KEY_OUT2 (IOCFG150) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - emmc_cfg_func: emmc_cfg_func { - pinctrl-single,pins = < - 0x0ac 0 /* eMMC_CMD (IOCFG40) */ - 0x0b0 0 /* eMMC_CLK (IOCFG41) */ - 0x058 0 /* NAND_CS3_N (IOCFG19) */ - 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ - 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ - 0x08c 0 /* NAND_DATA8 (IOCFG32) */ - 0x090 0 /* NAND_DATA9 (IOCFG33) */ - 0x094 0 /* NAND_DATA10 (IOCFG34) */ - 0x098 0 /* NAND_DATA11 (IOCFG35) */ - 0x09c 0 /* NAND_DATA12 (IOCFG36) */ - 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ - 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ - 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sd_cfg_func1: sd_cfg_func1 { - pinctrl-single,pins = < - 0x18c 0 /* SD_CLK (IOCFG107) */ - 0x190 0 /* SD_CMD (IOCFG108) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sd_cfg_func2: sd_cfg_func2 { - pinctrl-single,pins = < - 0x194 0 /* SD_DATA0 (IOCFG109) */ - 0x198 0 /* SD_DATA1 (IOCFG110) */ - 0x19c 0 /* SD_DATA2 (IOCFG111) */ - 0x1a0 0 /* SD_DATA3 (IOCFG112) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x70 0xf0>; - }; - nand_cfg_func1: nand_cfg_func1 { - pinctrl-single,pins = < - 0x03c 0 /* NAND_ALE (IOCFG12) */ - 0x040 0 /* NAND_CLE (IOCFG13) */ - 0x06c 0 /* NAND_DATA0 (IOCFG24) */ - 0x070 0 /* NAND_DATA1 (IOCFG25) */ - 0x074 0 /* NAND_DATA2 (IOCFG26) */ - 0x078 0 /* NAND_DATA3 (IOCFG27) */ - 0x07c 0 /* NAND_DATA4 (IOCFG28) */ - 0x080 0 /* NAND_DATA5 (IOCFG29) */ - 0x084 0 /* NAND_DATA6 (IOCFG30) */ - 0x088 0 /* NAND_DATA7 (IOCFG31) */ - 0x08c 0 /* NAND_DATA8 (IOCFG32) */ - 0x090 0 /* NAND_DATA9 (IOCFG33) */ - 0x094 0 /* NAND_DATA10 (IOCFG34) */ - 0x098 0 /* NAND_DATA11 (IOCFG35) */ - 0x09c 0 /* NAND_DATA12 (IOCFG36) */ - 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ - 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ - 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - nand_cfg_func2: nand_cfg_func2 { - pinctrl-single,pins = < - 0x044 0 /* NAND_RE_N (IOCFG14) */ - 0x048 0 /* NAND_WE_N (IOCFG15) */ - 0x04c 0 /* NAND_CS0_N (IOCFG16) */ - 0x050 0 /* NAND_CS1_N (IOCFG17) */ - 0x054 0 /* NAND_CS2_N (IOCFG18) */ - 0x058 0 /* NAND_CS3_N (IOCFG19) */ - 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */ - 0x060 0 /* NAND_BUSY1_N (IOCFG21) */ - 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ - 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ - >; - pinctrl-single,bias-pulldown = <0 2 0 2>; - pinctrl-single,bias-pullup = <1 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - sdio_cfg_func: sdio_cfg_func { - pinctrl-single,pins = < - 0x1a4 0 /* SDIO0_CLK (IOCG113) */ - 0x1a8 0 /* SDIO0_CMD (IOCG114) */ - 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */ - 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */ - 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */ - 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - pinctrl-single,drive-strength = <0x30 0xf0>; - }; - audio_out_cfg_func: audio_out_cfg_func { - pinctrl-single,pins = < - 0x200 0 /* GPIO (IOCFG136) */ - 0x204 0 /* GPIO (IOCFG137) */ - >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - call { - label = "call"; - gpios = <&gpio17 2 0>; - linux,code = <169>; /* KEY_PHONE */ - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hi3620.dtsi b/software/linux/kernel/arch/arm/boot/dts/hi3620.dtsi deleted file mode 100644 index c85d07e6d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hi3620.dtsi +++ /dev/null @@ -1,566 +0,0 @@ -/* - * Hisilicon Ltd. Hi3620 SoC - * - * Copyright (C) 2012-2013 Hisilicon Ltd. - * Copyright (C) 2012-2013 Linaro Ltd. - * - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - pclk: clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "apb_pclk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hi3620-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - amba { - - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0xfc000000 0x2000000>; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x100000 0x100000>; - interrupts = <0 15 4>; - cache-unified; - cache-level = <2>; - }; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - /* gic dist base, gic cpu base */ - reg = <0x1000 0x1000>, <0x100 0x100>; - }; - - sysctrl: system-controller@802000 { - compatible = "hisilicon,sysctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x802000 0x1000>; - reg = <0x802000 0x1000>; - - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - - clock: clock@0 { - compatible = "hisilicon,hi3620-clock"; - reg = <0 0x10000>; - #clock-cells = <1>; - }; - }; - - dual_timer0: dual_timer@800000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x800000 0x1000>; - /* timer00 & timer01 */ - interrupts = <0 0 4>, <0 1 4>; - clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dual_timer1: dual_timer@801000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x801000 0x1000>; - /* timer10 & timer11 */ - interrupts = <0 2 4>, <0 3 4>; - clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dual_timer2: dual_timer@a01000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa01000 0x1000>; - /* timer20 & timer21 */ - interrupts = <0 4 4>, <0 5 4>; - clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dual_timer3: dual_timer@a02000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa02000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 6 4>, <0 7 4>; - clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dual_timer4: dual_timer@a03000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xa03000 0x1000>; - /* timer40 & timer41 */ - interrupts = <0 96 4>, <0 97 4>; - clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer5: timer@600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x600 0x20>; - interrupts = <1 13 0xf01>; - }; - - uart0: uart@b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb00000 0x1000>; - interrupts = <0 20 4>; - clocks = <&clock HI3620_UARTCLK0>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart1: uart@b01000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb01000 0x1000>; - interrupts = <0 21 4>; - clocks = <&clock HI3620_UARTCLK1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart2: uart@b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb02000 0x1000>; - interrupts = <0 22 4>; - clocks = <&clock HI3620_UARTCLK2>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart3: uart@b03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb03000 0x1000>; - interrupts = <0 23 4>; - clocks = <&clock HI3620_UARTCLK3>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart4: uart@b04000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb04000 0x1000>; - interrupts = <0 24 4>; - clocks = <&clock HI3620_UARTCLK4>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio0: gpio@806000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x806000 0x1000>; - interrupts = <0 64 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1 - &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK0>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@807000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x807000 0x1000>; - interrupts = <0 65 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 - &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1 - &pmx0 6 5 1 &pmx0 7 6 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK1>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@808000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x808000 0x1000>; - interrupts = <0 66 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 - &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1 - &pmx0 6 3 1 &pmx0 7 3 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@809000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x809000 0x1000>; - interrupts = <0 67 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 - &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1 - &pmx0 6 11 1 &pmx0 7 11 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK3>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@80a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80a000 0x1000>; - interrupts = <0 68 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1 - &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1 - &pmx0 6 13 1 &pmx0 7 13 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK4>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@80b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80b000 0x1000>; - interrupts = <0 69 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1 - &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1 - &pmx0 6 16 1 &pmx0 7 16 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK5>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@80c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80c000 0x1000>; - interrupts = <0 70 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1 - &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1 - &pmx0 6 18 1 &pmx0 7 19 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK6>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@80d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80d000 0x1000>; - interrupts = <0 71 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1 - &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1 - &pmx0 6 25 1 &pmx0 7 26 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK7>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@80e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80e000 0x1000>; - interrupts = <0 72 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1 - &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1 - &pmx0 6 33 1 &pmx0 7 34 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK8>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@80f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x80f000 0x1000>; - interrupts = <0 73 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1 - &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1 - &pmx0 6 41 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK9>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@810000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x810000 0x1000>; - interrupts = <0 74 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1 - &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK10>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@811000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x811000 0x1000>; - interrupts = <0 75 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1 - &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1 - &pmx0 6 49 1 &pmx0 7 49 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK11>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@812000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x812000 0x1000>; - interrupts = <0 76 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1 - &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1 - &pmx0 6 51 1 &pmx0 7 52 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK12>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@813000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x813000 0x1000>; - interrupts = <0 77 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1 - &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1 - &pmx0 6 55 1 &pmx0 7 56 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK13>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@814000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x814000 0x1000>; - interrupts = <0 78 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1 - &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1 - &pmx0 6 60 1 &pmx0 7 61 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK14>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@815000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x815000 0x1000>; - interrupts = <0 79 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1 - &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1 - &pmx0 6 64 1 &pmx0 7 65 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK15>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@816000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x816000 0x1000>; - interrupts = <0 80 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1 - &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1 - &pmx0 6 72 1 &pmx0 7 73 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK16>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@817000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x817000 0x1000>; - interrupts = <0 81 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1 - &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1 - &pmx0 6 80 1 &pmx0 7 81 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK17>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@818000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x818000 0x1000>; - interrupts = <0 82 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1 - &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1 - &pmx0 6 86 1 &pmx0 7 87 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK18>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@819000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x819000 0x1000>; - interrupts = <0 83 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1 - &pmx0 3 88 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK19>; - clock-names = "apb_pclk"; - }; - - gpio20: gpio@81a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x81a000 0x1000>; - interrupts = <0 84 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 - &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK20>; - clock-names = "apb_pclk"; - }; - - gpio21: gpio@81b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x81b000 0x1000>; - interrupts = <0 85 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clock HI3620_GPIOCLK21>; - clock-names = "apb_pclk"; - }; - - pmx0: pinmux@803000 { - compatible = "pinctrl-single"; - reg = <0x803000 0x188>; - #address-cells = <1>; - #size-cells = <1>; - #gpio-range-cells = <3>; - ranges; - - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 - &range 12 1 0 &range 13 29 1 - &range 43 1 0 &range 44 49 1 - &range 94 1 1 &range 96 2 1>; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - }; - - pmx1: pinmux@803800 { - compatible = "pinconf-single"; - reg = <0x803800 0x2dc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pinctrl-single,register-width = <32>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/highbank.dts b/software/linux/kernel/arch/arm/boot/dts/highbank.dts deleted file mode 100644 index ed14aeac0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/highbank.dts +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright 2011-2012 Calxeda, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -/dts-v1/; - -/* First 4KB has pen for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; - -/ { - model = "Calxeda Highbank"; - compatible = "calxeda,highbank"; - #address-cells = <1>; - #size-cells = <1>; - clock-ranges; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@900 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x900>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - operating-points = < - /* kHz ignored */ - 1300000 1000000 - 1200000 1000000 - 1100000 1000000 - 800000 1000000 - 400000 1000000 - 200000 1000000 - >; - clock-latency = <100000>; - }; - - cpu@901 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x901>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@902 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x902>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - - cpu@903 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x903>; - next-level-cache = <&L2>; - clocks = <&a9pll>; - clock-names = "cpu"; - }; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x00000000 0xff900000>; - }; - - soc { - ranges = <0x00000000 0x00000000 0xffffffff>; - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - - timer@fff10600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfff10600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&a9periphclk>; - }; - - watchdog@fff10620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xfff10620 0x20>; - interrupts = <1 14 0xf01>; - clocks = <&a9periphclk>; - }; - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; - interrupt-controller; - reg = <0xfff11000 0x1000>, - <0xfff10100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xfff12000 0x1000>; - interrupts = <0 70 4>; - cache-unified; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; - }; - - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; - - }; -}; - -/include/ "ecx-common.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/hip01-ca9x2.dts b/software/linux/kernel/arch/arm/boot/dts/hip01-ca9x2.dts deleted file mode 100644 index eca5e4277..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hip01-ca9x2.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Hisilicon Ltd. HiP01 SoC - * - * Copyright (C) 2014 Hisilicon Ltd. - * Copyright (C) 2014 Huawei Ltd. - * - * Author: Wang Long - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -/* First 8KB reserved for secondary core boot */ -/memreserve/ 0x80000000 0x00002000; - -#include "hip01.dtsi" - -/ { - model = "Hisilicon HIP01 Development Board"; - compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hip01-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hip01.dtsi b/software/linux/kernel/arch/arm/boot/dts/hip01.dtsi deleted file mode 100644 index 4e9562f80..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hip01.dtsi +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Hisilicon Ltd. HiP01 SoC - * - * Copyright (c) 2014 Hisilicon Ltd. - * Copyright (c) 2014 Huawei Ltd. - * - * Author: Wang Long - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; - }; - - hisi_refclk144mhz: refclk144mkhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <144000000>; - clock-output-names = "hisi:refclk144khz"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0x10000000 0x20000000>; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - uart0: uart@10001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10001000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - interrupts = <0 32 4>; - status = "disabled"; - }; - - uart1: uart@10002000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10002000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - interrupts = <0 33 4>; - status = "disabled"; - }; - - uart2: uart@10003000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10003000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - interrupts = <0 34 4>; - status = "disabled"; - }; - - uart3: uart@10006000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10006000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - interrupts = <0 4 4>; - status = "disabled"; - }; - }; - - system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - - global_timer@0a000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x0a000200 0x100>; - interrupts = <1 11 0xf04>; - clocks = <&hisi_refclk144mhz>; - }; - - local_timer@0a000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x0a000600 0x100>; - interrupts = <1 13 0xf04>; - clocks = <&hisi_refclk144mhz>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hip04-d01.dts b/software/linux/kernel/arch/arm/boot/dts/hip04-d01.dts deleted file mode 100644 index 40a9e33c2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hip04-d01.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2013-2014 Linaro Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; - -#include "hip04.dtsi" - -/ { - /* memory bus is 64-bit */ - #address-cells = <2>; - #size-cells = <2>; - model = "Hisilicon D01 Development Board"; - compatible = "hisilicon,hip04-d01"; - - memory@00000000,10000000 { - device_type = "memory"; - reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, - <0x00000004 0xc0000000 0x00000003 0x40000000>; - }; - - soc { - uart0: uart@4007000 { - status = "ok"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hip04.dtsi b/software/linux/kernel/arch/arm/boot/dts/hip04.dtsi deleted file mode 100644 index 44044f275..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hip04.dtsi +++ /dev/null @@ -1,983 +0,0 @@ -/* - * Hisilicon Ltd. HiP04 SoC - * - * Copyright (C) 2013-2014 Hisilicon Ltd. - * Copyright (C) 2013-2014 Linaro Ltd. - * - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - /* memory bus is 64-bit */ - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - }; - - bootwrapper { - compatible = "hisilicon,hip04-bootwrapper"; - boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - cluster2 { - core0 { - cpu = <&CPU8>; - }; - core1 { - cpu = <&CPU9>; - }; - core2 { - cpu = <&CPU10>; - }; - core3 { - cpu = <&CPU11>; - }; - }; - cluster3 { - core0 { - cpu = <&CPU12>; - }; - core1 { - cpu = <&CPU13>; - }; - core2 { - cpu = <&CPU14>; - }; - core3 { - cpu = <&CPU15>; - }; - }; - }; - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - }; - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - }; - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x102>; - }; - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x103>; - }; - CPU8: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x200>; - }; - CPU9: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x201>; - }; - CPU10: cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x202>; - }; - CPU11: cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x203>; - }; - CPU12: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x300>; - }; - CPU13: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x301>; - }; - CPU14: cpu@302 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x302>; - }; - CPU15: cpu@303 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x303>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - clk_50m: clk_50m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - clk_168m: clk_168m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <168000000>; - }; - - clk_375m: clk_375m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <375000000>; - }; - - soc { - /* It's a 32-bit SoC. */ - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0 0xe0000000 0x10000000>; - - gic: interrupt-controller@c01000 { - compatible = "hisilicon,hip04-intc"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - interrupts = <1 9 0xf04>; - - reg = <0xc01000 0x1000>, <0xc02000 0x1000>, - <0xc04000 0x2000>, <0xc06000 0x2000>; - }; - - sysctrl: sysctrl { - compatible = "hisilicon,sysctrl"; - reg = <0x3e00000 0x00100000>; - }; - - fabric: fabric { - compatible = "hisilicon,hip04-fabric"; - reg = <0x302a000 0x1000>; - }; - - dual_timer0: dual_timer@3000000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x3000000 0x1000>; - interrupts = <0 224 4>; - clocks = <&clk_50m>, <&clk_50m>; - clock-names = "apb_pclk"; - }; - - arm-pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 64 4>, - <0 65 4>, - <0 66 4>, - <0 67 4>, - <0 68 4>, - <0 69 4>, - <0 70 4>, - <0 71 4>, - <0 72 4>, - <0 73 4>, - <0 74 4>, - <0 75 4>, - <0 76 4>, - <0 77 4>, - <0 78 4>, - <0 79 4>; - }; - - uart0: uart@4007000 { - compatible = "snps,dw-apb-uart"; - reg = <0x4007000 0x1000>; - interrupts = <0 381 4>; - clocks = <&clk_168m>; - clock-names = "uartclk"; - reg-shift = <2>; - status = "disabled"; - }; - - sata0: sata@a000000 { - compatible = "hisilicon,hisi-ahci"; - reg = <0xa000000 0x1000000>; - interrupts = <0 372 4>; - }; - - }; - - etb@0,e3c42000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3c42000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - port { - etb0_in_port: endpoint@0 { - slave-mode; - remote-endpoint = <&replicator0_out_port0>; - }; - }; - }; - - etb@0,e3c82000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3c82000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - port { - etb1_in_port: endpoint@0 { - slave-mode; - remote-endpoint = <&replicator1_out_port0>; - }; - }; - }; - - etb@0,e3cc2000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3cc2000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - port { - etb2_in_port: endpoint@0 { - slave-mode; - remote-endpoint = <&replicator2_out_port0>; - }; - }; - }; - - etb@0,e3d02000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0xe3d02000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - port { - etb3_in_port: endpoint@0 { - slave-mode; - remote-endpoint = <&replicator3_out_port0>; - }; - }; - }; - - tpiu@0,e3c05000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0xe3c05000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - port { - tpiu_in_port: endpoint@0 { - slave-mode; - remote-endpoint = <&funnel4_out_port0>; - }; - }; - }; - - replicator0 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator0_out_port0: endpoint { - remote-endpoint = <&etb0_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator0_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port0>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator0_in_port0: endpoint { - slave-mode; - remote-endpoint = <&funnel0_out_port0>; - }; - }; - }; - }; - - replicator1 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator1_out_port0: endpoint { - remote-endpoint = <&etb1_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator1_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port1>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator1_in_port0: endpoint { - slave-mode; - remote-endpoint = <&funnel1_out_port0>; - }; - }; - }; - }; - - replicator2 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator2_out_port0: endpoint { - remote-endpoint = <&etb2_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator2_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port2>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator2_in_port0: endpoint { - slave-mode; - remote-endpoint = <&funnel2_out_port0>; - }; - }; - }; - }; - - replicator3 { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator3_out_port0: endpoint { - remote-endpoint = <&etb3_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator3_out_port1: endpoint { - remote-endpoint = <&funnel4_in_port3>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator3_in_port0: endpoint { - slave-mode; - remote-endpoint = <&funnel3_out_port0>; - }; - }; - }; - }; - - funnel@0,e3c41000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0xe3c41000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output port */ - port@0 { - reg = <0>; - funnel0_out_port0: endpoint { - remote-endpoint = - <&replicator0_in_port0>; - }; - }; - - /* funnel input ports */ - port@1 { - reg = <0>; - funnel0_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@2 { - reg = <1>; - funnel0_in_port1: endpoint { - slave-mode; - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@3 { - reg = <2>; - funnel0_in_port2: endpoint { - slave-mode; - remote-endpoint = <&ptm2_out_port>; - }; - }; - - port@4 { - reg = <3>; - funnel0_in_port3: endpoint { - slave-mode; - remote-endpoint = <&ptm3_out_port>; - }; - }; - }; - }; - - funnel@0,e3c81000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0xe3c81000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output port */ - port@0 { - reg = <0>; - funnel1_out_port0: endpoint { - remote-endpoint = - <&replicator1_in_port0>; - }; - }; - - /* funnel input ports */ - port@1 { - reg = <0>; - funnel1_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ptm4_out_port>; - }; - }; - - port@2 { - reg = <1>; - funnel1_in_port1: endpoint { - slave-mode; - remote-endpoint = <&ptm5_out_port>; - }; - }; - - port@3 { - reg = <2>; - funnel1_in_port2: endpoint { - slave-mode; - remote-endpoint = <&ptm6_out_port>; - }; - }; - - port@4 { - reg = <3>; - funnel1_in_port3: endpoint { - slave-mode; - remote-endpoint = <&ptm7_out_port>; - }; - }; - }; - }; - - funnel@0,e3cc1000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0xe3cc1000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output port */ - port@0 { - reg = <0>; - funnel2_out_port0: endpoint { - remote-endpoint = - <&replicator2_in_port0>; - }; - }; - - /* funnel input ports */ - port@1 { - reg = <0>; - funnel2_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ptm8_out_port>; - }; - }; - - port@2 { - reg = <1>; - funnel2_in_port1: endpoint { - slave-mode; - remote-endpoint = <&ptm9_out_port>; - }; - }; - - port@3 { - reg = <2>; - funnel2_in_port2: endpoint { - slave-mode; - remote-endpoint = <&ptm10_out_port>; - }; - }; - - port@4 { - reg = <3>; - funnel2_in_port3: endpoint { - slave-mode; - remote-endpoint = <&ptm11_out_port>; - }; - }; - }; - }; - - funnel@0,e3d01000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0xe3d01000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output port */ - port@0 { - reg = <0>; - funnel3_out_port0: endpoint { - remote-endpoint = - <&replicator3_in_port0>; - }; - }; - - /* funnel input ports */ - port@1 { - reg = <0>; - funnel3_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ptm12_out_port>; - }; - }; - - port@2 { - reg = <1>; - funnel3_in_port1: endpoint { - slave-mode; - remote-endpoint = <&ptm13_out_port>; - }; - }; - - port@3 { - reg = <2>; - funnel3_in_port2: endpoint { - slave-mode; - remote-endpoint = <&ptm14_out_port>; - }; - }; - - port@4 { - reg = <3>; - funnel3_in_port3: endpoint { - slave-mode; - remote-endpoint = <&ptm15_out_port>; - }; - }; - }; - }; - - funnel@0,e3c04000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0xe3c04000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output port */ - port@0 { - reg = <0>; - funnel4_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - /* funnel input ports */ - port@1 { - reg = <0>; - funnel4_in_port0: endpoint { - slave-mode; - remote-endpoint = - <&replicator0_out_port1>; - }; - }; - - port@2 { - reg = <1>; - funnel4_in_port1: endpoint { - slave-mode; - remote-endpoint = - <&replicator1_out_port1>; - }; - }; - - port@3 { - reg = <2>; - funnel4_in_port2: endpoint { - slave-mode; - remote-endpoint = - <&replicator2_out_port1>; - }; - }; - - port@4 { - reg = <3>; - funnel4_in_port3: endpoint { - slave-mode; - remote-endpoint = - <&replicator3_out_port1>; - }; - }; - }; - }; - - ptm@0,e3c7c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7c000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU0>; - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel0_in_port0>; - }; - }; - }; - - ptm@0,e3c7d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7d000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU1>; - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel0_in_port1>; - }; - }; - }; - - ptm@0,e3c7e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7e000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU2>; - port { - ptm2_out_port: endpoint { - remote-endpoint = <&funnel0_in_port2>; - }; - }; - }; - - ptm@0,e3c7f000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3c7f000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU3>; - port { - ptm3_out_port: endpoint { - remote-endpoint = <&funnel0_in_port3>; - }; - }; - }; - - ptm@0,e3cbc000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbc000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU4>; - port { - ptm4_out_port: endpoint { - remote-endpoint = <&funnel1_in_port0>; - }; - }; - }; - - ptm@0,e3cbd000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbd000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU5>; - port { - ptm5_out_port: endpoint { - remote-endpoint = <&funnel1_in_port1>; - }; - }; - }; - - ptm@0,e3cbe000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbe000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU6>; - port { - ptm6_out_port: endpoint { - remote-endpoint = <&funnel1_in_port2>; - }; - }; - }; - - ptm@0,e3cbf000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cbf000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU7>; - port { - ptm7_out_port: endpoint { - remote-endpoint = <&funnel1_in_port3>; - }; - }; - }; - - ptm@0,e3cfc000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfc000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU8>; - port { - ptm8_out_port: endpoint { - remote-endpoint = <&funnel2_in_port0>; - }; - }; - }; - - ptm@0,e3cfd000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfd000 0 0x1000>; - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU9>; - port { - ptm9_out_port: endpoint { - remote-endpoint = <&funnel2_in_port1>; - }; - }; - }; - - ptm@0,e3cfe000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cfe000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU10>; - port { - ptm10_out_port: endpoint { - remote-endpoint = <&funnel2_in_port2>; - }; - }; - }; - - ptm@0,e3cff000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3cff000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU11>; - port { - ptm11_out_port: endpoint { - remote-endpoint = <&funnel2_in_port3>; - }; - }; - }; - - ptm@0,e3d3c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3c000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU12>; - port { - ptm12_out_port: endpoint { - remote-endpoint = <&funnel3_in_port0>; - }; - }; - }; - - ptm@0,e3d3d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3d000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU13>; - port { - ptm13_out_port: endpoint { - remote-endpoint = <&funnel3_in_port1>; - }; - }; - }; - - ptm@0,e3d3e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3e000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU14>; - port { - ptm14_out_port: endpoint { - remote-endpoint = <&funnel3_in_port2>; - }; - }; - }; - - ptm@0,e3d3f000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0xe3d3f000 0 0x1000>; - - clocks = <&clk_375m>; - clock-names = "apb_pclk"; - cpu = <&CPU15>; - port { - ptm15_out_port: endpoint { - remote-endpoint = <&funnel3_in_port3>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/software/linux/kernel/arch/arm/boot/dts/hisi-x5hd2-dkb.dts deleted file mode 100644 index d13af8437..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; -#include "hisi-x5hd2.dtsi" - -/ { - model = "Hisilicon HIX5HD2 Development Board"; - compatible = "hisilicon,hix5hd2"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "hisilicon,hix5hd2-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; - }; -}; - -&timer0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&gmac0 { - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy2>; - phy-mode = "mii"; - /* Placeholder, overwritten by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - phy2: ethernet-phy@2 { - reg = <2>; - }; -}; - -&gmac1 { - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy1>; - phy-mode = "rgmii"; - /* Placeholder, overwritten by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ahci { - phys = <&sata_phy>; - phy-names = "sata-phy"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/hisi-x5hd2.dtsi b/software/linux/kernel/arch/arm/boot/dts/hisi-x5hd2.dtsi deleted file mode 100644 index fdcc23d20..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ /dev/null @@ -1,556 +0,0 @@ -/* - * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - serial0 = &uart0; - }; - - gic: interrupt-controller@f8a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - /* gic dist base, gic cpu base */ - reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges = <0 0xf8000000 0x8000000>; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - timer0: timer@00002000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00002000 0x1000>; - /* timer00 & timer01 */ - interrupts = <0 24 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer1: timer@00a29000 { - /* - * Only used in NORMAL state, not available ins - * SLOW or DOZE state. - * The rate is fixed in 24MHz. - */ - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a29000 0x1000>; - /* timer10 & timer11 */ - interrupts = <0 25 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer2: timer@00a2a000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a2a000 0x1000>; - /* timer20 & timer21 */ - interrupts = <0 26 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer3: timer@00a2b000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a2b000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 27 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - timer4: timer@00a81000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00a81000 0x1000>; - /* timer30 & timer31 */ - interrupts = <0 28 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - status = "disabled"; - }; - - uart0: uart@00b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b00000 0x1000>; - interrupts = <0 49 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart1: uart@00006000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00006000 0x1000>; - interrupts = <0 50 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart2: uart@00b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b02000 0x1000>; - interrupts = <0 51 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart3: uart@00b03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x00b03000 0x1000>; - interrupts = <0 52 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart4: uart@00b04000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb04000 0x1000>; - interrupts = <0 53 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio0: gpio@b20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb20000 0x1000>; - interrupts = <0 108 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@b21000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb21000 0x1000>; - interrupts = <0 109 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio2: gpio@b22000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb22000 0x1000>; - interrupts = <0 110 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio3: gpio@b23000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb23000 0x1000>; - interrupts = <0 111 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio4: gpio@b24000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb24000 0x1000>; - interrupts = <0 112 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio5: gpio@004000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x004000 0x1000>; - interrupts = <0 113 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio6: gpio@b26000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb26000 0x1000>; - interrupts = <0 114 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio7: gpio@b27000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb27000 0x1000>; - interrupts = <0 115 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio8: gpio@b28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb28000 0x1000>; - interrupts = <0 116 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio9: gpio@b29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb29000 0x1000>; - interrupts = <0 117 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio10: gpio@b2a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2a000 0x1000>; - interrupts = <0 118 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio11: gpio@b2b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2b000 0x1000>; - interrupts = <0 119 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio12: gpio@b2c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2c000 0x1000>; - interrupts = <0 120 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio13: gpio@b2d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2d000 0x1000>; - interrupts = <0 121 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio14: gpio@b2e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2e000 0x1000>; - interrupts = <0 122 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio15: gpio@b2f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb2f000 0x1000>; - interrupts = <0 123 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio16: gpio@b30000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb30000 0x1000>; - interrupts = <0 124 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio17: gpio@b31000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xb31000 0x1000>; - interrupts = <0 125 0x4>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clock HIX5HD2_FIXED_100M>; - clock-names = "apb_pclk"; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - wdt0: watchdog@a2c000 { - compatible = "arm,sp805", "arm,primecell"; - arm,primecell-periphid = <0x00141805>; - reg = <0xa2c000 0x1000>; - interrupts = <0 29 4>; - clocks = <&clock HIX5HD2_WDG0_RST>; - clock-names = "apb_pclk"; - }; - }; - - local_timer@00a00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x00a00600 0x20>; - interrupts = <1 13 0xf01>; - }; - - l2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0x00a10000 0x100000>; - interrupts = <0 15 4>; - cache-unified; - cache-level = <2>; - }; - - sysctrl: system-controller@00000000 { - compatible = "hisilicon,sysctrl", "syscon"; - reg = <0x00000000 0x1000>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&sysctrl>; - offset = <0x4>; - mask = <0xdeadbeef>; - }; - - cpuctrl@00a22000 { - compatible = "hisilicon,cpuctrl"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00a22000 0x2000>; - ranges = <0 0x00a22000 0x2000>; - - clock: clock@0 { - compatible = "hisilicon,hix5hd2-clock"; - reg = <0 0x2000>; - #clock-cells = <1>; - }; - }; - - /* unremovable emmc as mmcblk0 */ - mmc: mmc@1830000 { - compatible = "snps,dw-mshc"; - reg = <0x1830000 0x1000>; - interrupts = <0 35 4>; - clocks = <&clock HIX5HD2_MMC_CIU_RST>, - <&clock HIX5HD2_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; - }; - - sd: mmc@1820000 { - compatible = "snps,dw-mshc"; - reg = <0x1820000 0x1000>; - interrupts = <0 34 4>; - clocks = <&clock HIX5HD2_SD_CIU_RST>, - <&clock HIX5HD2_SD_BIU_CLK>; - clock-names = "ciu","biu"; - }; - - gmac0: ethernet@1840000 { - compatible = "hisilicon,hix5hd2-gmac"; - reg = <0x1840000 0x1000>,<0x184300c 0x4>; - interrupts = <0 71 4>; - clocks = <&clock HIX5HD2_MAC0_CLK>; - status = "disabled"; - }; - - gmac1: ethernet@1841000 { - compatible = "hisilicon,hix5hd2-gmac"; - reg = <0x1841000 0x1000>,<0x1843010 0x4>; - interrupts = <0 72 4>; - clocks = <&clock HIX5HD2_MAC1_CLK>; - status = "disabled"; - }; - - usb0: ehci@1890000 { - compatible = "generic-ehci"; - reg = <0x1890000 0x1000>; - interrupts = <0 66 4>; - clocks = <&clock HIX5HD2_USB_CLK>; - }; - - usb1: ohci@1880000 { - compatible = "generic-ohci"; - reg = <0x1880000 0x1000>; - interrupts = <0 67 4>; - clocks = <&clock HIX5HD2_USB_CLK>; - }; - - peripheral_ctrl: syscon@a20000 { - compatible = "syscon"; - reg = <0xa20000 0x1000>; - }; - - sata_phy: phy@1900000 { - compatible = "hisilicon,hix5hd2-sata-phy"; - reg = <0x1900000 0x10000>; - #phy-cells = <0>; - hisilicon,peripheral-syscon = <&peripheral_ctrl>; - hisilicon,power-reg = <0x8 10>; - }; - - ahci: sata@1900000 { - compatible = "hisilicon,hisi-ahci"; - reg = <0x1900000 0x10000>; - interrupts = <0 70 4>; - clocks = <&clock HIX5HD2_SATA_CLK>; - }; - - ir: ir@001000 { - compatible = "hisilicon,hix5hd2-ir"; - reg = <0x001000 0x1000>; - interrupts = <0 47 4>; - clocks = <&clock HIX5HD2_FIXED_24M>; - hisilicon,power-syscon = <&sysctrl>; - }; - - i2c0: i2c@b10000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb10000 0x1000>; - interrupts = <0 38 4>; - clocks = <&clock HIX5HD2_I2C0_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@b11000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb11000 0x1000>; - interrupts = <0 39 4>; - clocks = <&clock HIX5HD2_I2C1_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@b12000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb12000 0x1000>; - interrupts = <0 40 4>; - clocks = <&clock HIX5HD2_I2C2_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@b13000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb13000 0x1000>; - interrupts = <0 41 4>; - clocks = <&clock HIX5HD2_I2C3_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@b16000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb16000 0x1000>; - interrupts = <0 43 4>; - clocks = <&clock HIX5HD2_I2C4_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@b17000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xb17000 0x1000>; - interrupts = <0 44 4>; - clocks = <&clock HIX5HD2_I2C5_RST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx1-ads.dts b/software/linux/kernel/arch/arm/boot/dts/imx1-ads.dts deleted file mode 100644 index f50498659..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx1-ads.dts +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2014 Alexander Shiyan - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx1.dtsi" - -/ { - model = "Freescale MX1 ADS"; - compatible = "fsl,imx1ads", "fsl,imx1"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x08000000 0x04000000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - clk32 { - compatible = "fsl,imx-clk32", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c>; - status = "okay"; - - extgpio0: pcf8575@22 { - compatible = "nxp,pcf8575"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - extgpio1: pcf8575@24 { - compatible = "nxp,pcf8575"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <4>; - fsl,weim-cs-timing = <0x00003e00 0x00000801>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&iomuxc { - imx1-ads { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 - MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 - MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 - MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 - MX1_PAD_SPI1_SS__GPIO3_15 0x0 - >; - }; - - pinctrl_i2c: i2cgrp { - fsl,pins = < - MX1_PAD_I2C_SCL__I2C_SCL 0x0 - MX1_PAD_I2C_SDA__I2C_SDA 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX1_PAD_UART1_TXD__UART1_TXD 0x0 - MX1_PAD_UART1_RXD__UART1_RXD 0x0 - MX1_PAD_UART1_CTS__UART1_CTS 0x0 - MX1_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX1_PAD_UART2_TXD__UART2_TXD 0x0 - MX1_PAD_UART2_RXD__UART2_RXD 0x0 - MX1_PAD_UART2_CTS__UART2_CTS 0x0 - MX1_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX1_PAD_A0__A0 0x0 - MX1_PAD_A16__A16 0x0 - MX1_PAD_A17__A17 0x0 - MX1_PAD_A18__A18 0x0 - MX1_PAD_A19__A19 0x0 - MX1_PAD_A20__A20 0x0 - MX1_PAD_A21__A21 0x0 - MX1_PAD_A22__A22 0x0 - MX1_PAD_A23__A23 0x0 - MX1_PAD_A24__A24 0x0 - MX1_PAD_BCLK__BCLK 0x0 - MX1_PAD_CS4__CS4 0x0 - MX1_PAD_DTACK__DTACK 0x0 - MX1_PAD_ECB__ECB 0x0 - MX1_PAD_LBA__LBA 0x0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx1-apf9328.dts b/software/linux/kernel/arch/arm/boot/dts/imx1-apf9328.dts deleted file mode 100644 index e8b4b52c2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx1-apf9328.dts +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2014 Alexander Shiyan - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx1.dtsi" - -/ { - model = "Armadeus APF9328"; - compatible = "armadeus,imx1-apf9328", "fsl,imx1"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x08000000 0x00800000>; - }; -}; - -&i2c { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00330e04 0x00000d01>; - #address-cells = <1>; - #size-cells = <1>; - }; - - eth: eth@4,c00000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth>; - compatible = "davicom,dm9000"; - reg = < - 4 0x00c00000 0x2 - 4 0x00c00002 0x2 - >; - interrupt-parent = <&gpio2>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - fsl,weim-cs-timing = <0x0000c700 0x19190d01>; - }; -}; - -&iomuxc { - imx1-apf9328 { - pinctrl_eth: ethgrp { - fsl,pins = < - MX1_PAD_SIM_SVEN__GPIO2_14 0x0 - >; - }; - - pinctrl_i2c: i2cgrp { - fsl,pins = < - MX1_PAD_I2C_SCL__I2C_SCL 0x0 - MX1_PAD_I2C_SDA__I2C_SDA 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX1_PAD_UART1_TXD__UART1_TXD 0x0 - MX1_PAD_UART1_RXD__UART1_RXD 0x0 - MX1_PAD_UART1_CTS__UART1_CTS 0x0 - MX1_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX1_PAD_UART2_TXD__UART2_TXD 0x0 - MX1_PAD_UART2_RXD__UART2_RXD 0x0 - MX1_PAD_UART2_CTS__UART2_CTS 0x0 - MX1_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX1_PAD_A0__A0 0x0 - MX1_PAD_A16__A16 0x0 - MX1_PAD_A17__A17 0x0 - MX1_PAD_A18__A18 0x0 - MX1_PAD_A19__A19 0x0 - MX1_PAD_A20__A20 0x0 - MX1_PAD_A21__A21 0x0 - MX1_PAD_A22__A22 0x0 - MX1_PAD_A23__A23 0x0 - MX1_PAD_A24__A24 0x0 - MX1_PAD_BCLK__BCLK 0x0 - MX1_PAD_CS4__CS4 0x0 - MX1_PAD_DTACK__DTACK 0x0 - MX1_PAD_ECB__ECB 0x0 - MX1_PAD_LBA__LBA 0x0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx1-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx1-pinfunc.h deleted file mode 100644 index 22bec8b87..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx1-pinfunc.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Copyright (C) 2014 Alexander Shiyan - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DTS_IMX1_PINFUNC_H -#define __DTS_IMX1_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - * mux_id consists of - * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) - * - * function: 0 - Primary function - * 1 - Alternate function - * 2 - GPIO - * direction: 0 - Input - * 1 - Output - * gpio_oconf: 0 - A_IN - * 1 - B_IN - * 2 - A_OUT - * 3 - Data Register - * gpio_iconfa/b: 0 - GPIO_IN - * 1 - Interrupt Status Register - * 2 - 0 - * 3 - 1 - * - * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). - */ - -#define MX1_PAD_A24__A24 0x00 0x004 -#define MX1_PAD_A24__GPIO1_0 0x00 0x032 -#define MX1_PAD_A24__SPI2_CLK 0x00 0x006 -#define MX1_PAD_TIN__TIN 0x01 0x000 -#define MX1_PAD_TIN__GPIO1_1 0x01 0x032 -#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022 -#define MX1_PAD_PWMO__PWMO 0x02 0x004 -#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032 -#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004 -#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032 -#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000 -#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032 -#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000 -#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032 -#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000 -#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032 -#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000 -#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032 -#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000 -#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032 -#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000 -#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032 -#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000 -#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032 -#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000 -#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032 -#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000 -#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032 -#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000 -#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032 -#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000 -#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032 -#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000 -#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032 -#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004 -#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032 -#define MX1_PAD_DTACK__DTACK 0x11 0x000 -#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032 -#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002 -#define MX1_PAD_DTACK__A25 0x11 0x016 -#define MX1_PAD_BCLK__BCLK 0x12 0x004 -#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032 -#define MX1_PAD_LBA__LBA 0x13 0x004 -#define MX1_PAD_LBA__GPIO1_19 0x13 0x032 -#define MX1_PAD_ECB__ECB 0x14 0x000 -#define MX1_PAD_ECB__GPIO1_20 0x14 0x032 -#define MX1_PAD_A0__A0 0x15 0x004 -#define MX1_PAD_A0__GPIO1_21 0x15 0x032 -#define MX1_PAD_CS4__CS4 0x16 0x004 -#define MX1_PAD_CS4__GPIO1_22 0x16 0x032 -#define MX1_PAD_CS5__CS5 0x17 0x004 -#define MX1_PAD_CS5__GPIO1_23 0x17 0x032 -#define MX1_PAD_A16__A16 0x18 0x004 -#define MX1_PAD_A16__GPIO1_24 0x18 0x032 -#define MX1_PAD_A17__A17 0x19 0x004 -#define MX1_PAD_A17__GPIO1_25 0x19 0x032 -#define MX1_PAD_A18__A18 0x1a 0x004 -#define MX1_PAD_A18__GPIO1_26 0x1a 0x032 -#define MX1_PAD_A19__A19 0x1b 0x004 -#define MX1_PAD_A19__GPIO1_27 0x1b 0x032 -#define MX1_PAD_A20__A20 0x1c 0x004 -#define MX1_PAD_A20__GPIO1_28 0x1c 0x032 -#define MX1_PAD_A21__A21 0x1d 0x004 -#define MX1_PAD_A21__GPIO1_29 0x1d 0x032 -#define MX1_PAD_A22__A22 0x1e 0x004 -#define MX1_PAD_A22__GPIO1_30 0x1e 0x032 -#define MX1_PAD_A23__A23 0x1f 0x004 -#define MX1_PAD_A23__GPIO1_31 0x1f 0x032 -#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000 -#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001 -#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032 -#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000 -#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001 -#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032 -#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000 -#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001 -#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032 -#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000 -#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001 -#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032 -#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004 -#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005 -#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032 -#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000 -#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005 -#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032 -#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004 -#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001 -#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032 -#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000 -#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001 -#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032 -#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000 -#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001 -#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032 -#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000 -#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005 -#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032 -#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004 -#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001 -#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032 -#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004 -#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001 -#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032 -#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004 -#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032 -#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004 -#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032 -#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000 -#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032 -#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004 -#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032 -#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000 -#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032 -#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000 -#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032 -#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004 -#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032 -#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004 -#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032 -#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004 -#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032 -#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000 -#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032 -#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004 -#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032 -#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000 -#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032 -#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000 -#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032 -#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000 -#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032 -#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000 -#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032 -#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004 -#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032 -#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000 -#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032 -#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000 -#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032 -#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004 -#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032 -#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000 -#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032 -#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004 -#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032 -#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000 -#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032 -#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000 -#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032 -#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004 -#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032 -#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000 -#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032 -#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000 -#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032 -#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004 -#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032 -#define MX1_PAD_BT13__BT13 0x53 0x004 -#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001 -#define MX1_PAD_BT13__GPIO3_19 0x53 0x032 -#define MX1_PAD_BT12__BT12 0x54 0x004 -#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001 -#define MX1_PAD_BT12__GPIO3_20 0x54 0x032 -#define MX1_PAD_BT11__BT11 0x55 0x004 -#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001 -#define MX1_PAD_BT11__GPIO3_21 0x55 0x032 -#define MX1_PAD_BT10__BT10 0x56 0x004 -#define MX1_PAD_BT10__SSI2_TX 0x56 0x001 -#define MX1_PAD_BT10__GPIO3_22 0x56 0x032 -#define MX1_PAD_BT9__BT9 0x57 0x004 -#define MX1_PAD_BT9__SSI2_RX 0x57 0x001 -#define MX1_PAD_BT9__GPIO3_23 0x57 0x032 -#define MX1_PAD_BT8__BT8 0x58 0x004 -#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001 -#define MX1_PAD_BT8__GPIO3_24 0x58 0x032 -#define MX1_PAD_BT8__UART3_RI 0x58 0x016 -#define MX1_PAD_BT7__BT7 0x59 0x004 -#define MX1_PAD_BT7__GPIO3_25 0x59 0x032 -#define MX1_PAD_BT7__UART3_DSR 0x59 0x016 -#define MX1_PAD_BT6__BT6 0x5a 0x004 -#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032 -#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016 -#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022 -#define MX1_PAD_BT5__BT5 0x5b 0x000 -#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032 -#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016 -#define MX1_PAD_BT4__BT4 0x5c 0x000 -#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032 -#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016 -#define MX1_PAD_BT3__BT3 0x5d 0x000 -#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032 -#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022 -#define MX1_PAD_BT2__BT2 0x5e 0x004 -#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032 -#define MX1_PAD_BT2__UART3_TX 0x5e 0x016 -#define MX1_PAD_BT1__BT1 0x5f 0x000 -#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032 -#define MX1_PAD_BT1__UART3_RX 0x5f 0x022 -#define MX1_PAD_LSCLK__LSCLK 0x66 0x004 -#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032 -#define MX1_PAD_REV__REV 0x67 0x004 -#define MX1_PAD_REV__UART2_DTR 0x67 0x001 -#define MX1_PAD_REV__GPIO4_7 0x67 0x032 -#define MX1_PAD_REV__SPI2_CLK 0x67 0x006 -#define MX1_PAD_CLS__CLS 0x68 0x004 -#define MX1_PAD_CLS__UART2_DCD 0x68 0x005 -#define MX1_PAD_CLS__GPIO4_8 0x68 0x032 -#define MX1_PAD_CLS__SPI2_SS 0x68 0x002 -#define MX1_PAD_PS__PS 0x69 0x004 -#define MX1_PAD_PS__UART2_RI 0x69 0x005 -#define MX1_PAD_PS__GPIO4_9 0x69 0x032 -#define MX1_PAD_PS__SPI2_RXD 0x69 0x022 -#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004 -#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005 -#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032 -#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006 -#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004 -#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032 -#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012 -#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004 -#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032 -#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004 -#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032 -#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004 -#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032 -#define MX1_PAD_LD0__LD0 0x6f 0x004 -#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032 -#define MX1_PAD_LD1__LD1 0x70 0x004 -#define MX1_PAD_LD1__GPIO4_16 0x70 0x032 -#define MX1_PAD_LD2__LD2 0x71 0x004 -#define MX1_PAD_LD2__GPIO4_17 0x71 0x032 -#define MX1_PAD_LD3__LD3 0x72 0x004 -#define MX1_PAD_LD3__GPIO4_18 0x72 0x032 -#define MX1_PAD_LD4__LD4 0x73 0x004 -#define MX1_PAD_LD4__GPIO4_19 0x73 0x032 -#define MX1_PAD_LD5__LD5 0x74 0x004 -#define MX1_PAD_LD5__GPIO4_20 0x74 0x032 -#define MX1_PAD_LD6__LD6 0x75 0x004 -#define MX1_PAD_LD6__GPIO4_21 0x75 0x032 -#define MX1_PAD_LD7__LD7 0x76 0x004 -#define MX1_PAD_LD7__GPIO4_22 0x76 0x032 -#define MX1_PAD_LD8__LD8 0x77 0x004 -#define MX1_PAD_LD8__GPIO4_23 0x77 0x032 -#define MX1_PAD_LD9__LD9 0x78 0x004 -#define MX1_PAD_LD9__GPIO4_24 0x78 0x032 -#define MX1_PAD_LD10__LD10 0x79 0x004 -#define MX1_PAD_LD10__GPIO4_25 0x79 0x032 -#define MX1_PAD_LD11__LD11 0x7a 0x004 -#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032 -#define MX1_PAD_LD12__LD12 0x7b 0x004 -#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032 -#define MX1_PAD_LD13__LD13 0x7c 0x004 -#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032 -#define MX1_PAD_LD14__LD14 0x7d 0x004 -#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032 -#define MX1_PAD_LD15__LD15 0x7e 0x004 -#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032 -#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000 -#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032 -#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006 - -#endif diff --git a/software/linux/kernel/arch/arm/boot/dts/imx1.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx1.dtsi deleted file mode 100644 index 22f5d1db5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx1.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (C) 2014 Alexander Shiyan - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" -#include "imx1-pinfunc.h" - -#include -#include -#include - -/ { - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &cspi1; - spi1 = &cspi2; - }; - - aitc: aitc-interrupt-controller@00223000 { - compatible = "fsl,imx1-aitc", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x00223000 0x1000>; - }; - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu: cpu@0 { - device_type = "cpu"; - compatible = "arm,arm920t"; - operating-points = <200000 1900000>; - clock-latency = <62500>; - clocks = <&clks IMX1_CLK_MCU>; - voltage-tolerance = <5>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&aitc>; - ranges; - - aipi@00200000 { - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00200000 0x10000>; - ranges; - - gpt1: timer@00202000 { - compatible = "fsl,imx1-gpt"; - reg = <0x00202000 0x1000>; - interrupts = <59>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - gpt2: timer@00203000 { - compatible = "fsl,imx1-gpt"; - reg = <0x00203000 0x1000>; - interrupts = <58>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - fb: fb@00205000 { - compatible = "fsl,imx1-fb"; - reg = <0x00205000 0x1000>; - interrupts = <14>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER2>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - uart1: serial@00206000 { - compatible = "fsl,imx1-uart"; - reg = <0x00206000 0x1000>; - interrupts = <30 29 26>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@00207000 { - compatible = "fsl,imx1-uart"; - reg = <0x00207000 0x1000>; - interrupts = <24 23 20>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm: pwm@00208000 { - #pwm-cells = <2>; - compatible = "fsl,imx1-pwm"; - reg = <0x00208000 0x1000>; - interrupts = <34>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; - - dma: dma@00209000 { - compatible = "fsl,imx1-dma"; - reg = <0x00209000 0x1000>; - interrupts = <61 60>; - clocks = <&clks IMX1_CLK_HCLK>, - <&clks IMX1_CLK_DMA_GATE>; - clock-names = "ipg", "ahb"; - #dma-cells = <1>; - }; - - uart3: serial@0020a000 { - compatible = "fsl,imx1-uart"; - reg = <0x0020a000 0x1000>; - interrupts = <54 4 1>; - clocks = <&clks IMX1_CLK_UART3_GATE>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - aipi@00210000 { - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00210000 0x10000>; - ranges; - - cspi1: cspi@00213000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-cspi"; - reg = <0x00213000 0x1000>; - interrupts = <41>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c: i2c@00217000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-i2c"; - reg = <0x00217000 0x1000>; - interrupts = <39>; - clocks = <&clks IMX1_CLK_HCLK>; - status = "disabled"; - }; - - cspi2: cspi@00219000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx1-cspi"; - reg = <0x00219000 0x1000>; - interrupts = <40>; - clocks = <&clks IMX1_CLK_DUMMY>, - <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - clks: ccm@0021b000 { - compatible = "fsl,imx1-ccm"; - reg = <0x0021b000 0x1000>; - #clock-cells = <1>; - }; - - iomuxc: iomuxc@0021c000 { - compatible = "fsl,imx1-iomuxc"; - reg = <0x0021c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@0021c000 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c000 0x100>; - interrupts = <11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@0021c100 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c100 0x100>; - interrupts = <12>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@0021c200 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c200 0x100>; - interrupts = <13>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@0021c300 { - compatible = "fsl,imx1-gpio"; - reg = <0x0021c300 0x100>; - interrupts = <62>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - }; - - weim: weim@00220000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx1-weim"; - reg = <0x00220000 0x1000>; - clocks = <&clks IMX1_CLK_DUMMY>; - ranges = < - 0 0 0x10000000 0x02000000 - 1 0 0x12000000 0x01000000 - 2 0 0x13000000 0x01000000 - 3 0 0x14000000 0x01000000 - 4 0 0x15000000 0x01000000 - 5 0 0x16000000 0x01000000 - >; - status = "disabled"; - }; - - esram: esram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x20000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx23-evk.dts b/software/linux/kernel/arch/arm/boot/dts/imx23-evk.dts deleted file mode 100644 index 57e29977b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx23-evk.dts +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Freescale i.MX23 Evaluation Kit"; - compatible = "fsl,imx23-evk", "fsl,imx23"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; - status = "okay"; - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - wp-gpios = <&gpio1 30 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_LCD_RESET__GPIO_1_18 - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_PWM4__GPIO_1_30 - MX23_PAD_SSP1_DETECT__SSP1_DETECT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hback-porch = <15>; - hfront-porch = <8>; - vback-porch = <12>; - vfront-porch = <4>; - hsync-len = <1>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_vddio_sd0: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - - reg_lcd_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 18 0>; - enable-active-high; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx23-olinuxino.dts b/software/linux/kernel/arch/arm/boot/dts/imx23-olinuxino.dts deleted file mode 100644 index a8b1c53eb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx23-olinuxino.dts +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include -#include "imx23.dtsi" - -/ { - model = "i.MX23 Olinuxino Low Cost Board"; - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; - - memory { - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - broken-cd; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_ALE__GPIO_0_17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pin_gpio2_1: led_gpio2_1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DETECT__GPIO_2_1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - ssp1: ssp@80034000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - i2c: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_b>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "host"; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ - gpio = <&gpio0 17 0>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio2_1>; - - user { - label = "green"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx23-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx23-pinfunc.h deleted file mode 100644 index 5c0f32ca3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx23-pinfunc.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Header providing constants for i.MX23 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MX23_PINCTRL_H__ -#define __DT_BINDINGS_MX23_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 -#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 -#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 -#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 -#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 -#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 -#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 -#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 -#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 -#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 -#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 -#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 -#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 -#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 -#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 -#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 -#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 -#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 -#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 -#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 -#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 -#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 -#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 -#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 -#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 -#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 -#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 -#define MX23_PAD_LCD_D00__LCD_D00 0x1000 -#define MX23_PAD_LCD_D01__LCD_D01 0x1010 -#define MX23_PAD_LCD_D02__LCD_D02 0x1020 -#define MX23_PAD_LCD_D03__LCD_D03 0x1030 -#define MX23_PAD_LCD_D04__LCD_D04 0x1040 -#define MX23_PAD_LCD_D05__LCD_D05 0x1050 -#define MX23_PAD_LCD_D06__LCD_D06 0x1060 -#define MX23_PAD_LCD_D07__LCD_D07 0x1070 -#define MX23_PAD_LCD_D08__LCD_D08 0x1080 -#define MX23_PAD_LCD_D09__LCD_D09 0x1090 -#define MX23_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX23_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX23_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX23_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX23_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX23_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX23_PAD_LCD_D16__LCD_D16 0x1100 -#define MX23_PAD_LCD_D17__LCD_D17 0x1110 -#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120 -#define MX23_PAD_LCD_RS__LCD_RS 0x1130 -#define MX23_PAD_LCD_WR__LCD_WR 0x1140 -#define MX23_PAD_LCD_CS__LCD_CS 0x1150 -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 -#define MX23_PAD_PWM0__PWM0 0x11a0 -#define MX23_PAD_PWM1__PWM1 0x11b0 -#define MX23_PAD_PWM2__PWM2 0x11c0 -#define MX23_PAD_PWM3__PWM3 0x11d0 -#define MX23_PAD_PWM4__PWM4 0x11e0 -#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 -#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 -#define MX23_PAD_ROTARYA__ROTARYA 0x2070 -#define MX23_PAD_ROTARYB__ROTARYB 0x2080 -#define MX23_PAD_EMI_A00__EMI_A00 0x2090 -#define MX23_PAD_EMI_A01__EMI_A01 0x20a0 -#define MX23_PAD_EMI_A02__EMI_A02 0x20b0 -#define MX23_PAD_EMI_A03__EMI_A03 0x20c0 -#define MX23_PAD_EMI_A04__EMI_A04 0x20d0 -#define MX23_PAD_EMI_A05__EMI_A05 0x20e0 -#define MX23_PAD_EMI_A06__EMI_A06 0x20f0 -#define MX23_PAD_EMI_A07__EMI_A07 0x2100 -#define MX23_PAD_EMI_A08__EMI_A08 0x2110 -#define MX23_PAD_EMI_A09__EMI_A09 0x2120 -#define MX23_PAD_EMI_A10__EMI_A10 0x2130 -#define MX23_PAD_EMI_A11__EMI_A11 0x2140 -#define MX23_PAD_EMI_A12__EMI_A12 0x2150 -#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160 -#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170 -#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180 -#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 -#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 -#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 -#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 -#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 -#define MX23_PAD_EMI_D00__EMI_D00 0x3000 -#define MX23_PAD_EMI_D01__EMI_D01 0x3010 -#define MX23_PAD_EMI_D02__EMI_D02 0x3020 -#define MX23_PAD_EMI_D03__EMI_D03 0x3030 -#define MX23_PAD_EMI_D04__EMI_D04 0x3040 -#define MX23_PAD_EMI_D05__EMI_D05 0x3050 -#define MX23_PAD_EMI_D06__EMI_D06 0x3060 -#define MX23_PAD_EMI_D07__EMI_D07 0x3070 -#define MX23_PAD_EMI_D08__EMI_D08 0x3080 -#define MX23_PAD_EMI_D09__EMI_D09 0x3090 -#define MX23_PAD_EMI_D10__EMI_D10 0x30a0 -#define MX23_PAD_EMI_D11__EMI_D11 0x30b0 -#define MX23_PAD_EMI_D12__EMI_D12 0x30c0 -#define MX23_PAD_EMI_D13__EMI_D13 0x30d0 -#define MX23_PAD_EMI_D14__EMI_D14 0x30e0 -#define MX23_PAD_EMI_D15__EMI_D15 0x30f0 -#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 -#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 -#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 -#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 -#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140 -#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 -#define MX23_PAD_GPMI_D00__LCD_D8 0x0001 -#define MX23_PAD_GPMI_D01__LCD_D9 0x0011 -#define MX23_PAD_GPMI_D02__LCD_D10 0x0021 -#define MX23_PAD_GPMI_D03__LCD_D11 0x0031 -#define MX23_PAD_GPMI_D04__LCD_D12 0x0041 -#define MX23_PAD_GPMI_D05__LCD_D13 0x0051 -#define MX23_PAD_GPMI_D06__LCD_D14 0x0061 -#define MX23_PAD_GPMI_D07__LCD_D15 0x0071 -#define MX23_PAD_GPMI_D08__LCD_D18 0x0081 -#define MX23_PAD_GPMI_D09__LCD_D19 0x0091 -#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1 -#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1 -#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1 -#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1 -#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 -#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 -#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101 -#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111 -#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 -#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 -#define MX23_PAD_AUART1_RX__IR_RX 0x01c1 -#define MX23_PAD_AUART1_TX__IR_TX 0x01d1 -#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 -#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 -#define MX23_PAD_LCD_D00__ETM_DA8 0x1001 -#define MX23_PAD_LCD_D01__ETM_DA9 0x1011 -#define MX23_PAD_LCD_D02__ETM_DA10 0x1021 -#define MX23_PAD_LCD_D03__ETM_DA11 0x1031 -#define MX23_PAD_LCD_D04__ETM_DA12 0x1041 -#define MX23_PAD_LCD_D05__ETM_DA13 0x1051 -#define MX23_PAD_LCD_D06__ETM_DA14 0x1061 -#define MX23_PAD_LCD_D07__ETM_DA15 0x1071 -#define MX23_PAD_LCD_D08__ETM_DA0 0x1081 -#define MX23_PAD_LCD_D09__ETM_DA1 0x1091 -#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1 -#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1 -#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1 -#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1 -#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1 -#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1 -#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 -#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131 -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 -#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 -#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 -#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 -#define MX23_PAD_PWM0__ROTARYA 0x11a1 -#define MX23_PAD_PWM1__ROTARYB 0x11b1 -#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1 -#define MX23_PAD_PWM3__ETM_TCTL 0x11d1 -#define MX23_PAD_PWM4__ETM_TCLK 0x11e1 -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 -#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 -#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 -#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071 -#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081 -#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 -#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 -#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 -#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 -#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 -#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 -#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 -#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 -#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 -#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 -#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 -#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 -#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 -#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 -#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 -#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 -#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 -#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 -#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 -#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 -#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 -#define MX23_PAD_PWM0__DUART_RX 0x11a2 -#define MX23_PAD_PWM1__DUART_TX 0x11b2 -#define MX23_PAD_PWM3__AUART1_CTS 0x11d2 -#define MX23_PAD_PWM4__AUART1_RTS 0x11e2 -#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 -#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 -#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 -#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 -#define MX23_PAD_ROTARYA__SPDIF 0x2072 -#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 -#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 -#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 -#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 -#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 -#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 -#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 -#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 -#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 -#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 -#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 -#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 -#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 -#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 -#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 -#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 -#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 -#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 -#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 -#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 -#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 -#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133 -#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143 -#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153 -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 -#define MX23_PAD_PWM0__GPIO_1_26 0x11a3 -#define MX23_PAD_PWM1__GPIO_1_27 0x11b3 -#define MX23_PAD_PWM2__GPIO_1_28 0x11c3 -#define MX23_PAD_PWM3__GPIO_1_29 0x11d3 -#define MX23_PAD_PWM4__GPIO_1_30 0x11e3 -#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 -#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 -#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073 -#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083 -#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093 -#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 -#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 -#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 -#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 -#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 -#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 -#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103 -#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113 -#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123 -#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133 -#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143 -#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153 -#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 -#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 -#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 -#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 -#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 -#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 -#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 -#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 - -#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx23-sansa.dts b/software/linux/kernel/arch/arm/boot/dts/imx23-sansa.dts deleted file mode 100644 index 4ec32f4c7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx23-sansa.dts +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (C) 2013-2016 Marek Vasut - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "SanDisk Sansa Fuze+"; - compatible = "sandisk,sansa_fuze_plus", "fsl,imx23"; - - memory { - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - cd-inverted; - status = "okay"; - }; - - ssp1: ssp@80034000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_8bit_pins_a>; - bus-width = <8>; - vmmc-supply = <®_vddio_sd1>; - non-removable; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D08__GPIO_0_8 - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_AUART1_RTS__GPIO_0_27 - MX23_PAD_AUART1_CTS__GPIO_0_26 - MX23_PAD_I2C_SCL__I2C_SCL - MX23_PAD_I2C_SDA__I2C_SDA - MX23_PAD_LCD_DOTCK__GPIO_1_22 - MX23_PAD_LCD_HSYNC__GPIO_1_24 - MX23_PAD_PWM3__GPIO_1_29 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - }; - }; - - apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "peripheral"; - status = "okay"; - }; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 8 0>; - }; - - reg_vddio_sd1: regulator-vddio-sd1 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - - reg_vdd_touchpad: regulator-vdd-touchpad0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-touchpad0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 26 0>; - regulator-always-on; - enable-active-low; - }; - - reg_vdd_tuner: regulator-vdd-tuner0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-tuner0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 29 0>; - regulator-always-on; - enable-active-low; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c-0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = < - &gpio1 24 0 /* SDA */ - &gpio1 22 0 /* SCL */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - }; - - i2c-1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = < - &gpio0 31 0 /* SDA */ - &gpio0 30 0 /* SCL */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - - touch: touch@20 { - compatible = "synaptics,synaptics_i2c"; - reg = <0x20>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - }; - -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/software/linux/kernel/arch/arm/boot/dts/imx23-stmp378x_devb.dts deleted file mode 100644 index 455169e99..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Freescale STMP378x Development Board"; - compatible = "fsl,stmp378x-devb", "fsl,imx23"; - - memory { - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - wp-gpios = <&gpio1 30 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_PWM4__GPIO_1_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - auart0: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_vddio_sd0: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx23-xfi3.dts b/software/linux/kernel/arch/arm/boot/dts/imx23-xfi3.dts deleted file mode 100644 index 025cf9496..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx23-xfi3.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2013-2016 Marek Vasut - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx23.dtsi" - -/ { - model = "Creative ZEN X-Fi3"; - compatible = "creative,x-fi3", "fsl,imx23"; - - memory { - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - cd-inverted; - status = "okay"; - }; - - ssp1: ssp@80034000 { - compatible = "fsl,imx23-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_4bit_pins_a>; - bus-width = <4>; - non-removable; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - key_pins_a: keys@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_ROTARYA__GPIO_2_7 - MX23_PAD_ROTARYB__GPIO_2_8 - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; - }; - }; - }; - - apbx@80040000 { - i2c: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_a>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart1: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_2pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - dr_mode = "peripheral"; - status = "okay"; - }; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0 7 0>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_a>; - - voldown { - label = "volume-down"; - linux,code = <114>; - gpios = <&gpio2 7 0>; - debounce-interval = <20>; - }; - - volup { - label = "volume-up"; - linux,code = <115>; - gpios = <&gpio2 8 0>; - debounce-interval = <20>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx23.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx23.dtsi deleted file mode 100644 index 440ee9a4a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx23.dtsi +++ /dev/null @@ -1,624 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" -#include "imx23-pinfunc.h" - -/ { - interrupt-parent = <&icoll>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - serial0 = &auart0; - serial1 = &auart1; - spi0 = &ssp0; - spi1 = &ssp1; - usbphy0 = &usbphy0; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - apb@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x80000>; - ranges; - - apbh@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x40000>; - ranges; - - icoll: interrupt-controller@80000000 { - compatible = "fsl,imx23-icoll", "fsl,icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80000000 0x2000>; - }; - - dma_apbh: dma-apbh@80004000 { - compatible = "fsl,imx23-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <0 14 20 0 - 13 13 13 13>; - interrupt-names = "empty", "ssp0", "ssp1", "empty", - "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <8>; - clocks = <&clks 15>; - }; - - ecc@80008000 { - reg = <0x80008000 0x2000>; - status = "disabled"; - }; - - gpmi-nand@8000c000 { - compatible = "fsl,imx23-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <56>; - interrupt-names = "bch"; - clocks = <&clks 34>; - clock-names = "gpmi_io"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp0: ssp@80010000 { - reg = <0x80010000 0x2000>; - interrupts = <15>; - clocks = <&clks 33>; - dmas = <&dma_apbh 1>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - etm@80014000 { - reg = <0x80014000 0x2000>; - status = "disabled"; - }; - - pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-pinctrl", "simple-bus"; - reg = <0x80018000 0x2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <0>; - interrupts = <16>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <1>; - interrupts = <17>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; - reg = <2>; - interrupts = <18>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - duart_pins_a: duart@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM0__DUART_RX - MX23_PAD_PWM1__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_pins_a: auart0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_AUART1_RX__AUART1_RX - MX23_PAD_AUART1_TX__AUART1_TX - MX23_PAD_AUART1_CTS__AUART1_CTS - MX23_PAD_AUART1_RTS__AUART1_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_2pins_a: auart0-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_I2C_SCL__AUART1_TX - MX23_PAD_I2C_SDA__AUART1_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_2pins_a: auart1-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D14__AUART2_RX - MX23_PAD_GPMI_D15__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_a: gpmi-nand@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__GPMI_D00 - MX23_PAD_GPMI_D01__GPMI_D01 - MX23_PAD_GPMI_D02__GPMI_D02 - MX23_PAD_GPMI_D03__GPMI_D03 - MX23_PAD_GPMI_D04__GPMI_D04 - MX23_PAD_GPMI_D05__GPMI_D05 - MX23_PAD_GPMI_D06__GPMI_D06 - MX23_PAD_GPMI_D07__GPMI_D07 - MX23_PAD_GPMI_CLE__GPMI_CLE - MX23_PAD_GPMI_ALE__GPMI_ALE - MX23_PAD_GPMI_RDY0__GPMI_RDY0 - MX23_PAD_GPMI_RDY1__GPMI_RDY1 - MX23_PAD_GPMI_WPN__GPMI_WPN - MX23_PAD_GPMI_WRN__GPMI_WRN - MX23_PAD_GPMI_RDN__GPMI_RDN - MX23_PAD_GPMI_CE1N__GPMI_CE1N - MX23_PAD_GPMI_CE0N__GPMI_CE0N - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_fixup: gpmi-pins-fixup { - fsl,pinmux-ids = < - MX23_PAD_GPMI_WPN__GPMI_WPN - MX23_PAD_GPMI_WRN__GPMI_WRN - MX23_PAD_GPMI_RDN__GPMI_RDN - >; - fsl,drive-strength = ; - }; - - mmc0_4bit_pins_a: mmc0-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA0__SSP1_DATA0 - MX23_PAD_SSP1_DATA1__SSP1_DATA1 - MX23_PAD_SSP1_DATA2__SSP1_DATA2 - MX23_PAD_SSP1_DATA3__SSP1_DATA3 - MX23_PAD_SSP1_CMD__SSP1_CMD - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA0__SSP1_DATA0 - MX23_PAD_SSP1_DATA1__SSP1_DATA1 - MX23_PAD_SSP1_DATA2__SSP1_DATA2 - MX23_PAD_SSP1_DATA3__SSP1_DATA3 - MX23_PAD_GPMI_D08__SSP1_DATA4 - MX23_PAD_GPMI_D09__SSP1_DATA5 - MX23_PAD_GPMI_D10__SSP1_DATA6 - MX23_PAD_GPMI_D11__SSP1_DATA7 - MX23_PAD_SSP1_CMD__SSP1_CMD - MX23_PAD_SSP1_DETECT__SSP1_DETECT - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_pins_fixup: mmc0-pins-fixup { - fsl,pinmux-ids = < - MX23_PAD_SSP1_DETECT__SSP1_DETECT - MX23_PAD_SSP1_SCK__SSP1_SCK - >; - fsl,pull-up = ; - }; - - mmc1_4bit_pins_a: mmc1-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D01__SSP2_DATA1 - MX23_PAD_GPMI_D02__SSP2_DATA2 - MX23_PAD_GPMI_D03__SSP2_DATA3 - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_WRN__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc1_8bit_pins_a: mmc1-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D01__SSP2_DATA1 - MX23_PAD_GPMI_D02__SSP2_DATA2 - MX23_PAD_GPMI_D03__SSP2_DATA3 - MX23_PAD_GPMI_D04__SSP2_DATA4 - MX23_PAD_GPMI_D05__SSP2_DATA5 - MX23_PAD_GPMI_D06__SSP2_DATA6 - MX23_PAD_GPMI_D07__SSP2_DATA7 - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_WRN__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm2_pins_a: pwm2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_PWM2__PWM2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_24bit_pins_a: lcdif-24bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_LCD_D00__LCD_D00 - MX23_PAD_LCD_D01__LCD_D01 - MX23_PAD_LCD_D02__LCD_D02 - MX23_PAD_LCD_D03__LCD_D03 - MX23_PAD_LCD_D04__LCD_D04 - MX23_PAD_LCD_D05__LCD_D05 - MX23_PAD_LCD_D06__LCD_D06 - MX23_PAD_LCD_D07__LCD_D07 - MX23_PAD_LCD_D08__LCD_D08 - MX23_PAD_LCD_D09__LCD_D09 - MX23_PAD_LCD_D10__LCD_D10 - MX23_PAD_LCD_D11__LCD_D11 - MX23_PAD_LCD_D12__LCD_D12 - MX23_PAD_LCD_D13__LCD_D13 - MX23_PAD_LCD_D14__LCD_D14 - MX23_PAD_LCD_D15__LCD_D15 - MX23_PAD_LCD_D16__LCD_D16 - MX23_PAD_LCD_D17__LCD_D17 - MX23_PAD_GPMI_D08__LCD_D18 - MX23_PAD_GPMI_D09__LCD_D19 - MX23_PAD_GPMI_D10__LCD_D20 - MX23_PAD_GPMI_D11__LCD_D21 - MX23_PAD_GPMI_D12__LCD_D22 - MX23_PAD_GPMI_D13__LCD_D23 - MX23_PAD_LCD_DOTCK__LCD_DOTCK - MX23_PAD_LCD_ENABLE__LCD_ENABLE - MX23_PAD_LCD_HSYNC__LCD_HSYNC - MX23_PAD_LCD_VSYNC__LCD_VSYNC - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_a: spi2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_GPMI_WRN__SSP2_SCK - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D03__SSP2_DATA3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_a: i2c@0 { - reg = <0>; - fsl,pinmux-ids = < - MX23_PAD_I2C_SCL__I2C_SCL - MX23_PAD_I2C_SDA__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_b: i2c@1 { - reg = <1>; - fsl,pinmux-ids = < - MX23_PAD_LCD_ENABLE__I2C_SCL - MX23_PAD_LCD_HSYNC__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c_pins_c: i2c@2 { - reg = <2>; - fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA1__I2C_SCL - MX23_PAD_SSP1_DATA2__I2C_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - digctl@8001c000 { - compatible = "fsl,imx23-digctl"; - reg = <0x8001c000 2000>; - status = "disabled"; - }; - - emi@80020000 { - reg = <0x80020000 0x2000>; - status = "disabled"; - }; - - dma_apbx: dma-apbx@80024000 { - compatible = "fsl,imx23-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <7 5 9 26 - 19 0 25 23 - 60 58 9 0 - 0 0 0 0>; - interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", - "saif0", "empty", "auart0-rx", "auart0-tx", - "auart1-rx", "auart1-tx", "saif1", "empty", - "empty", "empty", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 16>; - }; - - dcp@80028000 { - compatible = "fsl,imx23-dcp"; - reg = <0x80028000 0x2000>; - interrupts = <53 54>; - status = "okay"; - }; - - pxp@8002a000 { - reg = <0x8002a000 0x2000>; - status = "disabled"; - }; - - ocotp@8002c000 { - compatible = "fsl,imx23-ocotp", "fsl,ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8002c000 0x2000>; - clocks = <&clks 15>; - }; - - axi-ahb@8002e000 { - reg = <0x8002e000 0x2000>; - status = "disabled"; - }; - - lcdif@80030000 { - compatible = "fsl,imx23-lcdif"; - reg = <0x80030000 2000>; - interrupts = <46 45>; - clocks = <&clks 38>; - status = "disabled"; - }; - - ssp1: ssp@80034000 { - reg = <0x80034000 0x2000>; - interrupts = <2>; - clocks = <&clks 33>; - dmas = <&dma_apbh 2>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - tvenc@80038000 { - reg = <0x80038000 0x2000>; - status = "disabled"; - }; - }; - - apbx@80040000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80040000 0x40000>; - ranges; - - clks: clkctrl@80040000 { - compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; - }; - - saif0: saif@80042000 { - reg = <0x80042000 0x2000>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - power@80044000 { - reg = <0x80044000 0x2000>; - status = "disabled"; - }; - - saif1: saif@80046000 { - reg = <0x80046000 0x2000>; - dmas = <&dma_apbx 10>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - audio-out@80048000 { - reg = <0x80048000 0x2000>; - dmas = <&dma_apbx 1>; - dma-names = "tx"; - status = "disabled"; - }; - - audio-in@8004c000 { - reg = <0x8004c000 0x2000>; - dmas = <&dma_apbx 0>; - dma-names = "rx"; - status = "disabled"; - }; - - lradc: lradc@80050000 { - compatible = "fsl,imx23-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <36 37 38 39 40 41 42 43 44>; - status = "disabled"; - clocks = <&clks 26>; - #io-channel-cells = <1>; - }; - - spdif@80054000 { - reg = <0x80054000 2000>; - dmas = <&dma_apbx 2>; - dma-names = "tx"; - status = "disabled"; - }; - - i2c: i2c@80058000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx23-i2c"; - reg = <0x80058000 0x2000>; - interrupts = <27>; - clock-frequency = <100000>; - dmas = <&dma_apbx 3>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - rtc@8005c000 { - compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x8005c000 0x2000>; - interrupts = <22>; - }; - - pwm: pwm@80064000 { - compatible = "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; - clocks = <&clks 30>; - #pwm-cells = <2>; - fsl,pwm-number = <5>; - status = "disabled"; - }; - - timrot@80068000 { - compatible = "fsl,imx23-timrot", "fsl,timrot"; - reg = <0x80068000 0x2000>; - interrupts = <28 29 30 31>; - clocks = <&clks 28>; - }; - - auart0: serial@8006c000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <24>; - clocks = <&clks 32>; - dmas = <&dma_apbx 6>, <&dma_apbx 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - auart1: serial@8006e000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006e000 0x2000>; - interrupts = <59>; - clocks = <&clks 32>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - duart: serial@80070000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80070000 0x2000>; - interrupts = <0>; - clocks = <&clks 32>, <&clks 16>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; - }; - - usbphy0: usbphy@8007c000 { - compatible = "fsl,imx23-usbphy"; - reg = <0x8007c000 0x2000>; - clocks = <&clks 41>; - status = "disabled"; - }; - }; - }; - - ahb@80080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80080000 0x80000>; - ranges; - - usb0: usb@80080000 { - compatible = "fsl,imx23-usb", "fsl,imx27-usb"; - reg = <0x80080000 0x40000>; - interrupts = <11>; - fsl,usbphy = <&usbphy0>; - clocks = <&clks 40>; - status = "disabled"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&lradc 8>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi deleted file mode 100644 index d6f27641c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "imx25.dtsi" - -/ { - model = "Eukrea CPUIMX25"; - compatible = "eukrea,cpuimx25", "fsl,imx25"; - - memory { - reg = <0x80000000 0x4000000>; /* 64M */ - }; -}; - -&fec { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&iomuxc { - imx25-eukrea-cpuimx25 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts deleted file mode 100644 index 68d0834a2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the CMO-QVGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - cmo_qvga: display { - model = "CMO-QVGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xcad08b80>; - bus-width = <18>; - native-mode = <&qvga_timings>; - display-timings { - qvga_timings: 320x240 { - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <30>; - hfront-porch = <38>; - vback-porch = <20>; - vfront-porch = <3>; - hsync-len = <15>; - vsync-len = <4>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_lcd_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&iomuxc { - imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { - pinctrl_reg_lcd_3v3: reg_lcd_3v3 { - fsl,pins = ; - }; - }; -}; - -&lcdc { - display = <&cmo_qvga>; - fsl,lpccr = <0x00a903ff>; - lcd-supply = <®_lcd_3v3>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts deleted file mode 100644 index 8eee2f65f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the DVI-SVGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - dvi_svga: display { - model = "DVI-SVGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - native-mode = <&dvi_svga_timings>; - display-timings { - dvi_svga_timings: 800x600 { - clock-frequency = <40000000>; - hactive = <800>; - vactive = <600>; - hback-porch = <75>; - hfront-porch = <75>; - vback-porch = <7>; - vfront-porch = <75>; - hsync-len = <7>; - vsync-len = <7>; - }; - }; - }; -}; - -&lcdc { - display = <&dvi_svga>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts deleted file mode 100644 index 447da6263..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "imx25-eukrea-mbimxsd25-baseboard.dts" - -/ { - model = "Eukrea MBIMXSD25 with the DVI-VGA Display"; - compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - dvi_vga: display { - model = "DVI-VGA"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - native-mode = <&dvi_vga_timings>; - display-timings { - dvi_vga_timings: 640x480 { - clock-frequency = <31250000>; - hactive = <640>; - vactive = <480>; - hback-porch = <100>; - hfront-porch = <100>; - vback-porch = <7>; - vfront-porch = <100>; - hsync-len = <7>; - vsync-len = <7>; - }; - }; - }; -}; - -&lcdc { - display = <&dvi_vga>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts deleted file mode 100644 index 9300711f1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; - -#include -#include -#include "imx25-eukrea-cpuimx25.dtsi" - -/ { - model = "Eukrea MBIMXSD25"; - compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - bp1 { - label = "BP1"; - gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioled>; - - led1 { - label = "led1"; - gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx25-eukrea-tlv320aic23"; - ssi-controller = <&ssi1>; - fsl,mux-int-port = <1>; - fsl,mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 20>; - status = "okay"; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx25-eukrea-mbimxsd25-baseboard { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 - MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 - MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 - MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0 - MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0 - MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0 - MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0 - MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0 - MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0 - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = ; - }; - - pinctrl_gpioled: gpioledgrp { - fsl,pins = ; - }; - - pinctrl_lcdc: lcdcgrp { - fsl,pins = < - MX25_PAD_LD0__LD0 0x1 - MX25_PAD_LD1__LD1 0x1 - MX25_PAD_LD2__LD2 0x1 - MX25_PAD_LD3__LD3 0x1 - MX25_PAD_LD4__LD4 0x1 - MX25_PAD_LD5__LD5 0x1 - MX25_PAD_LD6__LD6 0x1 - MX25_PAD_LD7__LD7 0x1 - MX25_PAD_LD8__LD8 0x1 - MX25_PAD_LD9__LD9 0x1 - MX25_PAD_LD10__LD10 0x1 - MX25_PAD_LD11__LD11 0x1 - MX25_PAD_LD12__LD12 0x1 - MX25_PAD_LD13__LD13 0x1 - MX25_PAD_LD14__LD14 0x1 - MX25_PAD_LD15__LD15 0x1 - MX25_PAD_GPIO_E__LD16 0x1 - MX25_PAD_GPIO_F__LD17 0x1 - MX25_PAD_HSYNC__HSYNC 0x80000000 - MX25_PAD_VSYNC__VSYNC 0x80000000 - MX25_PAD_LSCLK__LSCLK 0x80000000 - MX25_PAD_OE_ACD__OE_ACD 0x80000000 - MX25_PAD_CONTRAST__CONTRAST 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 - MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 - MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 - MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 - >; - }; - }; -}; - -&ssi1 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - phy_type = "serial"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "otg"; - external-vbus-divider; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25-karo-tx25.dts b/software/linux/kernel/arch/arm/boot/dts/imx25-karo-tx25.dts deleted file mode 100644 index 9b31faa96..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25-karo-tx25.dts +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx25.dtsi" - -/ { - model = "Ka-Ro TX25"; - compatible = "karo,imx25-tx25", "fsl,imx25"; - - chosen { - stdout-path = &uart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_fec_phy: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "fec-phy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 9 0>; - enable-active-high; - }; - }; - - memory { - reg = <0x80000000 0x02000000 0x90000000 0x02000000>; - }; -}; - -&iomuxc { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 - MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 - MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ - MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX25_PAD_NF_CE0__NF_CE0 0x80000000 - MX25_PAD_NFWE_B__NFWE_B 0x80000000 - MX25_PAD_NFRE_B__NFRE_B 0x80000000 - MX25_PAD_NFALE__NFALE 0x80000000 - MX25_PAD_NFCLE__NFCLE 0x80000000 - MX25_PAD_NFWP_B__NFWP_B 0x80000000 - MX25_PAD_NFRB__NFRB 0x80000000 - MX25_PAD_D7__D7 0x80000000 - MX25_PAD_D6__D6 0x80000000 - MX25_PAD_D5__D5 0x80000000 - MX25_PAD_D4__D4 0x80000000 - MX25_PAD_D3__D3 0x80000000 - MX25_PAD_D2__D2 0x80000000 - MX25_PAD_D1__D1 0x80000000 - MX25_PAD_D0__D0 0x80000000 - >; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-reset-gpios = <&gpio3 7 0>; - phy-mode = "rmii"; - phy-supply = <®_fec_phy>; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-bus-width = <8>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25-pdk.dts b/software/linux/kernel/arch/arm/boot/dts/imx25-pdk.dts deleted file mode 100644 index 70292101b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25-pdk.dts +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include -#include -#include "imx25.dtsi" - -/ { - model = "Freescale i.MX25 Product Development Kit"; - compatible = "fsl,imx25-pdk", "fsl,imx25"; - - memory { - reg = <0x80000000 0x4000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_fec_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 3 0>; - enable-active-high; - }; - - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can_3v3: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 6 0>; - }; - }; - - sound { - compatible = "fsl,imx25-pdk-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx25-pdk-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - wvga: display { - model = "CLAA057VC01CW"; - bits-per-pixel = <16>; - fsl,pcr = <0xfa208b80>; - bus-width = <18>; - native-mode = <&wvga_timings>; - display-timings { - wvga_timings: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <45>; - hfront-porch = <114>; - hsync-len = <1>; - vback-porch = <33>; - vfront-porch = <11>; - vsync-len = <1>; - clock-frequency = <25200000>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_3v3>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 8 0>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks 129>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&iomuxc { - imx25-pdk { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX25_PAD_RW__AUD4_TXFS 0xe0 - MX25_PAD_OE__AUD4_TXC 0xe0 - MX25_PAD_EB0__AUD4_TXD 0xe0 - MX25_PAD_EB1__AUD4_RXD 0xe0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX25_PAD_GPIO_A__CAN1_TX 0x0 - MX25_PAD_GPIO_B__CAN1_RX 0x0 - MX25_PAD_D14__GPIO_4_6 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 - MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 - MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 - MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 - MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 - MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 - MX25_PAD_A14__GPIO_2_0 0x80000000 - MX25_PAD_A15__GPIO_2_1 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - MX25_PAD_A17__GPIO_2_3 0x80000000 - MX25_PAD_D12__GPIO_4_8 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 - MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 - MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 - MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 - MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 - MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 - MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 - MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX25_PAD_LD0__LD0 0xe0 - MX25_PAD_LD1__LD1 0xe0 - MX25_PAD_LD2__LD2 0xe0 - MX25_PAD_LD3__LD3 0xe0 - MX25_PAD_LD4__LD4 0xe0 - MX25_PAD_LD5__LD5 0xe0 - MX25_PAD_LD6__LD6 0xe0 - MX25_PAD_LD7__LD7 0xe0 - MX25_PAD_LD8__LD8 0xe0 - MX25_PAD_LD9__LD9 0xe0 - MX25_PAD_LD10__LD10 0xe0 - MX25_PAD_LD11__LD11 0xe0 - MX25_PAD_LD12__LD12 0xe0 - MX25_PAD_LD13__LD13 0xe0 - MX25_PAD_LD14__LD14 0xe0 - MX25_PAD_LD15__LD15 0xe0 - MX25_PAD_GPIO_E__LD16 0xe0 - MX25_PAD_GPIO_F__LD17 0xe0 - MX25_PAD_HSYNC__HSYNC 0xe0 - MX25_PAD_VSYNC__VSYNC 0xe0 - MX25_PAD_LSCLK__LSCLK 0xe0 - MX25_PAD_OE_ACD__OE_ACD 0xe0 - MX25_PAD_CONTRAST__CONTRAST 0xe0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - >; - }; - }; -}; - -&lcdc { - display = <&wvga>; - fsl,lpccr = <0x00a903ff>; - fsl,lscr1 = <0x00120300>; - fsl,dmacr = <0x00020010>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; -}; - -&nfc { - nand-on-flash-bbt; - status = "okay"; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0x0, 0x0, KEY_UP) - MATRIX_KEY(0x0, 0x1, KEY_DOWN) - MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) - MATRIX_KEY(0x0, 0x3, KEY_HOME) - MATRIX_KEY(0x1, 0x0, KEY_RIGHT) - MATRIX_KEY(0x1, 0x1, KEY_LEFT) - MATRIX_KEY(0x1, 0x2, KEY_ENTER) - MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) - MATRIX_KEY(0x2, 0x0, KEY_F6) - MATRIX_KEY(0x2, 0x1, KEY_F8) - MATRIX_KEY(0x2, 0x2, KEY_F9) - MATRIX_KEY(0x2, 0x3, KEY_F10) - MATRIX_KEY(0x3, 0x0, KEY_F1) - MATRIX_KEY(0x3, 0x1, KEY_F2) - MATRIX_KEY(0x3, 0x2, KEY_F3) - MATRIX_KEY(0x3, 0x2, KEY_POWER) - >; - status = "okay"; -}; - -&ssi1 { - codec-handle = <&codec>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - phy_type = "serial"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "otg"; - external-vbus-divider; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx25-pinfunc.h deleted file mode 100644 index f840f03ad..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25-pinfunc.h +++ /dev/null @@ -1,605 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * Based on imx35-pinfunc.h in the same directory Which is: - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX25_PINFUNC_H -#define __DTS_IMX25_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000 - -#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 -#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 - -#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 -#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 -#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 - -#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 -#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 -#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 -#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 - -#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 -#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x05 0x000 -#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x06 0x000 -#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x07 0x000 - -#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x00 0x000 -#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x05 0x000 -#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x06 0x000 -#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x07 0x000 - -#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x00 0x000 -#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x05 0x000 -#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x06 0x000 -#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x07 0x000 - -#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x00 0x000 -#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x05 0x000 -#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x06 0x000 -#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x07 0x000 - -#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x00 0x000 -#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x05 0x000 -#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x06 0x000 -#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x07 0x000 - -#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x00 0x000 -#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x05 0x000 -#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x06 0x000 -#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x07 0x000 - -#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x00 0x000 -#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x05 0x000 -#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x06 0x000 -#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x07 0x000 - -#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x00 0x000 -#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x05 0x000 -#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000 -#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x06 0x000 -#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x07 0x000 - -#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x00 0x000 -#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x05 0x000 -#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x06 0x000 -#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x07 0x000 - -#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x00 0x000 -#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x05 0x000 -#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x06 0x000 -#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x07 0x000 - -#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x00 0x000 -#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x05 0x000 -#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x07 0x000 - -#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000 -#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000 -#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000 - -#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 -#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 -#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 - -#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 -#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 -#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x05 0x000 - -#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000 -#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000 -#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000 -#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000 - -#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x00 0x000 -#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 -#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000 -#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000 - -#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 -#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 -#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 -#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 - -#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 -#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 - -#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 -#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000 -#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000 - -#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 -#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 -#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 - -#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 -#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 - -#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x00 0x000 -#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x04 0x000 -#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x05 0x000 - -#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x00 0x000 -#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x05 0x000 - -#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x00 0x000 -#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x05 0x000 - -#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 -#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 -#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 -#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 - -#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 -#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 -#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 -#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 - -#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 -#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 -#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 -#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 - -#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 -#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 -#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 - -#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 -#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 -#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000 - -#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000 -#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000 -#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000 - -#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000 -#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000 -#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000 - -#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000 -#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000 -#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000 - -#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000 -#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000 - -#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000 -#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000 - -#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000 -#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000 - -#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000 -#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000 - -#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000 -#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000 - -#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000 -#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000 - -#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000 -#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000 - -#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000 -#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000 - -#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x00 0x000 -#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x02 0x000 -#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x05 0x000 - -#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x00 0x000 -#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x02 0x000 -#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x05 0x000 - -#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x00 0x000 -#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x05 0x000 - -#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x00 0x000 -#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x05 0x000 - -#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x00 0x000 -#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x05 0x000 - -#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x00 0x000 -#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x05 0x000 - -#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x00 0x000 -#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x05 0x000 - -#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x00 0x000 -#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x05 0x000 - -#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000 -#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000 -#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000 -#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000 - -#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000 -#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000 -#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001 -#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 - -#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 -#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 -#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001 - -#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000 -#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000 -#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001 -#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 - -#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 -#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 -#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001 - -#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000 -#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 -#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000 - -#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000 -#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000 -#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x05 0x000 - -#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x00 0x000 -#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000 -#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x05 0x001 - -#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x00 0x000 -#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x05 0x000 - -#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x00 0x000 -#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x05 0x000 - -#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x00 0x000 -#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x05 0x000 - -#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x00 0x000 -#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000 -#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 - -#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 -#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000 -#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 -#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 -#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 - -#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x00 0x000 -#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x05 0x000 -#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x06 0x001 - -#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x00 0x000 -#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 -#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 -#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 -#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000 - -#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 -#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 -#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000 -#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x05 0x000 -#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x07 0x001 - -#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000 -#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 -#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 -#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 -#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000 - -#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 -#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 -#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 -#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 -#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000 - -#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 -#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x02 0x001 -#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 -#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 - -#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 -#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x02 0x001 -#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 - -#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 -#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 -#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x05 0x000 -#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x07 0x000 - -#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x00 0x000 -#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x02 0x000 -#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x05 0x000 -#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x07 0x000 - -#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000 -#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000 -#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 -#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000 - -#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000 -#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000 -#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 -#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000 - -#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000 -#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000 -#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 -#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000 - -#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000 -#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000 -#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 -#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000 - -#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000 -#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x05 0x000 - -#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x00 0x000 -#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x02 0x000 -#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001 -#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x02 0x000 -#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x05 0x000 - -#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x00 0x000 -#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x05 0x000 - -#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000 -#define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000 -#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x05 0x000 - -#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000 -#define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000 -#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000 - -#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 -#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 -#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000 -#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 -#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 - -#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x00 0x000 -#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x01 0x001 -#define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001 -#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000 - -#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x00 0x000 -#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x05 0x000 - -#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x00 0x000 -#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x05 0x000 - -#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 -#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 -#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000 -#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 - -#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 -#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 -#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 - -/* - * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD - * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM - * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon - * bug that configuring the SD1_CMD function doesn't enable the input path for - * this pin. - * This might have side effects for other hardware units that are connected to - * that pin and use the respective function as input. - */ -#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 -#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001 -#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002 -#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000 - -#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x00 0x000 -#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001 -#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002 -#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001 -#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 -#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 -#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 - -#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x00 0x000 -#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 -#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001 -#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW1__UART3_TXD 0x1ac 0x3a4 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW1__UART1_DSR 0x1ac 0x3a4 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW2__UART3_RTS 0x1b0 0x3a8 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x03 0x002 -#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x05 0x000 - -#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x00 0x000 -#define MX25_PAD_KPP_ROW3__UART3_CTS 0x1b4 0x3ac 0x000 0x01 0x000 -#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x03 0x002 -#define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000 -#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x01 0x001 -#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x01 0x000 -#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001 -#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000 - -#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x00 0x000 -#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x01 0x000 -#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x02 0x000 -#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x000 -#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x001 -#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x000 - -#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x00 0x000 -#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x02 0x001 -#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x00 0x000 -#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x00 0x000 -#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x02 0x001 -#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000 -#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000 - -#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000 -#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000 - -#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000 -/* - * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, - * 01/2011) this is CAN1_TX but that's wrong. - */ -#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x04 0x000 -#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x05 0x000 - -#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x00 0x000 -/* - * According to the i.MX25 Reference manual (IMX25RM, Rev. 2, - * 01/2011) this is CAN1_RX but that's wrong. - */ -#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x04 0x000 -#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x05 0x000 - -#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x00 0x000 -#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x05 0x000 - -#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x00 0x000 -#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x01 0x000 -#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x05 0x000 - -#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 -#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 - -#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000 -#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 -#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 - -#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000 -#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 -#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 - -#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000 -#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 -#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 -#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 -#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 - -#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 -#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 -#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 - -#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 -#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 -#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 -#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 -#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 - -#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000 -#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 -#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 -#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 - -#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x00 0x000 -#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x05 0x000 - -#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x00 0x000 -#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x05 0x000 - -#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000 -#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000 -#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000 -#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 - -#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 -#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 - -#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 -#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x04 0x001 -#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x05 0x000 -#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x06 0x000 - -#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x00 0x000 -#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x05 0x000 - -#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000 -#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000 - -#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 -#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 - -#endif /* __DTS_IMX25_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx25.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx25.dtsi deleted file mode 100644 index af6af8741..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx25.dtsi +++ /dev/null @@ -1,606 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" -#include "imx25-pinfunc.h" - -/ { - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - pwm0 = &pwm1; - pwm1 = &pwm2; - pwm2 = &pwm3; - pwm3 = &pwm4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &spi1; - spi1 = &spi2; - spi2 = &spi3; - usb0 = &usbotg; - usb1 = &usbhost1; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - asic: asic-interrupt-controller@68000000 { - compatible = "fsl,imx25-asic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x8000000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&asic>; - ranges; - - aips@43f00000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - i2c1: i2c@43f80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f80000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <3>; - status = "disabled"; - }; - - i2c3: i2c@43f84000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f84000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <10>; - status = "disabled"; - }; - - can1: can@43f88000 { - compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; - reg = <0x43f88000 0x4000>; - interrupts = <43>; - clocks = <&clks 75>, <&clks 75>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can2: can@43f8c000 { - compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan"; - reg = <0x43f8c000 0x4000>; - interrupts = <44>; - clocks = <&clks 76>, <&clks 76>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@43f90000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 120>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - interrupts = <32>; - clocks = <&clks 121>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@43f98000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-i2c", "fsl,imx21-i2c"; - reg = <0x43f98000 0x4000>; - clocks = <&clks 48>; - clock-names = ""; - interrupts = <4>; - status = "disabled"; - }; - - owire@43f9c000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x43f9c000 0x4000>; - clocks = <&clks 51>; - clock-names = ""; - interrupts = <2>; - status = "disabled"; - }; - - spi1: cspi@43fa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x43fa4000 0x4000>; - clocks = <&clks 78>, <&clks 78>; - clock-names = "ipg", "per"; - interrupts = <14>; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - clocks = <&clks 102>; - clock-names = ""; - interrupts = <24>; - status = "disabled"; - }; - - iomuxc: iomuxc@43fac000 { - compatible = "fsl,imx25-iomuxc"; - reg = <0x43fac000 0x4000>; - }; - - audmux: audmux@43fb0000 { - compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; - reg = <0x43fb0000 0x4000>; - status = "disabled"; - }; - }; - - spba@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - spi3: cspi@50004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x50004000 0x4000>; - interrupts = <0>; - clocks = <&clks 80>, <&clks 80>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@50008000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x50008000 0x4000>; - interrupts = <5>; - clocks = <&clks 123>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <18>; - clocks = <&clks 122>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - spi2: cspi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; - reg = <0x50010000 0x4000>; - clocks = <&clks 79>, <&clks 79>; - clock-names = "ipg", "per"; - interrupts = <13>; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <11>; - clocks = <&clks 118>; - clock-names = "ipg"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - esai@50018000 { - reg = <0x50018000 0x4000>; - interrupts = <7>; - }; - - uart5: serial@5002c000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x5002c000 0x4000>; - interrupts = <40>; - clocks = <&clks 124>, <&clks 57>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - tscadc: tscadc@50030000 { - compatible = "fsl,imx25-tsadc"; - reg = <0x50030000 0xc>; - interrupts = <46>; - clocks = <&clks 119>; - clock-names = "ipg"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - - adc: adc@50030800 { - compatible = "fsl,imx25-gcq"; - reg = <0x50030800 0x60>; - interrupt-parent = <&tscadc>; - interrupts = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tsc: tcq@50030400 { - compatible = "fsl,imx25-tcq"; - reg = <0x50030400 0x60>; - interrupt-parent = <&tscadc>; - interrupts = <0>; - fsl,wires = <4>; - status = "disabled"; - }; - }; - - ssi1: ssi@50034000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; - reg = <0x50034000 0x4000>; - interrupts = <12>; - clocks = <&clks 117>; - clock-names = "ipg"; - dmas = <&sdma 28 1 0>, - <&sdma 29 1 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - fec: ethernet@50038000 { - compatible = "fsl,imx25-fec"; - reg = <0x50038000 0x4000>; - interrupts = <57>; - clocks = <&clks 88>, <&clks 65>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - }; - - aips@53f00000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - clks: ccm@53f80000 { - compatible = "fsl,imx25-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; - }; - - gpt4: timer@53f84000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f84000 0x4000>; - clocks = <&clks 95>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <1>; - }; - - gpt3: timer@53f88000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f88000 0x4000>; - clocks = <&clks 94>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <29>; - }; - - gpt2: timer@53f8c000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f8c000 0x4000>; - clocks = <&clks 93>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <53>; - }; - - gpt1: timer@53f90000 { - compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - clocks = <&clks 92>, <&clks 47>; - clock-names = "ipg", "per"; - interrupts = <54>; - }; - - epit1: timer@53f94000 { - compatible = "fsl,imx25-epit"; - reg = <0x53f94000 0x4000>; - interrupts = <28>; - }; - - epit2: timer@53f98000 { - compatible = "fsl,imx25-epit"; - reg = <0x53f98000 0x4000>; - interrupts = <27>; - }; - - gpio4: gpio@53f9c000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53f9c000 0x4000>; - interrupts = <23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwm2: pwm@53fa0000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; - reg = <0x53fa0000 0x4000>; - clocks = <&clks 106>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <36>; - }; - - gpio3: gpio@53fa4000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fa4000 0x4000>; - interrupts = <16>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwm3: pwm@53fa8000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; - reg = <0x53fa8000 0x4000>; - clocks = <&clks 107>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <41>; - }; - - scc: crypto@53fac000 { - compatible = "fsl,imx25-scc"; - reg = <0x53fac000 0x4000>; - clocks = <&clks 111>; - clock-names = "ipg"; - interrupts = <49>, <50>; - interrupt-names = "scm", "smn"; - }; - - esdhc1: esdhc@53fb4000 { - compatible = "fsl,imx25-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <9>; - clocks = <&clks 86>, <&clks 63>, <&clks 45>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: esdhc@53fb8000 { - compatible = "fsl,imx25-esdhc"; - reg = <0x53fb8000 0x4000>; - interrupts = <8>; - clocks = <&clks 87>, <&clks 64>, <&clks 46>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - lcdc: lcdc@53fbc000 { - compatible = "fsl,imx25-fb", "fsl,imx21-fb"; - reg = <0x53fbc000 0x4000>; - interrupts = <39>; - clocks = <&clks 103>, <&clks 66>, <&clks 49>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - slcdc@53fc0000 { - reg = <0x53fc0000 0x4000>; - interrupts = <38>; - status = "disabled"; - }; - - pwm4: pwm@53fc8000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; - reg = <0x53fc8000 0x4000>; - clocks = <&clks 108>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <42>; - }; - - gpio1: gpio@53fcc000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fcc000 0x4000>; - interrupts = <52>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53fd0000 { - compatible = "fsl,imx25-gpio", "fsl,imx35-gpio"; - reg = <0x53fd0000 0x4000>; - interrupts = <51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sdma: sdma@53fd4000 { - compatible = "fsl,imx25-sdma"; - reg = <0x53fd4000 0x4000>; - clocks = <&clks 112>, <&clks 68>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - interrupts = <34>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; - }; - - wdog@53fdc000 { - compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; - reg = <0x53fdc000 0x4000>; - clocks = <&clks 126>; - clock-names = ""; - interrupts = <55>; - }; - - pwm1: pwm@53fe0000 { - compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; - reg = <0x53fe0000 0x4000>; - clocks = <&clks 105>, <&clks 52>; - clock-names = "ipg", "per"; - interrupts = <26>; - }; - - iim: iim@53ff0000 { - compatible = "fsl,imx25-iim", "fsl,imx27-iim"; - reg = <0x53ff0000 0x4000>; - interrupts = <19>; - clocks = <&clks 99>; - }; - - usbotg: usb@53ff4000 { - compatible = "fsl,imx25-usb", "fsl,imx27-usb"; - reg = <0x53ff4000 0x0200>; - interrupts = <37>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbhost1: usb@53ff4400 { - compatible = "fsl,imx25-usb", "fsl,imx27-usb"; - reg = <0x53ff4400 0x0200>; - interrupts = <35>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - status = "disabled"; - }; - - usbmisc: usbmisc@53ff4600 { - #index-cells = <1>; - compatible = "fsl,imx25-usbmisc"; - reg = <0x53ff4600 0x00f>; - }; - - dryice@53ffc000 { - compatible = "fsl,imx25-dryice", "fsl,imx25-rtc"; - reg = <0x53ffc000 0x4000>; - clocks = <&clks 81>; - clock-names = "ipg"; - interrupts = <25>; - }; - }; - - iram: sram@78000000 { - compatible = "mmio-sram"; - reg = <0x78000000 0x20000>; - }; - - emi@80000000 { - compatible = "fsl,emi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x3b002000>; - ranges; - - nfc: nand@bb000000 { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "fsl,imx25-nand"; - reg = <0xbb000000 0x2000>; - clocks = <&clks 50>; - clock-names = ""; - interrupts = <33>; - status = "disabled"; - }; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy@0 { - reg = <0>; - compatible = "usb-nop-xceiv"; - }; - - usbphy1: usb-phy@1 { - reg = <1>; - compatible = "usb-nop-xceiv"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-apf27.dts b/software/linux/kernel/arch/arm/boot/dts/imx27-apf27.dts deleted file mode 100644 index 73aae4f5e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-apf27.dts +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright 2012 Philippe Reynes - * Copyright 2012 Armadeus Systems - * - * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Armadeus Systems APF27 module"; - compatible = "armadeus,imx27-apf27", "fsl,imx27"; - - memory { - reg = <0xa0000000 0x04000000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc26m { - compatible = "fsl,imx-osc26m", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; -}; - -&iomuxc { - imx27-apf27 { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&nfc { - status = "okay"; - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "env2"; - reg = <0x180000 0x80000>; - }; - - partition@200000 { - label = "firmware"; - reg = <0x200000 0x80000>; - }; - - partition@280000 { - label = "dtb"; - reg = <0x280000 0x80000>; - }; - - partition@300000 { - label = "kernel"; - reg = <0x300000 0x500000>; - }; - - partition@800000 { - label = "rootfs"; - reg = <0x800000 0xf800000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-apf27dev.dts b/software/linux/kernel/arch/arm/boot/dts/imx27-apf27dev.dts deleted file mode 100644 index bba3f41b8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-apf27dev.dts +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright 2013 Armadeus Systems - - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* APF27Dev is a docking board for the APF27 SOM */ -#include "imx27-apf27.dts" - -/ { - model = "Armadeus Systems APF27Dev docking/development board"; - compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; - - display: display { - model = "Chimei-LW700AT9003"; - native-mode = <&timing0>; - bits-per-pixel = <16>; /* non-standard but required */ - fsl,pcr = <0xfae80083>; /* non-standard but required */ - display-timings { - timing0: 800x480 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - user-key { - label = "user"; - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - linux,code = <276>; /* BTN_EXTRA */ - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user { - label = "Heartbeat"; - gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_max5821: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "max5821-reg"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; -}; - -&cspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; - status = "okay"; - - adc@0 { - compatible = "maxim,max1027"; - reg = <0>; - interrupt-parent = <&gpio5>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_max1027>; - spi-max-frequency = <10000000>; - }; -}; - -&cspi2 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, - <&gpio4 27 GPIO_ACTIVE_LOW>, - <&gpio2 17 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; - status = "okay"; -}; - -&fb { - display = <&display>; - fsl,dmacr = <0x00020010>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb1>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - max5821@38 { - compatible = "maxim,max5821"; - reg = <0x38>; - vref-supply = <®_max5821>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - imx27-apf27dev { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - >; - }; - - pinctrl_cspi1_cs: cspi1csgrp { - fsl,pins = ; - }; - - pinctrl_cspi2: cspi2grp { - fsl,pins = < - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - >; - }; - - pinctrl_cspi2_cs: cspi2csgrp { - fsl,pins = < - MX27_PAD_CSI_D5__GPIO2_17 0x0 - MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 - MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = ; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = ; - }; - - pinctrl_imxfb1: imxfbgrp { - fsl,pins = < - MX27_PAD_CLS__CLS 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_LSCLK__LSCLK 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_PS__PS 0x0 - MX27_PAD_REV__REV 0x0 - MX27_PAD_SPL_SPR__SPL_SPR 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_max1027: max1027 { - fsl,pins = < - MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ - MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ - >; - }; - - pinctrl_pwm: pwmgrp { - fsl,pins = < - MX27_PAD_PWMO__PWMO 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - >; - }; - - pinctrl_sdhc2_cd: sdhc2cdgrp { - fsl,pins = ; - }; - }; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi deleted file mode 100644 index 2cf896c50..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (C) 2014 Alexander Shiyan - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Eukrea CPUIMX27"; - compatible = "eukrea,cpuimx27", "fsl,imx27"; - - memory { - reg = <0xa0000000 0x04000000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - clk14745600: clock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <14745600>; - reg = <0>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire>; - status = "okay"; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - dr_mode = "host"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&weim { - status = "okay"; - - nor: nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0 0x00000000 0x04000000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; - }; - - uart8250@3,200000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_1>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x200000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,400000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_2>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x400000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,800000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_3>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x800000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; - - uart8250@3,1000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8250_4>; - compatible = "ns8250"; - clocks = <&clk14745600>; - fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; - reg = <3 0x1000000 0x1000>; - reg-shift = <1>; - reg-io-width = <1>; - no-loopback-test; - }; -}; - -&iomuxc { - imx27-eukrea-cpuimx27 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_owire: owiregrp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 - MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 - MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 - MX27_PAD_USBH1_FS__UART4_RTS 0x0 - >; - }; - - pinctrl_uart8250_1: uart82501grp { - fsl,pins = < - MX27_PAD_USB_PWR__GPIO2_23 0x0 - >; - }; - - pinctrl_uart8250_2: uart82502grp { - fsl,pins = < - MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 - >; - }; - - pinctrl_uart8250_3: uart82503grp { - fsl,pins = < - MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 - >; - }; - - pinctrl_uart8250_4: uart82504grp { - fsl,pins = < - MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts deleted file mode 100644 index 27846ff9b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (C) 2014 Alexander Shiyan - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx27-eukrea-cpuimx27.dtsi" - -/ { - model = "Eukrea MBIMXSD27"; - compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27"; - - display0: CMO-QVGA { - model = "CMO-QVGA"; - native-mode = <&timing0>; - bits-per-pixel = <16>; - fsl,pcr = <0xfad08b80>; - - display-timings { - timing0: 320x240 { - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <20>; - hsync-len = <30>; - hfront-porch = <38>; - vback-porch = <4>; - vsync-len = <3>; - vfront-porch = <15>; - }; - }; - }; - - backlight { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioleds>; - - led1 { - label = "system::live"; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "system::user"; - gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - reg_lcd: regulator@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdreg>; - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "LCD"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - status = "okay"; - - ads7846 { - compatible = "ti,ads7846"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - reg = <0>; - interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; - spi-cpol; - spi-max-frequency = <1500000>; - ti,keep-vref-on; - }; -}; - -&fb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb>; - display = <&display0>; - lcd-supply = <®_lcd>; - fsl,dmacr = <0x00040060>; - fsl,lscr1 = <0x00120300>; - fsl,lpccr = <0x00a903ff>; - status = "okay"; -}; - -&i2c1 { - codec: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&kpp { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - >; - status = "okay"; -}; - -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&ssi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - codec-handle = <&codec>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&iomuxc { - imx27-eukrea-cpuimx27-baseboard { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX27_PAD_PWMO__GPIO5_5 0x0 - >; - }; - - pinctrl_gpioleds: gpioledsgrp { - fsl,pins = < - MX27_PAD_PC_PWRON__GPIO6_16 0x0 - MX27_PAD_PC_CD2_B__GPIO6_19 0x0 - >; - }; - - pinctrl_imxfb: imxfbgrp { - fsl,pins = < - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_lcdreg: lcdreggrp { - fsl,pins = < - MX27_PAD_CLS__GPIO1_25 0x0 - >; - }; - - pinctrl_sdhc1: sdhc1grp { - fsl,pins = < - MX27_PAD_SD1_CLK__SD1_CLK 0x0 - MX27_PAD_SD1_CMD__SD1_CMD 0x0 - MX27_PAD_SD1_D0__SD1_D0 0x0 - MX27_PAD_SD1_D1__SD1_D1 0x0 - MX27_PAD_SD1_D2__SD1_D2 0x0 - MX27_PAD_SD1_D3__SD1_D3 0x0 - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 - MX27_PAD_SSI4_FS__SSI4_FS 0x0 - MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 - MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-pdk.dts b/software/linux/kernel/arch/arm/boot/dts/imx27-pdk.dts deleted file mode 100644 index d0ef496a1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-pdk.dts +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Freescale i.MX27 Product Development Kit"; - compatible = "fsl,imx27-pdk", "fsl,imx27"; - - memory { - reg = <0xa0000000 0x08000000>; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - }; - }; -}; - -&cspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi2>; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13783@0 { - compatible = "fsl,mc13783"; - reg = <0>; - spi-cs-high; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio3>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - - regulators { - vgen_reg: vgen { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc1_reg: vmmc1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - }; - - gpo1_reg: gpo1 { - regulator-always-on; - regulator-boot-on; - }; - - gpo3_reg: gpo3 { - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&fec { - phy-mode = "mii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&kpp { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_ENTER) - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(2, 1, KEY_F8) - MATRIX_KEY(2, 2, KEY_F9) - MATRIX_KEY(2, 3, KEY_F10) - >; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - fsl,usbphy = <&usbphy0>; - phy_type = "ulpi"; - status = "okay"; -}; - -&iomuxc { - imx27-pdk { - pinctrl_cspi2: cspi2grp { - fsl,pins = < - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ - MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts deleted file mode 100644 index bfd4946cf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright 2012 Markus Pargmann, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx27-phytec-phycard-s-som.dtsi" - -/ { - model = "Phytec pca100 rapid development kit"; - compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; - - chosen { - stdout-path = &uart1; - }; - - display: display { - model = "Primeview-PD050VL1"; - native-mode = <&timing0>; - bits-per-pixel = <16>; /* non-standard but required */ - fsl,pcr = <0xf0c88080>; /* non-standard but required */ - display-timings { - timing0: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <112>; - hfront-porch = <36>; - hsync-len = <32>; - vback-porch = <33>; - vfront-porch = <33>; - vsync-len = <2>; - clock-frequency = <25000000>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&fb { - display = <&display>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - adc@64 { - compatible = "maxim,max1037"; - vcc-supply = <®_3v3>; - reg = <0x64>; - }; -}; - -&iomuxc { - imx27-phycard-s-rdk { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; - }; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire1>; - status = "okay"; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi deleted file mode 100644 index 1b6248079..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar - * and Markus Pargmann, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pca100"; - compatible = "phytec,imx27-pca100", "fsl,imx27"; - - memory { - reg = <0xa0000000 0x08000000>; /* 128MB */ - }; -}; - -&cspi1 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, - <&gpio4 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24@52 { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -&iomuxc { - imx27-phycard-s-som { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts deleted file mode 100644 index cf09e72ae..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ /dev/null @@ -1,324 +0,0 @@ -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx27-phytec-phycore-som.dtsi" - -/ { - model = "Phytec pcm970"; - compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; - - chosen { - stdout-path = &uart1; - }; - - display0: LQ035Q7 { - model = "Sharp-LQ035Q7"; - native-mode = <&timing0>; - bits-per-pixel = <16>; - fsl,pcr = <0xf00080c0>; - - display-timings { - timing0: 240x320 { - clock-frequency = <5500000>; - hactive = <240>; - vactive = <320>; - hback-porch = <5>; - hsync-len = <7>; - hfront-porch = <16>; - vback-porch = <7>; - vsync-len = <1>; - vfront-porch = <9>; - pixelclk-active = <1>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <0>; - }; - }; - }; - - regulators { - regulator@2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csien>; - reg = <2>; - regulator-name = "CSI_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; - }; - - usbphy { - usbphy2: usbphy@2 { - compatible = "usb-nop-xceiv"; - reg = <2>; - vcc-supply = <®_5v0>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - }; - }; -}; - -&cspi1 { - pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, - <&gpio4 27 GPIO_ACTIVE_LOW>; -}; - -&fb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imxfb1>; - display = <&display0>; - lcd-supply = <®_5v0>; - fsl,dmacr = <0x00020010>; - fsl,lscr1 = <0x00120300>; - fsl,lpccr = <0x00a903ff>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - camgpio: pca9536@41 { - compatible = "nxp,pca9536"; - reg = <0x41>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&iomuxc { - imx27_phycore_rdk { - pinctrl_csien: csiengrp { - fsl,pins = < - MX27_PAD_USB_OC_B__GPIO2_24 0x0 - >; - }; - - pinctrl_cspi1cs1: cspi1cs1grp { - fsl,pins = < - MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 - >; - }; - - pinctrl_imxfb1: imxfbgrp { - fsl,pins = < - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_CLS__CLS 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_LSCLK__LSCLK 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_PS__PS 0x0 - MX27_PAD_REV__REV 0x0 - MX27_PAD_SPL_SPR__SPL_SPR 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; - - pinctrl_i2c1: i2c1grp { - /* Add pullup to DATA line */ - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x1 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; - - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ - MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ - >; - }; - }; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire1>; - status = "okay"; -}; - -&pmicleds { - ledr1: led@3 { - reg = <3>; - label = "system:red1:user"; - }; - - ledg1: led@4 { - reg = <4>; - label = "system:green1:user"; - }; - - ledb1: led@5 { - reg = <5>; - label = "system:blue1:user"; - }; - - ledr2: led@6 { - reg = <6>; - label = "system:red2:user"; - }; - - ledg2: led@7 { - reg = <7>; - label = "system:green2:user"; - }; - - ledb2: led@8 { - reg = <8>; - label = "system:blue2:user"; - }; - - ledr3: led@9 { - reg = <9>; - label = "system:red3:nand"; - linux,default-trigger = "nand-disk"; - }; - - ledg3: led@10 { - reg = <10>; - label = "system:green3:live"; - linux,default-trigger = "heartbeat"; - }; - - ledb3: led@11 { - reg = <11>; - label = "system:blue3:cpu"; - linux,default-trigger = "cpu0"; - }; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - bus-width = <4>; - cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vmmc1_reg>; - status = "okay"; -}; - -&uart1 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh2>; - dr_mode = "host"; - phy_type = "ulpi"; - vbus-supply = <®_5v0>; - fsl,usbphy = <&usbphy2>; - disable-over-current; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - - can@4,0 { - compatible = "nxp,sja1000"; - reg = <4 0x00000000 0x00000100>; - interrupt-parent = <&gpio5>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; - nxp,external-clock-frequency = <16000000>; - nxp,tx-output-config = <0x16>; - nxp,no-comparator-bypass; - fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi deleted file mode 100644 index b4e955e3b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pcm038"; - compatible = "phytec,imx27-pcm038", "fsl,imx27"; - - memory { - reg = <0xa0000000 0x08000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - vcc-supply = <&sw3_reg>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "main_clk"; - }; - }; -}; - -&audmux { - status = "okay"; - - /* SSI0 <=> PINS_4 (MC13783 Audio) */ - ssi0 { - fsl,audmux-port = <0>; - fsl,port-config = <0xcb205000>; - }; - - pins4 { - fsl,audmux-port = <2>; - fsl,port-config = <0x00001000>; - }; -}; - -&cspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi1>; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13783@0 { - compatible = "fsl,mc13783"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0>; - spi-cs-high; - spi-max-frequency = <20000000>; - interrupt-parent = <&gpio2>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-adc; - fsl,mc13xxx-uses-rtc; - - pmicleds: leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; - }; - - regulators { - /* SW1A and SW1B joined operation */ - sw1_reg: sw1a { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1520000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SW2A and SW2B joined operation */ - sw2_reg: sw2a { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vaudio_reg: vaudio { - regulator-always-on; - regulator-boot-on; - }; - - violo_reg: violo { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - viohi_reg: viohi { - regulator-always-on; - regulator-boot-on; - }; - - vgen_reg: vgen { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vrf1_reg: vrf1 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vrf2_reg: vrf2 { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc1_reg: vmmc1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3000000>; - }; - - gpo1_reg: gpo1 { }; - - pwgt1spi_reg: pwgt1spi { - regulator-always-on; - }; - }; - }; -}; - -&fec { - phy-mode = "mii"; - phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; - phy-supply = <®_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24@52 { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - lm75@4a { - compatible = "national,lm75"; - reg = <0x4a>; - }; -}; - -&iomuxc { - imx27_phycore_som { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX27_PAD_SSI1_FS__SSI1_FS 0x0 - MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 - MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 - MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&ssi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - phy_type = "ulpi"; - fsl,usbphy = <&usbphy0>; - vbus-supply = <&sw3_reg>; - disable-over-current; - status = "okay"; -}; - -&weim { - status = "okay"; - - nor: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0x00000000 0x02000000>; - bank-width = <2>; - linux,mtd-name = "physmap-flash.0"; - fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; - #address-cells = <1>; - #size-cells = <1>; - }; - - sram: sram@1,0 { - compatible = "mtd-ram"; - reg = <1 0x00000000 0x00800000>; - bank-width = <2>; - linux,mtd-name = "mtd-ram.0"; - fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx27-pinfunc.h deleted file mode 100644 index 597bb5f74..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27-pinfunc.h +++ /dev/null @@ -1,480 +0,0 @@ -/* - * Copyright 2013 Markus Pargmann , Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DTS_IMX27_PINFUNC_H -#define __DTS_IMX27_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - * mux_id consists of - * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) - * - * function: 0 - Primary function - * 1 - Alternate function - * 2 - GPIO - * direction: 0 - Input - * 1 - Output - * gpio_oconf: 0 - A_IN - * 1 - B_IN - * 2 - C_IN - * 3 - Data Register - * gpio_iconfa/b: 0 - GPIO_IN - * 1 - Interrupt Status Register - * 2 - 0 - * 3 - 1 - * - * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable - * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin - * number on the specific port (between 0 and 31). - */ - -#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000 -#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032 -#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000 -#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032 -#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004 -#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032 -#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000 -#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032 -#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004 -#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032 -#define MX27_PAD_LSCLK__LSCLK 0x05 0x004 -#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032 -#define MX27_PAD_LD0__LD0 0x06 0x004 -#define MX27_PAD_LD0__GPIO1_6 0x06 0x032 -#define MX27_PAD_LD1__LD1 0x07 0x004 -#define MX27_PAD_LD1__GPIO1_7 0x07 0x032 -#define MX27_PAD_LD2__LD2 0x08 0x004 -#define MX27_PAD_LD2__GPIO1_8 0x08 0x032 -#define MX27_PAD_LD3__LD3 0x09 0x004 -#define MX27_PAD_LD3__GPIO1_9 0x09 0x032 -#define MX27_PAD_LD4__LD4 0x0a 0x004 -#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032 -#define MX27_PAD_LD5__LD5 0x0b 0x004 -#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032 -#define MX27_PAD_LD6__LD6 0x0c 0x004 -#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032 -#define MX27_PAD_LD7__LD7 0x0d 0x004 -#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032 -#define MX27_PAD_LD8__LD8 0x0e 0x004 -#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032 -#define MX27_PAD_LD9__LD9 0x0f 0x004 -#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032 -#define MX27_PAD_LD10__LD10 0x10 0x004 -#define MX27_PAD_LD10__GPIO1_16 0x10 0x032 -#define MX27_PAD_LD11__LD11 0x11 0x004 -#define MX27_PAD_LD11__GPIO1_17 0x11 0x032 -#define MX27_PAD_LD12__LD12 0x12 0x004 -#define MX27_PAD_LD12__GPIO1_18 0x12 0x032 -#define MX27_PAD_LD13__LD13 0x13 0x004 -#define MX27_PAD_LD13__GPIO1_19 0x13 0x032 -#define MX27_PAD_LD14__LD14 0x14 0x004 -#define MX27_PAD_LD14__GPIO1_20 0x14 0x032 -#define MX27_PAD_LD15__LD15 0x15 0x004 -#define MX27_PAD_LD15__GPIO1_21 0x15 0x032 -#define MX27_PAD_LD16__LD16 0x16 0x004 -#define MX27_PAD_LD16__GPIO1_22 0x16 0x032 -#define MX27_PAD_LD17__LD17 0x17 0x004 -#define MX27_PAD_LD17__GPIO1_23 0x17 0x032 -#define MX27_PAD_REV__REV 0x18 0x004 -#define MX27_PAD_REV__GPIO1_24 0x18 0x032 -#define MX27_PAD_CLS__CLS 0x19 0x004 -#define MX27_PAD_CLS__GPIO1_25 0x19 0x032 -#define MX27_PAD_PS__PS 0x1a 0x004 -#define MX27_PAD_PS__GPIO1_26 0x1a 0x032 -#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004 -#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032 -#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004 -#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032 -#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004 -#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032 -#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004 -#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032 -#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004 -#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032 -#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004 -#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005 -#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032 -#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004 -#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005 -#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032 -#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004 -#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005 -#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032 -#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004 -#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005 -#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032 -#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004 -#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005 -#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032 -#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004 -#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005 -#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032 -#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000 -#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005 -#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032 -#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000 -#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001 -#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032 -#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000 -#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005 -#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032 -#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000 -#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001 -#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032 -#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000 -#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032 -#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004 -#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032 -#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000 -#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032 -#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000 -#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032 -#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000 -#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005 -#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032 -#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000 -#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001 -#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032 -#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000 -#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005 -#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032 -#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000 -#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001 -#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032 -#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004 -#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032 -#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004 -#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032 -#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000 -#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032 -#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004 -#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032 -#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004 -#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001 -#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032 -#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004 -#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032 -#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004 -#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005 -#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032 -#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004 -#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005 -#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032 -#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004 -#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032 -#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004 -#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001 -#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032 -#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004 -#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032 -#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004 -#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032 -#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004 -#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032 -#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004 -#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032 -#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004 -#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032 -#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004 -#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032 -#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004 -#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032 -#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004 -#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032 -#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004 -#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032 -#define MX27_PAD_TOUT__TOUT 0x4e 0x004 -#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032 -#define MX27_PAD_TIN__TIN 0x4f 0x000 -#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032 -#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004 -#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032 -#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004 -#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032 -#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004 -#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032 -#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004 -#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032 -#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004 -#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032 -#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004 -#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032 -#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004 -#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032 -#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004 -#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032 -#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004 -#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005 -#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032 -#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004 -#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001 -#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032 -#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004 -#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005 -#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032 -#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004 -#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001 -#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032 -#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004 -#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001 -#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032 -#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004 -#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001 -#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032 -#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004 -#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001 -#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032 -#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004 -#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001 -#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032 -#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004 -#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006 -#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032 -#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004 -#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005 -#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006 -#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032 -#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004 -#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005 -#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006 -#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032 -#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004 -#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005 -#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006 -#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032 -#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004 -#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005 -#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002 -#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032 -#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004 -#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005 -#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002 -#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032 -#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004 -#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005 -#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002 -#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032 -#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004 -#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005 -#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002 -#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032 -#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004 -#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005 -#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032 -#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004 -#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005 -#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006 -#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032 -#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004 -#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005 -#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002 -#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032 -#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004 -#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005 -#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002 -#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032 -#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004 -#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005 -#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002 -#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032 -#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004 -#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005 -#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002 -#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032 -#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004 -#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005 -#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002 -#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032 -#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004 -#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005 -#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002 -#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032 -#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004 -#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005 -#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006 -#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032 -#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004 -#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032 -#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004 -#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032 -#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004 -#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005 -#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032 -#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004 -#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005 -#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032 -#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004 -#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005 -#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032 -#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004 -#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005 -#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032 -#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004 -#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005 -#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032 -#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004 -#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005 -#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032 -#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000 -#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032 -#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004 -#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005 -#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032 -#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004 -#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032 -#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004 -#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032 -#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004 -#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032 -#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004 -#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032 -#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004 -#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032 -#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000 -#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005 -#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032 -#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004 -#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005 -#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032 -#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000 -#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005 -#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032 -#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004 -#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005 -#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032 -#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000 -#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005 -#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032 -#define MX27_PAD_PWMO__PWMO 0x85 0x004 -#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032 -#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004 -#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005 -#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032 -#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000 -#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005 -#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032 -#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004 -#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032 -#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000 -#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032 -#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004 -#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032 -#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000 -#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032 -#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004 -#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032 -#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000 -#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032 -#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004 -#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032 -#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000 -#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032 -#define MX27_PAD_RTCK__RTCK 0x90 0x004 -#define MX27_PAD_RTCK__OWIRE 0x90 0x005 -#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032 -#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004 -#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032 -#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004 -#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001 -#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032 -#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004 -#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032 -#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004 -#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032 -#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004 -#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005 -#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032 -#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004 -#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005 -#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032 -#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004 -#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005 -#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032 -#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000 -#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032 -#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004 -#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032 -#define MX27_PAD_NFRB__NFRB 0xa0 0x000 -#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005 -#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032 -#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004 -#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005 -#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032 -#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004 -#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005 -#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032 -#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004 -#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005 -#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032 -#define MX27_PAD_NFALE__NFALE 0xa4 0x004 -#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005 -#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032 -#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004 -#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005 -#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032 -#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004 -#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005 -#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032 -#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004 -#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005 -#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032 -#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004 -#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001 -#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032 -#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000 -#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001 -#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032 -#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004 -#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005 -#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032 -#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000 -#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005 -#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032 -#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000 -#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001 -#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032 -#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000 -#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005 -#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032 -#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000 -#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005 -#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032 -#define MX27_PAD_CLKO__CLKO 0xaf 0x004 -#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032 -#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000 -#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005 -#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032 -#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000 -#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005 -#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032 -#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000 -#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005 -#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032 -#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000 -#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005 -#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032 -#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000 -#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005 -#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032 -#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004 -#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005 -#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032 -#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004 -#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005 -#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032 -#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004 -#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005 -#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006 -#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032 - -#endif /* __DTS_IMX27_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx27.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx27.dtsi deleted file mode 100644 index f818ea483..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx27.dtsi +++ /dev/null @@ -1,594 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" -#include "imx27-pinfunc.h" - -#include -#include -#include -#include - -/ { - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - spi0 = &cspi1; - spi1 = &cspi2; - spi2 = &cspi3; - }; - - aitc: aitc-interrupt-controller@e0000000 { - compatible = "fsl,imx27-aitc", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10040000 0x1000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc26m { - compatible = "fsl,imx-osc26m", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu: cpu@0 { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - operating-points = < - /* kHz uV */ - 266000 1300000 - 399000 1450000 - >; - clock-latency = <62500>; - clocks = <&clks IMX27_CLK_CPU_DIV>; - voltage-tolerance = <5>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&aitc>; - ranges; - - aipi@10000000 { /* AIPI1 */ - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10000000 0x20000>; - ranges; - - dma: dma@10001000 { - compatible = "fsl,imx27-dma"; - reg = <0x10001000 0x1000>; - interrupts = <32>; - clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, - <&clks IMX27_CLK_DMA_AHB_GATE>; - clock-names = "ipg", "ahb"; - #dma-cells = <1>; - #dma-channels = <16>; - }; - - wdog: wdog@10002000 { - compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; - reg = <0x10002000 0x1000>; - interrupts = <27>; - clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; - }; - - gpt1: timer@10003000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10003000 0x1000>; - interrupts = <26>; - clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt2: timer@10004000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10004000 0x1000>; - interrupts = <25>; - clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt3: timer@10005000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10005000 0x1000>; - interrupts = <24>; - clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - pwm: pwm@10006000 { - #pwm-cells = <2>; - compatible = "fsl,imx27-pwm"; - reg = <0x10006000 0x1000>; - interrupts = <23>; - clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - rtc: rtc@10007000 { - compatible = "fsl,imx21-rtc"; - reg = <0x10007000 0x1000>; - interrupts = <22>; - clocks = <&clks IMX27_CLK_CKIL>, - <&clks IMX27_CLK_RTC_IPG_GATE>; - clock-names = "ref", "ipg"; - }; - - kpp: kpp@10008000 { - compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; - reg = <0x10008000 0x1000>; - interrupts = <21>; - clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; - status = "disabled"; - }; - - owire: owire@10009000 { - compatible = "fsl,imx27-owire", "fsl,imx21-owire"; - reg = <0x10009000 0x1000>; - clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; - status = "disabled"; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@1000b000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000b000 0x1000>; - interrupts = <19>; - clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@1000c000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000c000 0x1000>; - interrupts = <18>; - clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@1000d000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000d000 0x1000>; - interrupts = <17>; - clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - cspi1: cspi@1000e000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x1000e000 0x1000>; - interrupts = <16>; - clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - cspi2: cspi@1000f000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x1000f000 0x1000>; - interrupts = <15>; - clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi1: ssi@10010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; - reg = <0x10010000 0x1000>; - interrupts = <14>; - clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; - dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; - dma-names = "rx0", "tx0", "rx1", "tx1"; - fsl,fifo-depth = <8>; - status = "disabled"; - }; - - ssi2: ssi@10011000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; - reg = <0x10011000 0x1000>; - interrupts = <13>; - clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; - dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; - dma-names = "rx0", "tx0", "rx1", "tx1"; - fsl,fifo-depth = <8>; - status = "disabled"; - }; - - i2c1: i2c@10012000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; - reg = <0x10012000 0x1000>; - interrupts = <12>; - clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; - status = "disabled"; - }; - - sdhci1: sdhci@10013000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x10013000 0x1000>; - interrupts = <11>; - clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 7>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - sdhci2: sdhci@10014000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x10014000 0x1000>; - interrupts = <10>; - clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 6>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - iomuxc: iomuxc@10015000 { - compatible = "fsl,imx27-iomuxc"; - reg = <0x10015000 0x600>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@10015000 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015000 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@10015100 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015100 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@10015200 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015200 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@10015300 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015300 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@10015400 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015400 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@10015500 { - compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; - reg = <0x10015500 0x100>; - clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - audmux: audmux@10016000 { - compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; - reg = <0x10016000 0x1000>; - clocks = <&clks IMX27_CLK_DUMMY>; - clock-names = "audmux"; - status = "disabled"; - }; - - cspi3: cspi@10017000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-cspi"; - reg = <0x10017000 0x1000>; - interrupts = <6>; - clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt4: timer@10019000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10019000 0x1000>; - interrupts = <4>; - clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - gpt5: timer@1001a000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x1001a000 0x1000>; - interrupts = <3>; - clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - - uart5: serial@1001b000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1001b000 0x1000>; - interrupts = <49>; - clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@1001c000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1001c000 0x1000>; - interrupts = <48>; - clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@1001d000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; - reg = <0x1001d000 0x1000>; - interrupts = <1>; - clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; - status = "disabled"; - }; - - sdhci3: sdhci@1001e000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x1001e000 0x1000>; - interrupts = <9>; - clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, - <&clks IMX27_CLK_PER2_GATE>; - clock-names = "ipg", "per"; - dmas = <&dma 36>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - gpt6: timer@1001f000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x1001f000 0x1000>; - interrupts = <2>; - clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; - }; - - aipi@10020000 { /* AIPI2 */ - compatible = "fsl,aipi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10020000 0x20000>; - ranges; - - fb: fb@10021000 { - compatible = "fsl,imx27-fb", "fsl,imx21-fb"; - interrupts = <61>; - reg = <0x10021000 0x1000>; - clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, - <&clks IMX27_CLK_LCDC_AHB_GATE>, - <&clks IMX27_CLK_PER3_GATE>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - coda: coda@10023000 { - compatible = "fsl,imx27-vpu", "cnm,codadx6"; - reg = <0x10023000 0x0200>; - interrupts = <53>; - clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, - <&clks IMX27_CLK_VPU_AHB_GATE>; - clock-names = "per", "ahb"; - iram = <&iram>; - }; - - usbotg: usb@10024000 { - compatible = "fsl,imx27-usb"; - reg = <0x10024000 0x200>; - interrupts = <56>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - status = "disabled"; - }; - - usbh1: usb@10024200 { - compatible = "fsl,imx27-usb"; - reg = <0x10024200 0x200>; - interrupts = <54>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@10024400 { - compatible = "fsl,imx27-usb"; - reg = <0x10024400 0x200>; - interrupts = <55>; - clocks = <&clks IMX27_CLK_USB_IPG_GATE>, - <&clks IMX27_CLK_USB_AHB_GATE>, - <&clks IMX27_CLK_USB_DIV>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@10024600 { - #index-cells = <1>; - compatible = "fsl,imx27-usbmisc"; - reg = <0x10024600 0x200>; - }; - - sahara2: sahara@10025000 { - compatible = "fsl,imx27-sahara"; - reg = <0x10025000 0x1000>; - interrupts = <59>; - clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, - <&clks IMX27_CLK_SAHARA_AHB_GATE>; - clock-names = "ipg", "ahb"; - }; - - clks: ccm@10027000{ - compatible = "fsl,imx27-ccm"; - reg = <0x10027000 0x1000>; - #clock-cells = <1>; - }; - - iim: iim@10028000 { - compatible = "fsl,imx27-iim"; - reg = <0x10028000 0x1000>; - interrupts = <62>; - clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; - }; - - fec: ethernet@1002b000 { - compatible = "fsl,imx27-fec"; - reg = <0x1002b000 0x1000>; - interrupts = <50>; - clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, - <&clks IMX27_CLK_FEC_AHB_GATE>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - }; - - nfc: nand@d8000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx27-nand"; - reg = <0xd8000000 0x1000>; - interrupts = <29>; - clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; - status = "disabled"; - }; - - weim: weim@d8002000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx27-weim"; - reg = <0xd8002000 0x1000>; - clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; - ranges = < - 0 0 0xc0000000 0x08000000 - 1 0 0xc8000000 0x08000000 - 2 0 0xd0000000 0x02000000 - 3 0 0xd2000000 0x02000000 - 4 0 0xd4000000 0x02000000 - 5 0 0xd6000000 0x02000000 - >; - status = "disabled"; - }; - - iram: iram@ffff4c00 { - compatible = "mmio-sram"; - reg = <0xffff4c00 0xb400>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-apf28.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-apf28.dts deleted file mode 100644 index 070e59cbd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-apf28.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2012 Armadeus Systems - - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Armadeus Systems APF28 module"; - compatible = "armadeus,imx28-apf28", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x300000>; - }; - - partition@300000 { - label = "env"; - reg = <0x300000 0x80000>; - }; - - partition@380000 { - label = "env2"; - reg = <0x380000 0x80000>; - }; - - partition@400000 { - label = "dtb"; - reg = <0x400000 0x80000>; - }; - - partition@480000 { - label = "splash"; - reg = <0x480000 0x80000>; - }; - - partition@500000 { - label = "kernel"; - reg = <0x500000 0x800000>; - }; - - partition@d00000 { - label = "rootfs"; - reg = <0xd00000 0xf300000>; - }; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-apf28dev.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-apf28dev.dts deleted file mode 100644 index c4fadbc1b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-apf28dev.dts +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright 2012 Armadeus Systems - - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* APF28Dev is a docking board for the APF28 SOM */ -#include "imx28-apf28.dts" - -/ { - model = "Armadeus Systems APF28Dev docking/development board"; - compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: ssp@80014000 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_apf28dev>; - - hog_pins_apf28dev: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D16__GPIO_1_16 - MX28_PAD_LCD_D17__GPIO_1_17 - MX28_PAD_LCD_D18__GPIO_1_18 - MX28_PAD_LCD_D19__GPIO_1_19 - MX28_PAD_LCD_D20__GPIO_1_20 - MX28_PAD_LCD_D21__GPIO_1_21 - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_apf28dev: lcdif-apf28dev@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_otg_apf28dev: otg-apf28dev@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_16bit_pins_a - &lcdif_pins_apf28dev>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can0_vcc>; - status = "okay"; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_apf28dev - &usb0_id_pins_b>; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - - usb1: usb@80090000 { - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 23 1>; - enable-active-high; - }; - - reg_can0_vcc: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "can0_vcc"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio0 21 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - - pwms = <&pwm 3 191000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-button { - label = "User button"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - wakeup-source; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-apx4devkit.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-apx4devkit.dts deleted file mode 100644 index 1092b761d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-apx4devkit.dts +++ /dev/null @@ -1,226 +0,0 @@ -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Bluegiga APX4 Development Kit"; - compatible = "bluegiga,apx4devkit", "fsl,imx28"; - - memory { - reg = <0x40000000 0x04000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: ssp@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; - bus-width = <4>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_RDY1__GPIO_0_21 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_JTAG_RTCK__GPIO_4_20 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_apx4: lcdif-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_SSP0_DATA7__SSP2_SCK - MX28_PAD_SSP2_SS1__SSP2_D1 - MX28_PAD_SSP2_SS2__SSP2_D2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_apx4>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hfront-porch = <40>; - vback-porch = <32>; - vfront-porch = <13>; - hsync-len = <48>; - vsync-len = <3>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - pcf8563: rtc@51 { - compatible = "phg,pcf8563"; - reg = <0x51>; - }; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_2pins_a>; - status = "okay"; - }; - - auart2: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "bluegiga,apx4devkit-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "apx4devkit-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio3 28 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10036.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10036.dts deleted file mode 100644 index 570aa339a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10036.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2012 Free Electrons - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Crystalfontz CFA-10036 Board"; - compatible = "crystalfontz,cfa10036", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - ssd1306_cfa10036: ssd1306-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_cfa10036: leds-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_otg_cfa10036: otg-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY0__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x31c3 /* - MX28_PAD_PWM3__GPIO_3_28 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - vmmc-supply = <®_vddio_sd0>; - bus-width = <4>; - status = "okay"; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_b>; - clock-frequency = <400000>; - status = "okay"; - - ssd1306: oled@3c { - compatible = "solomon,ssd1306fb-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&ssd1306_cfa10036>; - reg = <0x3c>; - reset-gpios = <&gpio2 7 0>; - solomon,height = <32>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,com-lrremap; - solomon,com-invdir; - solomon,com-offset = <32>; - }; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_cfa10036>; - dr_mode = "peripheral"; - phy_type = "utmi"; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cfa10036>; - - power { - gpios = <&gpio3 4 1>; - default-state = "on"; - }; - }; - - reg_vddio_sd0: vddio-sd0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pwr_cfa10036>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10037.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10037.dts deleted file mode 100644 index e5beaa58b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10037.dts +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2012 Free Electrons - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * The CFA-10049 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10037 Board"; - compatible = "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10037: usb-10037@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_cfa10037: mac0-10037@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a - &mac0_pins_cfa10037>; - phy-reset-gpios = <&gpio2 21 0>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10037>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10049.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10049.dts deleted file mode 100644 index a9c347e48..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10049.dts +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Copyright 2012 Free Electrons - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * The CFA-10049 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10049 Board"; - compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10049: usb-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2cmux_pins_cfa10049: i2cmux-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_cfa10049: mac0-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pca_pins_cfa10049: pca-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - rotary_pins_cfa10049: rotary-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - rotary_btn_pins_cfa10049: rotary-btn-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__GPIO_3_26 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_cfa10049: spi2-cfa10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_cfa10049: spi3-cfa10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPIO_0_24 - MX28_PAD_GPMI_RESETN__GPIO_0_28 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_ALE__GPIO_0_26 - MX28_PAD_GPMI_CLE__GPIO_0_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10049: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - w1_gpio_pins: w1-gpio@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D21__GPIO_1_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; /* 0 will enable the keeper */ - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10049 - &lcdif_pins_cfa10049 - &lcdif_pins_cfa10049_pullup>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - - i2c1: i2c@8005a000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2cmux_pins_cfa10049>; - mux-gpios = <&gpio1 22 0 &gpio1 23 0>; - i2c-parent = <&i2c1>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - adc0: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - adc1: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - adc2: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - pinctrl-0 = <&pca_pins_cfa10049>; - interrupt-parent = <&gpio2>; - interrupts = <19 0x2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x20>; - }; - }; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10049>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a - &mac0_pins_cfa10049>; - phy-reset-gpios = <&gpio2 21 0>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - spi2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10049>; - status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8357: hx8357@0 { - compatible = "himax,hx8357b", "himax,hx8357"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>; - }; - }; - - spi3 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins_cfa10049>; - status = "okay"; - gpio-sck = <&gpio0 24 0>; - gpio-mosi = <&gpio0 28 0>; - cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>; - num-chipselects = <3>; - #address-cells = <1>; - #size-cells = <0>; - - gpio5: gpio5@0 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - registers-number = <2>; - spi-max-frequency = <100000>; - }; - - gpio6: gpio6@1 { - compatible = "fairchild,74hc595"; - gpio-controller; - #gpio-cells = <2>; - reg = <1>; - registers-number = <4>; - spi-max-frequency = <100000>; - }; - - dac0: dh2228@2 { - compatible = "rohm,dh2228fv"; - reg = <2>; - spi-max-frequency = <100000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&rotary_btn_pins_cfa10049>; - #address-cells = <1>; - #size-cells = <0>; - - rotary_button { - label = "rotary_button"; - gpios = <&gpio3 26 1>; - debounce-interval = <10>; - linux,code = <28>; - }; - }; - - rotary { - compatible = "rotary-encoder"; - pinctrl-names = "default"; - pinctrl-0 = <&rotary_pins_cfa10049>; - gpios = <&gpio3 24 1>, <&gpio3 25 1>; - linux,axis = <1>; /* REL_Y */ - rotary-encoder,relative-axis; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - }; - - onewire { - compatible = "w1-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&w1_gpio_pins>; - status = "okay"; - gpios = <&gpio1 21 0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10055.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10055.dts deleted file mode 100644 index 6a34114be..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10055.dts +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright 2013 Crystalfontz America, Inc. - * Free Electrons - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * The CFA-10055 is an expansion board for the CFA-10036 module and - * CFA-10037, thus we need to include the CFA-10037 DTS. - */ -#include "imx28-cfa10037.dts" - -/ { - model = "Crystalfontz CFA-10055 Board"; - compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - spi2_pins_cfa10055: spi2-cfa10055@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10055: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10055 - &lcdif_pins_cfa10055 - &lcdif_pins_cfa10055_pullup>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - }; - }; - - spi2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10055>; - status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8357: hx8357@0 { - compatible = "himax,hx8357b", "himax,hx8357"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10056.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10056.dts deleted file mode 100644 index ba6495ca4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10056.dts +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2013 Free Electrons - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * The CFA-10055 is an expansion board for the CFA-10036 module and - * CFA-10037, thus we need to include the CFA-10037 DTS. - */ -#include "imx28-cfa10037.dts" - -/ { - model = "Crystalfontz CFA-10056 Board"; - compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - spi2_pins_cfa10056: spi2-cfa10056@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10056: lcdif-10056@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_cfa10056 - &lcdif_pins_cfa10056_pullup >; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <32000000>; - hactive = <480>; - vactive = <800>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <5>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - }; - - spi2 { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_cfa10056>; - status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; - cs-gpios = <&gpio3 5 0>; - num-chipselects = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hx8369: hx8369@0 { - compatible = "himax,hx8369a", "himax,hx8369"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - gpios-reset = <&gpio3 30 0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10057.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10057.dts deleted file mode 100644 index 7a80bd686..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10057.dts +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright 2013 Crystalfontz America, Inc. - * Copyright 2012 Free Electrons - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * The CFA-10057 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10057 Board"; - compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10057: usb-10057@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10057: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10057 - &lcdif_pins_cfa10057>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <12>; - hback-porch = <2>; - vfront-porch = <5>; - vback-porch = <3>; - hsync-len = <2>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; - }; - - i2c1: i2c@8005a000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10057>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 0>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10058.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10058.dts deleted file mode 100644 index f5c6dce34..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-cfa10058.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2013 Crystalfontz America, Inc. - * Copyright 2013 Free Electrons - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * The CFA-10058 is an expansion board for the CFA-10036 module, thus we - * need to include the CFA-10036 DTS. - */ -#include "imx28-cfa10036.dts" - -/ { - model = "Crystalfontz CFA-10058 Board"; - compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10058: usb-10058@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10058: lcdif-10058@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_cfa10058>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <13>; - vfront-porch = <29>; - hsync-len = <8>; - vsync-len = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10058>; - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; - }; - - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 0>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-duckbill.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-duckbill.dts deleted file mode 100644 index ce1a7effb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-duckbill.dts +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 2013 Michael Heimpold - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "I2SE Duckbill"; - compatible = "i2se,duckbill", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_a: led_gpio@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - - status { - label = "duckbill:green:status"; - gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; - }; - - failure { - label = "duckbill:red:status"; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts deleted file mode 100644 index 7c1572c5a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC - */ - -/dts-v1/; -#include "imx28-eukrea-mbmx28lc.dtsi" - -/ { - model = "Eukrea Electromatique MBMX283LC"; - compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; - - memory { - reg = <0x40000000 0x04000000>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pinctrl{ - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_cpuimx283>; - - hog_pins_cpuimx283: hog-cpuimx283@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_ENET0_TX_CLK__GPIO_4_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts deleted file mode 100644 index e773144e1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC - */ - -#include "imx28-eukrea-mbmx283lc.dts" - -/ { - model = "Eukrea Electromatique MBMX287LC"; - compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>; - hog_pins_cpuimx287: hog-cpuimx287@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SPDIF__GPIO_3_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi deleted file mode 100644 index 581e85f4f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "imx28.dtsi" - -/ { - model = "Eukrea Electromatique MBMX28LC"; - compatible = "eukrea,mbmx28lc", "fsl,imx28"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 1000000>; - brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>; - default-brightness-level = <10>; - }; - - button-sw3 { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; - - sw3 { - label = "SW3"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - button-sw4 { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; - - sw4 { - label = "SW4"; - gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - led-d6 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_d6_pins_mbmx28lc>; - - led1 { - label = "d6"; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - led-d7 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_d7_pins_mbmx28lc>; - - led1 { - label = "d7"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_lcd_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb0_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx28-mbmx28lc-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-mbmx28lc-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; -}; - -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; - status = "okay"; - - display0: display0 { - model = "43WVF1G-0"; - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9072000>; - hactive = <480>; - vactive = <272>; - hback-porch = <10>; - hfront-porch = <5>; - vback-porch = <8>; - vfront-porch = <8>; - hsync-len = <40>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&pinctrl { - gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D21__GPIO_1_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D20__GPIO_1_20 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_VSYNC__LCD_VSYNC - MX28_PAD_LCD_HSYNC__LCD_HSYNC - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_ENABLE__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D22__GPIO_1_22 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D18__GPIO_1_18 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D19__GPIO_1_19 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - cd-inverted; - status = "okay"; -}; - -&usb0 { - disable-over-current; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_b>; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-evk.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-evk.dts deleted file mode 100644 index a5ba669b4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-evk.dts +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Freescale i.MX28 Evaluation Kit"; - compatible = "fsl,imx28-evk", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg - &gpmi_pins_evk>; - status = "okay"; - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio2 12 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp1: ssp@80012000 { - compatible = "fsl,imx28-mmc"; - bus-width = <8>; - wp-gpios = <&gpio0 28 0>; - }; - - ssp2: ssp@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP1_CMD__GPIO_2_13 - MX28_PAD_SSP1_DATA3__GPIO_2_15 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_SSP1_SCK__GPIO_2_12 - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pin_gpio3_5: led_gpio3_5@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_evk: gpmi-nand-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPMI_CE1N - MX28_PAD_GPMI_RDY1__GPMI_READY1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_evk: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_evk>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hback-porch = <89>; - hfront-porch = <164>; - vback-porch = <23>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can_3v3>; - status = "okay"; - }; - - can1: can@80034000 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <®_can_3v3>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - fsl,ave-ctrl = <4>; - fsl,ave-delay = <2>; - fsl,settling = <10>; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - at24@51 { - compatible = "at24,24c32"; - pagesize = <32>; - reg = <0x51>; - }; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_a>; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 13 0>; - phy-reset-duration = <100>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; - - reg_fec_3v3: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 15 0>; - }; - - reg_usb0_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 9 0>; - enable-active-high; - }; - - reg_usb1_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; - - reg_lcd_3v3: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 0>; - enable-active-high; - }; - - reg_can_3v3: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 13 0>; - enable-active-high; - }; - - }; - - sound { - compatible = "fsl,imx28-evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio3_5>; - - user { - label = "Heartbeat"; - gpios = <&gpio3 5 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-m28.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx28-m28.dtsi deleted file mode 100644 index 214bb1506..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-m28.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx28.dtsi" - -/ { - model = "DENX M28"; - compatible = "denx,m28", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - }; - }; - - apbx@80040000 { - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - rtc: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-m28cu3.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-m28cu3.dts deleted file mode 100644 index 2df63bee6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-m28cu3.dts +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (C) 2013 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "MSR M28CU3"; - compatible = "msr,m28cu3", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "gpmi-nfc-0-boot"; - reg = <0x00000000 0x01400000>; - read-only; - }; - - partition@1 { - label = "gpmi-nfc-general-use"; - reg = <0x01400000 0x0ec00000>; - }; - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp2: ssp@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_a - &mmc2_cd_cfg - &mmc2_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd1>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - MX28_PAD_PWM4__GPIO_3_29 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_VSYNC__LCD_VSYNC - MX28_PAD_LCD_HSYNC__LCD_HSYNC - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_RESET__LCD_RESET - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_gpio: leds-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_MISO__GPIO_2_26 - MX28_PAD_SSP3_SCK__GPIO_2_24 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - ocotp@8002c000 { - status = "okay"; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <6410256>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hfront-porch = <20>; - vback-porch = <15>; - vfront-porch = <5>; - hsync-len = <30>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_2pins_b>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - disable-over-current; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 0>; - phy-reset-duration = <100>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_gpio>; - - user1 { - label = "sd0-led"; - gpios = <&gpio2 26 0>; - linux,default-trigger = "mmc0"; - }; - - user2 { - label = "sd1-led"; - gpios = <&gpio2 24 0>; - linux,default-trigger = "mmc2"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 0>; - }; - - reg_vddio_sd1: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vddio-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 0>; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-m28evk.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-m28evk.dts deleted file mode 100644 index 8d04e5703..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-m28evk.dts +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (C) 2012 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28-m28.dtsi" - -/ { - model = "DENX M28EVK"; - compatible = "denx,m28evk", "fsl,imx28"; - - apb@80000000 { - apbh@80000000 { - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio3 10 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp2: ssp@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_AUART2_CTS__GPIO_3_10 - MX28_PAD_AUART2_RTS__GPIO_3_11 - MX28_PAD_AUART3_RX__GPIO_3_12 - MX28_PAD_AUART3_TX__GPIO_3_13 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_ENABLE__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <0>; - hfront-porch = <256>; - vback-porch = <0>; - vfront-porch = <45>; - hsync-len = <1>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - status = "okay"; - }; - - can1: can@80034000 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - eeprom: eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; - }; - - auart2: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_b>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - vbus-supply = <®_usb0_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_a>; - status = "okay"; - }; - - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - clocks = <&clks 57>, <&clks 57>; - clock-names = "ipg", "ahb"; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 4 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - regulators { - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; - - reg_usb0_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 12 0>; - }; - - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 13 0>; - }; - }; - - sound { - compatible = "denx,m28evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "m28evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx28-pinfunc.h deleted file mode 100644 index e11f69ba0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-pinfunc.h +++ /dev/null @@ -1,506 +0,0 @@ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ -#define __DT_BINDINGS_MX28_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 -#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 -#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 -#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 -#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 -#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 -#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 -#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 -#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 -#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 -#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 -#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 -#define MX28_PAD_LCD_D00__LCD_D0 0x1000 -#define MX28_PAD_LCD_D01__LCD_D1 0x1010 -#define MX28_PAD_LCD_D02__LCD_D2 0x1020 -#define MX28_PAD_LCD_D03__LCD_D3 0x1030 -#define MX28_PAD_LCD_D04__LCD_D4 0x1040 -#define MX28_PAD_LCD_D05__LCD_D5 0x1050 -#define MX28_PAD_LCD_D06__LCD_D6 0x1060 -#define MX28_PAD_LCD_D07__LCD_D7 0x1070 -#define MX28_PAD_LCD_D08__LCD_D8 0x1080 -#define MX28_PAD_LCD_D09__LCD_D9 0x1090 -#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX28_PAD_LCD_D16__LCD_D16 0x1100 -#define MX28_PAD_LCD_D17__LCD_D17 0x1110 -#define MX28_PAD_LCD_D18__LCD_D18 0x1120 -#define MX28_PAD_LCD_D19__LCD_D19 0x1130 -#define MX28_PAD_LCD_D20__LCD_D20 0x1140 -#define MX28_PAD_LCD_D21__LCD_D21 0x1150 -#define MX28_PAD_LCD_D22__LCD_D22 0x1160 -#define MX28_PAD_LCD_D23__LCD_D23 0x1170 -#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 -#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 -#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 -#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 -#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 -#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 -#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 -#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 -#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 -#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 -#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 -#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 -#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 -#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 -#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 -#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 -#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 -#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 -#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 -#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 -#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 -#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 -#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 -#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 -#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 -#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 -#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 -#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 -#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 -#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 -#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 -#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 -#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 -#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 -#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 -#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 -#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 -#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 -#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 -#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 -#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 -#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 -#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 -#define MX28_PAD_PWM0__PWM_0 0x3100 -#define MX28_PAD_PWM1__PWM_1 0x3110 -#define MX28_PAD_PWM2__PWM_2 0x3120 -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 -#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 -#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 -#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 -#define MX28_PAD_PWM3__PWM_3 0x31c0 -#define MX28_PAD_PWM4__PWM_4 0x31d0 -#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 -#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 -#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 -#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 -#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 -#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 -#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 -#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 -#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 -#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 -#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 -#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 -#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 -#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 -#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 -#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 -#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 -#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 -#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 -#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 -#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 -#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 -#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 -#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 -#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 -#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 -#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 -#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 -#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 -#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 -#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 -#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 -#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 -#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 -#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 -#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 -#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 -#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 -#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 -#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 -#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 -#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 -#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 -#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 -#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 -#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 -#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 -#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 -#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 -#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 -#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 -#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 -#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 -#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 -#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 -#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 -#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 -#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 -#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 -#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 -#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 -#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 -#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 -#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 -#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 -#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 -#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 -#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 -#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 -#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 -#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 -#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 -#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 -#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 -#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 -#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 -#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 -#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 -#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 -#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 -#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 -#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 -#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 -#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 -#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 -#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 -#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 -#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 -#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 -#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 -#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 -#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 -#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 -#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 -#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 -#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 -#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 -#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 -#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 -#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 -#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 -#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 -#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 -#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 -#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 -#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 -#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 -#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 -#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 -#define MX28_PAD_PWM0__I2C1_SCL 0x3101 -#define MX28_PAD_PWM1__I2C1_SDA 0x3111 -#define MX28_PAD_PWM2__USB0_ID 0x3121 -#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 -#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 -#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 -#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 -#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 -#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 -#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 -#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 -#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 -#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 -#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 -#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 -#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 -#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 -#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 -#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 -#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 -#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 -#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 -#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 -#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 -#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 -#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 -#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 -#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 -#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 -#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 -#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 -#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 -#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 -#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 -#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 -#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 -#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 -#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 -#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 -#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 -#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 -#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 -#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 -#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 -#define MX28_PAD_AUART1_RX__PWM_0 0x3042 -#define MX28_PAD_AUART1_TX__PWM_1 0x3052 -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 -#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 -#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 -#define MX28_PAD_PWM0__DUART_RX 0x3102 -#define MX28_PAD_PWM1__DUART_TX 0x3112 -#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 -#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 -#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 -#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 -#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 -#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 -#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 -#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 -#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 -#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 -#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 -#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 -#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 -#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 -#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 -#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 -#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 -#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 -#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 -#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 -#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 -#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 -#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 -#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 -#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 -#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 -#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 -#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 -#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 -#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 -#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 -#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 -#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 -#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 -#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 -#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 -#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 -#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 -#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 -#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 -#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 -#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 -#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 -#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 -#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 -#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 -#define MX28_PAD_PWM0__GPIO_3_16 0x3103 -#define MX28_PAD_PWM1__GPIO_3_17 0x3113 -#define MX28_PAD_PWM2__GPIO_3_18 0x3123 -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 -#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 -#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 -#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 -#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 -#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 -#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 -#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 -#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 -#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 -#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 - -#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-sps1.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-sps1.dts deleted file mode 100644 index 0ce3cb8e7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-sps1.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (C) 2012 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "SchulerControl GmbH, SC SPS 1"; - compatible = "schulercontrol,imx28-sps1", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog-gpios@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPIO_0_0 - MX28_PAD_GPMI_D03__GPIO_0_3 - MX28_PAD_GPMI_D06__GPIO_0_6 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: ssp@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256", "mr25h256"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - }; - - apbx@80040000 { - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - eeprom: eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - pagesize = <32>; - }; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - vbus-supply = <®_usb0_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_b>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 9 0>; - }; - }; - - leds { - #address-cells = <1>; - #size-cells = <0>; - compatible = "gpio-leds"; - status = "okay"; - - led@1 { - label = "sps1-1:yellow:user"; - gpios = <&gpio0 6 0>; - linux,default-trigger = "heartbeat"; - reg = <0>; - }; - - led@2 { - label = "sps1-2:red:user"; - gpios = <&gpio0 3 0>; - linux,default-trigger = "heartbeat"; - reg = <1>; - }; - - led@3 { - label = "sps1-3:red:user"; - gpios = <&gpio0 0 0>; - default-trigger = "heartbeat"; - reg = <2>; - }; - - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28-tx28.dts b/software/linux/kernel/arch/arm/boot/dts/imx28-tx28.dts deleted file mode 100644 index 0ebbc8385..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28-tx28.dts +++ /dev/null @@ -1,723 +0,0 @@ -/* - * Copyright 2012 Shawn Guo - * Copyright 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28.dtsi" -#include -#include - -/ { - model = "Ka-Ro electronics TX28 module"; - compatible = "karo,tx28", "fsl,imx28"; - - aliases { - can0 = &can0; - can1 = &can1; - display = &display0; - ds1339 = &ds1339; - gpio5 = &gpio5; - lcdif = &lcdif; - lcdif_23bit_pins = &tx28_lcdif_23bit_pins; - lcdif_24bit_pins = &lcdif_24bit_pins_a; - reg_can_xcvr = ®_can_xcvr; - spi_gpio = &spi_gpio; - spi_mxs = &ssp3; - stk5led = &user_led; - usbotg = &usb0; - }; - - memory { - reg = <0 0>; /* will be filled in by U-Boot */ - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2p5v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_flexcan_xcvr_pins>; - }; - - reg_lcd: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_reset: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - startup-delay-us = <300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - sound { - compatible = "fsl,imx28-tx28-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-tx28-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - - user_led: user { - label = "Heartbeat"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 500000>; - /* - * a silly way to create a 1:1 relationship between the - * PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - matrix_keypad: matrix-keypad { - compatible = "gpio-matrix-keypad"; - col-gpios = < - &gpio5 0 GPIO_ACTIVE_HIGH - &gpio5 1 GPIO_ACTIVE_HIGH - &gpio5 2 GPIO_ACTIVE_HIGH - &gpio5 3 GPIO_ACTIVE_HIGH - >; - row-gpios = < - &gpio5 4 GPIO_ACTIVE_HIGH - &gpio5 5 GPIO_ACTIVE_HIGH - &gpio5 6 GPIO_ACTIVE_HIGH - &gpio5 7 GPIO_ACTIVE_HIGH - >; - /* sample keymap */ - linux,keymap = < - 0x00000074 /* row 0, col 0, KEY_POWER */ - 0x00010052 /* row 0, col 1, KEY_KP0 */ - 0x0002004f /* row 0, col 2, KEY_KP1 */ - 0x00030050 /* row 0, col 3, KEY_KP2 */ - 0x01000051 /* row 1, col 0, KEY_KP3 */ - 0x0101004b /* row 1, col 1, KEY_KP4 */ - 0x0102004c /* row 1, col 2, KEY_KP5 */ - 0x0103004d /* row 1, col 3, KEY_KP6 */ - 0x02000047 /* row 2, col 0, KEY_KP7 */ - 0x02010048 /* row 2, col 1, KEY_KP8 */ - 0x02020049 /* row 2, col 2, KEY_KP9 */ - >; - gpio-activelow; - wakeup-source; - debounce-delay-ms = <100>; - col-scan-delay-us = <5000>; - linux,no-autorepeat; - }; - - spi_gpio: spi-gpio { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_spi_gpio_pins>; - - gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>; - num-chipselects = <3>; - cs-gpios = < - &gpio2 27 GPIO_ACTIVE_LOW - &gpio3 8 GPIO_ACTIVE_LOW - &gpio3 9 GPIO_ACTIVE_LOW - >; - /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ - status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; - }; -}; - -/* 2nd TX-Std UART - (A)UART1 */ -&auart1 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; -}; - -/* 3rd TX-Std UART - (A)UART3 */ -&auart3 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&digctl { - status = "okay"; -}; - -/* 1st TX-Std UART - (D)UART */ -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; -}; - -&gpmi { - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - clocks = <&mclk>; - }; - - gpio5: pca953x@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_pca9554_pins>; - interrupt-parent = <&gpio3>; - interrupts = <28 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_edt_ft5x06_pins>; - interrupt-parent = <&gpio2>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_tsc2007_pins>; - interrupt-parent = <&gpio3>; - interrupts = <20 0>; - pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = /bits/ 16 <660>; - }; - - ds1339: rtc@68 { - compatible = "mxim,ds1339"; - reg = <0x68>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; - lcd-supply = <®_lcd>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - display-timings { - native-mode = <&timing5>; - timing0: timing0 { - panel-name = "VGA"; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing1: timing1 { - panel-name = "ETV570"; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing2: timing2 { - panel-name = "ET0350"; - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing3: timing3 { - panel-name = "ET0430"; - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing4: timing4 { - panel-name = "ET0500", "ET0700"; - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing5: timing5 { - panel-name = "ETQ570"; - clock-frequency = <6400000>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default", "gpio_mode"; - pinctrl-0 = <&mac0_pins_a>; - pinctrl-1 = <&tx28_mac0_pins_gpio>; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - /* not enabled by default */ -}; - -&mxs_rtc { - status = "okay"; -}; - -&ocotp { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins { - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */ - MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */ - MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins { - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__GPIO_1_0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_lcdif_23bit_pins: tx28-lcdif-23bit { - fsl,pinmux-ids = < - /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */ - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - MX28_PAD_LCD_D18__LCD_D18 - MX28_PAD_LCD_D19__LCD_D19 - MX28_PAD_LCD_D20__LCD_D20 - MX28_PAD_LCD_D21__LCD_D21 - MX28_PAD_LCD_D22__LCD_D22 - MX28_PAD_LCD_D23__LCD_D23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl { - fsl,pinmux-ids = < - MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */ - MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_mac0_pins_gpio: tx28-mac0-gpio-pins { - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__GPIO_4_0 - MX28_PAD_ENET0_MDIO__GPIO_4_1 - MX28_PAD_ENET0_RX_EN__GPIO_4_2 - MX28_PAD_ENET0_RXD0__GPIO_4_3 - MX28_PAD_ENET0_RXD1__GPIO_4_4 - MX28_PAD_ENET0_TX_EN__GPIO_4_6 - MX28_PAD_ENET0_TXD0__GPIO_4_7 - MX28_PAD_ENET0_TXD1__GPIO_4_8 - MX28_PAD_ENET_CLK__GPIO_4_16 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_pca9554_pins: tx28-pca9554-pins { - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_spi_gpio_pins: spi-gpiogrp { - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 - MX28_PAD_SSP3_SCK__GPIO_2_24 - MX28_PAD_SSP3_MOSI__GPIO_2_25 - MX28_PAD_SSP3_MISO__GPIO_2_26 - MX28_PAD_SSP3_SS0__GPIO_2_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_tsc2007_pins: tx28-tsc2007-pins { - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - - tx28_usbphy0_pins: tx28-usbphy0-pins { - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */ - MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - tx28_usbphy1_pins: tx28-usbphy1-pins { - fsl,pinmux-ids = < - MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */ - MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_b>; - fsl,saif-master; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default", "special"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; -}; - -&ssp3 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins_a>; - clock-frequency = <57600000>; - status = "okay"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; - }; - - spi@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <57600000>; - }; -}; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - disable-over-current; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&tx28_usbphy0_pins>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbphy1 { - pinctrl-names = "default"; - pinctrl-0 = <&tx28_usbphy1_pins>; - phy_type = "utmi"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx28.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx28.dtsi deleted file mode 100644 index 0ad893bf5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx28.dtsi +++ /dev/null @@ -1,1294 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include "skeleton.dtsi" -#include "imx28-pinfunc.h" - -/ { - interrupt-parent = <&icoll>; - - aliases { - ethernet0 = &mac0; - ethernet1 = &mac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - saif0 = &saif0; - saif1 = &saif1; - serial0 = &auart0; - serial1 = &auart1; - serial2 = &auart2; - serial3 = &auart3; - serial4 = &auart4; - spi0 = &ssp1; - spi1 = &ssp2; - usbphy0 = &usbphy0; - usbphy1 = &usbphy1; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - apb@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x80000>; - ranges; - - apbh@80000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x3c900>; - ranges; - - icoll: interrupt-controller@80000000 { - compatible = "fsl,imx28-icoll", "fsl,icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80000000 0x2000>; - }; - - hsadc: hsadc@80002000 { - reg = <0x80002000 0x2000>; - interrupts = <13>; - dmas = <&dma_apbh 12>; - dma-names = "rx"; - status = "disabled"; - }; - - dma_apbh: dma-apbh@80004000 { - compatible = "fsl,imx28-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <82 83 84 85 - 88 88 88 88 - 88 88 88 88 - 87 86 0 0>; - interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", - "gpmi0", "gmpi1", "gpmi2", "gmpi3", - "gpmi4", "gmpi5", "gpmi6", "gmpi7", - "hsadc", "lcdif", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 25>; - }; - - perfmon: perfmon@80006000 { - reg = <0x80006000 0x800>; - interrupts = <27>; - status = "disabled"; - }; - - gpmi: gpmi-nand@8000c000 { - compatible = "fsl,imx28-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <41>; - interrupt-names = "bch"; - clocks = <&clks 50>; - clock-names = "gpmi_io"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp0: ssp@80010000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80010000 0x2000>; - interrupts = <96>; - clocks = <&clks 46>; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp1: ssp@80012000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80012000 0x2000>; - interrupts = <97>; - clocks = <&clks 47>; - dmas = <&dma_apbh 1>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp2: ssp@80014000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80014000 0x2000>; - interrupts = <98>; - clocks = <&clks 48>; - dmas = <&dma_apbh 2>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - ssp3: ssp@80016000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80016000 0x2000>; - interrupts = <99>; - clocks = <&clks 49>; - dmas = <&dma_apbh 3>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - pinctrl: pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-pinctrl", "simple-bus"; - reg = <0x80018000 0x2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <0>; - interrupts = <127>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <1>; - interrupts = <126>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <2>; - interrupts = <125>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@3 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <3>; - interrupts = <124>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@4 { - compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; - reg = <4>; - interrupts = <123>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - duart_pins_a: duart@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__DUART_RX - MX28_PAD_PWM1__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - duart_pins_b: duart@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__DUART_RX - MX28_PAD_AUART0_RTS__DUART_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - duart_4pins_a: duart-4pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__DUART_RX - MX28_PAD_AUART0_RTS__DUART_TX - MX28_PAD_AUART0_RX__DUART_CTS - MX28_PAD_AUART0_TX__DUART_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_a: gpmi-nand@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPMI_D0 - MX28_PAD_GPMI_D01__GPMI_D1 - MX28_PAD_GPMI_D02__GPMI_D2 - MX28_PAD_GPMI_D03__GPMI_D3 - MX28_PAD_GPMI_D04__GPMI_D4 - MX28_PAD_GPMI_D05__GPMI_D5 - MX28_PAD_GPMI_D06__GPMI_D6 - MX28_PAD_GPMI_D07__GPMI_D7 - MX28_PAD_GPMI_CE0N__GPMI_CE0N - MX28_PAD_GPMI_RDY0__GPMI_READY0 - MX28_PAD_GPMI_RDN__GPMI_RDN - MX28_PAD_GPMI_WRN__GPMI_WRN - MX28_PAD_GPMI_ALE__GPMI_ALE - MX28_PAD_GPMI_CLE__GPMI_CLE - MX28_PAD_GPMI_RESETN__GPMI_RESETN - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_status_cfg: gpmi-status-cfg { - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPMI_RDN - MX28_PAD_GPMI_WRN__GPMI_WRN - MX28_PAD_GPMI_RESETN__GPMI_RESETN - >; - fsl,drive-strength = ; - }; - - auart0_pins_a: auart0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__AUART0_RX - MX28_PAD_AUART0_TX__AUART0_TX - MX28_PAD_AUART0_CTS__AUART0_CTS - MX28_PAD_AUART0_RTS__AUART0_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart0_2pins_a: auart0-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__AUART0_RX - MX28_PAD_AUART0_TX__AUART0_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_pins_a: auart1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__AUART1_RX - MX28_PAD_AUART1_TX__AUART1_TX - MX28_PAD_AUART1_CTS__AUART1_CTS - MX28_PAD_AUART1_RTS__AUART1_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart1_2pins_a: auart1-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__AUART1_RX - MX28_PAD_AUART1_TX__AUART1_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_2pins_a: auart2-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__AUART2_RX - MX28_PAD_SSP2_MOSI__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_2pins_b: auart2-2pins@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__AUART2_RX - MX28_PAD_AUART2_TX__AUART2_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart2_pins_a: auart2-pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__AUART2_RX - MX28_PAD_AUART2_TX__AUART2_TX - MX28_PAD_AUART2_CTS__AUART2_CTS - MX28_PAD_AUART2_RTS__AUART2_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_pins_a: auart3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART3_RX__AUART3_RX - MX28_PAD_AUART3_TX__AUART3_TX - MX28_PAD_AUART3_CTS__AUART3_CTS - MX28_PAD_AUART3_RTS__AUART3_RTS - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_2pins_a: auart3-2pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_MISO__AUART3_RX - MX28_PAD_SSP2_SS0__AUART3_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart3_2pins_b: auart3-2pins@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART3_RX__AUART3_RX - MX28_PAD_AUART3_TX__AUART3_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart4_2pins_a: auart4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_SCK__AUART4_TX - MX28_PAD_SSP3_MOSI__AUART4_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - auart4_2pins_b: auart4@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__AUART4_RX - MX28_PAD_AUART0_RTS__AUART4_TX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_a: mac0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__ENET0_MDC - MX28_PAD_ENET0_MDIO__ENET0_MDIO - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN - MX28_PAD_ENET0_RXD0__ENET0_RXD0 - MX28_PAD_ENET0_RXD1__ENET0_RXD1 - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN - MX28_PAD_ENET0_TXD0__ENET0_TXD0 - MX28_PAD_ENET0_TXD1__ENET0_TXD1 - MX28_PAD_ENET_CLK__CLKCTRL_ENET - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_b: mac0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__ENET0_MDC - MX28_PAD_ENET0_MDIO__ENET0_MDIO - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN - MX28_PAD_ENET0_RXD0__ENET0_RXD0 - MX28_PAD_ENET0_RXD1__ENET0_RXD1 - MX28_PAD_ENET0_RXD2__ENET0_RXD2 - MX28_PAD_ENET0_RXD3__ENET0_RXD3 - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN - MX28_PAD_ENET0_TXD0__ENET0_TXD0 - MX28_PAD_ENET0_TXD1__ENET0_TXD1 - MX28_PAD_ENET0_TXD2__ENET0_TXD2 - MX28_PAD_ENET0_TXD3__ENET0_TXD3 - MX28_PAD_ENET_CLK__CLKCTRL_ENET - MX28_PAD_ENET0_COL__ENET0_COL - MX28_PAD_ENET0_CRS__ENET0_CRS - MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK - MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac1_pins_a: mac1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_CRS__ENET1_RX_EN - MX28_PAD_ENET0_RXD2__ENET1_RXD0 - MX28_PAD_ENET0_RXD3__ENET1_RXD1 - MX28_PAD_ENET0_COL__ENET1_TX_EN - MX28_PAD_ENET0_TXD2__ENET1_TXD0 - MX28_PAD_ENET0_TXD3__ENET1_TXD1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_DATA4__SSP0_D4 - MX28_PAD_SSP0_DATA5__SSP0_D5 - MX28_PAD_SSP0_DATA6__SSP0_D6 - MX28_PAD_SSP0_DATA7__SSP0_D7 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_4bit_pins_a: mmc0-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc0_cd_cfg: mmc0-cd-cfg { - fsl,pinmux-ids = < - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc0_sck_cfg: mmc0-sck-cfg { - fsl,pinmux-ids = < - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - mmc1_4bit_pins_a: mmc1-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__SSP1_D0 - MX28_PAD_GPMI_D01__SSP1_D1 - MX28_PAD_GPMI_D02__SSP1_D2 - MX28_PAD_GPMI_D03__SSP1_D3 - MX28_PAD_GPMI_RDY1__SSP1_CMD - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT - MX28_PAD_GPMI_WRN__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc1_cd_cfg: mmc1-cd-cfg { - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc1_sck_cfg: mmc1-sck-cfg { - fsl,pinmux-ids = < - MX28_PAD_GPMI_WRN__SSP1_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - - mmc2_4bit_pins_a: mmc2-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP1_SCK__SSP2_D1 - MX28_PAD_SSP1_CMD__SSP2_D2 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_cd_cfg: mmc2-cd-cfg { - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - >; - fsl,pull-up = ; - }; - - mmc2_sck_cfg: mmc2-sck-cfg { - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - - i2c0_pins_a: i2c0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__I2C0_SCL - MX28_PAD_I2C0_SDA__I2C0_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c0_pins_b: i2c0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__I2C0_SCL - MX28_PAD_AUART0_TX__I2C0_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c1_pins_a: i2c1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__I2C1_SCL - MX28_PAD_PWM1__I2C1_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2c1_pins_b: i2c1@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_CTS__I2C1_SCL - MX28_PAD_AUART2_RTS__I2C1_SDA - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif0_pins_a: saif0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif0_pins_b: saif0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - saif1_pins_a: saif1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm0_pins_a: pwm0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM0__PWM_0 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm2_pins_a: pwm2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM2__PWM_2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm3_pins_a: pwm3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__PWM_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm3_pins_b: pwm3@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__PWM_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pwm4_pins_a: pwm4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM4__PWM_4 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_24bit_pins_a: lcdif-24bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - MX28_PAD_LCD_D18__LCD_D18 - MX28_PAD_LCD_D19__LCD_D19 - MX28_PAD_LCD_D20__LCD_D20 - MX28_PAD_LCD_D21__LCD_D21 - MX28_PAD_LCD_D22__LCD_D22 - MX28_PAD_LCD_D23__LCD_D23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_a: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_16bit_pins_a: lcdif-16bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_sync_pins_a: lcdif-sync@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - can0_pins_a: can0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY2__CAN0_TX - MX28_PAD_GPMI_RDY3__CAN0_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - can1_pins_a: can1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE2N__CAN1_TX - MX28_PAD_GPMI_CE3N__CAN1_RX - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_a: spi2@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - MX28_PAD_SSP2_MOSI__SSP2_CMD - MX28_PAD_SSP2_MISO__SSP2_D0 - MX28_PAD_SSP2_SS0__SSP2_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_a: spi3@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__SSP3_D4 - MX28_PAD_AUART2_TX__SSP3_D5 - MX28_PAD_SSP3_SCK__SSP3_SCK - MX28_PAD_SSP3_MOSI__SSP3_CMD - MX28_PAD_SSP3_MISO__SSP3_D0 - MX28_PAD_SSP3_SS0__SSP3_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_b: spi3@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_SCK__SSP3_SCK - MX28_PAD_SSP3_MOSI__SSP3_CMD - MX28_PAD_SSP3_MISO__SSP3_D0 - MX28_PAD_SSP3_SS0__SSP3_D3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_pins_a: usb0@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__USB0_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_pins_b: usb0@1 { - reg = <1>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_CTS__USB0_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb1_pins_a: usb1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS1__USB1_OVERCURRENT - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_id_pins_a: usb0id@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RTS__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_id_pins_b: usb0id1@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM2__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - }; - - digctl: digctl@8001c000 { - compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; - reg = <0x8001c000 0x2000>; - interrupts = <89>; - status = "disabled"; - }; - - etm: etm@80022000 { - reg = <0x80022000 0x2000>; - status = "disabled"; - }; - - dma_apbx: dma-apbx@80024000 { - compatible = "fsl,imx28-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <78 79 66 0 - 80 81 68 69 - 70 71 72 73 - 74 75 76 77>; - interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", - "saif0", "saif1", "i2c0", "i2c1", - "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", - "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; - #dma-cells = <1>; - dma-channels = <16>; - clocks = <&clks 26>; - }; - - dcp: dcp@80028000 { - compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; - reg = <0x80028000 0x2000>; - interrupts = <52 53 54>; - status = "okay"; - }; - - pxp: pxp@8002a000 { - reg = <0x8002a000 0x2000>; - interrupts = <39>; - status = "disabled"; - }; - - ocotp: ocotp@8002c000 { - compatible = "fsl,imx28-ocotp", "fsl,ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8002c000 0x2000>; - clocks = <&clks 25>; - }; - - axi-ahb@8002e000 { - reg = <0x8002e000 0x2000>; - status = "disabled"; - }; - - lcdif: lcdif@80030000 { - compatible = "fsl,imx28-lcdif"; - reg = <0x80030000 0x2000>; - interrupts = <38>; - clocks = <&clks 55>; - dmas = <&dma_apbh 13>; - dma-names = "rx"; - status = "disabled"; - }; - - can0: can@80032000 { - compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; - reg = <0x80032000 0x2000>; - interrupts = <8>; - clocks = <&clks 58>, <&clks 58>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can1: can@80034000 { - compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; - reg = <0x80034000 0x2000>; - interrupts = <9>; - clocks = <&clks 59>, <&clks 59>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - simdbg: simdbg@8003c000 { - reg = <0x8003c000 0x200>; - status = "disabled"; - }; - - simgpmisel: simgpmisel@8003c200 { - reg = <0x8003c200 0x100>; - status = "disabled"; - }; - - simsspsel: simsspsel@8003c300 { - reg = <0x8003c300 0x100>; - status = "disabled"; - }; - - simmemsel: simmemsel@8003c400 { - reg = <0x8003c400 0x100>; - status = "disabled"; - }; - - gpiomon: gpiomon@8003c500 { - reg = <0x8003c500 0x100>; - status = "disabled"; - }; - - simenet: simenet@8003c700 { - reg = <0x8003c700 0x100>; - status = "disabled"; - }; - - armjtag: armjtag@8003c800 { - reg = <0x8003c800 0x100>; - status = "disabled"; - }; - }; - - apbx@80040000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80040000 0x40000>; - ranges; - - clks: clkctrl@80040000 { - compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; - }; - - saif0: saif@80042000 { - compatible = "fsl,imx28-saif"; - reg = <0x80042000 0x2000>; - interrupts = <59>; - #clock-cells = <0>; - clocks = <&clks 53>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - power: power@80044000 { - reg = <0x80044000 0x2000>; - status = "disabled"; - }; - - saif1: saif@80046000 { - compatible = "fsl,imx28-saif"; - reg = <0x80046000 0x2000>; - interrupts = <58>; - clocks = <&clks 54>; - dmas = <&dma_apbx 5>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - lradc: lradc@80050000 { - compatible = "fsl,imx28-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <10 14 15 16 17 18 19 - 20 21 22 23 24 25>; - status = "disabled"; - clocks = <&clks 41>; - #io-channel-cells = <1>; - }; - - spdif: spdif@80054000 { - reg = <0x80054000 0x2000>; - interrupts = <45>; - dmas = <&dma_apbx 2>; - dma-names = "tx"; - status = "disabled"; - }; - - mxs_rtc: rtc@80056000 { - compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x80056000 0x2000>; - interrupts = <29>; - }; - - i2c0: i2c@80058000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-i2c"; - reg = <0x80058000 0x2000>; - interrupts = <111>; - clock-frequency = <100000>; - dmas = <&dma_apbx 6>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - i2c1: i2c@8005a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-i2c"; - reg = <0x8005a000 0x2000>; - interrupts = <110>; - clock-frequency = <100000>; - dmas = <&dma_apbx 7>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - pwm: pwm@80064000 { - compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; - clocks = <&clks 44>; - #pwm-cells = <2>; - fsl,pwm-number = <8>; - status = "disabled"; - }; - - timer: timrot@80068000 { - compatible = "fsl,imx28-timrot", "fsl,timrot"; - reg = <0x80068000 0x2000>; - interrupts = <48 49 50 51>; - clocks = <&clks 26>; - }; - - auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart1: serial@8006c000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <113>; - dmas = <&dma_apbx 10>, <&dma_apbx 11>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart2: serial@8006e000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006e000 0x2000>; - interrupts = <114>; - dmas = <&dma_apbx 12>, <&dma_apbx 13>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart3: serial@80070000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x80070000 0x2000>; - interrupts = <115>; - dmas = <&dma_apbx 14>, <&dma_apbx 15>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - auart4: serial@80072000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x80072000 0x2000>; - interrupts = <116>; - dmas = <&dma_apbx 0>, <&dma_apbx 1>; - dma-names = "rx", "tx"; - clocks = <&clks 45>; - status = "disabled"; - }; - - duart: serial@80074000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80074000 0x1000>; - interrupts = <47>; - clocks = <&clks 45>, <&clks 26>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; - }; - - usbphy0: usbphy@8007c000 { - compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; - reg = <0x8007c000 0x2000>; - clocks = <&clks 62>; - status = "disabled"; - }; - - usbphy1: usbphy@8007e000 { - compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; - reg = <0x8007e000 0x2000>; - clocks = <&clks 63>; - status = "disabled"; - }; - }; - }; - - ahb@80080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80080000 0x80000>; - ranges; - - usb0: usb@80080000 { - compatible = "fsl,imx28-usb", "fsl,imx27-usb"; - reg = <0x80080000 0x10000>; - interrupts = <93>; - clocks = <&clks 60>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usb1: usb@80090000 { - compatible = "fsl,imx28-usb", "fsl,imx27-usb"; - reg = <0x80090000 0x10000>; - interrupts = <92>; - clocks = <&clks 61>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - dflpt: dflpt@800c0000 { - reg = <0x800c0000 0x10000>; - status = "disabled"; - }; - - mac0: ethernet@800f0000 { - compatible = "fsl,imx28-fec"; - reg = <0x800f0000 0x4000>; - interrupts = <101>; - clocks = <&clks 57>, <&clks 57>, <&clks 64>; - clock-names = "ipg", "ahb", "enet_out"; - status = "disabled"; - }; - - mac1: ethernet@800f4000 { - compatible = "fsl,imx28-fec"; - reg = <0x800f4000 0x4000>; - interrupts = <102>; - clocks = <&clks 57>, <&clks 57>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - - etn_switch: switch@800f8000 { - reg = <0x800f8000 0x8000>; - status = "disabled"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&lradc 8>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx31-bug.dts b/software/linux/kernel/arch/arm/boot/dts/imx31-bug.dts deleted file mode 100644 index ae6cebbed..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx31-bug.dts +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2012 Denis 'GNUtoo' Carikli - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx31.dtsi" - -/ { - model = "Buglabs i.MX31 Bug 1.x"; - compatible = "buglabs,imx31-bug", "fsl,imx31"; - - memory { - reg = <0x80000000 0x8000000>; /* 128M */ - }; -}; - -&uart5 { - uart-has-rtscts; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx31.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx31.dtsi deleted file mode 100644 index 11e9e6bd8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx31.dtsi +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright 2012 Denis 'GNUtoo' Carikli - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - }; - }; - - avic: interrupt-controller@68000000 { - compatible = "fsl,imx31-avic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x100000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&avic>; - ranges; - - aips@43f00000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - uart1: serial@43f90000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 10>, <&clks 30>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - interrupts = <32>; - clocks = <&clks 10>, <&clks 31>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - interrupts = <24>; - clocks = <&clks 46>; - status = "disabled"; - }; - - uart4: serial@43fb0000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43fb0000 0x4000>; - clocks = <&clks 10>, <&clks 49>; - clock-names = "ipg", "per"; - interrupts = <46>; - status = "disabled"; - }; - - uart5: serial@43fb4000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43fb4000 0x4000>; - interrupts = <47>; - clocks = <&clks 10>, <&clks 50>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - spba@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x100000>; - ranges; - - uart3: serial@5000c000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <18>; - clocks = <&clks 10>, <&clks 48>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - iim: iim@5001c000 { - compatible = "fsl,imx31-iim", "fsl,imx27-iim"; - reg = <0x5001c000 0x1000>; - interrupts = <19>; - clocks = <&clks 25>; - }; - }; - - aips@53f00000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - clks: ccm@53f80000{ - compatible = "fsl,imx31-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>, <53>; - #clock-cells = <1>; - }; - - gpt: timer@53f90000 { - compatible = "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - interrupts = <29>; - clocks = <&clks 10>, <&clks 22>; - clock-names = "ipg", "per"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi deleted file mode 100644 index 9c2b715ab..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "imx35.dtsi" - -/ { - model = "Eukrea CPUIMX35"; - compatible = "eukrea,cpuimx35", "fsl,imx35"; - - memory { - reg = <0x80000000 0x8000000>; /* 128M */ - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsc2007: tsc2007@48 { - compatible = "ti,tsc2007"; - gpios = <&gpio3 2 0>; - interrupt-parent = <&gpio3>; - interrupts = <0x2 0x8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007_1>; - reg = <0x48>; - ti,x-plate-ohms = <180>; - }; -}; - -&iomuxc { - imx35-eukrea { - pinctrl_fec: fecgrp { - fsl,pins = < - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 - MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX35_PAD_FEC_COL__FEC_COL 0x80000000 - MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 - MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 - MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 - MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 - MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 - MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 - MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 - MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 - MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 - MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 - MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 - >; - }; - - pinctrl_tsc2007_1: tsc2007grp-1 { - fsl,pins = ; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts deleted file mode 100644 index e9357131b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; - -#include -#include -#include "imx35-eukrea-cpuimx35.dtsi" - -/ { - model = "Eukrea CPUIMX35"; - compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bp1>; - - bp1 { - label = "BP1"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - linux,input-type = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led1>; - - led1 { - label = "led1"; - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx35-eukrea-tlv320aic23"; - ssi-controller = <&ssi1>; - fsl,mux-int-port = <1>; - fsl,mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 24>; - status = "okay"; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx35-eukrea { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 - MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 - MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000 - >; - }; - - pinctrl_bp1: bp1grp { - fsl,pins = ; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */ - >; - }; - - pinctrl_led1: led1grp { - fsl,pins = ; - }; - - pinctrl_reg_lcd_3v3: reg-lcd-3v3 { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 - MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 - MX35_PAD_CTS1__UART1_CTS 0x1c5 - MX35_PAD_RTS1__UART1_RTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 - MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5 - MX35_PAD_RTS2__UART2_RTS 0x1c5 - MX35_PAD_CTS2__UART2_CTS 0x1c5 - >; - }; - }; -}; - -&ssi1 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbhost1 { - phy_type = "serial"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "otg"; - external-vbus-divider; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx35-pdk.dts b/software/linux/kernel/arch/arm/boot/dts/imx35-pdk.dts deleted file mode 100644 index 9bb628f22..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx35-pdk.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * Copyright 2014 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx35.dtsi" - -/ { - model = "Freescale i.MX35 Product Development Kit"; - compatible = "fsl,imx35-pdk", "fsl,imx35"; - - memory { - reg = <0x80000000 0x8000000>, - <0x90000000 0x8000000>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&iomuxc { - imx35-pdk { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 - MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 - MX35_PAD_CTS1__UART1_CTS 0x1c5 - MX35_PAD_RTS1__UART1_RTS 0x1c5 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx35-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx35-pinfunc.h deleted file mode 100644 index 4911f2c40..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx35-pinfunc.h +++ /dev/null @@ -1,970 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX35_PINFUNC_H -#define __DTS_IMX35_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 -#define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 -#define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 -#define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 -#define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 -#define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 -#define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 -#define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 -#define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 -#define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 -#define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0 -#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0 -#define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0 -#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0 -#define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0 -#define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0 -#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0 -#define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0 -#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0 -#define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0 -#define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0 -#define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0 -#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0 -#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0 -#define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0 -#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0 -#define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0 -#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0 -#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0 -#define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0 -#define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0 -#define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0 -#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0 -#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0 -#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0 -#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0 -#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0 -#define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0 -#define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0 -#define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0 -#define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0 -#define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0 -#define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0 -#define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0 -#define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0 -#define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0 -#define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0 -#define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0 -#define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0 -#define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0 -#define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0 -#define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0 -#define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0 -#define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0 -#define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0 -#define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0 -#define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0 -#define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0 -#define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0 -#define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0 -#define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0 -#define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0 -#define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0 -#define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0 -#define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0 -#define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0 -#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0 -#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0 -#define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0 -#define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0 -#define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0 -#define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0 -#define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0 -#define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0 -#define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0 -#define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0 -#define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0 -#define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0 -#define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0 -#define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0 -#define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0 -#define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0 -#define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0 -#define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0 -#define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0 -#define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0 -#define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0 -#define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0 -#define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0 -#define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0 -#define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0 -#define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0 -#define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0 -#define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0 -#define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0 -#define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0 -#define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0 -#define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0 -#define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0 -#define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0 -#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0 -#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0 -#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0 -#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0 -#define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0 -#define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0 -#define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0 -#define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0 -#define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0 -#define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0 -#define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0 -#define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0 -#define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0 -#define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0 -#define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0 -#define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0 -#define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0 -#define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0 -#define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1 -#define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0 -#define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0 -#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0 -#define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0 -#define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0 -#define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0 -#define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0 -#define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0 -#define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0 -#define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0 -#define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0 -#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0 -#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0 -#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0 -#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0 -#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0 -#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0 -#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0 -#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0 -#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0 -#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0 -#define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0 -#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0 -#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0 -#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0 -#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0 -#define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0 -#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0 -#define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0 -#define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0 -#define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0 -#define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0 -#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0 -#define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0 -#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0 -#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0 -#define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0 -#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0 -#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0 -#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0 -#define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0 -#define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0 -#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0 -#define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0 -#define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0 -#define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0 -#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0 -#define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0 -#define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0 -#define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0 -#define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0 -#define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0 -#define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0 -#define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0 -#define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0 -#define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0 -#define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0 -#define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0 -#define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0 -#define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0 -#define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0 -#define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0 -#define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0 -#define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0 -#define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0 -#define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1 -#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0 -#define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0 -#define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0 -#define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1 -#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0 -#define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0 -#define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0 -#define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1 -#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0 -#define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0 -#define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0 -#define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0 -#define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0 -#define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0 -#define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0 -#define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0 -#define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0 -#define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0 -#define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0 -#define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0 -#define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0 -#define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0 -#define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0 -#define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0 -#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0 -#define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0 -#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0 -#define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0 -#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0 -#define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0 -#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0 -#define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0 -#define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0 -#define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0 -#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0 -#define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0 -#define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0 -#define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0 -#define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0 -#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0 -#define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0 -#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0 -#define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0 -#define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0 -#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0 -#define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0 -#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0 -#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0 -#define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0 -#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0 -#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0 -#define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0 -#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0 -#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0 -#define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0 -#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0 -#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0 -#define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0 -#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0 -#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0 -#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0 -#define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0 -#define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1 -#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0 -#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0 -#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0 -#define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0 -#define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1 -#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0 -#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0 -#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0 -#define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0 -#define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0 -#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0 -#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0 -#define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0 -#define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0 -#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0 -#define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0 -#define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1 -#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0 -#define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0 -#define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1 -#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0 -#define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0 -#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0 -#define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0 -#define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0 -#define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1 -#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0 -#define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0 -#define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1 -#define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0 -#define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1 -#define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0 -#define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1 -#define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0 -#define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1 -#define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0 -#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0 -#define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0 -#define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0 -#define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1 -#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0 -#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0 -#define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1 -#define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0 -#define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0 -#define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0 -#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0 -#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0 -#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0 -#define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0 -#define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0 -#define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0 -#define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0 -#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0 -#define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1 -#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0 -#define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0 -#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0 -#define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0 -#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0 -#define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1 -#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0 -#define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0 -#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0 -#define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0 -#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0 -#define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1 -#define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0 -#define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1 -#define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2 -#define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0 -#define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0 -#define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0 -#define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0 -#define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1 -#define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0 -#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1 -#define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0 -#define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1 -#define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0 -#define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0 -#define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0 -#define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1 -#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1 -#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1 -#define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0 -#define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1 -#define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0 -#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0 -#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0 -#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0 -#define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0 -#define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1 -#define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0 -#define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0 -#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0 -#define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0 -#define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1 -#define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0 -#define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0 -#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0 -#define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0 -#define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1 -#define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1 -#define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1 -#define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0 -#define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0 -#define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0 -#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0 -#define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0 -#define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1 -#define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1 -#define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1 -#define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0 -#define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0 -#define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0 -#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0 -#define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0 -#define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0 -#define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0 -#define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0 -#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2 -#define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0 -#define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0 -#define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0 -#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1 -#define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1 -#define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1 -#define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0 -#define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0 -#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0 -#define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0 -#define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0 -#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0 -#define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0 -#define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1 -#define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0 -#define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0 -#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0 -#define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0 -#define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0 -#define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0 -#define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0 -#define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0 -#define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0 -#define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0 -#define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0 -#define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0 -#define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0 -#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0 -#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1 -#define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0 -#define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0 -#define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1 -#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0 -#define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0 -#define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0 -#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0 -#define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0 -#define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0 -#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0 -#define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0 -#define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0 -#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0 -#define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0 -#define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0 -#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0 -#define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0 -#define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0 -#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0 -#define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0 -#define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0 -#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0 -#define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0 -#define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0 -#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0 -#define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0 -#define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0 -#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0 -#define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0 -#define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0 -#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0 -#define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0 -#define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0 -#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0 -#define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0 -#define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0 -#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0 -#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0 -#define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0 -#define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0 -#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0 -#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0 -#define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0 -#define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0 -#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0 -#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0 -#define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0 -#define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0 -#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0 -#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0 -#define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0 -#define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0 -#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0 -#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0 -#define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0 -#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0 -#define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0 -#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0 -#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0 -#define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0 -#define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0 -#define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0 -#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0 -#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0 -#define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0 -#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1 -#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1 -#define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0 -#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0 -#define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0 -#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0 -#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0 -#define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0 -#define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0 -#define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0 -#define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0 -#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0 -#define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0 -#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0 -#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0 -#define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0 -#define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0 -#define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0 -#define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0 -#define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0 -#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0 -#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0 -#define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0 -#define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0 -#define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0 -#define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0 -#define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0 -#define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0 -#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0 -#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0 -#define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0 -#define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0 -#define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0 -#define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0 -#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0 -#define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0 -#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0 -#define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0 -#define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0 -#define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0 -#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1 -#define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0 -#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0 -#define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0 -#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0 -#define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0 -#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0 -#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2 -#define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0 -#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0 -#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0 -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0 -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0 -#define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0 -#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0 -#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0 -#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0 -#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0 -#define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2 -#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0 -#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0 -#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0 -#define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2 -#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0 -#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0 -#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0 -#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0 -#define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1 -#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0 -#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0 -#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0 -#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0 -#define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1 -#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0 -#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0 -#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0 -#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0 -#define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2 -#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0 -#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0 -#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0 -#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2 -#define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2 -#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0 -#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0 -#define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0 -#define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0 -#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2 -#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0 -#define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2 -#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0 -#define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0 -#define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0 -#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0 -#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0 -#define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2 -#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0 -#define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2 -#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0 -#define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1 -#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0 -#define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1 -#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0 -#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0 -#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0 -#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0 -#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0 -#define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1 -#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0 -#define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0 -#define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2 -#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0 -#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2 -#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0 -#define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2 -#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0 -#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3 -#define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0 -#define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2 -#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0 -#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2 -#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0 -#define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1 -#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2 -#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0 -#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1 -#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0 -#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1 -#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0 -#define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1 -#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3 -#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0 -#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0 -#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1 -#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0 -#define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1 -#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0 -#define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1 -#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1 -#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0 -#define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1 -#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0 -#define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0 -#define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0 -#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1 -#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0 -#define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1 -#define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0 -#define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1 -#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0 -#define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1 -#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0 -#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0 -#define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0 -#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0 -#define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1 -#define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1 -#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0 -#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0 -#define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0 -#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1 -#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1 -#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0 -#define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1 -#define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1 -#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0 -#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0 -#define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1 -#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0 -#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0 -#define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2 -#define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1 -#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1 -#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1 -#define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2 -#define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1 -#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0 -#define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0 -#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1 -#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1 -#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0 -#define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2 -#define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1 -#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0 -#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0 -#define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0 -#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0 -#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1 -#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3 -#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0 -#define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1 -#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0 -#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1 -#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4 -#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1 -#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1 -#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0 -#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1 -#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1 -#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0 -#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0 -#define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1 -#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1 -#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1 -#define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2 -#define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1 -#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1 -#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1 -#define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1 -#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1 -#define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1 -#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0 -#define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0 -#define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1 -#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2 -#define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0 -#define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1 -#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1 -#define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0 -#define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1 -#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0 -#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0 -#define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1 -#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2 -#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0 -#define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1 -#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0 -#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0 -#define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1 -#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3 -#define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1 -#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3 -#define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1 -#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2 -#define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2 -#define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1 -#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0 -#define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2 -#define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2 -#define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1 -#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0 -#define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0 -#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3 -#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2 -#define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1 -#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0 -#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0 -#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3 -#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2 -#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1 -#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0 -#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2 -#define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2 -#define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1 -#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0 -#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2 -#define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2 -#define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1 -#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2 -#define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2 -#define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0 -#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0 -#define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0 -#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2 -#define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2 -#define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0 -#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0 -#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0 -#define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0 -#define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0 -#define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0 -#define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1 -#define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0 -#define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1 -#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1 -#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3 -#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1 -#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3 -#define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1 -#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5 -#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1 -#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0 -#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0 -#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3 -#define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1 -#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4 -#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1 -#define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2 -#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1 -#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3 -#define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1 -#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0 -#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0 -#define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0 -#define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1 -#define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0 -#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1 -#define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3 -#define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1 -#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0 -#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0 -#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0 -#define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0 -#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1 -#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2 -#define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1 -#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0 -#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0 -#define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0 -#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1 -#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2 -#define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1 -#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0 -#define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3 -#define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0 -#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1 -#define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1 -#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0 -#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0 -#define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0 -#define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0 -#define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0 -#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1 -#define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1 -#define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0 -#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0 -#define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0 -#define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2 -#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1 -#define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1 -#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0 -#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0 -#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0 -#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2 -#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4 -#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1 -#define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1 -#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3 -#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0 -#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3 -#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1 -#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1 -#define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0 -#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5 -#define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0 -#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3 -#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0 -#define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1 -#define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0 -#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4 -#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0 -#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2 -#define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1 -#define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0 -#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4 -#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1 -#define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1 -#define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0 -#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0 -#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3 -#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1 -#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1 -#define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0 -#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3 -#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1 -#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1 -#define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0 -#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0 -#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3 -#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1 -#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1 -#define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0 -#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0 -#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3 -#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1 -#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1 -#define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0 -#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0 -#define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0 - -#endif /* __DTS_IMX35_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx35.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx35.dtsi deleted file mode 100644 index f812d586c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx35.dtsi +++ /dev/null @@ -1,401 +0,0 @@ -/* - * Copyright 2012 Steffen Trumtrar, Pengutronix - * - * based on imx27.dtsi - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include "imx35-pinfunc.h" - -/ { - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &spi1; - spi1 = &spi2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - }; - }; - - avic: avic-interrupt-controller@68000000 { - compatible = "fsl,imx35-avic", "fsl,avic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x68000000 0x10000000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&avic>; - ranges; - - L2: l2-cache@30000000 { - compatible = "arm,l210-cache"; - reg = <0x30000000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - aips1: aips@43f00000 { - compatible = "fsl,aips", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x43f00000 0x100000>; - ranges; - - i2c1: i2c@43f80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f80000 0x4000>; - clocks = <&clks 51>; - clock-names = "ipg_per"; - interrupts = <10>; - status = "disabled"; - }; - - i2c3: i2c@43f84000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f84000 0x4000>; - clocks = <&clks 53>; - clock-names = "ipg_per"; - interrupts = <3>; - status = "disabled"; - }; - - uart1: serial@43f90000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - clocks = <&clks 9>, <&clks 70>; - clock-names = "ipg", "per"; - interrupts = <45>; - status = "disabled"; - }; - - uart2: serial@43f94000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x43f94000 0x4000>; - clocks = <&clks 9>, <&clks 71>; - clock-names = "ipg", "per"; - interrupts = <32>; - status = "disabled"; - }; - - i2c2: i2c@43f98000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; - reg = <0x43f98000 0x4000>; - clocks = <&clks 52>; - clock-names = "ipg_per"; - interrupts = <4>; - status = "disabled"; - }; - - ssi1: ssi@43fa0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; - reg = <0x43fa0000 0x4000>; - interrupts = <11>; - clocks = <&clks 68>; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - spi1: cspi@43fa4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-cspi"; - reg = <0x43fa4000 0x4000>; - clocks = <&clks 35 &clks 35>; - clock-names = "ipg", "per"; - interrupts = <14>; - status = "disabled"; - }; - - kpp: kpp@43fa8000 { - compatible = "fsl,imx35-kpp", "fsl,imx21-kpp"; - reg = <0x43fa8000 0x4000>; - interrupts = <24>; - clocks = <&clks 56>; - status = "disabled"; - }; - - iomuxc: iomuxc@43fac000 { - compatible = "fsl,imx35-iomuxc"; - reg = <0x43fac000 0x4000>; - }; - }; - - spba: spba-bus@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x100000>; - ranges; - - uart3: serial@5000c000 { - compatible = "fsl,imx35-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - clocks = <&clks 9>, <&clks 72>; - clock-names = "ipg", "per"; - interrupts = <18>; - status = "disabled"; - }; - - spi2: cspi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx35-cspi"; - reg = <0x50010000 0x4000>; - interrupts = <13>; - clocks = <&clks 36 &clks 36>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - fec: fec@50038000 { - compatible = "fsl,imx35-fec", "fsl,imx27-fec"; - reg = <0x50038000 0x4000>; - clocks = <&clks 46>, <&clks 8>; - clock-names = "ipg", "ahb"; - interrupts = <57>; - status = "disabled"; - }; - }; - - aips2: aips@53f00000 { - compatible = "fsl,aips", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x53f00000 0x100000>; - ranges; - - clks: ccm@53f80000 { - compatible = "fsl,imx35-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; - }; - - gpt: timer@53f90000 { - compatible = "fsl,imx35-gpt", "fsl,imx31-gpt"; - reg = <0x53f90000 0x4000>; - interrupts = <29>; - clocks = <&clks 9>, <&clks 50>; - clock-names = "ipg", "per"; - }; - - gpio3: gpio@53fa4000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fa4000 0x4000>; - interrupts = <56>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - esdhc1: esdhc@53fb4000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <7>; - clocks = <&clks 9>, <&clks 8>, <&clks 43>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: esdhc@53fb8000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb8000 0x4000>; - interrupts = <8>; - clocks = <&clks 9>, <&clks 8>, <&clks 44>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc3: esdhc@53fbc000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fbc000 0x4000>; - interrupts = <9>; - clocks = <&clks 9>, <&clks 8>, <&clks 45>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - audmux: audmux@53fc4000 { - compatible = "fsl,imx35-audmux", "fsl,imx31-audmux"; - reg = <0x53fc4000 0x4000>; - status = "disabled"; - }; - - gpio1: gpio@53fcc000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fcc000 0x4000>; - interrupts = <52>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53fd0000 { - compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; - reg = <0x53fd0000 0x4000>; - interrupts = <51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sdma: sdma@53fd4000 { - compatible = "fsl,imx35-sdma"; - reg = <0x53fd4000 0x4000>; - clocks = <&clks 9>, <&clks 65>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - interrupts = <34>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; - }; - - wdog: wdog@53fdc000 { - compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; - reg = <0x53fdc000 0x4000>; - clocks = <&clks 74>; - clock-names = ""; - interrupts = <55>; - }; - - can1: can@53fe4000 { - compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; - reg = <0x53fe4000 0x1000>; - clocks = <&clks 33>, <&clks 33>; - clock-names = "ipg", "per"; - interrupts = <43>; - status = "disabled"; - }; - - can2: can@53fe8000 { - compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan"; - reg = <0x53fe8000 0x1000>; - clocks = <&clks 34>, <&clks 34>; - clock-names = "ipg", "per"; - interrupts = <44>; - status = "disabled"; - }; - - iim@53ff0000 { - compatible = "fsl,imx35-iim"; - reg = <0x53ff0000 0x4000>; - interrupts = <19>; - clocks = <&clks 80>; - }; - - usbotg: usb@53ff4000 { - compatible = "fsl,imx35-usb", "fsl,imx27-usb"; - reg = <0x53ff4000 0x0200>; - interrupts = <37>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbhost1: usb@53ff4400 { - compatible = "fsl,imx35-usb", "fsl,imx27-usb"; - reg = <0x53ff4400 0x0200>; - interrupts = <35>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@53ff4600 { - #index-cells = <1>; - compatible = "fsl,imx35-usbmisc"; - reg = <0x53ff4600 0x00f>; - }; - }; - - emi@80000000 { /* External Memory Interface */ - compatible = "fsl,emi", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x40000000>; - ranges; - - nfc: nand@bb000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx35-nand", "fsl,imx25-nand"; - reg = <0xbb000000 0x2000>; - clocks = <&clks 29>; - clock-names = ""; - interrupts = <33>; - status = "disabled"; - }; - - weim: weim@b8002000 { - #address-cells = <2>; - #size-cells = <1>; - clocks = <&clks 0>; - compatible = "fsl,imx35-weim", "fsl,imx27-weim"; - reg = <0xb8002000 0x1000>; - ranges = < - 0 0 0xa0000000 0x8000000 - 1 0 0xa8000000 0x8000000 - 2 0 0xb0000000 0x2000000 - 3 0 0xb2000000 0x2000000 - 4 0 0xb4000000 0x2000000 - 5 0 0xb6000000 0x2000000 - >; - status = "disabled"; - }; - }; - }; - - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy@0 { - reg = <0>; - compatible = "usb-nop-xceiv"; - }; - - usbphy1: usb-phy@1 { - reg = <1>; - compatible = "usb-nop-xceiv"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx50-evk.dts b/software/linux/kernel/arch/arm/boot/dts/imx50-evk.dts deleted file mode 100644 index 27d763c7a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx50-evk.dts +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2013 Greg Ungerer - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx50.dtsi" - -/ { - model = "Freescale i.MX50 Evaluation Kit"; - compatible = "fsl,imx50-evk", "fsl,imx50"; - - memory { - reg = <0x70000000 0x80000000>; - }; -}; - -&cspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi>; - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>; - status = "okay"; - - flash: m25p32@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p32", "jedec,spi-nor"; - spi-max-frequency = <25000000>; - reg = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "kernel"; - reg = <0x100000 0x300000>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 12 0>; - status = "okay"; -}; - -&iomuxc { - imx50-evk { - pinctrl_cspi: cspigrp { - fsl,pins = < - MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 - MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 - MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 - MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 - MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX50_PAD_SSI_RXFS__FEC_MDC 0x80 - MX50_PAD_SSI_RXC__FEC_MDIO 0x80 - MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 - MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 - MX50_PAD_DISP_D2__FEC_RX_DV 0x80 - MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 - MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 - MX50_PAD_DISP_D5__FEC_TX_EN 0x80 - MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 - MX50_PAD_DISP_D7__FEC_TDATA_0 0x80 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 - MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 - MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 - MX50_PAD_UART1_CTS__UART1_CTS 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbh2 { - status = "okay"; -}; - -&usbh3 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx50-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx50-pinfunc.h deleted file mode 100644 index 97e6e7f4e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx50-pinfunc.h +++ /dev/null @@ -1,923 +0,0 @@ -/* - * Copyright 2013 Greg Ungerer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX50_PINFUNC_H -#define __DTS_IMX50_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL2__KPP_COL_1 0x030 0x2dc 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 -#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 -#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 -#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 -#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL3__KPP_COL_2 0x038 0x2e4 0x000 0x0 0x0 -#define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 -#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 -#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 -#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0 -#define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0 -#define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0 -#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0 -#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0 -#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0 -#define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0 -#define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0 -#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0 -#define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0 -#define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0 -#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1 -#define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0 -#define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0 -#define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0 -#define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0 -#define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0 -#define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1 -#define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0 -#define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0 -#define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0 -#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0 -#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0 -#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0 -#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0 -#define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0 -#define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0 -#define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0 -#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0 -#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0 -#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0 -#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0 -#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0 -#define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0 -#define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0 -#define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1 -#define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0 -#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0 -#define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0 -#define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0 -#define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0 -#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0 -#define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0 -#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0 -#define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0 -#define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0 -#define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0 -#define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0 -#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0 -#define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0 -#define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0 -#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0 -#define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0 -#define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0 -#define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0 -#define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0 -#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0 -#define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0 -#define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0 -#define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0 -#define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0 -#define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0 -#define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0 -#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0 -#define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0 -#define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0 -#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0 -#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0 -#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0 -#define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0 -#define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0 -#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0 -#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0 -#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0 -#define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0 -#define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0 -#define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0 -#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0 -#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0 -#define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0 -#define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1 -#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0 -#define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0 -#define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0 -#define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1 -#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0 -#define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0 -#define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0 -#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0 -#define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1 -#define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0 -#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0 -#define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0 -#define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0 -#define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2 -#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0 -#define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0 -#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0 -#define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3 -#define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0 -#define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3 -#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0 -#define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0 -#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0 -#define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2 -#define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0 -#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0 -#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1 -#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0 -#define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3 -#define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0 -#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0 -#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1 -#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0 -#define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0 -#define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0 -#define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1 -#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1 -#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0 -#define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2 -#define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0 -#define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1 -#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1 -#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0 -#define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0 -#define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0 -#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0 -#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0 -#define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0 -#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0 -#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0 -#define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1 -#define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0 -#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0 -#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0 -#define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0 -#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0 -#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0 -#define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0 -#define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0 -#define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0 -#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0 -#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0 -#define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0 -#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0 -#define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1 -#define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0 -#define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1 -#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0 -#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0 -#define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0 -#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0 -#define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0 -#define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0 -#define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0 -#define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0 -#define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0 -#define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0 -#define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0 -#define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1 -#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2 -#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0 -#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1 -#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0 -#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0 -#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1 -#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0 -#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0 -#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0 -#define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1 -#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0 -#define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0 -#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0 -#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0 -#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0 -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0 -#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1 -#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1 -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0 -#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1 -#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4 -#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0 -#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1 -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0 -#define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0 -#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0 -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0 -#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5 -#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0 -#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0 -#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1 -#define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0 -#define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0 -#define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0 -#define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0 -#define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0 -#define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0 -#define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0 -#define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0 -#define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0 -#define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0 -#define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0 -#define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0 -#define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0 -#define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0 -#define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0 -#define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0 -#define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0 -#define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0 -#define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0 -#define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0 -#define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0 -#define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0 -#define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0 -#define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0 -#define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0 -#define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0 -#define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0 -#define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0 -#define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0 -#define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0 -#define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0 -#define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0 -#define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0 -#define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0 -#define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0 -#define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0 -#define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0 -#define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0 -#define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0 -#define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0 -#define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0 -#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0 -#define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0 -#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0 -#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0 -#define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0 -#define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0 -#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0 -#define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0 -#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0 -#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0 -#define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0 -#define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0 -#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0 -#define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0 -#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0 -#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0 -#define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0 -#define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0 -#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0 -#define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0 -#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0 -#define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0 -#define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1 -#define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0 -#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0 -#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0 -#define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0 -#define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1 -#define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0 -#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0 -#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0 -#define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0 -#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0 -#define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0 -#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0 -#define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0 -#define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0 -#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0 -#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0 -#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0 -#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0 -#define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0 -#define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0 -#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0 -#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0 -#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0 -#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0 -#define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0 -#define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0 -#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0 -#define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1 -#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0 -#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0 -#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0 -#define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0 -#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0 -#define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0 -#define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0 -#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0 -#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0 -#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0 -#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0 -#define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0 -#define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0 -#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0 -#define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1 -#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0 -#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0 -#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0 -#define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0 -#define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0 -#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0 -#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0 -#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0 -#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0 -#define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0 -#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0 -#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0 -#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0 -#define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0 -#define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0 -#define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0 -#define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0 -#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0 -#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0 -#define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0 -#define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0 -#define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0 -#define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1 -#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0 -#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0 -#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0 -#define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0 -#define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0 -#define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1 -#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0 -#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0 -#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0 -#define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0 -#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2 -#define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0 -#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0 -#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0 -#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0 -#define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0 -#define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0 -#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0 -#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0 -#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0 -#define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0 -#define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0 -#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0 -#define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0 -#define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0 -#define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0 -#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0 -#define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0 -#define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0 -#define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0 -#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0 -#define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0 -#define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1 -#define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0 -#define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0 -#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0 -#define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0 -#define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0 -#define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0 -#define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0 -#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0 -#define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0 -#define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1 -#define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0 -#define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0 -#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0 -#define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0 -#define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0 -#define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0 -#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0 -#define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0 -#define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0 -#define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0 -#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0 -#define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0 -#define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0 -#define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0 -#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0 -#define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0 -#define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0 -#define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0 -#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0 -#define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0 -#define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0 -#define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0 -#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0 -#define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0 -#define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0 -#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0 -#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0 -#define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0 -#define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0 -#define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0 -#define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2 -#define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1 -#define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1 -#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0 -#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0 -#define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0 -#define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0 -#define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0 -#define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2 -#define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1 -#define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1 -#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0 -#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0 -#define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0 -#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0 -#define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0 -#define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0 -#define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1 -#define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1 -#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0 -#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0 -#define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0 -#define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1 -#define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1 -#define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1 -#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0 -#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0 -#define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0 -#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0 -#define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0 -#define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1 -#define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1 -#define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1 -#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0 -#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0 -#define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0 -#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0 -#define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0 -#define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1 -#define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1 -#define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0 -#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0 -#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0 -#define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0 -#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1 -#define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0 -#define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0 -#define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1 -#define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0 -#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0 -#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0 -#define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0 -#define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1 -#define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0 -#define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0 -#define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1 -#define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0 -#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1 -#define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1 -#define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1 -#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2 -#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1 -#define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3 -#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1 -#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1 -#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1 -#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1 -#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2 -#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2 -#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2 -#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2 -#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1 -#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1 -#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1 -#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0 -#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0 -#define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0 -#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1 -#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0 -#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0 -#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0 -#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0 -#define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0 -#define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0 -#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0 -#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0 -#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0 -#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0 -#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0 -#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1 -#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1 -#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0 -#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1 -#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1 -#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1 -#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1 -#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1 -#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1 -#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0 -#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1 -#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0 -#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1 -#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0 -#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0 -#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0 -#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0 -#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1 -#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0 -#define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0 -#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1 -#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1 -#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0 -#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1 -#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1 -#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1 -#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0 -#define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0 -#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1 -#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2 -#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2 -#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2 -#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2 -#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2 -#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2 -#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2 -#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2 -#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0 -#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2 -#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0 -#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0 -#define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0 -#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2 -#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0 -#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0 -#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0 -#define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0 -#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0 -#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0 -#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0 -#define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0 -#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0 -#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0 -#define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0 -#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0 -#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0 -#define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0 -#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0 -#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0 -#define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0 -#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0 -#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0 -#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0 -#define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0 -#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0 -#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0 -#define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0 -#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0 -#define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0 -#define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0 -#define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0 -#define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0 -#define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0 -#define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0 -#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0 -#define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0 -#define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0 -#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0 -#define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0 - -#endif /* __DTS_IMX50_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx50.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx50.dtsi deleted file mode 100644 index 8fe8beeb6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx50.dtsi +++ /dev/null @@ -1,502 +0,0 @@ -/* - * Copyright 2013 Greg Ungerer - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" -#include "imx50-pinfunc.h" -#include - -/ { - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - - tzic: tz-interrupt-controller@0fffc000 { - compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x0fffc000 0x4000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22579200>; - }; - - ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - aips@50000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x10000000>; - ranges; - - spba@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - esdhc1: esdhc@50004000 { - compatible = "fsl,imx50-esdhc"; - reg = <0x50004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc2: esdhc@50008000 { - compatible = "fsl,imx50-esdhc"; - reg = <0x50008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi1: ecspi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; - reg = <0x50010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx50-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: esdhc@50020000 { - compatible = "fsl,imx50-esdhc"; - reg = <0x50020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: esdhc@50024000 { - compatible = "fsl,imx50-esdhc"; - reg = <0x50024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - usbotg: usb@53f80000 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; - status = "disabled"; - }; - - usbh1: usb@53f80200 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@53f80400 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@53f80600 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - - gpio1: gpio@53f84000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 151 28>; - }; - - gpio2: gpio@53f88000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>, - <&iomuxc 16 83 1>, <&iomuxc 17 85 1>, - <&iomuxc 18 87 1>, <&iomuxc 19 84 1>, - <&iomuxc 20 88 1>, <&iomuxc 21 86 1>; - }; - - gpio3: gpio@53f8c000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 108 32>; - }; - - gpio4: gpio@53f90000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>, - <&iomuxc 20 140 11>; - }; - - wdog1: wdog@53f98000 { - compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; - reg = <0x53f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - gpt: timer@53fa0000 { - compatible = "fsl,imx50-gpt", "fsl,imx31-gpt"; - reg = <0x53fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx50-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; - }; - - pwm1: pwm@53fb4000 { - #pwm-cells = <2>; - compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; - reg = <0x53fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@53fb8000 { - #pwm-cells = <2>; - compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; - reg = <0x53fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@53fbc000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@53fc0000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - src: src@53fd0000 { - compatible = "fsl,imx50-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - #reset-cells = <1>; - }; - - clks: ccm@53fd4000{ - compatible = "fsl,imx50-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - - gpio5: gpio@53fdc000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53fdc000 0x4000>; - interrupts = <103 104>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>; - }; - - gpio6: gpio@53fe0000 { - compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; - reg = <0x53fe0000 0x4000>; - interrupts = <105 106>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>; - }; - - i2c3: i2c@53fec000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x53fec000 0x4000>; - interrupts = <64>; - clocks = <&clks IMX5_CLK_I2C3_GATE>; - status = "disabled"; - }; - - uart4: serial@53ff0000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x53ff0000 0x4000>; - interrupts = <13>; - clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - - aips@60000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x60000000 0x10000000>; - ranges; - - uart5: serial@63f90000 { - compatible = "fsl,imx50-uart", "fsl,imx21-uart"; - reg = <0x63f90000 0x4000>; - interrupts = <86>; - clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - owire: owire@63fa4000 { - compatible = "fsl,imx50-owire", "fsl,imx21-owire"; - reg = <0x63fa4000 0x4000>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: ecspi@63fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; - reg = <0x63fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: sdma@63fb0000 { - compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; - reg = <0x63fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; - clock-names = "ipg", "ahb"; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; - }; - - cspi: cspi@63fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; - reg = <0x63fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@63fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x63fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@63fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx50-i2c", "fsl,imx21-i2c"; - reg = <0x63fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@63fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@63fd0000 { - compatible = "fsl,imx50-audmux", "fsl,imx31-audmux"; - reg = <0x63fd0000 0x4000>; - status = "disabled"; - }; - - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-apf51.dts b/software/linux/kernel/arch/arm/boot/dts/imx51-apf51.dts deleted file mode 100644 index e88b2a6be..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-apf51.dts +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2012 Armadeus Systems - - * Copyright 2012 Laurent Cans - * - * Based on mx51-babbage.dts - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Armadeus Systems APF51 module"; - compatible = "armadeus,imx51-apf51", "fsl,imx51"; - - memory { - reg = <0x90000000 0x20000000>; - }; - - clocks { - osc { - clock-frequency = <33554432>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&iomuxc { - imx51-apf51 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-apf51dev.dts b/software/linux/kernel/arch/arm/boot/dts/imx51-apf51dev.dts deleted file mode 100644 index 0f3fe29b8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-apf51dev.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright 2013 Armadeus Systems - - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* APF51Dev is a docking board for the APF51 SOM */ -#include "imx51-apf51.dts" - -/ { - model = "Armadeus Systems APF51Dev docking/development board"; - compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; - - backlight@bl1{ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - compatible = "gpio-backlight"; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - default-on; - }; - - display@di1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - display-timings { - lw700 { - native-mode; - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - port { - display_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - user-key { - label = "user"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - linux,code = <256>; /* BTN_0 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - user { - label = "Heartbeat"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>, - <&gpio3 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx51-apf51dev { - pinctrl_backlight: bl1grp { - fsl,pins = < - MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 - MX51_PAD_EIM_EB3__GPIO2_23 0x0C5 - MX51_PAD_EIM_CS4__GPIO2_29 0x100 - MX51_PAD_NANDF_D13__GPIO3_27 0x0C5 - MX51_PAD_NANDF_D12__GPIO3_28 0x0C5 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5 - MX51_PAD_GPIO1_2__GPIO1_2 0x0C5 - MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 - MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 - MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed - MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - >; - }; - }; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display_in>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-babbage.dts b/software/linux/kernel/arch/arm/boot/dts/imx51-babbage.dts deleted file mode 100644 index f097b4f29..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-babbage.dts +++ /dev/null @@ -1,655 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Freescale i.MX51 Babbage Board"; - compatible = "fsl,imx51-babbage", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x90000000 0x20000000>; - }; - - clocks { - ckih1 { - clock-frequency = <22579200>; - }; - - clk_26M: codec_clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; - }; - - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - display-timings { - native-mode = <&timing0>; - timing0: dvi { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - }; - - display1: display@di1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb565"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp2>; - status = "disabled"; - display-timings { - native-mode = <&timing1>; - timing1: claawvga { - clock-frequency = <27000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <60>; - vback-porch = <10>; - vfront-porch = <10>; - hsync-len = <20>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-diagnostic { - label = "diagnostic"; - gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_hub_reset: regulator@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgreg>; - reg = <0>; - regulator-name = "hub_reset"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx51-babbage-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx51-babbage-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; - - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbh1phy: usbh1phy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_DUMMY>; - clock-names = "main_clk"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - pmic: mc13892@0 { - compatible = "fsl,mc13892"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - spi-max-frequency = <6000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-rtc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; - }; - - flash: at45db321d@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0x3c0000>; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clkcodec>; - reg = <0x0a>; - clocks = <&clk_26M>; - VDDA-supply = <&vdig_reg>; - VDDIO-supply = <&vvideo_reg>; - }; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 3, KEY_HOME) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_ENTER) - MATRIX_KEY(1, 3, KEY_VOLUMEUP) - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(2, 1, KEY_F8) - MATRIX_KEY(2, 2, KEY_F9) - MATRIX_KEY(2, 3, KEY_F10) - MATRIX_KEY(3, 0, KEY_F1) - MATRIX_KEY(3, 1, KEY_F2) - MATRIX_KEY(3, 2, KEY_F3) - MATRIX_KEY(3, 3, KEY_POWER) - >; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_hub_reset>; - fsl,usbphy = <&usbh1phy>; - phy_type = "ulpi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - disable-over-current; - phy_type = "utmi_wide"; - status = "okay"; -}; - -&iomuxc { - imx51-babbage { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 - >; - }; - - pinctrl_clkcodec: clkcodecgrp { - fsl,pins = < - MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_GPIO1_0__GPIO1_0 0x100 - MX51_PAD_GPIO1_1__GPIO1_1 0x100 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ - MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 - MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 - MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 - MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 - MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 - MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 - MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX51_PAD_EIM_A27__GPIO2_21 0x5 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX51_PAD_EIM_D22__GPIO2_6 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed - MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - >; - }; - - pinctrl_ipu_disp2: ipudisp2grp { - fsl,pins = < - MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 - MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 - MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 - MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 - MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 - MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 - MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 - MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 - MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 - MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 - MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 - MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 - MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 - MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 - MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 - MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 - MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 - MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - MX51_PAD_DI_GP4__DI2_PIN15 0x5 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 - MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 - MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 - MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 - MX51_PAD_KEY_COL0__KEY_COL0 0xe8 - MX51_PAD_KEY_COL1__KEY_COL1 0xe8 - MX51_PAD_KEY_COL2__KEY_COL2 0xe8 - MX51_PAD_KEY_COL3__KEY_COL3 0xe8 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - MX51_PAD_EIM_D27__UART3_RTS 0x1c5 - MX51_PAD_EIM_D24__UART3_CTS 0x1c5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 - >; - }; - - pinctrl_usbh1reg: usbh1reggrp { - fsl,pins = < - MX51_PAD_EIM_D21__GPIO2_5 0x85 - >; - }; - - pinctrl_usbotgreg: usbotgreggrp { - fsl,pins = < - MX51_PAD_GPIO1_7__GPIO1_7 0x85 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/software/linux/kernel/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts deleted file mode 100644 index 1db517d3d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2014 Alexander Shiyan - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx51-digi-connectcore-som.dtsi" - -/ { - model = "Digi ConnectCore CC(W)-MX51 JSK"; - compatible = "digi,connectcore-ccxmx51-jsk", - "digi,connectcore-ccxmx51-som", "fsl,imx51"; - - chosen { - linux,stdout-path = &uart1; - }; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - dr_mode = "host"; - phy_type = "ulpi"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - imx51-digi-connectcore-jsk { - pinctrl_owire: owiregrp { - fsl,pins = < - MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi deleted file mode 100644 index 16fc69c69..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright (C) 2014 Alexander Shiyan - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Digi ConnectCore CC(W)-MX51"; - compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; - - memory { - reg = <0x90000000 0x08000000>; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pmic: mc13892@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mc13892>; - compatible = "fsl,mc13892"; - spi-max-frequency = <16000000>; - spi-cs-high; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-rtc; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { }; - - viohi_reg: viohi { - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - regulator-always-on; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vusb_reg: vusb { - regulator-always-on; - }; - - gpo1_reg: gpo1 { }; - - gpo2_reg: gpo2 { }; - - gpo3_reg: gpo3 { }; - - gpo4_reg: gpo4 { }; - - pwgt2spi_reg: pwgt2spi { - regulator-always-on; - }; - - vcoincell_reg: vcoincell { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - }; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cap-sdio-irq; - wakeup-source; - keep-power-in-suspend; - max-frequency = <50000000>; - no-1-8-v; - non-removable; - vmmc-supply = <&gpo4_reg>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-supply = <&gpo3_reg>; - /* Pins shared with LCD2, keep status disabled */ -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; - - mma7455l@1d { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mma7455l>; - compatible = "fsl,mma7455l"; - reg = <0x1d>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi_wide"; - disable-over-current; - /* Device role is not known, keep status disabled */ -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - lan9221: lan9221@5,0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lan9221>; - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <5 0x00000000 0x1000>; - fsl,weim-cs-timing = < - 0x00420081 0x00000000 - 0x32260000 0x00000000 - 0x72080f00 0x00000000 - >; - clocks = <&clks IMX5_CLK_DUMMY>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - phy-mode = "mii"; - reg-io-width = <2>; - smsc,irq-push-pull; - vdd33a-supply = <&gpo2_reg>; - vddvario-supply = <&gpo2_reg>; - }; -}; - -&iomuxc { - imx51-digi-connectcore-som { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed - MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 - MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 - MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 - MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 - MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 - MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 - MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 - MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 - MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 - MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 - MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 - MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 - MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 - MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 - MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 - >; - }; - - pinctrl_lan9221: lan9221grp { - fsl,pins = < - MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ - >; - }; - - pinctrl_mc13892: mc13892grp { - fsl,pins = < - MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ - >; - }; - - pinctrl_mma7455l: mma7455lgrp { - fsl,pins = < - MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ - MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 - MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 - MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 - MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 - MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 - MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 - MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 - MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 - MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 - MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 - MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 - MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 - MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 - MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 - MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 - MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 - MX51_PAD_EIM_A16__EIM_A16 0x80000000 - MX51_PAD_EIM_A17__EIM_A17 0x80000000 - MX51_PAD_EIM_A18__EIM_A18 0x80000000 - MX51_PAD_EIM_A19__EIM_A19 0x80000000 - MX51_PAD_EIM_A20__EIM_A20 0x80000000 - MX51_PAD_EIM_A21__EIM_A21 0x80000000 - MX51_PAD_EIM_A22__EIM_A22 0x80000000 - MX51_PAD_EIM_A23__EIM_A23 0x80000000 - MX51_PAD_EIM_A24__EIM_A24 0x80000000 - MX51_PAD_EIM_A25__EIM_A25 0x80000000 - MX51_PAD_EIM_A26__EIM_A26 0x80000000 - MX51_PAD_EIM_A27__EIM_A27 0x80000000 - MX51_PAD_EIM_D16__EIM_D16 0x80000000 - MX51_PAD_EIM_D17__EIM_D17 0x80000000 - MX51_PAD_EIM_D18__EIM_D18 0x80000000 - MX51_PAD_EIM_D19__EIM_D19 0x80000000 - MX51_PAD_EIM_D20__EIM_D20 0x80000000 - MX51_PAD_EIM_D21__EIM_D21 0x80000000 - MX51_PAD_EIM_D22__EIM_D22 0x80000000 - MX51_PAD_EIM_D23__EIM_D23 0x80000000 - MX51_PAD_EIM_D24__EIM_D24 0x80000000 - MX51_PAD_EIM_D25__EIM_D25 0x80000000 - MX51_PAD_EIM_D26__EIM_D26 0x80000000 - MX51_PAD_EIM_D27__EIM_D27 0x80000000 - MX51_PAD_EIM_D28__EIM_D28 0x80000000 - MX51_PAD_EIM_D29__EIM_D29 0x80000000 - MX51_PAD_EIM_D30__EIM_D30 0x80000000 - MX51_PAD_EIM_D31__EIM_D31 0x80000000 - MX51_PAD_EIM_OE__EIM_OE 0x80000000 - MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 - MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 - MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi deleted file mode 100644 index 63164266a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include "imx51.dtsi" - -/ { - model = "Eukrea CPUIMX51"; - compatible = "eukrea,cpuimx51", "fsl,imx51"; - - memory { - reg = <0x90000000 0x10000000>; /* 256M */ - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsc2007: tsc2007@49 { - compatible = "ti,tsc2007"; - gpios = <&gpio4 0 1>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 0x8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007_1>; - reg = <0x49>; - ti,x-plate-ohms = <180>; - }; -}; - -&iomuxc { - imx51-eukrea { - pinctrl_tsc2007_1: tsc2007grp-1 { - fsl,pins = < - MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5 - MX51_PAD_NANDF_D8__GPIO4_0 0x1f5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed - MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed - >; - }; - }; -}; - -&nfc { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts deleted file mode 100644 index 728212861..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -/dts-v1/; -#include "imx51-eukrea-cpuimx51.dtsi" -#include - -/ { - model = "Eukrea CPUIMX51"; - compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; - - clocks { - clk24M: can_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys_1>; - - button-1 { - label = "BP1"; - gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - linux,code = <256>; - wakeup-source; - linux,input-type = <1>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioled>; - - led1 { - label = "led1"; - gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_can: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "CAN_RST"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <20000>; - enable-active-high; - }; - }; - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx51-eukrea-tlv320aic23"; - ssi-controller = <&ssi2>; - fsl,mux-int-port = <2>; - fsl,mux-ext-port = <3>; - }; - - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbh1phy: usbh1phy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - status = "okay"; - - can0: can@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can>; - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk24M>; - spi-max-frequency = <10000000>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <®_can>; - }; -}; - -&i2c1 { - tlv320aic23: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; -}; - -&iomuxc { - imx51-eukrea { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 - >; - }; - - - pinctrl_can: cangrp { - fsl,pins = < - MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ - MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - - pinctrl_uart3_rtscts: uart3rtsctsgrp { - fsl,pins = < - MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 - MX51_PAD_KEY_COL5__UART3_CTS 0x1c5 - >; - }; - - pinctrl_backlight_1: backlightgrp-1 { - fsl,pins = < - MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5 - >; - }; - - pinctrl_esdhc1_cd: esdhc1_cd { - fsl,pins = < - MX51_PAD_GPIO1_0__GPIO1_0 0xd5 - >; - }; - - pinctrl_gpiokeys_1: gpiokeysgrp-1 { - fsl,pins = < - MX51_PAD_NANDF_D9__GPIO3_31 0x1f5 - >; - }; - - pinctrl_gpioled: gpioledgrp-1 { - fsl,pins = < - MX51_PAD_NANDF_D10__GPIO3_30 0x80000000 - >; - }; - - pinctrl_reg_lcd_3v3: reg_lcd_3v3 { - fsl,pins = < - MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 - MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 - MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 - MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 - MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 - MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 - MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 - MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 - MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 - MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 - MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 - MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 - >; - }; - }; -}; - -&ssi2 { - codec-handle = <&tlv320aic23>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - fsl,usbphy = <&usbh1phy>; - dr_mode = "host"; - phy_type = "ulpi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - phy_type = "utmi_wide"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx51-pinfunc.h deleted file mode 100644 index 82eae3c8a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-pinfunc.h +++ /dev/null @@ -1,772 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX51_PINFUNC_H -#define __DTS_IMX51_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 -#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 -#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 -#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 -#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 -#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 -#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 -#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 -#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 -#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 -#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0 -#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0 -#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0 -#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0 -#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0 -#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0 -#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0 -#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1 -#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0 -#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0 -#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0 -#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0 -#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0 -#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0 -#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1 -#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0 -#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0 -#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0 -#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0 -#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0 -#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0 -#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0 -#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0 -#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0 -#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0 -#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0 -#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0 -#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0 -#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0 -#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0 -#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0 -#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0 -#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0 -#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0 -#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0 -#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0 -#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0 -#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0 -#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0 -#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0 -#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0 -#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0 -#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0 -#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0 -#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0 -#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0 -#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0 -#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3 -#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0 -#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0 -#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0 -#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0 -#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0 -#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3 -#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0 -#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0 -#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0 -#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0 -#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0 -#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0 -#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0 -#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0 -#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0 -#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0 -#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0 -#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0 -#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0 -#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0 -#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0 -#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0 -#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0 -#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0 -#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0 -#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0 -#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0 -#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0 -#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0 -#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0 -#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0 -#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0 -#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0 -#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0 -#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0 -#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0 -#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0 -#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0 -#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0 -#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0 -#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0 -#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0 -#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0 -#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0 -#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0 -#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0 -#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0 -#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0 -#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0 -#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0 -#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0 -#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0 -#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0 -#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0 -#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0 -#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0 -#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0 -#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0 -#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0 -#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0 -#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0 -#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0 -#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0 -#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0 -#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0 -#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0 -#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0 -#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1 -#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0 -#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1 -#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0 -#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1 -#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0 -#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1 -#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0 -#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0 -#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0 -#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0 -#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0 -#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0 -#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0 -#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0 -#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0 -#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0 -#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0 -#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0 -#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0 -#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0 -#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0 -#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0 -#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0 -#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0 -#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0 -#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0 -#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0 -#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0 -#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0 -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0 -#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0 -#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0 -#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0 -#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0 -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0 -#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0 -#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0 -#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0 -#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0 -#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0 -#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0 -#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0 -#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0 -#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0 -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0 -#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1 -#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0 -#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1 -#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1 -#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0 -#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1 -#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1 -#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0 -#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0 -#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0 -#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0 -#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0 -#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0 -#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0 -#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0 -#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1 -#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0 -#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0 -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0 -#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0 -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0 -#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0 -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0 -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0 -#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0 -#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0 -#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0 -#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0 -#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2 -#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0 -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1 -#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1 -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1 -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1 -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1 -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1 -#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0 -#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0 -#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0 -#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0 -#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0 -#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0 -#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0 -#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0 -#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0 -#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0 -#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0 -#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2 -#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0 -#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0 -#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0 -#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0 -#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0 -#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0 -#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4 -#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0 -#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0 -#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0 -#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0 -#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0 -#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0 -#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0 -#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0 -#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0 -#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0 -#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1 -#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0 -#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0 -#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4 -#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1 -#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0 -#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0 -#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1 -#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0 -#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2 -#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1 -#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2 -#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0 -#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0 -#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6 -#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0 -#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0 -#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0 -#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0 -#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4 -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5 -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0 -#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1 -#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1 -#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0 -#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0 -#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1 -#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1 -#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0 -#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1 -#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0 -#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0 -#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0 -#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1 -#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1 -#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0 -#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1 -#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1 -#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1 -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0 -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0 -#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1 -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0 -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0 -#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1 -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0 -#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0 -#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0 -#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0 -#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1 -#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1 -#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0 -#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0 -#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1 -#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1 -#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0 -#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1 -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0 -#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1 -#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0 -#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1 -#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0 -#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1 -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1 -#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1 -#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8 -#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1 -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1 -#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1 -#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1 -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1 -#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1 -#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1 -#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1 -#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1 -#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1 -#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1 -#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1 -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1 -#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1 -#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1 -#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1 -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1 -#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0 -#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1 -#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1 -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1 -#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1 -#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1 -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1 -#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1 -#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1 -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1 -#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1 -#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1 -#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1 -#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1 -#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2 -#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0 -#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1 -#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2 -#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2 -#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1 -#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2 -#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2 -#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2 -#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1 -#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0 -#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2 -#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3 -#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2 -#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0 -#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3 -#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2 -#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3 -#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0 -#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0 -#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1 -#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0 -#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3 -#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1 -#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3 -#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1 -#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0 -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0 -#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1 -#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1 -#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0 -#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2 -#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0 -#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0 - -#endif /* __DTS_IMX51_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51-ts4800.dts b/software/linux/kernel/arch/arm/boot/dts/imx51-ts4800.dts deleted file mode 100644 index ca1cc5eca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51-ts4800.dts +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright 2015 Savoir-faire Linux - * - * This device tree is based on imx51-babbage.dts - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -/dts-v1/; -#include "imx51.dtsi" - -/ { - model = "Technologic Systems TS-4800"; - compatible = "technologic,imx51-ts4800", "fsl,imx51"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x90000000 0x10000000>; - }; - - clocks { - ckih1 { - clock-frequency = <22579200>; - }; - - ckih2 { - clock-frequency = <24576000>; - }; - }; - - backlight_reg: regulator-backlight { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enable_lcd>; - regulator-name = "enable_lcd_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 78770>; - brightness-levels = <0 150 200 255>; - default-brightness-level = <1>; - power-supply = <&backlight_reg>; - }; - - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <30066000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <50>; - hback-porch = <70>; - hsync-len = <50>; - vback-porch = <0>; - vfront-porch = <0>; - vsync-len = <50>; - }; - }; - - port@0 { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - rtc: m41t00@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_backlight>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim>; - status = "okay"; - - fpga@0 { - compatible = "simple-bus"; - fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000 - 0x00000000 0x1c092480 0x00000000>; - reg = <0 0x0000000 0x1d000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x1d000>; - - syscon: syscon@b0010000 { - compatible = "syscon", "simple-mfd"; - reg = <0x10000 0x3d>; - reg-io-width = <2>; - - wdt@e { - compatible = "technologic,ts4800-wdt"; - syscon = <&syscon 0xe>; - }; - }; - - touchscreen { - compatible = "technologic,ts4800-ts"; - reg = <0x12000 0x1000>; - syscon = <&syscon 0x10 6>; - }; - - fpga_irqc: fpga-irqc@15000 { - compatible = "technologic,ts4800-irqc"; - reg = <0x15000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_interrupt_fpga>; - interrupt-parent = <&gpio2>; - interrupts= <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - can@1a000 { - compatible = "technologic,sja1000"; - reg = <0x1a000 0x100>; - interrupt-parent = <&fpga_irqc>; - interrupts = <1>; - reg-io-width = <2>; - nxp,tx-output-config = <0x06>; - nxp,external-clock-frequency = <24000000>; - }; - }; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ - >; - }; - - pinctrl_enable_lcd: enablelcdgrp { - fsl,pins = < - MX51_PAD_CSI2_D12__GPIO4_9 0x1c5 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - MX51_PAD_GPIO1_0__GPIO1_0 0x100 - MX51_PAD_GPIO1_1__GPIO1_1 0x100 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 - MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 - MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 - MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4 - MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_interrupt_fpga: fpgaicgrp { - fsl,pins = < - MX51_PAD_EIM_D27__GPIO2_9 0xe5 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - MX51_PAD_DI_GP4__DI2_PIN15 0x5 - >; - }; - - pinctrl_pwm_backlight: backlightgrp { - fsl,pins = < - MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - >; - }; - - pinctrl_weim: weimgrp { - fsl,pins = < - MX51_PAD_EIM_DTACK__EIM_DTACK 0x85 - MX51_PAD_EIM_CS0__EIM_CS0 0x0 - MX51_PAD_EIM_CS1__EIM_CS1 0x0 - MX51_PAD_EIM_EB0__EIM_EB0 0x85 - MX51_PAD_EIM_EB1__EIM_EB1 0x85 - MX51_PAD_EIM_OE__EIM_OE 0x85 - MX51_PAD_EIM_LBA__EIM_LBA 0x85 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx51.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx51.dtsi deleted file mode 100644 index f46fe9bf0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx51.dtsi +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" -#include "imx51-pinfunc.h" -#include -#include -#include -#include - -/ { - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &i2c1; - i2c1 = &i2c2; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - mmc3 = &esdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &cspi; - }; - - tzic: tz-interrupt-controller@e0000000 { - compatible = "fsl,imx51-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xe0000000 0x4000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - clock-latency = <62500>; - clocks = <&clks IMX5_CLK_CPU_PODF>; - clock-names = "cpu"; - operating-points = < - 166000 1000000 - 600000 1050000 - 800000 1100000 - >; - voltage-tolerance = <5>; - }; - }; - - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - }; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu_di0>, <&ipu_di1>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - iram: iram@1ffe0000 { - compatible = "mmio-sram"; - reg = <0x1ffe0000 0x20000>; - }; - - ipu: ipu@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ipu"; - reg = <0x40000000 0x20000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu_di0: port@2 { - reg = <2>; - - ipu_di0_disp0: endpoint { - }; - }; - - ipu_di1: port@3 { - reg = <3>; - - ipu_di1_disp1: endpoint { - }; - }; - }; - - aips@70000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x70000000 0x10000000>; - ranges; - - spba@70000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x70000000 0x40000>; - ranges; - - esdhc1: esdhc@70004000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc2: esdhc@70008000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@7000c000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x7000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi1: ecspi@70010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ecspi"; - reg = <0x70010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@70014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x70014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, - <&clks IMX5_CLK_SSI2_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: esdhc@70020000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: esdhc@70024000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - usbotg: usb@73f80000 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbh1: usb@73f80200 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@73f80400 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@73f80600 { - compatible = "fsl,imx51-usb", "fsl,imx27-usb"; - reg = <0x73f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@73f80800 { - #index-cells = <1>; - compatible = "fsl,imx51-usbmisc"; - reg = <0x73f80800 0x200>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - }; - - gpio1: gpio@73f84000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@73f88000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@73f8c000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@73f90000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: kpp@73f94000 { - compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; - reg = <0x73f94000 0x4000>; - interrupts = <60>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: wdog@73f98000 { - compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; - reg = <0x73f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - wdog2: wdog@73f9c000 { - compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; - reg = <0x73f9c000 0x4000>; - interrupts = <59>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - gpt: timer@73fa0000 { - compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; - reg = <0x73fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - iomuxc: iomuxc@73fa8000 { - compatible = "fsl,imx51-iomuxc"; - reg = <0x73fa8000 0x4000>; - }; - - pwm1: pwm@73fb4000 { - #pwm-cells = <2>; - compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; - reg = <0x73fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@73fb8000 { - #pwm-cells = <2>; - compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; - reg = <0x73fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@73fbc000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x73fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@73fc0000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x73fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - src: src@73fd0000 { - compatible = "fsl,imx51-src"; - reg = <0x73fd0000 0x4000>; - #reset-cells = <1>; - }; - - clks: ccm@73fd4000{ - compatible = "fsl,imx51-ccm"; - reg = <0x73fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - }; - - aips@80000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80000000 0x10000000>; - ranges; - - iim: iim@83f98000 { - compatible = "fsl,imx51-iim", "fsl,imx27-iim"; - reg = <0x83f98000 0x4000>; - interrupts = <69>; - clocks = <&clks IMX5_CLK_IIM_GATE>; - }; - - owire: owire@83fa4000 { - compatible = "fsl,imx51-owire", "fsl,imx21-owire"; - reg = <0x83fa4000 0x4000>; - interrupts = <88>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: ecspi@83fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ecspi"; - reg = <0x83fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: sdma@83fb0000 { - compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; - reg = <0x83fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; - }; - - cspi: cspi@83fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; - reg = <0x83fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@83fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; - reg = <0x83fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@83fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; - reg = <0x83fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@83fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x83fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, - <&clks IMX5_CLK_SSI1_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@83fd0000 { - compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; - reg = <0x83fd0000 0x4000>; - clocks = <&clks IMX5_CLK_DUMMY>; - clock-names = "audmux"; - status = "disabled"; - }; - - weim: weim@83fda000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,imx51-weim"; - reg = <0x83fda000 0x1000>; - clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; - ranges = < - 0 0 0xb0000000 0x08000000 - 1 0 0xb8000000 0x08000000 - 2 0 0xc0000000 0x08000000 - 3 0 0xc8000000 0x04000000 - 4 0 0xcc000000 0x02000000 - 5 0 0xce000000 0x02000000 - >; - status = "disabled"; - }; - - nfc: nand@83fdb000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx51-nand"; - reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; - interrupts = <8>; - clocks = <&clks IMX5_CLK_NFC_GATE>; - status = "disabled"; - }; - - pata: pata@83fe0000 { - compatible = "fsl,imx51-pata", "fsl,imx27-pata"; - reg = <0x83fe0000 0x4000>; - interrupts = <70>; - clocks = <&clks IMX5_CLK_PATA_GATE>; - status = "disabled"; - }; - - ssi3: ssi@83fe8000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x83fe8000 0x4000>; - interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, - <&clks IMX5_CLK_SSI3_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 46 0 0>, - <&sdma 47 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - fec: ethernet@83fec000 { - compatible = "fsl,imx51-fec", "fsl,imx27-fec"; - reg = <0x83fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-ard.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-ard.dts deleted file mode 100644 index 4486bc47d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-ard.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53.dtsi" - -/ { - model = "Freescale i.MX53 Automotive Reference Design Board"; - compatible = "fsl,imx53-ard", "fsl,imx53"; - - memory { - reg = <0x70000000 0x40000000>; - }; - - eim-cs1@f4000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,eim-bus", "simple-bus"; - reg = <0xf4000000 0x3ff0000>; - ranges; - - lan9220@f4000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0xf4000000 0x2000000>; - phy-mode = "mii"; - interrupt-parent = <&gpio2>; - interrupts = <31 0x8>; - reg-io-width = <4>; - /* - * VDD33A and VDDVARIO of LAN9220 are supplied by - * SW4_3V3 of LTC3589. Before the regulator driver - * for this PMIC is available, we use a fixed dummy - * 3V3 regulator to get LAN9220 driver probing work. - */ - vdd33a-supply = <®_3p3v>; - vddvario-supply = <®_3p3v>; - smsc,irq-push-pull; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - home { - label = "Home"; - gpios = <&gpio5 10 0>; - linux,code = <102>; /* KEY_HOME */ - wakeup-source; - }; - - back { - label = "Back"; - gpios = <&gpio5 11 0>; - linux,code = <158>; /* KEY_BACK */ - wakeup-source; - }; - - program { - label = "Program"; - gpios = <&gpio5 12 0>; - linux,code = <362>; /* KEY_PROGRAM */ - wakeup-source; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio5 13 0>; - linux,code = <115>; /* KEY_VOLUMEUP */ - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 0 0>; - linux,code = <114>; /* KEY_VOLUMEDOWN */ - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-ard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_1__GPIO1_1 0x80000000 - MX53_PAD_GPIO_9__GPIO1_9 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - MX53_PAD_GPIO_10__GPIO4_0 0x80000000 - MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 - MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 - MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 - MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 - MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 - MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 - MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 - MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 - MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 - MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 - MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 - MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 - MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 - MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 - MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 - MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 - MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 - MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 - MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 - MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 - MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 - MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-m53.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx53-m53.dtsi deleted file mode 100644 index d259f57bf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-m53.dtsi +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx53.dtsi" - -/ { - model = "DENX M53"; - compatible = "denx,imx53-m53", "fsl,imx53"; - - memory { - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_backlight: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd-supply"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; - - stmpe610@41 { - compatible = "st,stmpe610"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - id = <0>; - blocks = <0x5>; - interrupts = <6 0x0>; - interrupt-parent = <&gpio7>; - irq-trigger = <0x1>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - reg = <0>; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <3>; - st,touch-det-delay = <3>; - st,settling = <4>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <32>; - }; - - rtc: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-m53evk { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 - MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-m53evk.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-m53evk.dts deleted file mode 100644 index dcee1e0f9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-m53evk.dts +++ /dev/null @@ -1,375 +0,0 @@ -/* - * Copyright (C) 2013 Marek Vasut - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53-m53.dtsi" - -/ { - model = "DENX M53EVK"; - compatible = "denx,imx53-m53evk", "fsl,imx53"; - - display1: display@di1 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1>; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <31500000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <128>; - vback-porch = <33>; - vfront-porch = <9>; - vsync-len = <3>; - vsync-active = <1>; - }; - }; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 3000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_backlight>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio>; - - user1 { - label = "user1"; - gpios = <&gpio2 8 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "user2"; - gpios = <&gpio2 9 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usbh1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 0>; - }; - - reg_usb_otg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 0>; - }; - }; - - sound { - compatible = "fsl,imx53-m53evk-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-m53evk-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Ext Spk", "LINE_OUT"; - mux-int-port = <2>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-m53evk { - pinctrl_usb: usbgrp { - fsl,pins = < - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 - MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX53_PAD_GPIO_4__GPIO1_4 0x000b0 - >; - }; - - led_pin_gpio: led_gpio@0 { - fsl,pins = < - MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 - MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 - MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 - MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 - MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_disp1: ipudisp1grp { - fsl,pins = < - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 - MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 - MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 - MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 - MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - }; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb>; - vbus-supply = <®_usbh1_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - vbus-supply = <®_usb_otg_vbus>; - disable-over-current; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-mba53.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-mba53.dts deleted file mode 100644 index 2e44d2aba..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-mba53.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer , Pengutronix - * Copyright 2012 Steffen Trumtrar , Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53-tqma53.dtsi" - -/ { - model = "TQ MBa53 starter kit"; - compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; - - chosen { - stdout-path = &uart2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; - brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; - default-brightness-level = <10>; - enable-gpios = <&gpio7 7 0>; - power-supply = <®_backlight>; - }; - - disp1: display@disp1 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp1_1>; - interface-pix-fmt = "rgb24"; - status = "disabled"; - - port { - display1_in: endpoint { - remote-endpoint = <&ipu_di1_disp1>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_backlight: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "lcd-supply"; - gpio = <&gpio2 5 0>; - startup-delay-us = <5000>; - }; - - reg_3p2v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - }; - - sound { - compatible = "tq,imx53-mba53-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-mba53-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; -}; - -&ldb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds1_1>; - status = "disabled"; -}; - -&iomuxc { - lvds1 { - pinctrl_lvds1_1: lvds1-grp1 { - fsl,pins = < - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - >; - }; - - pinctrl_lvds1_2: lvds1-grp2 { - fsl,pins = < - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 - >; - }; - }; - - disp1 { - pinctrl_disp1_1: disp1-grp1 { - fsl,pins = < - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ - MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ - MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 - >; - }; - }; - - tve { - pinctrl_vga_sync_1: vgasync-grp1 { - fsl,pins = < - /* VGA_VSYNC, HSYNC with max drive strength */ - MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 - MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 - >; - }; - }; -}; - -&ipu_di1_disp1 { - remote-endpoint = <&display1_in>; -}; - -&cspi { - status = "okay"; -}; - -&audmux { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; -}; - -&i2c2 { - codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - }; - - expander: pca9554@20 { - compatible = "pca9554"; - reg = <0x20>; - interrupts = <109>; - #gpio-cells = <2>; - gpio-controller; - }; - - sensor2: lm75@49 { - compatible = "lm75"; - reg = <0x49>; - }; -}; - -&fec { - phy-reset-gpios = <&gpio7 6 0>; - status = "okay"; -}; - -&esdhc2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&ecspi1 { - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&tve { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vga_sync_1>; - ddc-i2c-bus = <&i2c3>; - fsl,tve-mode = "vga"; - fsl,hsync-pin = <4>; - fsl,vsync-pin = <6>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx53-pinfunc.h deleted file mode 100644 index aec406bc6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-pinfunc.h +++ /dev/null @@ -1,1189 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX53_PINFUNC_H -#define __DTS_IMX53_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 -#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 -#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 -#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 -#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 -#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 -#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 -#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 -#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 -#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 -#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 -#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 -#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 -#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 -#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 -#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 -#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 -#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 -#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 -#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 -#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 -#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 -#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 -#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 -#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 -#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 -#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 -#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 -#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 -#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 -#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 -#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 -#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 -#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 -#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 -#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 -#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 -#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 -#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 -#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 -#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 -#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 -#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 -#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 -#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 -#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 -#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 -#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 -#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 -#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 -#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 -#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 -#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 -#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 -#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 -#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 -#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 -#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 -#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 -#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 -#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 -#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 -#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 -#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 -#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 -#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 -#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 -#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 -#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 -#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 -#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 -#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 -#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 -#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 -#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 -#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 -#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 -#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 -#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 -#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 -#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 -#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 -#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 -#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 -#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 -#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 -#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 -#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 -#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 -#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 -#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 -#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 -#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 -#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 -#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 -#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 -#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 -#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 -#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 -#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 -#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 -#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 -#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 -#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 -#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 -#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 -#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 -#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 -#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 -#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 -#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 -#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 -#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 -#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 -#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 -#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 -#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 -#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 -#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 -#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 -#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 -#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 -#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 -#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 -#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 -#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 -#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 -#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 -#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 -#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 -#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 -#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 -#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 -#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 -#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 -#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 -#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 -#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 -#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 -#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 -#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 -#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 -#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 -#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 -#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 -#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 -#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 -#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 -#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 -#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 -#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 -#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 -#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 -#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 -#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 -#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 -#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 -#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 -#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 -#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 -#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 -#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 -#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 -#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 -#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 -#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 -#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 -#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 -#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 -#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 -#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 -#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 -#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 -#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 -#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 -#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 -#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 -#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 -#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 -#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 -#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 -#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 -#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 -#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 -#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 -#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 -#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 -#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 -#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 -#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 -#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 -#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 -#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 -#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 -#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 -#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 -#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 -#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 -#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 -#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 -#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 -#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 -#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 -#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 -#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 -#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 -#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 -#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 -#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 -#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 -#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 -#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 -#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 -#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 -#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 -#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 -#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 -#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 -#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 -#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 -#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 -#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 -#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 -#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 -#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 -#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 -#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 -#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 -#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 -#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 -#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 -#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 -#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 -#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 -#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 -#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 -#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 -#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 -#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 -#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 -#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 -#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 -#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 -#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 -#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 -#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 -#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 -#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 -#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 -#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 -#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 -#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 -#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 -#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 -#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 -#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 -#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 -#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 -#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 -#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 -#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 -#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 -#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 -#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 -#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 -#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 -#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 -#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 -#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 -#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 -#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 -#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 -#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 -#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 -#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 -#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 -#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 -#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 -#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 -#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 -#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 -#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 -#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 -#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 -#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 -#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 -#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 -#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 -#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 -#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 -#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 -#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 -#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 -#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 -#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 -#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 -#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 -#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 -#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 -#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 -#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 -#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 -#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 -#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 -#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 -#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 -#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 -#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 -#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 -#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 -#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 -#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 -#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 -#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 -#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 -#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 -#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 -#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 -#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 -#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 -#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 -#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 -#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 -#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 -#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 -#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 -#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 -#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 -#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 -#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 -#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 -#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 -#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 -#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 -#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 -#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 -#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 -#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 -#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 -#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 -#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 -#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 -#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 -#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 -#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 -#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 -#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 -#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 -#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 -#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 -#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 -#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 -#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 -#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 -#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 -#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 -#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 -#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 -#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 -#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 -#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 -#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 -#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 -#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 -#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 -#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 -#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 -#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 -#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 -#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 -#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 -#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 -#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 -#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 -#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 -#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 -#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 -#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 -#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 -#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 -#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 -#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 -#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 -#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 -#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 -#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 -#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 -#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 -#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 -#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 -#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 -#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 -#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 -#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 -#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 -#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 -#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 -#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 -#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 -#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 -#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 -#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 -#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 -#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 -#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 -#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 -#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 -#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 -#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 -#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 -#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 -#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 -#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 -#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 -#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 -#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 -#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 -#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 -#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 -#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 -#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 -#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 -#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 -#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 -#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 -#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 -#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 -#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 -#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 -#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 -#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 -#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 -#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 -#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 -#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 -#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 -#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 -#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 -#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 -#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 -#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 -#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 -#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 -#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 -#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 -#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 -#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 -#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 -#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 -#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 -#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 -#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 -#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 -#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 -#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 -#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 -#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 -#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 -#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 -#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 -#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 -#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 -#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 -#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 -#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 -#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 -#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 -#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 -#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 -#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 -#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 -#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 -#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 -#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 -#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 -#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 -#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 -#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 -#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 -#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 -#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 -#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 -#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 -#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 -#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 -#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 -#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 -#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 -#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 -#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 -#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 -#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 -#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 -#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 -#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 -#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 -#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 -#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 -#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 -#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 -#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 -#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 -#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 -#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 -#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 -#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 -#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 -#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 -#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 -#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 -#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 -#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 -#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 -#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 -#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 -#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 -#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 -#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 -#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 -#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 -#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 -#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 -#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 -#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 -#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 -#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 -#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 -#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 -#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 -#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 -#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 -#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 - -#endif /* __DTS_IMX53_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-qsb-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx53-qsb-common.dtsi deleted file mode 100644 index c05e7cfd0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx53.dtsi" - -/ { - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x70000000 0x20000000>, - <0xb0000000 0x20000000>; - }; - - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb565"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp0>; - status = "disabled"; - display-timings { - claawvga { - native-mode; - clock-frequency = <27000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <60>; - vback-porch = <10>; - vfront-porch = <10>; - hsync-len = <20>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power Button"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio7_7>; - - user { - label = "Heartbeat"; - gpios = <&gpio7 7 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 0>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx53-qsb-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-qsb-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&ssi2 { - status = "okay"; -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - bus-width = <8>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-qsb { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 - MX53_PAD_GPIO_8__GPIO1_8 0x80000000 - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 - MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 - MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 - >; - }; - - led_pin_gpio7_7: led_gpio7_7@0 { - fsl,pins = < - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - /* open drain */ - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec - MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_ipu_disp0: ipudisp0grp { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - - pinctrl_vga_sync: vgasync-grp { - fsl,pins = < - /* VGA_HSYNC, VSYNC with max drive strength */ - MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 - MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&tve { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vga_sync>; - ddc-i2c-bus = <&i2c2>; - fsl,tve-mode = "vga"; - fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */ - fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p2v>; - VDDIO-supply = <®_3p2v>; - clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 0>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-qsb.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-qsb.dts deleted file mode 100644 index 379939699..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-qsb.dts +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53-qsb-common.dtsi" - -/ { - model = "Freescale i.MX53 Quick Start Board"; - compatible = "fsl,imx53-qsb", "fsl,imx53"; -}; - -&i2c1 { - pmic: dialog@48 { - compatible = "dlg,da9053-aa", "dlg,da9052"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */ - - regulators { - buck1_reg: buck1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - buck4_reg: buck4 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1725000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo9_reg: ldo9 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - - ldo10_reg: ldo10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-qsrb.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-qsrb.dts deleted file mode 100644 index 96d7eede4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-qsrb.dts +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include "imx53-qsb-common.dtsi" - -/ { - model = "Freescale i.MX53 Quick Start-R Board"; - compatible = "fsl,imx53-qsrb", "fsl,imx53"; -}; - -&iomuxc { - imx53-qsrb { - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */ - >; - }; - }; -}; - -&i2c1 { - pmic: mc34708@8 { - compatible = "fsl,mc34708"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x08>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - regulators { - sw1_reg: sw1a { - regulator-name = "SW1"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw1b_reg: sw1b { - regulator-name = "SW1B"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-name = "SW2"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1437500>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-name = "SW3"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - }; - - sw4a_reg: sw4a { - regulator-name = "SW4A"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4b_reg: sw4b { - regulator-name = "SW4B"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw5_reg: sw5 { - regulator-name = "SW5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-name = "SWBST"; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-name = "VPLL"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - vrefddr_reg: vrefddr { - regulator-name = "VREFDDR"; - regulator-boot-on; - regulator-always-on; - }; - - vusb_reg: vusb { - regulator-name = "VUSB"; - regulator-boot-on; - regulator-always-on; - }; - - vusb2_reg: vusb2 { - regulator-name = "VUSB2"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vdac_reg: vdac { - regulator-name = "VDAC"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-name = "VGEN1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-name = "VGEN2"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-smd.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-smd.dts deleted file mode 100644 index 9f5190040..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-smd.dts +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53.dtsi" - -/ { - model = "Freescale i.MX53 Smart Mobile Reference Design Board"; - compatible = "fsl,imx53-smd", "fsl,imx53"; - - memory { - reg = <0x70000000 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - volume-up { - label = "Volume Up"; - gpios = <&gpio2 14 0>; - linux,code = <115>; /* KEY_VOLUMEUP */ - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio2 15 0>; - linux,code = <114>; /* KEY_VOLUMEDOWN */ - }; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - non-removable; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; - status = "okay"; - - zigbee: mc1323@0 { - compatible = "fsl,mc1323"; - spi-max-frequency = <8000000>; - reg = <0>; - }; - - flash: m25p32@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "st,m25p", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0x3c0000>; - }; - }; -}; - -&esdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-smd { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 - MX53_PAD_EIM_EB2__GPIO2_30 0x80000000 - MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 - MX53_PAD_EIM_D19__GPIO3_19 0x80000000 - MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 - MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - }; - - magnetometer: mag3110@0e { - compatible = "fsl,mag3110"; - reg = <0x0e>; - }; - - touchkey: mpr121@5a { - compatible = "fsl,mpr121"; - reg = <0x5a>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; - - camera: ov5642@3c { - compatible = "ovti,ov5642"; - reg = <0x3c>; - }; - - pmic: dialog@48 { - compatible = "dlg,da9053", "dlg,da9052"; - reg = <0x48>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 0>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-tqma53.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx53-tqma53.dtsi deleted file mode 100644 index 91a6a9ff5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-tqma53.dtsi +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer , Pengutronix - * Copyright 2012 Steffen Trumtrar , Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx53.dtsi" - -/ { - model = "TQ TQMa53"; - compatible = "tq,tqma53", "fsl,imx53"; - - memory { - reg = <0x70000000 0x40000000>; /* Up to 1GiB */ - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>, - <&pinctrl_esdhc2_cdwp>; - vmmc-supply = <®_3p3v>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "disabled"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <4>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, - <&gpio3 24 0>, <&gpio3 25 0>; - status = "disabled"; -}; - -&esdhc3 { /* EMMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc3>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-tqma53 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ - MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ - MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ - MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ - MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ - MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ - MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ - MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ - MX53_PAD_GPIO_3__GPIO1_3 0x80000000 - MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 - MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_cspi: cspigrp { - fsl,pins = < - MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 - MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 - MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_esdhc2_cdwp: esdhc2cdwp { - fsl,pins = < - MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ - MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ - >; - }; - - pinctrl_esdhc3: esdhc3grp { - fsl,pins = < - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 - MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 - MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "disabled"; -}; - -&cspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi>; - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, - <&gpio1 21 0>; - status = "disabled"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: mc34708@8 { - compatible = "fsl,mc34708"; - reg = <0x8>; - fsl,mc13xxx-uses-rtc; - interrupt-parent = <&gpio2>; - interrupts = <6 4>; /* PATA_DATA6, active high */ - }; - - sensor1: lm75@48 { - compatible = "lm75"; - reg = <0x48>; - }; - - eeprom: 24c64@50 { - compatible = "at,24c64"; - pagesize = <32>; - reg = <0x50>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-tx53-x03x.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-tx53-x03x.dts deleted file mode 100644 index 0ecb43d88..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-tx53-x03x.dts +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53-tx53.dtsi" -#include -#include -#include - -/ { - model = "Ka-Ro electronics TX53 module (LCD)"; - compatible = "karo,tx53", "fsl,imx53"; - - aliases { - display = &display; - }; - - soc { - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgb24_vga1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - regulators { - reg_lcd_pwr: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd_reset: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06_1>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 0>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&iomuxc { - imx53-tx53-x03x { - pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 { - fsl,pins = < - MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */ - MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */ - MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */ - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX53_PAD_GPIO_9__KPP_COL_6 0x1f4 - MX53_PAD_GPIO_4__KPP_COL_7 0x1f4 - MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4 - MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4 - MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4 - MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4 - MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4 - MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4 - >; - }; - - pinctrl_rgb24_vga1: rgb24-vgagrp1 { - fsl,pins = < - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */ - >; - }; - }; -}; - -&ipu_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0,1 are mapped to KPP row/col 6,7 */ - linux,keymap = < - MATRIX_KEY(6, 6, KEY_POWER) - MATRIX_KEY(6, 7, KEY_KP0) - MATRIX_KEY(6, 2, KEY_KP1) - MATRIX_KEY(6, 3, KEY_KP2) - MATRIX_KEY(7, 6, KEY_KP3) - MATRIX_KEY(7, 7, KEY_KP4) - MATRIX_KEY(7, 2, KEY_KP5) - MATRIX_KEY(7, 3, KEY_KP6) - MATRIX_KEY(2, 6, KEY_KP7) - MATRIX_KEY(2, 7, KEY_KP8) - MATRIX_KEY(2, 2, KEY_KP9) - >; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-tx53-x13x.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-tx53-x13x.dts deleted file mode 100644 index 3cf682a68..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-tx53-x13x.dts +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53-tx53.dtsi" -#include - -/ { - model = "Ka-Ro electronics TX53 module (LVDS)"; - compatible = "karo,tx53", "fsl,imx53"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_3v3>; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <50>; - }; - - regulators { - reg_lcd_pwr0: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LVDS0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd_pwr1: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "LVDS1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - touchscreen2: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti2>; - interrupt-parent = <&gpio3>; - interrupts = <23 0>; - wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - touchscreen1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti1>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&iomuxc { - imx53-tx53-x13x { - pinctrl_i2c2: i2c2-grp1 { - fsl,pins = < - MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 - MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 - >; - }; - - pinctrl_lvds0: lvds0grp { - fsl,pins = < - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 - >; - }; - - pinctrl_lvds1: lvds1grp { - fsl,pins = < - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = ; - }; - - pinctrl_eeti1: eeti1grp { - fsl,pins = < - MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */ - >; - }; - - pinctrl_eeti2: eeti2grp { - fsl,pins = < - MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */ - >; - }; - }; -}; - -&ldb { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>; - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing0>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hsync-len = <60>; - hfront-porch = <40>; - vback-porch = <21>; - vsync-len = <10>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hsync-len = <60>; - hfront-porch = <50>; - vback-porch = <5>; - vsync-len = <13>; - vfront-porch = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing0>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hsync-len = <60>; - hfront-porch = <40>; - vback-porch = <21>; - vsync-len = <10>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-tx53.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx53-tx53.dtsi deleted file mode 100644 index 57e75f163..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-tx53.dtsi +++ /dev/null @@ -1,549 +0,0 @@ -/* - * Copyright 2012 - * based on imx53-qsb.dts - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx53.dtsi" -#include - -/ { - model = "Ka-Ro electronics TX53 module"; - compatible = "karo,tx53", "fsl,imx53"; - - aliases { - can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */ - can1 = &can1; - ipu = &ipu; - reg_can_xcvr = ®_can_xcvr; - usbh1 = &usbh1; - usbotg = &usbotg; - }; - - clocks { - ckih1 { - clock-frequency = <0>; - }; - - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_key>; - - power { - label = "Power Button"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - linux,code = <116>; /* KEY_POWER */ - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stk5led>; - - user { - label = "Heartbeat"; - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2v5: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can_xcvr: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - reg_usbh1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000"; - model = "tx53-audio-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - /* '1' based port numbers according to datasheet names */ - mux-int-port = <1>; - mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssi1>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <2>; - status = "okay"; - - cs-gpios = < - &gpio2 30 GPIO_ACTIVE_HIGH - &gpio3 19 GPIO_ACTIVE_HIGH - >; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; -}; - -&esdhc1 { - cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&esdhc2 { - cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; - phy-handle = <&phy0>; - mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ - status = "okay"; - - phy0: ethernet-phy@0 { - interrupt-parent = <&gpio2>; - interrupts = <4>; - device_type = "ethernet-phy"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; - - rtc1: ds1339@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ds1339>; - interrupt-parent = <&gpio4>; - interrupts = <20 0>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-tx53 { - pinctrl_hog: hoggrp { - /* pins not in use by any device on the Starterkit board series */ - fsl,pins = < - /* CMOS Sensor Interface */ - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4 - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4 - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4 - MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4 - MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4 - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4 - MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4 - MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4 - MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4 - MX53_PAD_GPIO_0__GPIO1_0 0x1f4 - /* Module Specific Signal */ - /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */ - /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */ - MX53_PAD_EIM_D29__GPIO3_29 0x1f4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1f4 - /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */ - /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */ - MX53_PAD_EIM_A19__GPIO2_19 0x1f4 - MX53_PAD_EIM_A20__GPIO2_18 0x1f4 - MX53_PAD_EIM_A21__GPIO2_17 0x1f4 - MX53_PAD_EIM_A22__GPIO2_16 0x1f4 - MX53_PAD_EIM_A23__GPIO6_6 0x1f4 - MX53_PAD_EIM_A24__GPIO5_4 0x1f4 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4 - /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */ - /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */ - MX53_PAD_GPIO_13__GPIO4_3 0x1f4 - MX53_PAD_EIM_CS0__GPIO2_23 0x1f4 - MX53_PAD_EIM_CS1__GPIO2_24 0x1f4 - MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4 - MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4 - MX53_PAD_EIM_EB0__GPIO2_28 0x1f4 - MX53_PAD_EIM_EB1__GPIO2_29 0x1f4 - MX53_PAD_EIM_OE__GPIO2_25 0x1f4 - MX53_PAD_EIM_LBA__GPIO2_27 0x1f4 - MX53_PAD_EIM_RW__GPIO2_26 0x1f4 - MX53_PAD_EIM_DA8__GPIO3_8 0x1f4 - MX53_PAD_EIM_DA9__GPIO3_9 0x1f4 - MX53_PAD_EIM_DA10__GPIO3_10 0x1f4 - MX53_PAD_EIM_DA11__GPIO3_11 0x1f4 - MX53_PAD_EIM_DA12__GPIO3_12 0x1f4 - MX53_PAD_EIM_DA13__GPIO3_13 0x1f4 - MX53_PAD_EIM_DA14__GPIO3_14 0x1f4 - MX53_PAD_EIM_DA15__GPIO3_15 0x1f4 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 - MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 - MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = ; /* Flexcan XCVR enable */ - }; - - pinctrl_ds1339: ds1339grp { - fsl,pins = ; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 - MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - MX53_PAD_EIM_D24__GPIO3_24 0x1f0 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - MX53_PAD_EIM_D25__GPIO3_25 0x1f0 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_gpio_key: gpio-keygrp { - fsl,pins = ; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 - MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 - >; - }; - - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_ssi2: ssi2grp { - fsl,pins = < - MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 - MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 - MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 - MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 - MX53_PAD_EIM_D27__GPIO3_27 0x1f0 - >; - }; - - pinctrl_stk5led: stk5ledgrp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 - MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 - MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 - MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */ - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */ - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */ - MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */ - >; - }; - }; -}; - -&ipu { - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <3>; -}; - -&sdma { - fsl,sdma-ram-script-name = "sdma-imx53.bin"; -}; - -&ssi1 { - codec-handle = <&sgtl5000>; - status = "okay"; -}; - -&ssi2 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - phy_type = "utmi"; - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - phy_type = "utmi"; - dr_mode = "peripheral"; - disable-over-current; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-usbarmory.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-usbarmory.dts deleted file mode 100644 index 6782d7fc5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-usbarmory.dts +++ /dev/null @@ -1,224 +0,0 @@ -/* - * USB armory MkI device tree file - * https://inversepath.com/usbarmory - * - * Copyright (C) 2015, Inverse Path - * Andrej Rosano - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx53.dtsi" - -/ { - model = "Inverse Path USB armory"; - compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; -}; - -/ { - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x70000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user { - label = "LED"; - gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -/* - * Not every i.MX53 P/N supports clock > 800MHz. - * As USB armory does not mount a specific P/N set a safe clock upper limit. - */ -&cpu0 { - operating-points = < - /* kHz */ - 166666 850000 - 400000 900000 - 800000 1050000 - >; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - status = "okay"; -}; - -&iomuxc { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 - >; - }; - - pinctrl_i2c1_pmic: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0x80 - MX53_PAD_EIM_D28__I2C1_SDA 0x80 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4 - >; - }; - - /* - * UART mode pin header configration - * 3 - GPIO5[26], pull-down 100K - * 4 - GPIO5[27], pull-down 100K - * 5 - TX, pull-up 100K - * 6 - RX, pull-up 100K - * 7 - GPIO5[30], pull-down 100K - */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0 - MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0 - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 - MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0 - >; - }; -}; - -&i2c1 { - pinctrl-0 = <&pinctrl_i2c1_pmic>; - status = "okay"; - - ltc3589: pmic@34 { - compatible = "lltc,ltc3589-2"; - reg = <0x34>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <591930>; - regulator-max-microvolt = <1224671>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456803>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1341250>; - regulator-max-microvolt = <2775000>; - lltc,fb-voltage-divider = <270000 100000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - bb_out_reg: bb-out { - regulator-min-microvolt = <3387341>; - regulator-max-microvolt = <3387341>; - lltc,fb-voltage-divider = <511000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <1306329>; - regulator-max-microvolt = <1306329>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456806>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3200000>; - }; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-voipac-bsb.dts b/software/linux/kernel/arch/arm/boot/dts/imx53-voipac-bsb.dts deleted file mode 100644 index fc51b87ad..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-voipac-bsb.dts +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx53-voipac-dmm-668.dtsi" - -/ { - sound { - compatible = "fsl,imx53-voipac-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx53-voipac-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <5>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio>; - - led1 { - label = "led-red"; - gpios = <&gpio3 29 0>; - default-state = "off"; - }; - - led2 { - label = "led-orange"; - gpios = <&gpio2 31 0>; - default-state = "off"; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-voipac { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SD2_CD */ - MX53_PAD_EIM_D25__GPIO3_25 0x80000000 - /* SD2_WP */ - MX53_PAD_EIM_A19__GPIO2_19 0x80000000 - >; - }; - - led_pin_gpio: led_gpio { - fsl,pins = < - MX53_PAD_EIM_D29__GPIO3_29 0x80000000 - MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 - >; - }; - - /* Keyboard controller */ - pinctrl_kpp_1: kppgrp-1 { - fsl,pins = < - MX53_PAD_GPIO_9__KPP_COL_6 0xe8 - MX53_PAD_GPIO_4__KPP_COL_7 0xe8 - MX53_PAD_KEY_COL2__KPP_COL_2 0xe8 - MX53_PAD_KEY_COL3__KPP_COL_3 0xe8 - MX53_PAD_KEY_COL4__KPP_COL_4 0xe8 - MX53_PAD_GPIO_2__KPP_ROW_6 0xe0 - MX53_PAD_GPIO_5__KPP_ROW_7 0xe0 - MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0 - MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0 - MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 - >; - }; - - pinctrl_esdhc2: esdhc2grp { - fsl,pins = < - MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 - MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 - MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 - >; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */ - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&clks 150>; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp_1>; - linux,keymap = < - 0x0203003b /* KEY_F1 */ - 0x0603003c /* KEY_F2 */ - 0x0207003d /* KEY_F3 */ - 0x0607003e /* KEY_F4 */ - >; - keypad,num-rows = <8>; - keypad,num-columns = <1>; - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi deleted file mode 100644 index ba689fbd0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright 2013 Rostislav Lisovy , PiKRON s.r.o. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx53.dtsi" - -/ { - model = "Voipac i.MX53 X53-DMM-668"; - compatible = "voipac,imx53-dmm-668", "fsl,imx53"; - - memory@70000000 { - device_type = "memory"; - reg = <0x70000000 0x20000000>; - }; - - memory@b0000000 { - device_type = "memory"; - reg = <0xb0000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 0>; /* PEN */ - enable-active-high; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx53-voipac { - pinctrl_hog: hoggrp { - fsl,pins = < - /* Make DA9053 regulator functional */ - MX53_PAD_GPIO_16__GPIO7_11 0x80000000 - /* FEC Power enable */ - MX53_PAD_GPIO_11__GPIO4_1 0x80000000 - /* FEC RST */ - MX53_PAD_GPIO_12__GPIO4_2 0x80000000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 - MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 - MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 - MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 - >; - }; - - pinctrl_nand: nandgrp { - fsl,pins = < - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 - >; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <4>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 2 0>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: dialog@48 { - compatible = "dlg,da9053-aa", "dlg,da9052"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */ - - regulators { - buck1_reg: buck1 { - regulator-name = "BUCKCORE"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-name = "BUCKPRO"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-name = "BUCKMEM"; - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1580000>; - regulator-always-on; - }; - - buck4_reg: buck4 { - regulator-name = "BUCKPERI"; - regulator-min-microvolt = <2370000>; - regulator-max-microvolt = <2630000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "ldo1_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-name = "ldo2_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "ldo3_3v3"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3350000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-name = "ldo4_2v775"; - regulator-min-microvolt = <2770000>; - regulator-max-microvolt = <2780000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "ldo5_3v3"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3350000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "ldo6_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - ldo7_reg: ldo7 { - regulator-name = "ldo7_2v75"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "ldo8_1v8"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1850000>; - regulator-always-on; - }; - - ldo9_reg: ldo9 { - regulator-name = "ldo9_1v5"; - regulator-min-microvolt = <1450000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - ldo10_reg: ldo10 { - regulator-name = "ldo10_1v3"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_vbus>; - phy_type = "utmi"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx53.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx53.dtsi deleted file mode 100644 index 0777b41cd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx53.dtsi +++ /dev/null @@ -1,812 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" -#include "imx53-pinfunc.h" -#include -#include -#include -#include - -/ { - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &esdhc1; - mmc1 = &esdhc2; - mmc2 = &esdhc3; - mmc3 = &esdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &cspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&clks IMX5_CLK_ARM>; - clock-latency = <61036>; - voltage-tolerance = <5>; - operating-points = < - /* kHz */ - 166666 850000 - 400000 900000 - 800000 1050000 - 1000000 1200000 - 1200000 1300000 - >; - }; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu_di0>, <&ipu_di1>; - }; - - tzic: tz-interrupt-controller@0fffc000 { - compatible = "fsl,imx53-tzic", "fsl,tzic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x0fffc000 0x4000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22579200>; - }; - - ckih2 { - compatible = "fsl,imx-ckih2", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&tzic>; - ranges; - - sata: sata@10000000 { - compatible = "fsl,imx53-ahci"; - reg = <0x10000000 0x1000>; - interrupts = <28>; - clocks = <&clks IMX5_CLK_SATA_GATE>, - <&clks IMX5_CLK_SATA_REF>, - <&clks IMX5_CLK_AHB>; - clock-names = "sata", "sata_ref", "ahb"; - status = "disabled"; - }; - - ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x08000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu_csi0: port@0 { - reg = <0>; - }; - - ipu_csi1: port@1 { - reg = <1>; - }; - - ipu_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu_di0_lvds0: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds0_in>; - }; - }; - - ipu_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu_di1_disp1: endpoint@0 { - reg = <0>; - }; - - ipu_di1_lvds1: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds1_in>; - }; - - ipu_di1_tve: endpoint@2 { - reg = <2>; - remote-endpoint = <&tve_in>; - }; - }; - }; - - aips@50000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x10000000>; - ranges; - - spba@50000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x50000000 0x40000>; - ranges; - - esdhc1: esdhc@50004000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50004000 0x4000>; - interrupts = <1>; - clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC1_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc2: esdhc@50008000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50008000 0x4000>; - interrupts = <2>; - clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC2_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - uart3: serial@5000c000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x5000c000 0x4000>; - interrupts = <33>; - clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, - <&clks IMX5_CLK_UART3_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi1: ecspi@50010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; - reg = <0x50010000 0x4000>; - interrupts = <36>; - clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, - <&clks IMX5_CLK_ECSPI1_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ssi2: ssi@50014000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", - "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x50014000 0x4000>; - interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, - <&clks IMX5_CLK_SSI2_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - esdhc3: esdhc@50020000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50020000 0x4000>; - interrupts = <3>; - clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC3_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - esdhc4: esdhc@50024000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x50024000 0x4000>; - interrupts = <4>; - clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, - <&clks IMX5_CLK_DUMMY>, - <&clks IMX5_CLK_ESDHC4_PER_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - }; - - aipstz1: bridge@53f00000 { - compatible = "fsl,imx53-aipstz"; - reg = <0x53f00000 0x60>; - }; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; - clock-names = "main_clk"; - status = "okay"; - }; - - usbphy1: usbphy@1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; - clock-names = "main_clk"; - status = "okay"; - }; - - usbotg: usb@53f80000 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80000 0x0200>; - interrupts = <18>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; - status = "disabled"; - }; - - usbh1: usb@53f80200 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80200 0x0200>; - interrupts = <14>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 1>; - fsl,usbphy = <&usbphy1>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh2: usb@53f80400 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@53f80600 { - compatible = "fsl,imx53-usb", "fsl,imx27-usb"; - reg = <0x53f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc: usbmisc@53f80800 { - #index-cells = <1>; - compatible = "fsl,imx53-usbmisc"; - reg = <0x53f80800 0x200>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - }; - - gpio1: gpio@53f84000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@53f88000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f88000 0x4000>; - interrupts = <52 53>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@53f8c000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f8c000 0x4000>; - interrupts = <54 55>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@53f90000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53f90000 0x4000>; - interrupts = <56 57>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: kpp@53f94000 { - compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; - reg = <0x53f94000 0x4000>; - interrupts = <60>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: wdog@53f98000 { - compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; - reg = <0x53f98000 0x4000>; - interrupts = <58>; - clocks = <&clks IMX5_CLK_DUMMY>; - }; - - wdog2: wdog@53f9c000 { - compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; - reg = <0x53f9c000 0x4000>; - interrupts = <59>; - clocks = <&clks IMX5_CLK_DUMMY>; - status = "disabled"; - }; - - gpt: timer@53fa0000 { - compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; - reg = <0x53fa0000 0x4000>; - interrupts = <39>; - clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, - <&clks IMX5_CLK_GPT_HF_GATE>; - clock-names = "ipg", "per"; - }; - - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx53-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; - }; - - ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - reg = <0x53fa8008 0x4>; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; - - port@1 { - reg = <1>; - - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; - }; - }; - - pwm1: pwm@53fb4000 { - #pwm-cells = <2>; - compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; - reg = <0x53fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; - }; - - pwm2: pwm@53fb8000 { - #pwm-cells = <2>; - compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; - reg = <0x53fb8000 0x4000>; - clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, - <&clks IMX5_CLK_PWM2_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <94>; - }; - - uart1: serial@53fbc000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fbc000 0x4000>; - interrupts = <31>; - clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, - <&clks IMX5_CLK_UART1_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@53fc0000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; - reg = <0x53fc8000 0x4000>; - interrupts = <82>; - clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, - <&clks IMX5_CLK_CAN1_SERIAL_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can2: can@53fcc000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; - reg = <0x53fcc000 0x4000>; - interrupts = <83>; - clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, - <&clks IMX5_CLK_CAN2_SERIAL_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - src: src@53fd0000 { - compatible = "fsl,imx53-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - #reset-cells = <1>; - }; - - clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; - }; - - gpio5: gpio@53fdc000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fdc000 0x4000>; - interrupts = <103 104>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@53fe0000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fe0000 0x4000>; - interrupts = <105 106>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@53fe4000 { - compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; - reg = <0x53fe4000 0x4000>; - interrupts = <107 108>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c3: i2c@53fec000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x53fec000 0x4000>; - interrupts = <64>; - clocks = <&clks IMX5_CLK_I2C3_GATE>; - status = "disabled"; - }; - - uart4: serial@53ff0000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53ff0000 0x4000>; - interrupts = <13>; - clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, - <&clks IMX5_CLK_UART4_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - aips@60000000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x60000000 0x10000000>; - ranges; - - aipstz2: bridge@63f00000 { - compatible = "fsl,imx53-aipstz"; - reg = <0x63f00000 0x60>; - }; - - iim: iim@63f98000 { - compatible = "fsl,imx53-iim", "fsl,imx27-iim"; - reg = <0x63f98000 0x4000>; - interrupts = <69>; - clocks = <&clks IMX5_CLK_IIM_GATE>; - }; - - uart5: serial@63f90000 { - compatible = "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x63f90000 0x4000>; - interrupts = <86>; - clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, - <&clks IMX5_CLK_UART5_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - owire: owire@63fa4000 { - compatible = "fsl,imx53-owire", "fsl,imx21-owire"; - reg = <0x63fa4000 0x4000>; - clocks = <&clks IMX5_CLK_OWIRE_GATE>; - status = "disabled"; - }; - - ecspi2: ecspi@63fac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; - reg = <0x63fac000 0x4000>; - interrupts = <37>; - clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, - <&clks IMX5_CLK_ECSPI2_PER_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sdma: sdma@63fb0000 { - compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; - reg = <0x63fb0000 0x4000>; - interrupts = <6>; - clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - - cspi: cspi@63fc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; - reg = <0x63fc0000 0x4000>; - interrupts = <38>; - clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, - <&clks IMX5_CLK_CSPI_IPG_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c2: i2c@63fc4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x63fc4000 0x4000>; - interrupts = <63>; - clocks = <&clks IMX5_CLK_I2C2_GATE>; - status = "disabled"; - }; - - i2c1: i2c@63fc8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; - reg = <0x63fc8000 0x4000>; - interrupts = <62>; - clocks = <&clks IMX5_CLK_I2C1_GATE>; - status = "disabled"; - }; - - ssi1: ssi@63fcc000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fcc000 0x4000>; - interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, - <&clks IMX5_CLK_SSI1_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 28 0 0>, - <&sdma 29 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - audmux: audmux@63fd0000 { - compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; - reg = <0x63fd0000 0x4000>; - status = "disabled"; - }; - - nfc: nand@63fdb000 { - compatible = "fsl,imx53-nand"; - reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; - interrupts = <8>; - clocks = <&clks IMX5_CLK_NFC_GATE>; - status = "disabled"; - }; - - ssi3: ssi@63fe8000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", - "fsl,imx21-ssi"; - reg = <0x63fe8000 0x4000>; - interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, - <&clks IMX5_CLK_SSI3_ROOT_GATE>; - clock-names = "ipg", "baud"; - dmas = <&sdma 46 0 0>, - <&sdma 47 0 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - tve: tve@63ff0000 { - compatible = "fsl,imx53-tve"; - reg = <0x63ff0000 0x1000>; - interrupts = <92>; - clocks = <&clks IMX5_CLK_TVE_GATE>, - <&clks IMX5_CLK_IPU_DI1_SEL>; - clock-names = "tve", "di_sel"; - status = "disabled"; - - port { - tve_in: endpoint { - remote-endpoint = <&ipu_di1_tve>; - }; - }; - }; - - vpu: vpu@63ff4000 { - compatible = "fsl,imx53-vpu", "cnm,coda7541"; - reg = <0x63ff4000 0x1000>; - interrupts = <9>; - clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, - <&clks IMX5_CLK_VPU_GATE>; - clock-names = "per", "ahb"; - resets = <&src 1>; - iram = <&ocram>; - }; - - sahara: crypto@63ff8000 { - compatible = "fsl,imx53-sahara"; - reg = <0x63ff8000 0x4000>; - interrupts = <19 20>; - clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, - <&clks IMX5_CLK_SAHARA_IPG_GATE>; - clock-names = "ipg", "ahb"; - }; - }; - - ocram: sram@f8000000 { - compatible = "mmio-sram"; - reg = <0xf8000000 0x20000>; - clocks = <&clks IMX5_CLK_OCRAM>; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <77>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-apf6dev.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-apf6dev.dts deleted file mode 100644 index df26e542a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-apf6dev.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2015 Armadeus Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-apf6.dtsi" -#include "imx6qdl-apf6dev.dtsi" - -/ { - model = "Armadeus APF6 Solo Module on APF6Dev Board"; - compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts deleted file mode 100644 index bb92f309c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts +++ /dev/null @@ -1,159 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x40000000>; - }; - - display0: display@di0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - - port@0 { - reg = <0>; - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&ecspi1 { - lcd_panel: display@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <0>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts deleted file mode 100644 index 3d5ad2cc7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts +++ /dev/null @@ -1,97 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x40000000>; - }; - - panel: panel { - compatible = "lg,lb070wv8"; - backlight = <&backlight>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos_4.dts deleted file mode 100644 index d4c4a22db..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ /dev/null @@ -1,89 +0,0 @@ -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos.dtsi" - -/ { - model = "aristainetos i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - status = "okay"; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - soc { - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; - - display-timings { - 480x800p60 { - native-mode; - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <59>; - hback-porch = <10>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; - }; -}; - -&ecspi2 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos_7.dts deleted file mode 100644 index 15203f0e9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-aristainetos.dtsi" - -/ { - model = "aristainetos i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x40000000>; - }; - - soc { - display0: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - status = "okay"; - - display-timings { - 800x480p60 { - native-mode; - clock-frequency = <33246000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <88>; - hback-porch = <88>; - hsync-len = <80>; - vback-porch = <10>; - vfront-porch = <10>; - vsync-len = <25>; - vsync-active = <1>; - }; - }; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 3000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&pwm3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-cubox-i.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-cubox-i.dts deleted file mode 100644 index 2a43917d0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-cubox-i.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Solo/DualLite"; - compatible = "solidrun,cubox-i/dl", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts deleted file mode 100644 index 994f96a3f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2013 Sascha Hauer - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DTS_V1__ -#define __DTS_V1__ -/dts-v1/; -#endif - -#include "imx6dl.dtsi" -#include "imx6qdl-dfi-fs700-m60.dtsi" - -/ { - model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; - compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw51xx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw51xx.dts deleted file mode 100644 index b2bd022fc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw51xx.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw51xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX"; - compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw52xx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw52xx.dts deleted file mode 100644 index a2e0b73fd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw52xx.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw52xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; - compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw53xx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw53xx.dts deleted file mode 100644 index 6844b708d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw53xx.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw53xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; - compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw54xx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw54xx.dts deleted file mode 100644 index be915412f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw54xx.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw54xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; - compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw551x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw551x.dts deleted file mode 100644 index 82d5f8572..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw551x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw551x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X"; - compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw552x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw552x.dts deleted file mode 100644 index a4b700cef..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw552x.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-gw552x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X"; - compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw553x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw553x.dts deleted file mode 100644 index 59b8afc36..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-gw553x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-gw553x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X"; - compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-hummingboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-hummingboard.dts deleted file mode 100644 index d5c966031..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Solo/DualLite"; - compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-nit6xlite.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-nit6xlite.dts deleted file mode 100644 index e0161e461..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-nit6xlite.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-nit6xlite.dtsi" - -/ { - model = "Boundary Devices i.MX6 Solo Nitrogen6_Lite Board"; - compatible = "boundary,imx6dl-nit6xlite", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-nitrogen6x.dts deleted file mode 100644 index 8398f979b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-nitrogen6x.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-nitrogen6x.dtsi" - -/ { - model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board"; - compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts deleted file mode 100644 index 08e978014..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6dl-phytec-pfla02.dtsi" -#include "imx6qdl-phytec-pbab01.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; - compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi deleted file mode 100644 index 964bc2ad3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-phytec-pfla02.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; - compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx6dl-pinfunc.h deleted file mode 100644 index 0ead323fd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-pinfunc.h +++ /dev/null @@ -1,1091 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX6DL_PINFUNC_H -#define __DTS_IMX6DL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 -#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 -#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 -#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 -#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 -#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 -#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 -#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 -#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 -#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 -#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 -#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 -#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 -#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 -#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 -#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 -#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 -#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 -#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 -#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 -#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 -#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 -#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 -#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 -#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 -#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 -#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 -#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 -#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 -#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 -#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 -#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 -#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 -#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 -#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 -#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 -#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 -#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 -#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 -#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 -#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 -#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 -#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 -#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 -#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 -#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 -#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 -#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 -#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 -#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 -#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 -#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 -#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 -#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 -#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 -#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 -#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 -#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 -#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 -#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 -#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 -#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 -#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 -#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 -#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 -#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 -#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 -#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 -#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 -#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 -#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 -#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 -#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 -#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 -#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 -#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 -#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 -#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 -#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 -#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 -#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 -#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 -#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 -#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 -#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 -#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 -#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 -#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 -#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 -#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 -#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 -#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 -#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 -#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 -#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 -#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 -#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 -#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 -#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 -#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 -#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 -#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 -#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 -#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 -#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 -#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 -#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 -#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 -#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 -#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 -#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 -#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 -#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 -#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 -#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 -#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 -#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 -#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 -#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 -#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 -#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 -#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 -#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 -#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 -#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 -#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 -#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 -#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 -#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 -#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 -#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 -#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 -#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 -#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 -#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 -#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 -#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 -#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 -#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 -#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 -#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 -#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 -#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 -#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 -#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 -#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 -#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 -#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 -#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 -#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 -#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 -#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 -#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 -#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 -#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 -#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 -#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 -#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 - -#endif /* __DTS_IMX6DL_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-rex-basic.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-rex-basic.dts deleted file mode 100644 index c3a14a433..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-rex-basic.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-rex.dtsi" - -/ { - model = "Rex Basic i.MX6 Dual Lite Board"; - compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x20000000>; - }; -}; - -&ecspi3 { - flash: m25p80@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-riotboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-riotboard.dts deleted file mode 100644 index 75d73437a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-riotboard.dts +++ /dev/null @@ -1,539 +0,0 @@ -/* - * Copyright 2014 Iain Paton - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include - -/ { - model = "RIoTboard i.MX6S"; - compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led0: user1 { - label = "user1"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6-riotboard-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 31 0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - pmic: pf0100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - interrupt-parent = <&gpio5>; - interrupts = <16 8>; - - regulators { - reg_vddcore: sw1ab { /* VDDARM_IN */ - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_vddsoc: sw1c { /* VDDSOC_IN */ - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_gen_3v3: sw2 { /* VDDHIGH_IN */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_vtt: sw4 { /* MIPI conn */ - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_5v_600mA: swbst { /* not used */ - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { /* VREF_DDR */ - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1_1v5: vgen1 { /* not used */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - reg_vgen3_2v8: vgen3 { /* not used */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&clks 116>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - vmmc-supply = <®_3p3v>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - - imx6-riotboard { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabreauto.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabreauto.dts deleted file mode 100644 index a6ce7b487..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabrelite.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabrelite.dts deleted file mode 100644 index 0f06ca5c9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabrelite.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-sabrelite.dtsi" - -/ { - model = "Freescale i.MX6 DualLite SABRE Lite Board"; - compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabresd.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabresd.dts deleted file mode 100644 index 1e45f2f9d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-sabresd.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-ts4900.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-ts4900.dts deleted file mode 100644 index 85eddeb30..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-ts4900.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-ts4900.dtsi" - -/ { - model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts deleted file mode 100644 index 063fe7510..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6DL Module on CoMpact TFT"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&kpp { - status = "disabled"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6s-8034.dts deleted file mode 100644 index ff8f7b1c4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6s-8034.dts +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright 2015-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6S-8034 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - ipu1 = &ipu1; - }; - - cpus { - /delete-node/ cpu@1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&pinctrl_usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 - MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ - >; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6s-8035.dts deleted file mode 100644 index f988950e9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6s-8035.dts +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright 2015-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6S-8035 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - ipu1 = &ipu1; - }; - - cpus { - /delete-node/ cpu@1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-801x.dts deleted file mode 100644 index b7a72840b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-801x.dts +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-801x Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-8033.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-8033.dts deleted file mode 100644 index 4d3204a56..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-8033.dts +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-8033 Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -®_lcd0_pwr { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-811x.dts deleted file mode 100644 index 5e0c6bb49..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-811x.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-811x Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&i2c3 { - polytouch2: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&kpp { - status = "disabled"; /* pad conflict with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds_timing0>; - lvds_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "disabled"; - - display-timings { - native-mode = <&lvds_timing1>; - lvds_timing1: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts deleted file mode 100644 index b9a783f71..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6U-81xx Module on MB7 baseboard"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&kpp { - status = "disabled"; /* pads partially clash with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing1>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds0_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing2>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds1_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds1_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-udoo.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-udoo.dts deleted file mode 100644 index e3713f00e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-udoo.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-udoo.dtsi" - -/ { - model = "Udoo i.MX6 Dual-lite Board"; - compatible = "udoo,imx6dl-udoo", "fsl,imx6dl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts deleted file mode 100644 index 8c314eee4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revb1.dtsi" - -/ { - model = "Wandboard i.MX6 Dual Lite Board rev B1"; - compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl-wandboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx6dl-wandboard.dts deleted file mode 100644 index bbb616723..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl-wandboard.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revc1.dtsi" - -/ { - model = "Wandboard i.MX6 Dual Lite Board"; - compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; - - memory { - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6dl.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6dl.dtsi deleted file mode 100644 index 7aa120fbd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6dl.dtsi +++ /dev/null @@ -1,186 +0,0 @@ - -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include "imx6dl-pinfunc.h" -#include "imx6qdl.dtsi" - -/ { - aliases { - i2c3 = &i2c4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - soc { - ocram: sram@00900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips1: aips-bus@02000000 { - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6dl-iomuxc"; - }; - - pxp: pxp@020f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - }; - - epdc: epdc@020f4000 { - reg = <0x020f4000 0x4000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - }; - - lcdif: lcdif@020f8000 { - reg = <0x020f8000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips2: aips-bus@02100000 { - i2c4: i2c@021f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6DL_CLK_I2C4>; - status = "disabled"; - }; - }; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>; - }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu_2d>, <&gpu_3d>; - }; -}; - -&gpio1 { - gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, - <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, - <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>, - <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>, - <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>, - <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>, - <&iomuxc 30 129 1>, <&iomuxc 31 122 1>; -}; - -&gpio2 { - gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>, - <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>, - <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>, - <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>, - <&iomuxc 28 113 4>; -}; - -&gpio3 { - gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>, - <&iomuxc 16 81 16>; -}; - -&gpio4 { - gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>, - <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>, - <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>, - <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>, - <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>; -}; - -&gpio5 { - gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>, - <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>, - <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>, - <&iomuxc 22 29 6>, <&iomuxc 28 19 4>; -}; - -&gpio6 { - gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>, - <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>, - <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>, - <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>, - <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>, - <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>; -}; - -&gpio7 { - gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>, - <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>, - <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; -}; - -&gpt { - compatible = "fsl,imx6dl-gpt"; -}; - -&hdmi { - compatible = "fsl,imx6dl-hdmi"; -}; - -&ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; -}; - -&vpu { - compatible = "fsl,imx6dl-vpu", "cnm,coda960"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-apalis-ixora.dts deleted file mode 100644 index 207b85b91..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright 2014-2016 Toradex AG - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" - -/ { - model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board"; - compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", - "fsl,imx6q"; - - aliases { - i2c0 = &i2cddc; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - aliases { - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: display@di0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - - led4-green { - label = "LED_4_GREEN"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - }; - - led4-red { - label = "LED_4_RED"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - }; - - led5-green { - label = "LED_5_GREEN"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - led5-red { - label = "LED_5_RED"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - ledpwm1 { - label = "PWM1"; - pwms = <&pwm1 0 50000>; - max-brightness = <255>; - }; - - ledpwm2 { - label = "PWM2"; - pwms = <&pwm2 0 50000>; - max-brightness = <255>; - }; - - ledpwm3 { - label = "PWM3"; - pwms = <&pwm3 0 50000>; - max-brightness = <255>; - }; - }; -}; - -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2cddc>; - status = "okay"; -}; - -&i2cddc { - status = "okay"; -}; - -/* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; -}; - -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -/* SD1 */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd_cd>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - /* - * Mux the Apalis GPIOs - * GPIO5, 6 used by optional fusion_F0710A kernel module - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; - - pinctrl_leds_ixora: ledsixoragrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-apf6dev.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-apf6dev.dts deleted file mode 100644 index 4e4de821d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-apf6dev.dts +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2015 Armadeus Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-apf6.dtsi" -#include "imx6qdl-apf6dev.dtsi" - -/ { - model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board"; - compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x40000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-arm2.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-arm2.dts deleted file mode 100644 index 4989d0bff..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-arm2.dts +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include -#include "imx6q.dtsi" - -/ { - model = "Freescale i.MX6 Quad Armadillo2 Board"; - compatible = "fsl,imx6q-arm2", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - leds { - compatible = "gpio-leds"; - - debug-led { - label = "Heartbeat"; - gpios = <&gpio3 25 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "disabled"; /* gpmi nand conflicts with SD */ -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-arm2 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - status = "okay"; -}; - -&usdhc4 { - non-removable; - vmmc-supply = <®_3p3v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - fsl,dte-mode; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-b450v3.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-b450v3.dts deleted file mode 100644 index 78bfc1a30..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-b450v3.dts +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B450v3"; - compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; - - panel-lvds0 { - compatible = "innolux,g121x1-l03"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pca9539 { - P04 { - gpio-hog; - gpios = <4 0>; - output-low; - line-name = "PCA9539-P04"; - }; - - P05 { - gpio-hog; - gpios = <5 0>; - output-low; - line-name = "PCA9539-P05"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-b650v3.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-b650v3.dts deleted file mode 100644 index d85388725..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-b650v3.dts +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B650v3"; - compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; - - panel-lvds0 { - compatible = "innolux,g121x1-l03"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pca9539 { - P05 { - gpio-hog; - gpios = <5 0>; - output-low; - line-name = "PCA9539-P05"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-b850v3.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-b850v3.dts deleted file mode 100644 index 167f74467..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-b850v3.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q-bx50v3.dtsi" - -/ { - model = "General Electric B850v3"; - compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q"; - - chosen { - stdout-path = &uart3; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; -}; - -&ldb { - fsl,dual-channel; - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - }; -}; - -&i2c2 { - pca9547_ddc: mux@70 { - compatible = "nxp,pca9547"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - mux2_i2c1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - }; - - mux2_i2c2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - }; - - mux2_i2c3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - - mux2_i2c4: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - }; - - mux2_i2c5: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - }; - - mux2_i2c6: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - - mux2_i2c7: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - - mux2_i2c8: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&mux2_i2c1>; -}; - -&mux1_i2c1 { - ads7830@4a { - compatible = "ti,ads7830"; - reg = <0x4a>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-ba16.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6q-ba16.dtsi deleted file mode 100644 index 308e11cea..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-ba16.dtsi +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Support for imx6 based Advantech DMS-BA16 Qseven module - * - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6q.dtsi" -#include - -/ { - memory { - reg = <0x10000000 0x40000000>; - }; - - backlight_lvds: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_display>; - pwms = <&pwm1 0 5000000>; - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 101 102 103 104 105 106 107 108 109 - 110 111 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 128 129 - 130 131 132 133 134 135 136 137 138 139 - 140 141 142 143 144 145 146 147 148 149 - 150 151 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 168 169 - 170 171 172 173 174 175 176 177 178 179 - 180 181 182 183 184 185 186 187 188 189 - 190 191 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 208 209 - 210 211 212 213 214 215 216 217 218 219 - 220 221 222 223 224 225 226 227 228 229 - 230 231 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 248 249 - 250 251 252 253 254 255>; - default-brightness-level = <255>; - enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_lvds: regulator-lvds { - compatible = "regulator-fixed"; - regulator-name = "lvds_ppen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator-usbh1vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: n25q032@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - reg = <0>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0xc0000>; - }; - - partition@c0000 { - label = "env"; - reg = <0xc0000 0x10000>; - }; - - partition@d0000 { - label = "spare"; - reg = <0xd0000 0x130000>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio7>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - regulators { - vdd_bcore1: bcore1 { - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1420000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bcore2: bcore2 { - regulator-min-microvolt = <1420000>; - regulator-max-microvolt = <1420000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bpro: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bmem: bmem { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bio: bio { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bperi: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_ldo1: ldo1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1860000>; - }; - - vdd_ldo2: ldo2 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1860000>; - }; - - vdd_ldo3: ldo3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3440000>; - }; - - vdd_ldo4: ldo4 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3440000>; - }; - - vdd_ldo5: ldo5 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo6: ldo6 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo7: ldo7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo8: ldo8 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo9: ldo9 { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo10: ldo10 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - vdd_ldo11: ldo11 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - rtc@32 { - compatible = "epson,rx8010"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x32>; - interrupt-parent = <&gpio4>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - fsl,tx-swing-full = <103>; - fsl,tx-swing-low = <103>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -&sata { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhub>; - vbus-supply = <®_usb_h1_vbus>; - reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; - bus-width = <8>; - vmmc-supply = <&vdd_bperi>; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_display: dispgrp { - fsl,pins = < - /* BLEN_OUT */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - /* LVDS_PPEN_OUT */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SPI1 CS */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* FEC Reset */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - /* AR8033 Interrupt */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* GPIO 0-7 */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 - /* SUS_S3_OUT to CPLD */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe Reset */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* PCIe Wake */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - /* PMIC Interrupt */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - /* RTC_INT */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbhub: usbhubgrp { - fsl,pins = < - /* HUB_RESET */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - /* uSDHC2 CD */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_reset: usdhc3grp-reset { - fsl,pins = < - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - /* uSDHC4 CD */ - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 - /* uSDHC4 SDIO PWR */ - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - /* uSDHC4 SDIO WP */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - /* uSDHC4 SDIO LED */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6q-bx50v3.dtsi deleted file mode 100644 index e4a415fd8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Copyright 2015 Timesys Corporation. - * Copyright 2015 General Electric Company - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6q-ba16.dtsi" - -/ { - clocks { - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <22000000>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - reg_wl18xx_vmmc: regulator-wl18xx { - compatible = "regulator-fixed"; - regulator-name = "vwl1807"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-name = "3P3V_wlan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "fsl,imx6q-ba16-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-ba16-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&ecspi5 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5>; - status = "okay"; - - m25_eeprom: m25p80@0 { - compatible = "atmel,at25"; - spi-max-frequency = <20000000>; - size = <0x8000>; - pagesize = <64>; - reg = <0>; - address-width = <16>; - }; -}; - -&i2c1 { - pca9547: mux@70 { - compatible = "nxp,pca9547"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - mux1_i2c1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - ads7830: ads7830@48 { - compatible = "ti,ads7830"; - reg = <0x48>; - }; - - mma8453: mma8453@1c { - compatible = "fsl,mma8453"; - reg = <0x1c>; - }; - }; - - mux1_i2c2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - - eeprom: eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; - - mpl3115: mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - }; - - mux1_i2c3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - }; - - mux1_i2c4: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&mclk>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - }; - - mux1_i2c5: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - pca9539: pca9539@74 { - compatible = "nxp,pca9539"; - reg = <0x74>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - P06 { - gpio-hog; - gpios = <6 0>; - output-low; - line-name = "PCA9539-P06"; - }; - - P07 { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; - - P10 { - gpio-hog; - gpios = <8 0>; - output-low; - line-name = "PCA9539-P10"; - }; - - P11 { - gpio-hog; - gpios = <9 0>; - output-low; - line-name = "PCA9539-P11"; - }; - - P12 { - gpio-hog; - gpios = <10 0>; - output-low; - line-name = "PCA9539-P12"; - }; - - P13 { - gpio-hog; - gpios = <11 0>; - output-low; - line-name = "PCA9539-P13"; - }; - - P14 { - gpio-hog; - gpios = <12 0>; - output-low; - line-name = "PCA9539-P14"; - }; - - P15 { - gpio-hog; - gpios = <13 0>; - output-low; - line-name = "PCA9539-P15"; - }; - - P16 { - gpio-hog; - gpios = <14 0>; - output-low; - line-name = "PCA9539-P16"; - }; - - P17 { - gpio-hog; - gpios = <15 0>; - output-low; - line-name = "PCA9539-P17"; - }; - }; - }; - - mux1_i2c6: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - }; - - mux1_i2c7: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x6>; - }; - - mux1_i2c8: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x7>; - }; - }; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - vmmc-supply = <®_wl18xx_vmmc>; - no-1-8-v; - non-removable; - wakeup-source; - keep-power-in-suspend; - cap-power-off-card; - max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; - tcxo-clock-frequency = <26000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-cm-fx6.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-cm-fx6.dts deleted file mode 100644 index a150bca84..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright 2013 CompuLab Ltd. - * - * Author: Valentin Raevsky - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "imx6q.dtsi" - -/ { - model = "CompuLab CM-FX6"; - compatible = "compulab,cm-fx6", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat-led { - label = "Heartbeat"; - gpios = <&gpio2 31 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { - compatible = "regulator-fixed"; - regulator-name = "regulator-pcie-power-on-gpio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: usb_h1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: usb_otg_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&cpu0 { - /* - * Although the imx6q fuse indicates that 1.2GHz operation is possible, - * the module behaves unstable at this frequency. Hence, remove the - * 1.2GHz operation point here. - */ - operating-points = < - /* kHz uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - clock-frequency = <100000>; - - eeprom@50 { - compatible = "at24,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 - >; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - vdd-supply = <®_pcie_power_on_gpio>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-cubox-i.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-cubox-i.dts deleted file mode 100644 index 353425edc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-cubox-i.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-cubox-i.dtsi" - -/ { - model = "SolidRun Cubox-i Dual/Quad"; - compatible = "solidrun,cubox-i/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <9>; - fsl,no-spread-spectrum; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts deleted file mode 100644 index fd0ad9a88..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2013 Sascha Hauer - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DTS_V1__ -#define __DTS_V1__ -/dts-v1/; -#endif - -#include "imx6q.dtsi" -#include "imx6qdl-dfi-fs700-m60.dtsi" - -/ { - model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; - compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts deleted file mode 100644 index 908dab68b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ /dev/null @@ -1,487 +0,0 @@ -/* - * Copyright 2013 Data Modul AG - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include -#include "imx6q.dtsi" - -/ { - model = "Data Modul eDM-QMX6 Board"; - compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; - - aliases { - gpio7 = &stmpe_gpio1; - gpio8 = &stmpe_gpio2; - stmpe-i2c0 = &stmpe1; - stmpe-i2c1 = &stmpe2; - }; - - memory { - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_switch: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_switch"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 12 0>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_host1: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_host1_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 0>; - enable-active-high; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led-blue { - label = "blue"; - gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-green { - label = "green"; - gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - led-pink { - label = "pink"; - gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - led-red { - label = "red"; - gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&ecspi5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5>; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio1 12 0>; - status = "okay"; - - flash: m25p80@0 { - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 0>; - phy-supply = <&vgen2_1v2_eth>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2 - &pinctrl_stmpe1 - &pinctrl_stmpe2 - &pinctrl_pfuze>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - interrupt-parent = <&gpio3>; - interrupts = <20 8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_1v2_eth: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vdd_high_in: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - stmpe1: stmpe1601@40 { - compatible = "st,stmpe1601"; - reg = <0x40>; - interrupts = <30 0>; - interrupt-parent = <&gpio3>; - vcc-supply = <&sw2_reg>; - vio-supply = <&sw2_reg>; - - stmpe_gpio1: stmpe_gpio { - #gpio-cells = <2>; - compatible = "st,stmpe-gpio"; - }; - }; - - stmpe2: stmpe1601@44 { - compatible = "st,stmpe1601"; - reg = <0x44>; - interrupts = <2 0>; - interrupt-parent = <&gpio5>; - vcc-supply = <&sw2_reg>; - vio-supply = <&sw2_reg>; - - stmpe_gpio2: stmpe_gpio { - #gpio-cells = <2>; - compatible = "st,stmpe-gpio"; - }; - }; - - temp1: ad7414@4c { - compatible = "ad,ad7414"; - reg = <0x4c>; - }; - - temp2: ad7414@4d { - compatible = "ad,ad7414"; - reg = <0x4d>; - }; - - rtc: m41t62@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-dmo-edmqmx6 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5rp-1 { - fsl,pins = < - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 - >; - }; - - pinctrl_pfuze: pfuze100grp1 { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 - >; - }; - - pinctrl_stmpe1: stmpe1grp { - fsl,pins = ; - }; - - pinctrl_stmpe2: stmpe2grp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 8 0>; - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host1>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - vmmc-supply = <®_3p3v>; - non-removable; - bus-width = <8>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-evi.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-evi.dts deleted file mode 100644 index 6de21ff47..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-evi.dts +++ /dev/null @@ -1,506 +0,0 @@ -/* - * Copyright 2016 United Western Technologies. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include -#include - -/ { - model = "Uniwest Evi"; - compatible = "uniwest,imx6q-evi", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x40000000>; - }; - - reg_usbh1_vbus: regulator-usbhubreset { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_hubreset>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - }; - - reg_usb_otg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgvbus>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - panel { - compatible = "sharp,lq101k1ly04"; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; - status = "okay"; -}; - -&ecspi3 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, - <&gpio4 25 GPIO_ACTIVE_LOW>, - <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>; - status = "okay"; -}; - -&ecspi5 { - fsl,spi-num-chipselects = <4>; - cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, - <&gpio1 13 GPIO_ACTIVE_LOW>, - <&gpio1 12 GPIO_ACTIVE_LOW>, - <&gpio2 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>; - status = "okay"; - - eeprom: m95m02@1 { - compatible = "st,m95m02", "atmel,at25"; - size = <262144>; - pagesize = <256>; - address-width = <24>; - spi-max-frequency = <5000000>; - reg = <1>; - }; - - pb_rtc: rtc@3 { - compatible = "nxp,rtc-pcf2123"; - spi-max-frequency = <2450000>; - spi-cs-high; - reg = <3>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpminand>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - clock-frequency = <100000>; - scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0x0b>; - sbs,poll-retry-count = <100>; - sbs,i2c-retry-count = <100>; - }; -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - status = "okay"; -}; - -&weim { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>; - fsl,weim-cs-gpr = <&gpr>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* pwr mcu alert irq */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* remainder ???? */ - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi1cs: ecspi1csgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068 - >; - }; - - pinctrl_ecspi3cs: ecspi3csgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 - >; - }; - - pinctrl_ecspi5: ecspi5grp { - fsl,pins = < - MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1 - MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1 - MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1 - >; - }; - - pinctrl_ecspi5cs: ecspi5csgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpminand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1 - >; - }; - - pinctrl_weimcs: weimcsgrp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 - >; - }; - - pinctrl_weimfpga: weimfpgagrp { - fsl,pins = < - /* weim misc */ - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1 - MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1 - MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1 - MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1 - MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1 - MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1 - /* weim data */ - MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - /* weim address */ - MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1 - MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0 - /* usbh1_b OC */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_usbh1_hubreset: usbh1hubresetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usbotgvbus: usbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gk802.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gk802.dts deleted file mode 100644 index b715deb4e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gk802.dts +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2013 Philipp Zabel - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include -#include "imx6q.dtsi" - -/ { - model = "Zealz GK802"; - compatible = "zealz,imx6q-gk802", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - recovery-button { - label = "recovery"; - gpios = <&gpio3 16 1>; - linux,code = <0x198>; /* KEY_RESTART */ - wakeup-source; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -/* Internal I2C */ -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */ - eeprom: dm2016@51 { - compatible = "sdmc,dm2016"; - reg = <0x51>; - }; -}; - -/* External I2C via HDMI */ -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-gk802 { - pinctrl_hog: hoggrp { - fsl,pins = < - /* Recovery button, active-low */ - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1 - /* RTL8192CU enable GPIO, active-low */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - >; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* External USB-A port (USBOTG) */ -&usbotg { - disable-over-current; - status = "okay"; -}; - -/* Internal USB port (USBH1), connected to RTL8192CU */ -&usbh1 { - disable-over-current; - status = "okay"; -}; - -/* External microSD */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* Internal microSD */ -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw51xx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gw51xx.dts deleted file mode 100644 index 8e8bcd8fe..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw51xx.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw51xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX"; - compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw52xx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gw52xx.dts deleted file mode 100644 index a12c47e5e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw52xx.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw52xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX"; - compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw53xx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gw53xx.dts deleted file mode 100644 index d76aaa83d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw53xx.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw53xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; - compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw5400-a.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gw5400-a.dts deleted file mode 100644 index 747bc104a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ /dev/null @@ -1,524 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include -#include "imx6q.dtsi" - -/ { - model = "Gateworks Ventana GW5400-A"; - compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; - - /* these are used by bootloader for disabling nodes */ - aliases { - ethernet1 = ð1; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - led0 = &led0; - led1 = &led1; - led2 = &led2; - ssi0 = &ssi1; - spi0 = &ecspi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "sst,w25q256", "jedec,spi-nor"; - spi-max-frequency = <30000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; - }; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <&sw4_reg>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&iomuxc { - imx6q-gw5400-a { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw54xx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gw54xx.dts deleted file mode 100644 index 6e8f53e92..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw54xx.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw54xx.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; - compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw551x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gw551x.dts deleted file mode 100644 index 2c7feeef1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw551x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw551x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW551X"; - compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw552x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gw552x.dts deleted file mode 100644 index f87a8fa6e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw552x.dts +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-gw552x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW552X"; - compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw553x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-gw553x.dts deleted file mode 100644 index e9c224cea..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-gw553x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-gw553x.dtsi" - -/ { - model = "Gateworks Ventana i.MX6 Dual/Quad GW553X"; - compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-h100.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-h100.dts deleted file mode 100644 index 65e66f994..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-h100.dts +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Copyright (C) 2015 Lucas Stach - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" - -/ { - model = "Auvidea H100"; - compatible = "auvidea,h100", "fsl,imx6q"; - - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = &uart2; - }; - - hdmi_osc: hdmi-osc { - compatible = "fixed-clock"; - clock-output-names = "hdmi-osc"; - clock-frequency = <27000000>; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_leds>; - - led0: power { - label = "power"; - gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led1: stream { - label = "stream"; - gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2: rec { - label = "rec"; - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_hdmi: regulator-hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_reg_hdmi>; - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - regulator-name = "V_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_nvcc_sd2: regulator-nvcc-sd2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_reg_nvcc_sd2>; - compatible = "regulator-gpio"; - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; - }; - - reg_usbh1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbh1_vbus>; - regulator-name = "USB_H1_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbotg_vbus>; - regulator-name = "USB_OTG_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound-sgtl5000 { - compatible = "fsl,imx-audio-sgtl5000"; - model = "H100 on-board codec"; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-ext-port = <5>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; -}; - -&audmux { - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_i2c1>; - status = "okay"; - - eeprom: 24c02@51 { - compatible = "microchip,24c02", "at24"; - reg = <0x51>; - }; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - sgtl5000: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_sgtl5000>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; - - tc358743: tc358743@0f { - compatible = "toshiba,tc358743"; - reg = <0x0f>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_tc358743>; - clocks = <&hdmi_osc>; - clock-names = "refclk"; - reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - /* IRQ has a wrong pull resistor which renders it useless */ - - port@0 { - tc358743_out: endpoint { - remote-endpoint = <&mipi_csi2_in>; - data-lanes = <1 2 3 4>; - clock-lanes = <0>; - clock-noncontinuous; - link-frequencies = /bits/ 64 <297000000>; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_i2c2>; - status = "okay"; -}; - -&iomuxc { - h100 { - pinctrl_h100_hdmi: h100-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_h100_i2c1: h100-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_h100_i2c2: h100-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_h100_leds: pinctrl-h100-leds { - fsl,pins = < - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 - >; - }; - - pinctrl_h100_reg_hdmi: h100-reg-hdmi { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 - >; - }; - - pinctrl_h100_reg_nvcc_sd2: h100-reg-nvcc-sd2 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_h100_sgtl5000: h100-sgtl5000 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_h100_tc358743: h100-tc358743 { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - >; - }; - - pinctrl_h100_uart2: h100-uart2 { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_h100_usbotg_id: hummingboard-usbotg-id { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - >; - }; - - pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_h100_usdhc2: h100-usdhc2 { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - - pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - }; -}; - -&mipi_csi { - status = "okay"; - - port@0 { - mipi_csi2_in: endpoint { - remote-endpoint = <&tc358743_out>; - data-lanes = <1 2 3 4>; - clock-lanes = <0>; - clock-noncontinuous; - link-frequencies = /bits/ 64 <297000000>; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_uart2>; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_h100_usbotg_id>; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_h100_usdhc2>; - pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_nvcc_sd2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-hummingboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-hummingboard.dts deleted file mode 100644 index 1884c1678..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-hummingboard.dts +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) - * Based on dt work by Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-hummingboard.dtsi" - -/ { - model = "SolidRun HummingBoard Dual/Quad"; - compatible = "solidrun,hummingboard/q", "fsl,imx6q"; -}; - -&sata { - status = "okay"; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-icore-rqs.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-icore-rqs.dts deleted file mode 100644 index 005318865..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-icore-rqs.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2015 Amarula Solutions B.V. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-icore-rqs.dtsi" - -/ { - model = "Engicam i.CoreM6 Quad SOM"; - compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx-audio-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&i2c3 { - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - VDDD-supply = <®_1p8v>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-marsboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-marsboard.dts deleted file mode 100644 index f7995c513..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-marsboard.dts +++ /dev/null @@ -1,403 +0,0 @@ -/* - * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com) - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include - -/ { - model = "Embest MarS Board i.MX6Dual"; - compatible = "embest,imx6q-marsboard", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x40000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user1 { - label = "imx6:green:user1"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "imx6:green:user2"; - gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - fsl,spi-num-chipselects = <1>; - status = "okay"; - - m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - non-removable; - status = "okay"; -}; - -&iomuxc { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* RGMII_nRST */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-nitrogen6_max.dts deleted file mode 100644 index d417457ca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-nitrogen6_max.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-nitrogen6_max.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Nitrogen6_MAX Board"; - compatible = "boundary,imx6q-nitrogen6_max", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-nitrogen6x.dts deleted file mode 100644 index d1686339d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-nitrogen6x.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-nitrogen6x.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Nitrogen6x Board"; - compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-novena.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-novena.dts deleted file mode 100644 index 1723e89e3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-novena.dts +++ /dev/null @@ -1,785 +0,0 @@ -/* - * Copyright 2015 Sutajio Ko-Usagi PTE LTD - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include -#include - -/ { - model = "Kosagi Novena Dual/Quad"; - compatible = "kosagi,imx6q-novena", "fsl,imx6q"; - - chosen { - stdout-path = &uart2; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 10000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_novena>; - power-supply = <®_lvds_lcd>; - brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>; - default-brightness-level = <12>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys_novena>; - - user-button { - label = "User Button"; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - lid { - label = "Lid"; - gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_novena>; - - heartbeat { - label = "novena:white:panel"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - panel: panel { - compatible = "innolux,n133hse-ea1", "simple-panel"; - backlight = <&backlight>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_audio_codec: regulator-audio-codec { - compatible = "regulator-fixed"; - regulator-name = "es8328-power"; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <400000>; - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_display: regulator-display { - compatible = "regulator-fixed"; - regulator-name = "lcd-display-power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lvds_lcd: regulator-lvds-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd-lvds-power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "pcie-bus-power"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_sata: regulator-sata { - compatible = "regulator-fixed"; - regulator-name = "sata-power"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <10000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-es8328"; - model = "imx-audio-es8328"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-amp-supply = <®_audio_codec>; - jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>; - audio-routing = - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Speaker", "audio-amp", - "Headphone", "ROUT1", - "Headphone", "LOUT1", - "LINPUT1", "Mic Jack", - "RINPUT1", "Mic Jack", - "Mic Jack", "Mic Bias"; - mux-int-port = <0x1>; - mux-ext-port = <0x3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_novena>; - status = "okay"; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3_novena>; - fsl,spi-num-chipselects = <3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_novena>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - rxc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - txc-skew-ps = <3000>; - txen-skew-ps = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <3000>; - txd1-skew-ps = <3000>; - txd2-skew-ps = <3000>; - txd3-skew-ps = <3000>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_novena>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_novena>; - status = "okay"; - - accel: mma8452@1c { - compatible = "fsl,mma8452"; - reg = <0x1c>; - }; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - sbs_battery: bq20z75@0b { - compatible = "sbs,sbs-battery"; - reg = <0x0b>; - sbs,i2c-retry-count = <50>; - }; - - touch: stmpe811@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - #address-cells = <1>; - #size-cells = <0>; - irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe_novena>; - vio-supply = <®_3p3v>; - vcc-supply = <®_3p3v>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_novena>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - reg_sw1a: sw1a { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - reg_sw1c: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw2: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw3a: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw3b: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sw4: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - reg_swbst: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - }; - - reg_snvs: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vref: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen2: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - reg_vgen3: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vgen4: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_novena>; - status = "okay"; - - codec: es8328@11 { - compatible = "everest,es8328"; - reg = <0x11>; - DVDD-supply = <®_audio_codec>; - AVDD-supply = <®_audio_codec>; - PVDD-supply = <®_audio_codec>; - HPVDD-supply = <®_audio_codec>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sound_novena>; - clocks = <&clks IMX6QDL_CLK_CKO1>; - assigned-clocks = <&clks IMX6QDL_CLK_CKO>, - <&clks IMX6QDL_CLK_CKO1_SEL>, - <&clks IMX6QDL_CLK_PLL4_AUDIO>, - <&clks IMX6QDL_CLK_CKO1>; - assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>, - <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>, - <&clks IMX6QDL_CLK_OSC>, - <&clks IMX6QDL_CLK_CKO1_PODF>; - assigned-clock-rates = <0 0 722534400 22579200>; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp_novena>; - linux,keymap = < - MATRIX_KEY(1, 1, KEY_CONFIG) - >; - status = "okay"; -}; - -&ldb { - fsl,dual-channel; - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "jeida"; - fsl,data-width = <24>; - fsl,panel = <&panel>; - status = "okay"; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_novena>; - reset-gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sata { - target-supply = <®_sata>; - fsl,transmit-level-mV = <1025>; - fsl,transmit-boost-mdB = <0>; - fsl,transmit-atten-16ths = <8>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_novena>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_novena>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_novena>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - dr_mode = "otg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_novena>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_swbst>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_novena>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_novena>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux_novena: audmuxgrp-novena { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight_novena: backlightgrp-novena { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 - >; - }; - - pinctrl_ecspi3_novena: ecspi3grp-novena { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_enet_novena: enetgrp-novena { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* Ethernet reset */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 - >; - }; - - pinctrl_fpga_gpio: fpgagpiogrp-novena { - fsl,pins = < - /* FPGA power */ - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 - /* Reset */ - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - /* FPGA GPIOs */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 - >; - }; - - pinctrl_fpga_eim: fpgaeimgrp-novena { - fsl,pins = < - /* FPGA power */ - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1 - /* Reset */ - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - /* FPGA GPIOs */ - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1 - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1 - MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1 - MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1 - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1 - MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1 - >; - }; - - pinctrl_gpio_keys_novena: gpiokeysgrp-novena { - fsl,pins = < - /* User button */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 - /* PCIe Wakeup */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0 - /* Lid switch */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 - >; - }; - - pinctrl_hdmi_novena: hdmigrp-novena { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 - >; - }; - - pinctrl_i2c1_novena: i2c1grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_novena: i2c2grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_novena: i2c3grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp_novena: kppgrp-novena { - fsl,pins = < - /* Front panel button */ - MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1 - /* Fake column driver, not connected */ - MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1 - >; - }; - - pinctrl_leds_novena: ledsgrp-novena { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1 - >; - }; - - pinctrl_pcie_novena: pciegrp-novena { - fsl,pins = < - /* Reset */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 - /* Power On */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 - /* Wifi kill */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 - >; - }; - - pinctrl_sata_novena: satagrp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1 - >; - }; - - pinctrl_senoko_novena: senokogrp-novena { - fsl,pins = < - /* Senoko IRQ line */ - MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048 - /* Senoko reset line */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 - >; - }; - - pinctrl_sound_novena: soundgrp-novena { - fsl,pins = < - /* Audio power regulator */ - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 - /* Headphone plug */ - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_stmpe_novena: stmpegrp-novena { - fsl,pins = < - /* Touchscreen interrupt */ - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 - >; - }; - - pinctrl_uart2_novena: uart2grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3_novena: uart3grp-novena { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4_novena: uart4grp-novena { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg_novena: usbotggrp-novena { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2_novena: usdhc2grp-novena { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - /* Write protect */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 - /* Card detect */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 - >; - }; - - pinctrl_usdhc3_novena: usdhc3grp-novena { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-phytec-pbab01.dts deleted file mode 100644 index c139ac0eb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx6q-phytec-pfla02.dtsi" -#include "imx6qdl-phytec-pbab01.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; - compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi deleted file mode 100644 index cd20d0a94..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx6q.dtsi" -#include "imx6qdl-phytec-pfla02.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x80000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx6q-pinfunc.h deleted file mode 100644 index 9fc6120a1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-pinfunc.h +++ /dev/null @@ -1,1047 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX6Q_PINFUNC_H -#define __DTS_IMX6Q_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 -#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 -#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 -#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 -#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 -#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 -#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 -#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 -#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 -#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 -#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 -#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 -#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 -#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 -#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 -#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 -#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 -#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 -#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 -#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 -#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 -#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 -#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 -#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 -#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 -#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 -#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 -#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 -#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 -#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 -#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 -#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 -#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 -#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 -#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 -#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 -#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 -#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 -#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 -#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 -#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 -#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 -#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 -#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 -#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 -#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 -#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 -#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 -#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 -#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 -#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 -#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 -#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 -#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 -#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 -#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 -#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 -#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 -#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 -#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 -#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 -#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 -#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 -#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 -#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 -#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 -#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 -#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 -#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 -#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 -#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 -#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 -#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 -#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 -#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 -#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 -#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 -#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 -#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 -#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 -#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 -#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 -#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 -#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 -#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 -#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 -#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 -#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 -#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 -#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 -#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 -#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 -#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 -#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 -#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 -#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 -#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 -#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 -#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 -#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 -#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 -#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 -#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 -#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 -#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 -#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 -#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 -#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 -#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 -#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 -#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 -#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 -#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 -#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 -#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 -#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 -#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 -#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 -#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 -#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 -#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 -#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 -#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 -#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 -#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 -#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 -#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 -#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 -#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 -#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 -#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 -#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 -#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 -#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 -#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 -#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 -#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 -#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 -#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 -#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 -#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 -#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 -#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 -#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 -#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 - -#endif /* __DTS_IMX6Q_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-rex-pro.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-rex-pro.dts deleted file mode 100644 index 90ea61ae0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-rex-pro.dts +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-rex.dtsi" - -/ { - model = "Rex Pro i.MX6 Quad Board"; - compatible = "rex,imx6q-rex-pro", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x80000000>; - }; -}; - -&ecspi3 { - flash: m25p80@0 { - compatible = "sst,sst25vf032b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-sabreauto.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-sabreauto.dts deleted file mode 100644 index 334b9247e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-sabreauto.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Automotive Board"; - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-sabrelite.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-sabrelite.dts deleted file mode 100644 index 66d10d8d5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-sabrelite.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-sabrelite.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Lite Board"; - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-sabresd.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-sabresd.dts deleted file mode 100644 index 9cbdfe7a0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-sabresd.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 Quad SABRE Smart Device Board"; - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-sbc6x.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-sbc6x.dts deleted file mode 100644 index 255733063..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-sbc6x.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright 2013 Pavel Machek - * - * The code contained herein is licensed under the GNU General Public - * License V2. - */ - -/dts-v1/; -#include "imx6q.dtsi" - -/ { - model = "MicroSys sbc6x board"; - compatible = "microsys,sbc6x", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x80000000>; - }; -}; - - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&iomuxc { - imx6q-sbc6x { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-tbs2910.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-tbs2910.dts deleted file mode 100644 index 06f492e17..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-tbs2910.dts +++ /dev/null @@ -1,430 +0,0 @@ -/* - * Copyright 2014 Soeren Moch - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6q.dtsi" -#include -#include - -/ { - model = "TBS2910 Matrix ARM mini PC"; - compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x10000000 0x80000000>; - }; - - fan { - compatible = "gpio-fan"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_fan>; - gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 3000 1>; - }; - - ir_recv { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - blue { - label = "blue_status_led"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound-sgtl5000 { - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - compatible = "fsl,imx-audio-sgtl5000"; - model = "On-board Codec"; - mux-ext-port = <3>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "On-board SPDIF"; - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - sgtl5000: sgtl5000@0a { - clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - rtc: ds1307@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sata { - fsl,transmit-level-mV = <1104>; - fsl,transmit-boost-mdB = <3330>; - fsl,transmit-atten-16ths = <16>; - fsl,receive-eq-mdB = <3000>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_5p0v>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_5p0v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - voltage-ranges = <3300 3300>; - non-removable; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 - >; - }; - - pinctrl_gpio_fan: gpiofangrp { - fsl,pins = < - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 - >; - }; - - pinctrl_hdmi: hdmigrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = ; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-ts4900.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-ts4900.dts deleted file mode 100644 index 9b81ebc8b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-ts4900.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-ts4900.dtsi" - -/ { - model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; - compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts deleted file mode 100644 index 65e95ae75..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&kpp { - status = "disabled"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1010.dts deleted file mode 100644 index 20cd0e7b3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1010.dts +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1010 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts deleted file mode 100644 index 9ed243b70..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&ET070001DM6>; - - ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&kpp { - status = "disabled"; -}; - -®_can_xcvr { - status = "disabled"; -}; - -&touchscreen { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1020.dts deleted file mode 100644 index 347b531d3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1020.dts +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1020 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_3v3>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1036.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1036.dts deleted file mode 100644 index 7c152e327..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1036.dts +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1036 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &display; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - display: display@di0 { - compatible = "fsl,imx-parallel-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_2>; - interface-pix-fmt = "rgb24"; - status = "okay"; - - port { - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - display-timings { - native-mode = <&vga>; - - vga: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&ds1339 { - status = "disabled"; -}; - -&gpmi { - status = "disabled"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&ipu2 { - status = "disabled"; -}; - -®_lcd0_pwr { - status = "disabled"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <4>; - non-removable; - no-1-8-v; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1110.dts deleted file mode 100644 index 0433e220a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-1110.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1110 Module"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &lvds0; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 0>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 0>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&kpp { - status = "disabled"; /* pad conflict with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds_timing0>; - lvds_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "disabled"; - - display-timings { - native-mode = <&lvds_timing1>; - lvds_timing1: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts deleted file mode 100644 index d78b129d0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright 2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-tx6.dtsi" - -/ { - model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; - compatible = "karo,imx6q-tx6q", "fsl,imx6q"; - - aliases { - display = &lvds0; - ipu1 = &ipu2; - lvds0 = &lvds0; - lvds1 = &lvds1; - }; - - backlight0: backlight0 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd0_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - backlight1: backlight1 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd1_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; -}; - -&can1 { - status = "disabled"; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&i2c3 { - polytouch1: eeti@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eeti>; - interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; -}; - -&ipu2 { - status = "disabled"; -}; - -&kpp { - status = "disabled"; /* pads partially clash with backlight1 PWM */ -}; - -&ldb { - status = "okay"; - - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds0_timing1>; - - lvds0_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds0_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds0_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - lvds1: lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&lvds1_timing2>; - - lvds1_timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - lvds1_timing1: VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <31>; - vfront-porch = <12>; - hsync-len = <96>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - lvds1_timing2: nl12880bc20 { - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <50>; - hfront-porch = <50>; - vback-porch = <5>; - vfront-porch = <5>; - hsync-len = <60>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-udoo.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-udoo.dts deleted file mode 100644 index c3e64ff3d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-udoo.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-udoo.dtsi" - -/ { - model = "Udoo i.MX6 Quad Board"; - compatible = "udoo,imx6q-udoo", "fsl,imx6q"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-utilite-pro.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-utilite-pro.dts deleted file mode 100644 index 61990630a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright 2013 CompuLab Ltd. - * Copyright 2016 Christopher Spinrath - * - * Based on the devicetree distributed with the vendor kernel for the - * Utilite Pro: - * Copyright 2013 CompuLab Ltd. - * Author: Valentin Raevsky - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "imx6q-cm-fx6.dts" - -/ { - model = "CompuLab Utilite Pro"; - compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q"; - - aliases { - ethernet1 = ð1; - rtc0 = &em3027; - rtc1 = &snvs_rtc; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - linux,code = ; - gpio-key,wakeup; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom@50 { - compatible = "at24,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - em3027: rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 - >; - }; -}; - -&pcie { - pcie@0,0 { - reg = <0x000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - - /* non-removable i211 ethernet card */ - eth1: intel,i211@pcie0,0 { - reg = <0x010000 0 0 0 0>; - }; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - no-1-8-v; - broken-cd; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-wandboard-revb1.dts deleted file mode 100644 index 9207d80f9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-wandboard-revb1.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-wandboard-revb1.dtsi" - -/ { - model = "Wandboard i.MX6 Quad Board rev B1"; - compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q-wandboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx6q-wandboard.dts deleted file mode 100644 index 4a8a6ee13..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q-wandboard.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -/dts-v1/; -#include "imx6q.dtsi" -#include "imx6qdl-wandboard-revc1.dtsi" - -/ { - model = "Wandboard i.MX6 Quad Board"; - compatible = "wand,imx6q-wandboard", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x80000000>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6q.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6q.dtsi deleted file mode 100644 index e9a5d0b8c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6q.dtsi +++ /dev/null @@ -1,337 +0,0 @@ - -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include "imx6q-pinfunc.h" -#include "imx6qdl.dtsi" - -/ { - aliases { - ipu1 = &ipu2; - spi4 = &ecspi5; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - soc { - ocram: sram@00900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x40000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips-bus@02000000 { /* AIPS1 */ - spba-bus@02000000 { - ecspi5: ecspi@02018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02018000 0x4000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6Q_CLK_ECSPI5>, - <&clks IMX6Q_CLK_ECSPI5>; - clock-names = "ipg", "per"; - dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6q-iomuxc"; - }; - }; - - sata: sata@02200000 { - compatible = "fsl,imx6q-ahci"; - reg = <0x02200000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SATA>, - <&clks IMX6QDL_CLK_SATA_REF_100M>, - <&clks IMX6QDL_CLK_AHB>; - clock-names = "sata", "sata_ref", "ahb"; - status = "disabled"; - }; - - gpu_vg: gpu@02204000 { - compatible = "vivante,gc"; - reg = <0x02204000 0x4000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_GPU2D_CORE>; - clock-names = "bus", "core"; - power-domains = <&gpc 1>; - }; - - ipu2: ipu@02800000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ipu"; - reg = <0x02800000 0x400000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPU2>, - <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; - resets = <&src 4>; - - ipu2_csi0: port@0 { - reg = <0>; - }; - - ipu2_csi1: port@1 { - reg = <1>; - }; - - ipu2_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu2_di0_disp0: disp0-endpoint { - }; - - ipu2_di0_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_mux_2>; - }; - - ipu2_di0_mipi: mipi-endpoint { - remote-endpoint = <&mipi_mux_2>; - }; - - ipu2_di0_lvds0: lvds0-endpoint { - remote-endpoint = <&lvds0_mux_2>; - }; - - ipu2_di0_lvds1: lvds1-endpoint { - remote-endpoint = <&lvds1_mux_2>; - }; - }; - - ipu2_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu2_di1_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_mux_3>; - }; - - ipu2_di1_mipi: mipi-endpoint { - remote-endpoint = <&mipi_mux_3>; - }; - - ipu2_di1_lvds0: lvds0-endpoint { - remote-endpoint = <&lvds0_mux_3>; - }; - - ipu2_di1_lvds1: lvds1-endpoint { - remote-endpoint = <&lvds1_mux_3>; - }; - }; - }; - }; - - display-subsystem { - compatible = "fsl,imx-display-subsystem"; - ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; - }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; - }; -}; - -&gpio1 { - gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>, - <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>, - <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>, - <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>, - <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>, - <&iomuxc 22 116 10>; -}; - -&gpio2 { - gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>, - <&iomuxc 31 44 1>; -}; - -&gpio3 { - gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>; -}; - -&gpio4 { - gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>; -}; - -&gpio5 { - gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>, - <&iomuxc 5 103 13>, <&iomuxc 18 150 14>; -}; - -&gpio6 { - gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>, - <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>, - <&iomuxc 31 86 1>; -}; - -&gpio7 { - gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; -}; - -&hdmi { - compatible = "fsl,imx6q-hdmi"; - - port@2 { - reg = <2>; - - hdmi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_hdmi>; - }; - }; - - port@3 { - reg = <3>; - - hdmi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_hdmi>; - }; - }; -}; - -&ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; - - lvds-channel@0 { - port@2 { - reg = <2>; - - lvds0_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds0>; - }; - }; - - port@3 { - reg = <3>; - - lvds0_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - port@2 { - reg = <2>; - - lvds1_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_lvds1>; - }; - }; - - port@3 { - reg = <3>; - - lvds1_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_lvds1>; - }; - }; - }; -}; - -&mipi_dsi { - ports { - port@2 { - reg = <2>; - - mipi_mux_2: endpoint { - remote-endpoint = <&ipu2_di0_mipi>; - }; - }; - - port@3 { - reg = <3>; - - mipi_mux_3: endpoint { - remote-endpoint = <&ipu2_di1_mipi>; - }; - }; - }; -}; - -&vpu { - compatible = "fsl,imx6q-vpu", "cnm,coda960"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apalis.dtsi deleted file mode 100644 index 99e323b57..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ /dev/null @@ -1,984 +0,0 @@ -/* - * Copyright 2014-2016 Toradex AG - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - model = "Toradex Apalis iMX6Q/D Module"; - compatible = "toradex,apalis_imx6q", "fsl,imx6q"; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - status = "disabled"; - }; - - /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */ - i2cddc: i2c@0 { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_ddc>; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */ - &gpio2 30 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - status = "disabled"; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - status = "disabled"; - }; - - /* on module USB hub */ - reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; - regulator-name = "usb_host_vbus_hub"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; - startup-delay-us = <2000>; - enable-active-high; - status = "okay"; - }; - - reg_usb_host_vbus: regulator-usb-host-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_usb_host_vbus_hub>; - status = "disabled"; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6q-apalis-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - sound_spdif: sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-in; - spdif-out; - status = "disabled"; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -/* Apalis SPI1 */ -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "disabled"; -}; - -/* Apalis SPI2 */ -&ecspi2 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "disabled"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@7 { - interrupt-parent = <&gpio1>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - reg = <7>; - }; - }; -}; - -/* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier - * board) - */ -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "disabled"; -}; - -/* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - /* STMPE811 touch screen controller */ - stmpe811@41 { - compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio4>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - reg = <0>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - }; -}; - -/* - * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused) - */ -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "recovery"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "disabled"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - fsl,dte-mode; - uart-has-rtscts; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_dte>; - fsl,dte-mode; - uart-has-rtscts; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_dte>; - fsl,dte-mode; - status = "disabled"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5_dte>; - fsl,dte-mode; - status = "disabled"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -/* MMC1 */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vqmmc-supply = <®_3p3v>; - bus-width = <8>; - voltage-ranges = <3300 3300>; - status = "disabled"; -}; - -/* SD1 */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_3p3v>; - bus-width = <4>; - voltage-ranges = <3300 3300>; - status = "disabled"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; - bus-width = <8>; - voltage-ranges = <3300 3300>; - non-removable; - status = "okay"; -}; - -&weim { - status = "disabled"; -}; - -&iomuxc { - /* pins used on module */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - - pinctrl_apalis_gpio1: gpio2io04grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 - >; - }; - - pinctrl_apalis_gpio2: gpio2io05grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 - >; - }; - - pinctrl_apalis_gpio3: gpio2io06grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 - >; - }; - - pinctrl_apalis_gpio4: gpio2io07grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 - >; - }; - - pinctrl_apalis_gpio5: gpio6io10grp { - fsl,pins = < - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 - >; - }; - - pinctrl_apalis_gpio6: gpio6io09grp { - fsl,pins = < - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 - >; - }; - - pinctrl_apalis_gpio7: gpio1io02grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 - >; - }; - - pinctrl_apalis_gpio8: gpio1io06grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_cam_mclk: cammclkgrp { - fsl,pins = < - /* CAM sys_mclk */ - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 - /* SPI1 cs */ - MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - /* SPI2 cs */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Ethernet PHY reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 - /* Ethernet PHY interrupt */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpio1io04grp { - fsl,pins = < - /* Power button */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c_ddc: gpioi2cddcgrp { - fsl,pins = < - /* DDC bitbang */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3_recovery: i2c3recoverygrp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 - >; - }; - - pinctrl_ipu1_lcdif: ipu1lcdifgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 - /* DE */ - MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 - /* HSync */ - MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 - /* VSync */ - MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 - MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 - MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 - MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 - MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 - MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 - MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 - MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 - MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 - MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 - MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 - MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 - MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 - MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 - MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 - MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 - MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 - MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 - MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 - MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 - MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 - MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 - MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 - MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 - MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 - >; - }; - - pinctrl_ipu2_vdac: ipu2vdacgrp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 - MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 - MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 - MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 - MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 - MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 - MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 - MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 - MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 - MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 - MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 - MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 - MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 - MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 - MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 - MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 - MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 - MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 - MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 - MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 - >; - }; - - pinctrl_mmc_cd: gpiommccdgrp { - fsl,pins = < - /* MMC1 CD */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { - fsl,pins = < - /* USBH_EN */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 - >; - }; - - pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { - fsl,pins = < - /* USBH_HUB_EN */ - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 - >; - }; - - pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { - fsl,pins = < - /* USBO1 power en */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 - >; - }; - - pinctrl_reset_moci: gpioresetmocigrp { - fsl,pins = < - /* RESET_MOCI control */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 - >; - }; - - pinctrl_sd_cd: gpiosdcdgrp { - fsl,pins = < - /* SD1 CD */ - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 - MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_touch_int: gpiotouchintgrp { - fsl,pins = < - /* STMPE811 interrupt */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_uart1_dce: uart1dcegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart1_dte: uart1dtegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 - >; - }; - - /* Additional DTR, DSR, DCD */ - pinctrl_uart1_ctrl: uart1ctrlgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - - pinctrl_uart2_dce: uart2dcegrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart2_dte: uart2dtegrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4_dce: uart4dcegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart4_dte: uart4dtegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5_dce: uart5dcegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - /* DTE mode */ - pinctrl_uart5_dte: uart5dtegrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apf6.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apf6.dtsi deleted file mode 100644 index 1ebf29f43..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apf6.dtsi +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright 2015 Armadeus Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-duration = <10>; - phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* Bluetooth */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* Wi-Fi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - tcxo-clock-frequency = <38400000>; - }; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&iomuxc { - apf6 { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* WL_EN */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* WL_IRQ */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi deleted file mode 100644 index edbce222c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ /dev/null @@ -1,479 +0,0 @@ -/* - * Copyright 2015 Armadeus Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - display@di0 { - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_disp1>; - - display-timings { - lw700 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - port { - display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - user-button { - label = "User button"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user-led { - label = "User LED"; - gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - }; - - sound { - compatible = "fsl,imx6-armadeus-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-armadeus-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, - <&gpio4 10 GPIO_ACTIVE_LOW>, - <&gpio4 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - touchscreen@48 { - compatible = "semtech,sx8654"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display_in>; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* GSM */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>; - uart-has-rtscts; - status = "okay"; -}; - -/* console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - vbus-supply = <®_usb_otg_vbus>; - dr_mode = "otg"; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpios>; - - apf6dev { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0 - >; - }; - - pinctrl_gpios: gpiosgrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 - >; - }; - - pinctrl_gsm: gsmgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_ipu1_disp1: ipu1disp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_touchscreen: touchscreengrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi deleted file mode 100644 index 54f4f0193..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ /dev/null @@ -1,418 +0,0 @@ -/* - * support fot the imx6 based aristainetos board - * - * Copyright (C) 2014 Heiko Schocher - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -/ { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator@2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: regulator@3 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - tmp103: tmp103@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - rtc@68 { - compatible = "dallas,m41t00"; - reg = <0x68>; - }; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 20 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>; - - imx6qdl-aristainetos { - pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1 - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi deleted file mode 100644 index 7fff02c40..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ /dev/null @@ -1,633 +0,0 @@ -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - }; - - regulators { - compatible = "simple-bus"; - - reg_2p5v: 2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; -}; - -&ecspi2 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - - flash: m25p80@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <04 0x8>; - - regulators { - bcore1 { - regulator-name = "bcore1"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bcore2 { - regulator-name = "bcore2"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bpro { - regulator-name = "bpro"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bperi { - regulator-name = "bperi"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bmem { - regulator-name = "bmem"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "ldo2"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1800000>; - }; - - ldo3 { - regulator-name = "ldo3"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4 { - regulator-name = "ldo4"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5 { - regulator-name = "ldo5"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6 { - regulator-name = "ldo6"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "ldo7"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo8 { - regulator-name = "ldo8"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9 { - regulator-name = "ldo9"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo10 { - regulator-name = "ldo10"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo11 { - regulator-name = "ldo11"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bio { - regulator-name = "bio"; - regulator-always-on = <1>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - tmp103: tmp103@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - expander: tca6416@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - }; - - rtc@68 { - compatible = "dallas,m41t00"; - reg = <0x68>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - eeprom@50{ - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@57{ - compatible = "atmel,24c64"; - reg = <0x57>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_HIGH>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - pinctrl_audmux: audmux { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */ - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi deleted file mode 100644 index ff41f8355..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (C) 2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" -#include -#include - -/ { - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 9 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_ir>; - }; - - pwmleds { - compatible = "pwm-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_pwm1>; - - front { - active-low; - label = "imx6:red:front"; - max-brightness = <248>; - pwms = <&pwm1 0 50000>; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "Integrated SPDIF"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_gpio_key>; - pinctrl-names = "default"; - - button_0 { - label = "Button 0"; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c3>; - - status = "okay"; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; -}; - -&iomuxc { - cubox_i { - pinctrl_cubox_i_hdmi: cubox-i-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_cubox_i_i2c2: cubox-i-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_cubox_i_i2c3: cubox-i-i2c3 { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_cubox_i_ir: cubox-i-ir { - fsl,pins = < - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 - >; - }; - - pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led { - fsl,pins = ; - }; - - pinctrl_cubox_i_spdif: cubox-i-spdif { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbh1: cubox-i-usbh1 { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_cubox_i_usbotg: cubox-i-usbotg { - /* - * The Cubox-i pulls ID low, but as it's pointless - * leaving it as a pull-up, even if it is just 10uA. - */ - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 - >; - }; - - pinctrl_cubox_i_usdhc2: cubox-i-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - - pinctrl_gpio_key: gpio-key { - fsl,pins = < - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 - >; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_spdif>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbh1>; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usbotg>; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi deleted file mode 100644 index b2c083d57..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -#include - -/ { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "dummy-supply"; - }; - - reg_usb_otg_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - chosen { - stdout-path = &uart1; - }; -}; - -&ecspi3 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 24 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf040b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - status = "okay"; - phy-mode = "rgmii"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-dfi-fs700-m60 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - >; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { /* module slot */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc3 { /* baseboard slot */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; -}; - -&usdhc4 { /* eMMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi deleted file mode 100644 index afec2c762..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ /dev/null @@ -1,380 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory { - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - imx6qdl-gw51xx { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi deleted file mode 100644 index a7100f991..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ /dev/null @@ -1,568 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory { - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - /* remove this fixed regulator once ltc3676__sw2 driver available */ - reg_1p8v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi3 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - imx6qdl-gw52xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_ecspi3: escpi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi deleted file mode 100644 index 8953eba05..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ /dev/null @@ -1,558 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - ethernet1 = ð1; - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - /* remove when pmic 1p8 regulator available */ - reg_1p8v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <11 2>; - wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - imx6qdl-gw53xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi deleted file mode 100644 index 6ac41c7ed..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ /dev/null @@ -1,678 +0,0 @@ -/* - * Copyright 2013 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - ethernet1 = ð1; - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6q-ventana-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <&sw4_reg>; - VDDIO-supply = <®_3p3v>; - }; - - touchscreen: egalax_ts@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio7>; - interrupts = <12 2>; - wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default", "state_dio"; - pinctrl-0 = <&pinctrl_pwm4_backlight>; - pinctrl-1 = <&pinctrl_pwm4_dio>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - no-1-8-v; /* firmware will remove if board revision supports */ - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - imx6qdl-gw54xx { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4_backlight: pwm4grpbacklight { - fsl,pins = < - /* LVDS_PWM J6.5 */ - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4_dio: pwm4grpdio { - fsl,pins = < - /* DIO3 J16.4 */ - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw551x.dtsi deleted file mode 100644 index 4b9fef834..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - nand = &gpmi; - ssi0 = &ssi1; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - memory { - reg = <0x10000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_5p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - gpio_exp: pca9555@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; - -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - imx6qdl-gw51xx { - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw552x.dtsi deleted file mode 100644 index 805e23674..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Copyright 2014 Gateworks Corporation - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - bootargs = "console=ttymxc1,115200"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - - led2: user3 { - label = "user3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ - default-state = "off"; - }; - }; - - memory { - reg = <0x10000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; }; - -&usbh1 { - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - imx6qdl-gw552x { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw553x.dtsi deleted file mode 100644 index 86cec0527..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ /dev/null @@ -1,433 +0,0 @@ -/* - * Copyright 2016 Gateworks Corporation - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - /* these are used by bootloader for disabling nodes */ - aliases { - led0 = &led0; - led1 = &led1; - nand = &gpmi; - usb0 = &usbh1; - usb1 = &usbotg; - }; - - chosen { - stdout-path = &uart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led0: user1 { - label = "user1"; - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led1: user2 { - label = "user2"; - gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ - default-state = "off"; - }; - }; - - memory { - reg = <0x10000000 0x20000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P0V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "5P0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom1: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom2: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom3: eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom4: eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc: ds1672@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_hdmi: hdmigrp { - fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi deleted file mode 100644 index d6c2358ff..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" - -/ { - chosen { - stdout-path = &uart1; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - sound-sgtl5000 { - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - compatible = "fsl,imx-audio-sgtl5000"; - model = "On-board Codec"; - mux-ext-port = <5>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "On-board SPDIF"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c1>; - status = "okay"; - - /* Pro baseboard model */ - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - - /* Pro baseboard model */ - sgtl5000: sgtl5000@0a { - clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c2>; - status = "okay"; -}; - -&iomuxc { - hummingboard { - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 - >; - }; - - pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { - fsl,pins = < - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 - >; - }; - - pinctrl_hummingboard_hdmi: hummingboard-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hummingboard_i2c1: hummingboard-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_i2c2: hummingboard-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { - fsl,pins = < - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 - >; - }; - - pinctrl_hummingboard_pwm1: pwm1grp { - fsl,pins = ; - }; - - pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_hummingboard_spdif: hummingboard-spdif { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { - /* - * Similar to pinctrl_usbotg_2, but we want it - * pulled down for a fixed host connection. - */ - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - >; - }; - - pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>; - reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_hummingboard_usdhc2_aux - &pinctrl_hummingboard_usdhc2 - >; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi deleted file mode 100644 index d5c3aa88a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (C) 2015 Amarula Solutions B.V. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - memory { - reg = <0x10000000 0x80000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_sd3_vmmc: regulator-sd3-vmmc { - compatible = "regulator-fixed"; - regulator-name = "P3V3_SD3_SWITCHED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; - enable-active-high; - }; - - reg_sd4_vmmc: regulator-sd4-vmmc { - compatible = "regulator-fixed"; - regulator-name = "P3V3_SD4_SWITCHED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - usb_hub: usb-hub { - compatible = "smsc,usb3503a"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhub>; - reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; - clock-names = "refclk"; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ð_phy>; - phy-mode = "rgmii"; - status = "okay"; - - mdio { - eth_phy: ethernet-phy { - rxc-skew-ps = <1140>; - txc-skew-ps = <1140>; - txen-skew-ps = <600>; - rxdv-skew-ps = <240>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <600>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <240>; - txd0-skew-ps = <60>; - txd1-skew-ps = <60>; - txd2-skew-ps = <60>; - txd3-skew-ps = <240>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - disable-over-current; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - no-1-8-v; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - vmcc-supply = <®_sd3_vmmc>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - bus-witdh=<4>; - no-1-8-v; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - vmcc-supply = <®_sd4_vmmc>; - bus-witdh=<8>; - no-1-8-v; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_audmux: audmux { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbhub: usbhubgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4grp_100mhz { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4grp_200mhz { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi deleted file mode 100644 index 469ef58ce..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This describes the hookup for an AR8035 to the iMX6 on the SolidRun - * MicroSOM. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; - phy-mode = "rgmii"; - phy-reset-duration = <2>; - phy-reset-gpios = <&gpio4 15 0>; - status = "okay"; -}; - -&iomuxc { - enet { - pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - /* AR8035 reset */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 - /* AR8035 interrupt */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000 - /* GPIO16 -> AR8035 25MHz */ - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 - /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - - /* - * As the RMII pins are also connected to RGMII - * so that an AR8030 can be placed, set these - * to high-z with the same pulls as above. - * Use the GPIO settings to avoid changing the - * input select registers. - */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-microsom.dtsi deleted file mode 100644 index 3d62401db..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-microsom.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (C) 2013,2014 Russell King - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -/ { - clk_sdio: sdio-clock { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_osc>; - enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - }; - - regulators { - compatible = "simple-bus"; - - reg_brcm: brcm-reg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - }; - - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, - <&gpio6 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_sdio>; - clock-names = "ext_clock"; - }; -}; - -&iomuxc { - microsom { - pinctrl_microsom_brcm_bt: microsom-brcm-bt { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 - MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 - MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 - >; - }; - - pinctrl_microsom_brcm_osc: microsom-brcm-osc { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 - >; - }; - - pinctrl_microsom_brcm_reg: microsom-brcm-reg { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 - >; - }; - - pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { - fsl,pins = < - MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 - >; - }; - - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_microsom_uart4: microsom-uart4 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_microsom_usdhc1: microsom-usdhc1 { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_uart1>; - status = "okay"; -}; - -/* UART4 - Connected to optional BRCM Wifi/BT/FM */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - vmmc-supply = <®_brcm>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi deleted file mode 100644 index 880bd782a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ /dev/null @@ -1,631 +0,0 @@ -/* - * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0x10000000 0x20000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - }; - - bt_rfkill { - compatible = "rfkill-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_rfkill>; - gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - name = "bt_rfkill"; - type = <2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - home { - label = "Home"; - gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>; - linux,code = <102>; - }; - - back { - label = "Back"; - gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; - linux,code = <158>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - j14-pin1 { - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - j14-pin3 { - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - j14-pins8-9 { - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - j46-pin2 { - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - - j46-pin3 { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - retain-state-suspended; - default-state = "off"; - }; - }; - - backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds0: backlight_lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - panel_lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx6dl-nit6xlite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6dl-nit6xlite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - }; - - rtc@6f { - compatible = "isil,isl1208"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x6f>; - interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j10>; - pinctrl-1 = <&pinctrl_j28>; - - imx6dl-nit6xlite { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_bt_rfkill: bt_rfkillgrp { - fsl,pins = < - /* BT wake */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* BT reset */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0 - /* BT reg en */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - /* BT host wake irq */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - /* Home Button: J14 pin 5 */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Back Button: J14 pin 7 */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - /* Touch IRQ: J7 pin 4 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - /* tcs2004 IRQ */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 - /* tsc2004 reset */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 - >; - }; - - pinctrl_j10: j10grp { - fsl,pins = < - /* Broadcom WiFi module pins */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - - pinctrl_j28: j28grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0 - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_wlan_vmmc: wlan_vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_wlan_vmmc>; - vqmmc-1-8-v; - ocr-limit = <0x180>; /* 1.65v - 2.1v */ - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi deleted file mode 100644 index 01166ba36..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ /dev/null @@ -1,874 +0,0 @@ -/* - * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0x10000000 0xF0000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_can_xcvr: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - i2cmux@2 { - compatible = "i2c-mux-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2mux>; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH - &gpio4 15 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c2>; - idle-state = <0>; - - i2c2@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2cmux@3 { - compatible = "i2c-mux-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3mux>; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; - i2c-parent = <&i2c3>; - idle-state = <0>; - - i2c3@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - leds { - compatible = "gpio-leds"; - - speaker-enable { - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - retain-state-suspended; - default-state = "off"; - }; - - ttymxc4-rs232 { - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - retain-state-suspended; - default-state = "on"; - }; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds0: backlight_lvds0 { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds1: backlight_lvds1 { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: display@di0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel_lcd { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel_lvds0 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds0>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - panel_lvds1 { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds1>; - - port { - panel_in_lvds1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - - sound { - compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6_max-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc: rtc@68 { - compatible = "st,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&iomuxc { - imx6q-nitrogen6_max { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2mux: i2c2muxgrp { - fsl,pins = < - /* ov5642 camera i2c enable */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 - /* ov5640_mipi camera i2c enable */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_i2c3mux: i2c3muxgrp { - fsl,pins = < - /* PCIe I2C enable */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* PCIe reset */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_rv4162: rv4162grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 - /* RS485 RX Enable: pull up */ - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 - /* RS485 DEN: pull down */ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 - /* RS485/!RS232 Select: pull down (rs232) */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 - /* ON: pull down */ - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wlan_vmmc: wlan_vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; - }; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds1_out: endpoint { - remote-endpoint = <&panel_in_lvds1>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi deleted file mode 100644 index db868bc42..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ /dev/null @@ -1,682 +0,0 @@ -/* - * Copyright 2013 Boundary Devices, Inc. - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_wlan_vmmc: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-nitrogen6x-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-nitrogen6x-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds: backlight_lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: display@di0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - lcd_panel { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 27 0>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - - rtc: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreen@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-nitrogen6x { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ - >; - }; - - pinctrl_wlan_vmmc: wlan_vmmcgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 - MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan_vmmc>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi deleted file mode 100644 index 585b4f698..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - chosen { - linux,stdout-path = &uart4; - }; - - regulators { - sound_1v8: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "i2s-audio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - sound_3v3: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "i2s-audio-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - tlv320_mclk: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "tlv320-mclk"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "OnboardTLV320AIC3007"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "Speaker", "SPOP", - "Speaker", "SPOM", - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - - simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&tlv320_mclk>; - }; - }; - -}; - -&audmux { - status = "okay"; - - ssi2 { - fsl,audmux-port = <1>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(4) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(4)) - IMX_AUDMUX_V2_PDCR_RXDSEL(4) - >; - }; - - pins5 { - fsl,audmux-port = <4>; - fsl,port-config = < - 0x00000000 - IMX_AUDMUX_V2_PDCR_RXDSEL(1) - >; - }; -}; - -&can1 { - status = "okay"; -}; - -&fec { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - codec: tlv320@18 { - compatible = "ti,tlv320aic3007"; - #sound-dai-cells = <0>; - reg = <0x18>; - ai3x-micbias-vg = <2>; - - AVDD-supply = <&sound_3v3>; - IOVDD-supply = <&sound_3v3>; - DRVDD-supply = <&sound_3v3>; - DVDD-supply = <&sound_1v8>; - }; - - stmpe@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - }; - - rtc@51 { - compatible = "nxp,rtc8564"; - reg = <0x51>; - }; - - adc@64 { - compatible = "maxim,max1037"; - reg = <0x64>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi deleted file mode 100644 index e0280cac2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 0>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 0>; - enable-active-high; - }; - }; - - gpio_leds: leds { - compatible = "gpio-leds"; - - green { - label = "phyflex:green"; - gpios = <&gpio1 30 0>; - }; - - red { - label = "phyflex:red"; - gpios = <&gpio2 31 0>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 24 0>; - - flash@0 { - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - phy-supply = <&vdd_eth_io_reg>; - status = "disabled"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio2>; - interrupts = <9 0x8>; /* active-low GPIO2_9 */ - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_buckmem_reg: bmem { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_eth_reg: bio { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_eth_io_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_3v3_pmic_io_reg: ldo6 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd0_reg: ldo9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_sd1_reg: ldo10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_mx6_high_reg: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-phytec-pfla02 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = ; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 17 0>; - status = "disabled"; -}; - -®_arm { - vin-supply = <&vddcore_reg>; -}; - -®_pu { - vin-supply = <&vddsoc_reg>; -}; - -®_soc { - vin-supply = <&vddsoc_reg>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-rex.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-rex.dtsi deleted file mode 100644 index 17704a5c1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright 2014 FEDEVEL, Inc. - * - * Author: Robert Nelson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - led0: usr { - label = "usr"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; - - sound { - compatible = "fsl,imx6-rex-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-rex-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi2 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&ecspi3 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@57 { - compatible = "at,24c02"; - reg = <0x57>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-rex { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - /* user led */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - /* power enable, high active */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - /* CD */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* WP */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - /* CD */ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - /* WP */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 - >; - }; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi deleted file mode 100644 index e000e6f12..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ /dev/null @@ -1,630 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - memory { - reg = <0x10000000 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user { - label = "debug"; - gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - }; - }; - - clocks { - codec_osc: anaclk2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_audio: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "cs42888_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound-cs42888 { - compatible = "fsl,imx6-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; - model = "imx-cs42888"; - audio-cpu = <&esai>; - audio-asrc = <&asrc>; - audio-codec = <&codec>; - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "Line In Jack", - "AIN1R", "Line In Jack", - "AIN2L", "Line In Jack", - "AIN2R", "Line In Jack"; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif", - "fsl,imx-sabreauto-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-in; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - status = "okay"; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_PLL4_BYPASS>, - <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_PLL4_POST_DIV>; - assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, - <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; - status = "disabled"; /* pin conflict with WEIM NOR */ - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&esai { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esai>; - assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>, - <&clks IMX6QDL_CLK_ESAI_EXTAL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - codec: cs42888@48 { - compatible = "cirrus,cs42888"; - reg = <0x48>; - clocks = <&codec_osc>; - clock-names = "mclk"; - VA-supply = <®_audio>; - VD-supply = <®_audio>; - VLS-supply = <®_audio>; - VLC-supply = <®_audio>; - }; - -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - max7310_a: gpio@30 { - compatible = "maxim,max7310"; - reg = <0x30>; - gpio-controller; - #gpio-cells = <2>; - }; - - max7310_b: gpio@32 { - compatible = "maxim,max7310"; - reg = <0x32>; - gpio-controller; - #gpio-cells = <2>; - }; - - max7310_c: gpio@34 { - compatible = "maxim,max7310"; - reg = <0x34>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-sabreauto { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 - MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - >; - }; - - pinctrl_ecspi1_cs: ecspi1cs { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_esai: esaigrp { - fsl,pins = < - MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 - MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 - MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 - MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 - MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 - MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 - MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 - MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 - MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm3: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; - - pinctrl_weim_cs0: weimcs0grp { - fsl,pins = < - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_nor: weimnorgrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&weim { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>; - status = "disabled"; /* pin conflict with SPI NOR */ - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi deleted file mode 100644 index 81dd6cd19..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - menu { - label = "Menu"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - back { - label = "Back"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - backlight_lvds: backlight_lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - power-supply = <®_3p3v>; - status = "okay"; - }; - - lcd_display: display@di0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_j15>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - lcd_panel { - compatible = "okaya,rs800480t-7x0gp"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - txen-skew-ps = <0>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-sabrelite { - pinctrl_hog: hoggrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_can_xcvr: can-xcvrgrp { - fsl,pins = < - /* Flexcan XCVR enable */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - /* Phy reset */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - /* Power Button */ - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - /* Menu Button */ - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - /* Home Button */ - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - /* Back Button */ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - /* Volume Up Button */ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 - /* Volume Down Button */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_j15: j15grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ - >; - }; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabresd.dtsi deleted file mode 100644 index 8e9e0d98d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ /dev/null @@ -1,615 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 29 0>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_audio: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "wm8962-supply"; - gpio = <&gpio4 10 0>; - enable-active-high; - }; - - reg_pcie: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 19 0>; - regulator-always-on; - enable-active-high; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - }; - - sound { - compatible = "fsl,imx6q-sabresd-wm8962", - "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - red { - gpios = <&gpio1 2 0>; - default-state = "on"; - }; - }; - - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 9 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 0>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0013 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x8014 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - egalax_ts@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio6>; - interrupts = <7 2>; - wakeup-gpios = <&gpio6 7 0>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-sabresd { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - >; - }; - - pinctrl_pcie_reg: pciereggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 - >; - }; - }; - - gpio_leds { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <8>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - non-removable; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - status = "disabled"; -}; - -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-ts4900.dtsi deleted file mode 100644 index 5c26b26e8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-ts4900.dtsi +++ /dev/null @@ -1,481 +0,0 @@ -/* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -/ { - aliases { - ethernet0 = &fec; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds1>; - compatible = "gpio-leds"; - - green-led { - label = "green-led"; - gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - red-led { - label = "red-led"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - n25q064: flash@0 { - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&ecspi2 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - status = "okay"; - - isl12022: rtc@6f { - compatible = "isil,isl12022"; - reg = <0x6f>; - }; - - gpio8: gpio@28 { - compatible = "technologic,ts4900-gpio"; - reg = <0x28>; - #gpio-cells = <2>; - gpio-controller; - ngpio = <32>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ - MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ - MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 - MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 - MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 - MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 - MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 - MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 - >; - }; - - pinctrl_leds1: leds1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; -}; - -&pcie { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -/* SD */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - fsl,wp-controller; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - bus-width = <4>; - non-removable; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-tx6.dtsi deleted file mode 100644 index ac9529f85..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ /dev/null @@ -1,744 +0,0 @@ -/* - * Copyright 2014-2016 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -/ { - aliases { - can0 = &can2; - can1 = &can1; - ethernet0 = &fec; - lcdif_23bit_pins_a = &pinctrl_disp0_1; - lcdif_24bit_pins_a = &pinctrl_disp0_2; - pwm0 = &pwm1; - pwm1 = &pwm2; - reg_can_xcvr = ®_can_xcvr; - stk5led = &user_led; - usbotg = &usbotg; - sdhc0 = &usdhc1; - sdhc1 = &usdhc2; - }; - - memory { - reg = <0 0>; /* will be filled by U-Boot */ - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power Button"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led: user { - label = "Heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_user_led>; - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v3_etn: regulator-3v3-etn { - compatible = "regulator-fixed"; - regulator-name = "3V3_ETN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_power>; - gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2v5: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-low; - }; - - reg_lcd0_pwr: regulator-lcd0-pwr { - compatible = "regulator-fixed"; - regulator-name = "LCD0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_lcd1_pwr: regulator-lcd1-pwr { - compatible = "regulator-fixed"; - regulator-name = "LCD1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_pwr>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "karo,imx6qdl-tx6qdl-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "sgtl5000-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <5>; - }; -}; - -&audmux { - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - fsl,spi-num-chipselects = <2>; - cs-gpios = < - &gpio2 30 GPIO_ACTIVE_HIGH - &gpio3 19 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <54000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <54000000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; - phy-handle = <&etnphy>; - phy-supply = <®_3v3_etn>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_mdio>; - interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - interrupt-parent = <&gpio6>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 0>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ - >; - }; - - pinctrl_disp0_1: disp0grp-1 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_disp0_2: disp0grp-2 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 - MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ - >; - }; - - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - >; - }; - - pinctrl_enet_mdio: enet-mdiogrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - >; - }; - - pinctrl_etnphy_power: etnphy-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_flexcan_xcvr: flexcan-xcvrgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 - MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 - MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 - MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 - MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 - MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 - MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 - MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 - >; - }; - - pinctrl_lcd0_pwr: lcd0-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ - >; - }; - - pinctrl_lcd1_pwr: lcd-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart1_rtscts: uart1_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2_rtscts: uart2_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3_rtscts: uart3_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 - MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 - MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ - >; - }; - - pinctrl_user_led: user-ledgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ - >; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0,1 are mapped to KPP row/col 6,7 */ - linux,keymap = < - MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ - MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ - MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ - MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ - MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ - MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ - MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ - MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ - MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ - MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ - MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ - >; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - #pwm-cells = <3>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <3>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-udoo.dtsi deleted file mode 100644 index c96c91d83..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -/ { - aliases { - backlight = &backlight; - panelchan = &panelchan; - panel7 = &panel7; - touchscreenp7 = &touchscreenp7; - }; - - chosen { - stdout-path = &uart2; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpio1 4 0>; - default-on; - status = "disabled"; - }; - - memory { - reg = <0x10000000 0x40000000>; - }; - - panel7: panel7 { - /* - * in reality it is a -20t (parallel) model, - * but with LVDS bridge chip attached, - * so it is equivalent to -19t model in drive - * characteristics - */ - compatible = "urt,umsh-8596md-19t"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_panel>; - power-supply = <®_panel>; - backlight = <&backlight>; - status = "disabled"; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_h1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ - gpio = <&gpio7 12 0>; - }; - - reg_panel: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd_panel"; - enable-active-high; - gpio = <&gpio1 2 0>; - }; - }; - - sound { - compatible = "fsl,imx6q-udoo-ac97", - "fsl,imx-audio-ac97"; - model = "fsl,imx6q-udoo-ac97"; - audio-cpu = <&ssi1>; - audio-routing = - "RX", "Mic Jack", - "Headphone Jack", "TX"; - mux-int-port = <1>; - mux-ext-port = <6>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touchscreenp7: touchscreenp7@55 { - compatible = "sitronix,st1232"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreenp7>; - reg = <0x55>; - interrupt-parent = <&gpio1>; - interrupts = <13 8>; - gpios = <&gpio1 15 0>; - status = "disabled"; - }; -}; - -&iomuxc { - imx6q-udoo { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_panel: panelgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 - >; - }; - - pinctrl_touchscreenp7: touchscreenp7grp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh: usbhgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 - MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_ac97_running: ac97running { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ac97_warm_reset: ac97warmreset { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - - pinctrl_ac97_reset: ac97reset { - fsl,pins = < - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x1b0b0 - MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x1b0b0 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - >; - }; - }; -}; - -&ldb { - status = "okay"; - - panelchan: lvds-channel@0 { - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh>; - vbus-supply = <®_usb_h1_vbus>; - clocks = <&clks IMX6QDL_CLK_CKO>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; - status = "okay"; -}; - -&audmux { - status = "okay"; -}; - -&ssi1 { - cell-index = <0>; - fsl,mode = "ac97-slave"; - pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset"; - pinctrl-0 = <&pinctrl_ac97_running>; - pinctrl-1 = <&pinctrl_ac97_reset>; - pinctrl-2 = <&pinctrl_ac97_warm_reset>; - ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi deleted file mode 100644 index ef7fa62b9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include "imx6qdl-wandboard.dtsi" - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ - >; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi deleted file mode 100644 index 8d893a78c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include "imx6qdl-wandboard.dtsi" - -&iomuxc { - pinctrl-0 = <&pinctrl_hog>; - - imx6qdl-wandboard { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ - MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */ - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */ - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ - >; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard.dtsi deleted file mode 100644 index 2b9c2be43..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -/ { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "fsl,imx6-wandboard-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6-wandboard-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c1>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - - imx6qdl-wandboard { - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 29 0>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qdl.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qdl.dtsi deleted file mode 100644 index b13b0b2db..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qdl.dtsi +++ /dev/null @@ -1,1281 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include - -#include "skeleton.dtsi" - -/ { - aliases { - ethernet0 = &fec; - can0 = &can1; - can1 = &can2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - ipu0 = &ipu1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ckil { - compatible = "fsl,imx-ckil", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - ckih1 { - compatible = "fsl,imx-ckih1", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - osc { - compatible = "fsl,imx-osc", "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - dma_apbh: dma-apbh@00110000 { - compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x00110000 0x2000>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6QDL_CLK_APBH_DMA>; - }; - - gpmi: gpmi-nand@00112000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00112000 0x2000>, <0x00114000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bch"; - clocks = <&clks IMX6QDL_CLK_GPMI_IO>, - <&clks IMX6QDL_CLK_GPMI_APB>, - <&clks IMX6QDL_CLK_GPMI_BCH>, - <&clks IMX6QDL_CLK_GPMI_BCH_APB>, - <&clks IMX6QDL_CLK_PER1_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - hdmi: hdmi@0120000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; - status = "disabled"; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; - }; - }; - - gpu_3d: gpu@00130000 { - compatible = "vivante,gc"; - reg = <0x00130000 0x4000>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, - <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>; - clock-names = "bus", "core", "shader"; - power-domains = <&gpc 1>; - }; - - gpu_2d: gpu@00134000 { - compatible = "vivante,gc"; - reg = <0x00134000 0x4000>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_GPU2D_CORE>; - clock-names = "bus", "core"; - power-domains = <&gpc 1>; - }; - - timer@00a00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x00a00600 0x20>; - interrupts = <1 13 0xf01>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6QDL_CLK_TWD>; - }; - - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: l2-cache@00a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - arm,shared-override; - }; - - pcie: pcie@0x01000000 { - compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; - reg = <0x01ffc000 0x04000>, - <0x01f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, - <&clks IMX6QDL_CLK_LVDS1_GATE>, - <&clks IMX6QDL_CLK_PCIE_REF_125M>; - clock-names = "pcie", "pcie_bus", "pcie_phy"; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - aips-bus@02000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@02000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@02004000 { - compatible = "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, - <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, - <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, - <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: ecspi@02008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI1>, - <&clks IMX6QDL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: ecspi@0200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI2>, - <&clks IMX6QDL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: ecspi@02010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI3>, - <&clks IMX6QDL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi4: ecspi@02014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI4>, - <&clks IMX6QDL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@02020000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - esai: esai@02024000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx35-esai"; - reg = <0x02024000 0x4000>; - interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, - <&clks IMX6QDL_CLK_ESAI_MEM>, - <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_ESAI_IPG>, - <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "mem", "extal", "fsys", "spba"; - dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ssi1: ssi@02028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, - <&clks IMX6QDL_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@0202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, - <&clks IMX6QDL_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@02030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6q-ssi", - "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, - <&clks IMX6QDL_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - asrc: asrc@02034000 { - compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, - <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, - <&clks IMX6QDL_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck_0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f", "spba"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, - <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; - status = "okay"; - }; - - spba@0203c000 { - reg = <0x0203c000 0x4000>; - }; - }; - - vpu: vpu@02040000 { - compatible = "cnm,coda960"; - reg = <0x02040000 0x3c000>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bit", "jpeg"; - clocks = <&clks IMX6QDL_CLK_VPU_AXI>, - <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; - clock-names = "per", "ahb"; - power-domains = <&gpc 1>; - resets = <&src 1>; - iram = <&ocram>; - }; - - aipstz@0207c000 { /* AIPSTZ1 */ - reg = <0x0207c000 0x4000>; - }; - - pwm1: pwm@02080000 { - #pwm-cells = <2>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm2: pwm@02084000 { - #pwm-cells = <2>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm3: pwm@02088000 { - #pwm-cells = <2>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm4: pwm@0208c000 { - #pwm-cells = <2>; - compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>, - <&clks IMX6QDL_CLK_PWM4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can1: flexcan@02090000 { - compatible = "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, - <&clks IMX6QDL_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can2: flexcan@02094000 { - compatible = "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, - <&clks IMX6QDL_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt: gpt@02098000 { - compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; - reg = <0x02098000 0x4000>; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPT_IPG>, - <&clks IMX6QDL_CLK_GPT_IPG_PER>, - <&clks IMX6QDL_CLK_GPT_3M>; - clock-names = "ipg", "per", "osc_per"; - }; - - gpio1: gpio@0209c000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, - <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@020a0000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@020a4000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@020a8000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@020ac000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, - <0 75 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@020b0000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020b0000 0x4000>; - interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, - <0 77 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@020b4000 { - compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; - reg = <0x020b4000 0x4000>; - interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, - <0 79 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - kpp: kpp@020b8000 { - compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - status = "disabled"; - }; - - wdog1: wdog@020bc000 { - compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_DUMMY>; - }; - - wdog2: wdog@020c0000 { - compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_DUMMY>; - status = "disabled"; - }; - - clks: ccm@020c4000 { - compatible = "fsl,imx6q-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - }; - - anatop: anatop@020c8000 { - compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; - reg = <0x020c8000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 54 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - - regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - }; - - regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - }; - - regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2000000>; - anatop-max-voltage = <2750000>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pu: regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-enable-ramp-delay = <150>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - }; - - usbphy1: usbphy@020c9000 { - compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@020ca000 { - compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x60>; - status = "disabled"; - }; - }; - - epit1: epit@020d0000 { /* EPIT1 */ - reg = <0x020d0000 0x4000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - }; - - epit2: epit@020d4000 { /* EPIT2 */ - reg = <0x020d4000 0x4000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - }; - - src: src@020d8000 { - compatible = "fsl,imx6q-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, - <0 96 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@020dc000 { - compatible = "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; - pu-supply = <®_pu>; - clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>, - <&clks IMX6QDL_CLK_GPU2D_CORE>, - <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; - #power-domain-cells = <1>; - }; - - gpr: iomuxc-gpr@020e0000 { - compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e0000 0x38>; - }; - - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - ldb: ldb@020e0008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; - gpr = <&gpr>; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@1 { - reg = <1>; - - lvds0_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds1_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds1>; - }; - }; - - port@1 { - reg = <1>; - - lvds1_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds1>; - }; - }; - }; - }; - - dcic1: dcic@020e4000 { - reg = <0x020e4000 0x4000>; - interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; - }; - - dcic2: dcic@020e8000 { - reg = <0x020e8000 0x4000>; - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdma: sdma@020ec000 { - compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SDMA>, - <&clks IMX6QDL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - }; - - aips-bus@02100000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - crypto: caam@2100000 { - compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, - <&clks IMX6QDL_CLK_CAAM_ACLK>, - <&clks IMX6QDL_CLK_CAAM_IPG>, - <&clks IMX6QDL_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - aipstz@0217c000 { /* AIPSTZ2 */ - reg = <0x0217c000 0x4000>; - }; - - usbotg: usb@02184000 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh1: usb@02184200 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh2: usb@02184400 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh3: usb@02184600 { - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184600 0x200>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbmisc = <&usbmisc 3>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@02184800 { - #index-cells = <1>; - compatible = "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6QDL_CLK_USBOH3>; - }; - - fec: ethernet@02188000 { - compatible = "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupts-extended = - <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - mlb@0218c000 { - reg = <0x0218c000 0x4000>; - interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, - <0 117 IRQ_TYPE_LEVEL_HIGH>, - <0 126 IRQ_TYPE_LEVEL_HIGH>; - }; - - usdhc1: usdhc@02190000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC1>, - <&clks IMX6QDL_CLK_USDHC1>, - <&clks IMX6QDL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@02194000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC2>, - <&clks IMX6QDL_CLK_USDHC2>, - <&clks IMX6QDL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@02198000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC3>, - <&clks IMX6QDL_CLK_USDHC3>, - <&clks IMX6QDL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: usdhc@0219c000 { - compatible = "fsl,imx6q-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USDHC4>, - <&clks IMX6QDL_CLK_USDHC4>, - <&clks IMX6QDL_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@021a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@021a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@021a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_I2C3>; - status = "disabled"; - }; - - romcp@021ac000 { - reg = <0x021ac000 0x4000>; - }; - - mmdc0: mmdc@021b0000 { /* MMDC0 */ - compatible = "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - }; - - mmdc1: mmdc@021b4000 { /* MMDC1 */ - reg = <0x021b4000 0x4000>; - }; - - weim: weim@021b8000 { - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; - }; - - ocotp: ocotp@021bc000 { - compatible = "fsl,imx6q-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6QDL_CLK_IIM>; - }; - - tzasc@021d0000 { /* TZASC1 */ - reg = <0x021d0000 0x4000>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - }; - - tzasc@021d4000 { /* TZASC2 */ - reg = <0x021d4000 0x4000>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; - }; - - audmux: audmux@021d8000 { - compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - - mipi_csi: mipi@021dc000 { - reg = <0x021dc000 0x4000>; - }; - - mipi_dsi: mipi@021e0000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x021e0000 0x4000>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mipi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_mipi>; - }; - }; - - port@1 { - reg = <1>; - - mipi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_mipi>; - }; - }; - }; - }; - - vdoa@021e4000 { - reg = <0x021e4000 0x4000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - }; - - uart2: serial@021e8000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021e8000 0x4000>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@021ec000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021ec000 0x4000>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@021f0000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f0000 0x4000>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@021f4000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, - <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - ipu1: ipu@02400000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ipu"; - reg = <0x02400000 0x400000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, - <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - - ipu1_csi0: port@0 { - reg = <0>; - }; - - ipu1_csi1: port@1 { - reg = <1>; - }; - - ipu1_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu1_di0_disp0: disp0-endpoint { - }; - - ipu1_di0_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_mux_0>; - }; - - ipu1_di0_mipi: mipi-endpoint { - remote-endpoint = <&mipi_mux_0>; - }; - - ipu1_di0_lvds0: lvds0-endpoint { - remote-endpoint = <&lvds0_mux_0>; - }; - - ipu1_di0_lvds1: lvds1-endpoint { - remote-endpoint = <&lvds1_mux_0>; - }; - }; - - ipu1_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu1_di1_disp1: disp1-endpoint { - }; - - ipu1_di1_hdmi: hdmi-endpoint { - remote-endpoint = <&hdmi_mux_1>; - }; - - ipu1_di1_mipi: mipi-endpoint { - remote-endpoint = <&mipi_mux_1>; - }; - - ipu1_di1_lvds0: lvds0-endpoint { - remote-endpoint = <&lvds0_mux_1>; - }; - - ipu1_di1_lvds1: lvds1-endpoint { - remote-endpoint = <&lvds1_mux_1>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/software/linux/kernel/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts deleted file mode 100644 index a39b86036..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-nitrogen6_max.dtsi" - -/ { - model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board"; - compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp"; -}; - -&pcie { - status = "disabled"; -}; - -&sata { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qp-sabreauto.dts b/software/linux/kernel/arch/arm/boot/dts/imx6qp-sabreauto.dts deleted file mode 100644 index 5ce3840d8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qp-sabreauto.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-sabreauto.dtsi" - -/ { - model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; -}; - -&i2c2 { - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&iomuxc { - imx6qdl-sabreauto { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - }; -}; - -&pcie { - status = "disabled"; -}; - -&vgen3_reg { - regulator-always-on; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qp-sabresd.dts b/software/linux/kernel/arch/arm/boot/dts/imx6qp-sabresd.dts deleted file mode 100644 index b23458062..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qp-sabresd.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6qp.dtsi" -#include "imx6qdl-sabresd.dtsi" - -/ { - model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; -}; - -&cpu0 { - arm-supply = <&sw2_reg>; -}; - -&iomuxc { - imx6qdl-sabresd { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - }; -}; - -&pcie { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6qp.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6qp.dtsi deleted file mode 100644 index 886dbf2ec..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6qp.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6q.dtsi" - -/ { - soc { - ocram2: sram@00940000 { - compatible = "mmio-sram"; - reg = <0x00940000 0x20000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - ocram3: sram@00960000 { - compatible = "mmio-sram"; - reg = <0x00960000 0x20000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - ipu1: ipu@02400000 { - compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; - clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>, - <&clks IMX6QDL_CLK_PRG0_APB>; - clock-names = "bus", - "di0", "di1", - "di0_sel", "di1_sel", - "ldb_di0", "ldb_di1", "prg"; - }; - - ipu2: ipu@02800000 { - compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; - clocks = <&clks IMX6QDL_CLK_IPU2>, - <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>, - <&clks IMX6QDL_CLK_PRG1_APB>; - clock-names = "bus", - "di0", "di1", - "di0_sel", "di1_sel", - "ldb_di0", "ldb_di1", "prg"; - }; - - pcie: pcie@0x01000000 { - compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sl-evk.dts b/software/linux/kernel/arch/arm/boot/dts/imx6sl-evk.dts deleted file mode 100644 index be118820e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sl-evk.dts +++ /dev/null @@ -1,642 +0,0 @@ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include -#include -#include "imx6sl.dtsi" - -/ { - model = "Freescale i.MX6 SoloLite EVK Board"; - compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; - - memory { - reg = <0x80000000 0x40000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user { - label = "debug"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 0>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_usb_otg2_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 0>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_aud3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "wm8962-supply-3v15"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-boot-on; - }; - - reg_aud4v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "wm8962-supply-4v2"; - regulator-min-microvolt = <4325000>; - regulator-max-microvolt = <4325000>; - regulator-boot-on; - }; - - reg_lcd_3v3: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "lcd-3v3"; - gpio = <&gpio4 3 0>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux3>; - status = "okay"; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 11 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - phy-mode = "rmii"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; - DCVDD-supply = <&vgen3_reg>; - DBVDD-supply = <®_aud3v>; - AVDD-supply = <&vgen3_reg>; - CPVDD-supply = <&vgen3_reg>; - MICVDD-supply = <®_aud3v>; - PLLVDD-supply = <&vgen3_reg>; - SPKVDD1-supply = <®_aud4v>; - SPKVDD2-supply = <®_aud4v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6sl-evk { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 - MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 - MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 - MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 - >; - }; - - pinctrl_audmux3: audmux3grp { - fsl,pins = < - MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 - MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 - MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 - MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 - MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 - MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 - MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 - MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 - MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 - MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 - MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 - >; - }; - - pinctrl_fec_sleep: fecgrp-sleep { - fsl,pins = < - MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 - MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 - MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 - MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 - MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 - MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 - MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 - MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 - >; - }; - - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 - MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 - MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 - MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 - MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 - MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 - MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 - MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 - MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 - MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 - MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 - MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 - MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 - MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 - MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 - MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 - MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 - MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 - MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 - MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 - MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 - MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 - MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 - MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 - MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 - MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 - MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 - MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 - MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 - MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 - MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 - MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 - MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 - >; - }; - - pinctrl_pwm1: pwmgrp { - fsl,pins = < - MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ - MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ - MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ - MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ - MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ - MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ - MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ - MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ - >; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hback-porch = <89>; - hfront-porch = <164>; - vback-porch = <23>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sl-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx6sl-pinfunc.h deleted file mode 100644 index 77b17bcc7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sl-pinfunc.h +++ /dev/null @@ -1,1077 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX6SL_PINFUNC_H -#define __DTS_IMX6SL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 -#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 -#define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 -#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 -#define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 -#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0 -#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 -#define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0 -#define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0 -#define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0 -#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0 -#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 -#define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0 -#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1 -#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 -#define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0 -#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0 -#define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0 -#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1 -#define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 -#define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0 -#define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0 -#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 -#define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0 -#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1 -#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 -#define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0 -#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0 -#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0 -#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1 -#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0 -#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0 -#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0 -#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1 -#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0 -#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0 -#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0 -#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0 -#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0 -#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2 -#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1 -#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3 -#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1 -#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0 -#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0 -#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1 -#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0 -#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0 -#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0 -#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2 -#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0 -#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3 -#define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0 -#define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0 -#define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0 -#define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0 -#define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1 -#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0 -#define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1 -#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0 -#define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0 -#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1 -#define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1 -#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0 -#define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0 -#define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0 -#define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0 -#define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0 -#define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1 -#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1 -#define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0 -#define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0 -#define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0 -#define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0 -#define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0 -#define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0 -#define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0 -#define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0 -#define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0 -#define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0 -#define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1 -#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1 -#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1 -#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1 -#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1 -#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1 -#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1 -#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1 -#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0 -#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0 -#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1 -#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0 -#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0 -#define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1 -#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0 -#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1 -#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0 -#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0 -#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4 -#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0 -#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5 -#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1 -#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1 -#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0 -#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1 -#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0 -#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1 -#define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1 -#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0 -#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1 -#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0 -#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0 -#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0 -#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2 -#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1 -#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1 -#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0 -#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1 -#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0 -#define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0 -#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1 -#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1 -#define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1 -#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0 -#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1 -#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0 -#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1 -#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1 -#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0 -#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1 -#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0 -#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0 -#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0 -#define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1 -#define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1 -#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1 -#define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0 -#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1 -#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0 -#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0 -#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1 -#define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1 -#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0 -#define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0 -#define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1 -#define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0 -#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0 -#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0 -#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0 -#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1 -#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0 -#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0 -#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2 -#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0 -#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0 -#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1 -#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1 -#define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0 -#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0 -#define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2 -#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0 -#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1 -#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1 -#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0 -#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0 -#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0 -#define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1 -#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0 -#define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1 -#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0 -#define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2 -#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0 -#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0 -#define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1 -#define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0 -#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0 -#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0 -#define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2 -#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0 -#define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2 -#define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0 -#define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2 -#define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0 -#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2 -#define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0 -#define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0 -#define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0 -#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2 -#define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0 -#define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0 -#define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0 -#define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1 -#define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0 -#define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1 -#define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0 -#define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1 -#define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0 -#define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2 -#define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0 -#define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1 -#define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0 -#define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2 -#define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0 -#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2 -#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0 -#define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2 -#define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0 -#define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2 -#define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0 -#define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1 -#define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2 -#define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0 -#define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2 -#define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3 -#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0 -#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2 -#define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0 -#define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0 -#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0 -#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2 -#define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0 -#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0 -#define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1 -#define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0 -#define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1 -#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0 -#define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1 -#define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2 -#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1 -#define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0 -#define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1 -#define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0 -#define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2 -#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2 -#define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0 -#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3 -#define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0 -#define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2 -#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0 -#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3 -#define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0 -#define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1 -#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3 -#define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2 -#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1 -#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1 -#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1 -#define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1 -#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2 -#define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1 -#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1 -#define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2 -#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1 -#define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1 -#define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1 -#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1 -#define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2 -#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1 -#define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1 -#define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3 -#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1 -#define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2 -#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1 -#define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1 -#define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3 -#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1 -#define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1 -#define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3 -#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1 -#define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1 -#define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1 -#define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3 -#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1 -#define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0 -#define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1 -#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1 -#define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0 -#define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1 -#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1 -#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1 -#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0 -#define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1 -#define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0 -#define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1 -#define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1 -#define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1 -#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1 -#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1 -#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1 -#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1 -#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1 -#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2 -#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1 -#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1 -#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2 -#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1 -#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1 -#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1 -#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2 -#define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1 -#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1 -#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1 -#define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1 -#define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1 -#define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1 -#define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2 -#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1 -#define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1 -#define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2 -#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2 -#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2 -#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0 -#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2 -#define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3 -#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1 -#define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1 -#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1 -#define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2 -#define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1 -#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2 -#define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3 -#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0 -#define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0 -#define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0 -#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0 -#define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0 -#define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0 -#define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0 -#define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0 -#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0 -#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2 -#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0 -#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2 -#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2 -#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0 -#define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3 -#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0 -#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2 -#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0 -#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3 -#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0 -#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0 -#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3 -#define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2 -#define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2 -#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2 -#define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2 -#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2 -#define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2 -#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2 -#define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2 -#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2 -#define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2 -#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2 -#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2 -#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4 -#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2 -#define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2 -#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5 -#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2 -#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4 -#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2 -#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3 -#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5 -#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2 -#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2 -#define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2 -#define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2 -#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2 -#define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2 -#define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2 -#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2 -#define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2 -#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4 -#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2 -#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2 -#define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2 -#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5 -#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2 -#define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1 -#define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2 -#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4 -#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2 -#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1 -#define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2 -#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5 -#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1 -#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4 -#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2 -#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1 -#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5 -#define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2 -#define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2 -#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1 -#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4 -#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2 -#define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2 -#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1 -#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5 -#define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2 -#define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2 -#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0 -#define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0 -#define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1 -#define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2 -#define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2 -#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1 -#define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2 -#define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2 -#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3 -#define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1 -#define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2 -#define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1 -#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4 -#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1 -#define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2 -#define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1 -#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1 -#define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2 -#define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1 -#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3 -#define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1 -#define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2 -#define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1 -#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2 -#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0 -#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0 -#define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0 -#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6 -#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0 -#define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2 -#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6 -#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0 -#define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0 -#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0 -#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1 -#define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0 -#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0 -#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7 -#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2 -#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0 -#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7 -#define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0 -#define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0 -#define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0 -#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0 -#define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0 -#define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0 - -#endif /* __DTS_IMX6SL_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sl-warp.dts b/software/linux/kernel/arch/arm/boot/dts/imx6sl-warp.dts deleted file mode 100644 index 72c7745f5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sl-warp.dts +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright 2014, 2015 O.S. Systems Software LTDA. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include "imx6sl.dtsi" - -/ { - model = "WaRP Board"; - compatible = "warp,imx6sl-warp", "fsl,imx6sl"; - - memory { - reg = <0x80000000 0x20000000>; - }; - - usdhc3_pwrseq: usdhc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ - <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ - <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ - <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ - <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ - <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - wakeup-source; - mmc-pwrseq = <&usdhc3_pwrseq>; - status = "okay"; -}; - -&iomuxc { - imx6sl-warp { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 - >; - }; - - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 - MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 - MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 - MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 - MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 - MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 - MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 - MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 - MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 - MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 - MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 - MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sl.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6sl.dtsi deleted file mode 100644 index 02378db3f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sl.dtsi +++ /dev/null @@ -1,913 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include "skeleton.dtsi" -#include "imx6sl-pinfunc.h" -#include - -/ { - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1225000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - }; - }; - - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram: sram@00900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - clocks = <&clks IMX6SL_CLK_OCRAM>; - }; - - L2: l2-cache@00a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - aips1: aips-bus@02000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba: spba-bus@02000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@02004000 { - compatible = "fsl,imx6sl-spdif", - "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, - <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: ecspi@02008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI1>, - <&clks IMX6SL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: ecspi@0200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI2>, - <&clks IMX6SL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: ecspi@02010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI3>, - <&clks IMX6SL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: ecspi@02014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI4>, - <&clks IMX6SL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@02018000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02018000 0x4000>; - interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@02020000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@02024000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02024000 0x4000>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ssi1: ssi@02028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI1_IPG>, - <&clks IMX6SL_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@0202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI2_IPG>, - <&clks IMX6SL_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@02030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI3_IPG>, - <&clks IMX6SL_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - uart3: serial@02034000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02034000 0x4000>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@02038000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02038000 0x4000>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - pwm1: pwm@02080000 { - #pwm-cells = <2>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM1>, - <&clks IMX6SL_CLK_PWM1>; - clock-names = "ipg", "per"; - }; - - pwm2: pwm@02084000 { - #pwm-cells = <2>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM2>, - <&clks IMX6SL_CLK_PWM2>; - clock-names = "ipg", "per"; - }; - - pwm3: pwm@02088000 { - #pwm-cells = <2>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM3>, - <&clks IMX6SL_CLK_PWM3>; - clock-names = "ipg", "per"; - }; - - pwm4: pwm@0208c000 { - #pwm-cells = <2>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM4>, - <&clks IMX6SL_CLK_PWM4>; - clock-names = "ipg", "per"; - }; - - gpt: gpt@02098000 { - compatible = "fsl,imx6sl-gpt"; - reg = <0x02098000 0x4000>; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_GPT>, - <&clks IMX6SL_CLK_GPT_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@0209c000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, - <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, - <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, - <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, - <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, - <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, - <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; - }; - - gpio2: gpio@020a0000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, - <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, - <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, - <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, - <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, - <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, - <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; - }; - - gpio3: gpio@020a4000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, - <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, - <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, - <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, - <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, - <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, - <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, - <&iomuxc 31 102 1>; - }; - - gpio4: gpio@020a8000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, - <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, - <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, - <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, - <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, - <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, - <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, - <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, - <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, - <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, - <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, - <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, - <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, - <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, - <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; - }; - - gpio5: gpio@020ac000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, - <0 75 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, - <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, - <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, - <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, - <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, - <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, - <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, - <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, - <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, - <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, - <&iomuxc 21 161 1>; - }; - - kpp: kpp@020b8000 { - compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: wdog@020bc000 { - compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_DUMMY>; - }; - - wdog2: wdog@020c0000 { - compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_DUMMY>; - status = "disabled"; - }; - - clks: ccm@020c4000 { - compatible = "fsl,imx6sl-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - }; - - anatop: anatop@020c8000 { - compatible = "fsl,imx6sl-anatop", - "fsl,imx6q-anatop", - "syscon", "simple-bus"; - reg = <0x020c8000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 54 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - - regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - }; - - regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - }; - - regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2850000>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pu: regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; - }; - - usbphy1: usbphy@020c9000 { - compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@020ca000 { - compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x60>; - status = "disabled"; - }; - }; - - epit1: epit@020d0000 { - reg = <0x020d0000 0x4000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - }; - - epit2: epit@020d4000 { - reg = <0x020d4000 0x4000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - }; - - src: src@020d8000 { - compatible = "fsl,imx6sl-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, - <0 96 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@020dc000 { - compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; - pu-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; - #power-domain-cells = <1>; - }; - - gpr: iomuxc-gpr@020e0000 { - compatible = "fsl,imx6sl-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e0000 0x38>; - }; - - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6sl-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - csi: csi@020e4000 { - reg = <0x020e4000 0x4000>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - spdc: spdc@020e8000 { - reg = <0x020e8000 0x4000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdma: sdma@020ec000 { - compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SDMA>, - <&clks IMX6SL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - /* imx6sl reuses imx6q sdma firmware */ - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pxp: pxp@020f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - }; - - epdc: epdc@020f4000 { - reg = <0x020f4000 0x4000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - }; - - lcdif: lcdif@020f8000 { - compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; - reg = <0x020f8000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, - <&clks IMX6SL_CLK_LCDIF_AXI>, - <&clks IMX6SL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - dcp: dcp@020fc000 { - compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; - reg = <0x020fc000 0x4000>; - interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, - <0 100 IRQ_TYPE_LEVEL_HIGH>, - <0 101 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips2: aips-bus@02100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - usbotg1: usb@02184000 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@02184200 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh: usb@02184400 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@02184800 { - #index-cells = <1>; - compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - }; - - fec: ethernet@02188000 { - compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; - reg = <0x02188000 0x4000>; - interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ENET>, - <&clks IMX6SL_CLK_ENET_REF>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - - usdhc1: usdhc@02190000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC1>, - <&clks IMX6SL_CLK_USDHC1>, - <&clks IMX6SL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@02194000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC2>, - <&clks IMX6SL_CLK_USDHC2>, - <&clks IMX6SL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@02198000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC3>, - <&clks IMX6SL_CLK_USDHC3>, - <&clks IMX6SL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: usdhc@0219c000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC4>, - <&clks IMX6SL_CLK_USDHC4>, - <&clks IMX6SL_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@021a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@021a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@021a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C3>; - status = "disabled"; - }; - - mmdc: mmdc@021b0000 { - compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - }; - - rngb: rngb@021b4000 { - reg = <0x021b4000 0x4000>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; - }; - - weim: weim@021b8000 { - reg = <0x021b8000 0x4000>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocotp: ocotp@021bc000 { - compatible = "fsl,imx6sl-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SL_CLK_OCOTP>; - }; - - audmux: audmux@021d8000 { - compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/software/linux/kernel/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts deleted file mode 100644 index 9b817f350..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ /dev/null @@ -1,709 +0,0 @@ -/* - * Copyright (C) 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6sx.dtsi" - -/ { - model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; - compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; - - aliases { - fb_lcd = &lcdif1; - t_lcd = &t_lcd; - }; - - memory { - reg = <0x80000000 0x40000000>; - }; - - backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3p3v>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can1_3v3: regulator-can1-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can1-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; - }; - - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan: regulator-wlan { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wlan>; - compatible = "regulator-fixed"; - clocks = <&clks IMX6SX_CLK_CKO>; - clock-names = "slow"; - regulator-name = "wlan-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6sx-nitrogen6sx-sgtl5000"; - cpu-dai = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <5>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: m25p80@0 { - compatible = "microchip,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0xc0000>; - read-only; - }; - - partition@c0000 { - label = "env"; - reg = <0xc0000 0x2000>; - read-only; - }; - - partition@c2000 { - label = "Kernel"; - reg = <0xc2000 0x11e000>; - }; - - partition@1e0000 { - label = "M4"; - reg = <0x1e0000 0x20000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - phy-supply = <®_3p3v>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@4 { - reg = <4>; - }; - - ethphy2: ethernet-phy@5 { - reg = <5>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - phy-supply = <®_3p3v>; - fsl,magic-packet; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_3v3>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - reg = <0x0a>; - clocks = <&clks IMX6SX_CLK_CKO2>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - VDDD-supply = <®_1p8v>; - assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, - <&clks IMX6SX_CLK_CKO2>; - assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; - assigned-clock-rates = <0>, <24000000>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif1>; - lcd-supply = <®_3p3v>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - clock-frequency = <74160000>; - hactive = <1280>; - vactive = <720>; - hback-porch = <220>; - hfront-porch = <110>; - vback-porch = <20>; - vfront-porch = <5>; - hsync-len = <40>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - dr_mode = "host"; - disable-over-current; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - vmmc-supply = <®_wlan>; - cap-power-off-card; - cap-sdio-irq; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - }; - - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc4 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc4_50mhz>; - pinctrl-1 = <&pinctrl_usdhc4_100mhz>; - pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - bus-width = <8>; - non-removable; - vmmc-supply = <®_1p8v>; - keep-power-in-suspend; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 - MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 - MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 - MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 - MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 - MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 - MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 - MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 - MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 - MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 - MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 - MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 - MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 - MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 - MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 - MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 - MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0 - MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 - /* Test points */ - MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 - MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 - MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_lcdif1: lcdif1grp { - fsl,pins = < - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 - MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0 - MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_reg_wlan: reg-wlangrp { - fsl,pins = < - MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 - MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 - >; - }; - - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 - MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 - MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 - MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 - MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 - MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 - >; - }; - - pinctrl_usbotg1_vbus: usbotg1-vbusgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 - >; - }; - - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 - >; - }; - - pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 - MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 - >; - }; - - pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { - fsl,pins = < - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 - MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 - MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 - MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 - MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sx-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx6sx-pinfunc.h deleted file mode 100644 index 42c4c800f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sx-pinfunc.h +++ /dev/null @@ -1,1558 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX6SX_PINFUNC_H -#define __DTS_IMX6SX_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 -#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1 -#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2 -#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0 -#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1 -#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0 -#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0 -#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1 -#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0 -#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0 -#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1 -#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1 -#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0 -#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0 -#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1 -#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1 -#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0 -#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0 -#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0 -#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1 -#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0 -#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1 -#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1 -#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1 -#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0 -#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1 -#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 -#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 -#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0 -#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0 -#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 -#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0 -#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 -#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 -#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2 -#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0 -#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1 -#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2 -#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0 -#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1 -#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3 -#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2 -#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 -#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 -#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 -#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0 -#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1 -#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1 -#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1 -#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1 -#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1 -#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1 -#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2 -#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0 -#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1 -#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1 -#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 -/* - * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is - * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a - * PHY in RMII mode. This configuration is valid if: - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset - * It seems to be a silicon bug that in this configuration ENET1_TX reference - * clock isn't provided automatically. According to i.MX6SX reference manual - * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it - * should be the case. - * So this might have unwanted side effects for other hardware units that are - * also connected to that pin and using respective function as input (e.g. - * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). - */ -#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 -#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 -#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1 -#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2 -#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3 -#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1 -#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2 -#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1 -#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3 -#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1 -#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1 -#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2 -#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0 -#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2 -#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 -#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 -#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1 -#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0 -#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2 -#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0 -#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0 -#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0 -#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 -#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2 -#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 -#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2 -#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0 -#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2 -#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0 -#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 -#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 -#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 -#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1 -#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3 -#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0 -#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0 -#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0 -#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 -#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 -#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 -#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3 -#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1 -#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1 -#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3 -#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2 -#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0 -#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0 -#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1 -#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0 -#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0 -#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1 -#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0 -#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0 -#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0 -#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1 -#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0 -#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0 -#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1 -#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0 -#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0 -#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1 -#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1 -#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0 -#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0 -#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0 -#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0 -#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0 -#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0 -#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0 -#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0 -#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0 -#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0 -#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0 -#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0 -#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0 -#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0 -#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0 -#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0 -#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0 -#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0 -#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0 -#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0 -#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0 -#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 -#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 -#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0 -#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1 -#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0 -#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0 -#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0 -#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0 -#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0 -#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0 -#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0 -#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0 -#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0 -#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1 -#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1 -#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1 -#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2 -#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1 -#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2 -#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1 -#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2 -#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2 -#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2 -#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1 -#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 -#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5 -#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 -#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2 -#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2 -#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1 -#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 -#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 -#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1 -#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3 -#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2 -#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2 -#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1 -#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1 -#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1 -#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1 -#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1 -#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1 -#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1 -#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1 -#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2 -#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1 -#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3 -#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 -#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1 -#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 -#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3 -#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 -#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2 -#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1 -#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1 -#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2 -#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2 -#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1 -#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1 -#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2 -#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2 -#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1 -#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0 -#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3 -#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4 -#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2 -#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1 -#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3 -#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5 -#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2 -#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1 -#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1 -#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2 -#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4 -#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2 -#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1 -#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1 -#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2 -#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4 -#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5 -#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 -#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 -#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0 -#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0 -#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0 -#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1 -#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0 -#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0 -#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0 -#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0 -#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1 -#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 -#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 -#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1 -#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0 -#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0 -#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0 -#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0 -#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2 -#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3 -#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2 -#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 -#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 -#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1 -#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0 -#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1 -#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0 -#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1 -#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1 -#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0 -#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0 -#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0 -#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0 -#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0 -#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1 -#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0 -#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0 -#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0 -#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 -#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0 -#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0 -#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0 -#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0 -#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0 -#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0 -#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0 -#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1 -#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0 -#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0 -#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0 -#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0 -#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0 -#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1 -#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0 -#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0 - -#endif /* __DTS_IMX6SX_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sabreauto.dts b/software/linux/kernel/arch/arm/boot/dts/imx6sx-sabreauto.dts deleted file mode 100644 index 240a2864d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "imx6sx.dtsi" - -/ { - model = "Freescale i.MX6 SoloX Sabre Auto Board"; - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; - - memory { - reg = <0x80000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vcc_sd3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&vcc_sd3>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&iomuxc { - imx6x-sabreauto { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ - >; - }; - - pinctrl_vcc_sd3: vccsd3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb-reva.dts deleted file mode 100644 index 71005478c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "imx6sx-sdb.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB RevA Board"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: s25fl128s@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl128s", "jedec,spi-nor"; - spi-max-frequency = <66000000>; - }; - - flash1: s25fl128s@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl128s", "jedec,spi-nor"; - spi-max-frequency = <66000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb-sai.dts b/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb-sai.dts deleted file mode 100644 index 0155450d6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb-sai.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2016 NXP Semiconductors - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx6sx-sdb.dts" - -/ { - sound { - audio-cpu = <&sai1>; - }; -}; - -&audmux { - /* pin conflict with sai */ - status = "disabled"; -}; - -&sai1 { - status = "okay"; -}; - -&sdma { - gpr = <&gpr>; - /* SDMA event remap for SAI1 */ - fsl,sdma-event-remap = <0 15 1>, <0 16 1>; -}; - -&ssi2 { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb.dts b/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb.dts deleted file mode 100644 index d71da30c9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb.dts +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "imx6sx-sdb.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB RevB Board"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@08 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <0>; - }; - - flash1: n25q256a@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb.dtsi deleted file mode 100644 index 9d70cfd40..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ /dev/null @@ -1,604 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include -#include -#include "imx6sx.dtsi" - -/ { - model = "Freescale i.MX6 SoloX SDB Board"; - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x80000000 0x40000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - volume-up { - label = "Volume Up"; - gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vcc_sd3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_psu_5v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "PSU-5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_lcd_3v3: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "lcd-3v3"; - gpio = <&gpio3 27 0>; - enable-active-high; - }; - - reg_peri_3v3: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_enet_3v3: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_3v3>; - regulator-name = "enet_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - }; - }; - - sound { - compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <6>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-supply = <®_enet_3v3>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; - phy-handle = <ðphy2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SX_CLK_AUDIO>; - DCVDD-supply = <&vgen4_reg>; - DBVDD-supply = <&vgen4_reg>; - AVDD-supply = <&vgen4_reg>; - CPVDD-supply = <&vgen4_reg>; - MICVDD-supply = <&vgen3_reg>; - PLLVDD-supply = <&vgen4_reg>; - SPKVDD1-supply = <®_psu_5v>; - SPKVDD2-supply = <®_psu_5v>; - }; -}; - -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hback-porch = <89>; - hfront-porch = <164>; - vback-porch = <23>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "disabled"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart5 { /* for bluetooth */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - non-removable; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&vcc_sd3>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - imx6x-sdb { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 - MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 - MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 - MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 - MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 - MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 - MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 - MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 - MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 - >; - }; - - pinctrl_enet_3v3: enet3v3grp { - fsl,pins = < - MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 - MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 - MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 - MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 - MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 - MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 - MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 - MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 - MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 - MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 - MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 - MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 - >; - }; - - pinctrl_gpio_keys: gpio_keysgrp { - fsl,pins = < - MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 - MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 - MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 - MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - >; - }; - - pinctrl_peri_3v3: peri3v3grp { - fsl,pins = < - MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 - >; - }; - - pinctrl_pwm3: pwm3grp-1 { - fsl,pins = < - MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 - >; - }; - - pinctrl_qspi2: qspi2grp { - fsl,pins = < - MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 - MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 - MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 - MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 - MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 - MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 - MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 - MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 - MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 - MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 - MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 - MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 - >; - }; - - pinctrl_vcc_sd3: vccsd3grp { - fsl,pins = < - MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 - MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 - MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 - MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 - MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 - MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usb_otg2: usbot2ggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 - MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 - MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 - MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 - MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 - MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6sx.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6sx.dtsi deleted file mode 100644 index 1a473e83e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6sx.dtsi +++ /dev/null @@ -1,1298 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include "imx6sx-pinfunc.h" -#include "skeleton.dtsi" - -/ { - aliases { - can0 = &flexcan1; - can1 = &flexcan2; - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - spi4 = &ecspi5; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1075000 - 198000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6SX_CLK_ARM>, - <&clks IMX6SX_CLK_PLL2_PFD2>, - <&clks IMX6SX_CLK_STEP>, - <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - soc-supply = <®_soc>; - }; - }; - - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ckil: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock@3 { - compatible = "fixed-clock"; - reg = <3>; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - ocram: sram@00900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - clocks = <&clks IMX6SX_CLK_OCRAM>; - }; - - L2: l2-cache@00a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - gpu: gpu@01800000 { - compatible = "vivante,gc"; - reg = <0x01800000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>, - <&clks IMX6SX_CLK_GPU>; - clock-names = "bus", "core", "shader"; - }; - - dma_apbh: dma-apbh@01804000 { - compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x01804000 0x2000>; - interrupts = , - , - , - ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6SX_CLK_APBH_DMA>; - }; - - gpmi: gpmi-nand@01806000{ - compatible = "fsl,imx6sx-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01806000 0x2000>, <0x01808000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clks IMX6SX_CLK_GPMI_IO>, - <&clks IMX6SX_CLK_GPMI_APB>, - <&clks IMX6SX_CLK_GPMI_BCH>, - <&clks IMX6SX_CLK_GPMI_BCH_APB>, - <&clks IMX6SX_CLK_PER1_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - aips1: aips-bus@02000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@02000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@02004000 { - compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = ; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, - <&clks IMX6SX_CLK_OSC>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks 0>, <&clks 0>, <&clks 0>, - <&clks IMX6SX_CLK_IPG>, - <&clks 0>, <&clks 0>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: ecspi@02008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI1>, - <&clks IMX6SX_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: ecspi@0200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI2>, - <&clks IMX6SX_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: ecspi@02010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI3>, - <&clks IMX6SX_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: ecspi@02014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI4>, - <&clks IMX6SX_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@02020000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - esai: esai@02024000 { - reg = <0x02024000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ESAI_IPG>, - <&clks IMX6SX_CLK_ESAI_MEM>, - <&clks IMX6SX_CLK_ESAI_EXTAL>, - <&clks IMX6SX_CLK_ESAI_IPG>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "core", "mem", "extal", - "fsys", "spba"; - status = "disabled"; - }; - - ssi1: ssi@02028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI1_IPG>, - <&clks IMX6SX_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@0202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI2_IPG>, - <&clks IMX6SX_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@02030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SSI3_IPG>, - <&clks IMX6SX_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - asrc: asrc@02034000 { - reg = <0x02034000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ASRC_MEM>, - <&clks IMX6SX_CLK_ASRC_IPG>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck", "spba"; - dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, - <&sdma 19 20 1>, <&sdma 20 20 1>, - <&sdma 21 20 1>, <&sdma 22 20 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - status = "okay"; - }; - }; - - pwm1: pwm@02080000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM1>, - <&clks IMX6SX_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm2: pwm@02084000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM2>, - <&clks IMX6SX_CLK_PWM2>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm3: pwm@02088000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM3>, - <&clks IMX6SX_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm4: pwm@0208c000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM4>, - <&clks IMX6SX_CLK_PWM4>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - flexcan1: can@02090000 { - compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_CAN1_IPG>, - <&clks IMX6SX_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - flexcan2: can@02094000 { - compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_CAN2_IPG>, - <&clks IMX6SX_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt: gpt@02098000 { - compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_GPT_BUS>, - <&clks IMX6SX_CLK_GPT_3M>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@0209c000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 5 26>; - }; - - gpio2: gpio@020a0000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 31 20>; - }; - - gpio3: gpio@020a4000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 51 29>; - }; - - gpio4: gpio@020a8000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 80 32>; - }; - - gpio5: gpio@020ac000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 24>; - }; - - gpio6: gpio@020b0000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020b0000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; - }; - - gpio7: gpio@020b4000 { - compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; - reg = <0x020b4000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; - }; - - kpp: kpp@020b8000 { - compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; - status = "disabled"; - }; - - wdog1: wdog@020bc000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; - }; - - wdog2: wdog@020c0000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; - status = "disabled"; - }; - - clks: ccm@020c4000 { - compatible = "fsl,imx6sx-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; - }; - - anatop: anatop@020c8000 { - compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", - "syscon", "simple-bus"; - reg = <0x020c8000 0x1000>; - interrupts = , - , - ; - - regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - }; - - regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - }; - - regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2875000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2875000>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pcie: regulator-vddpcie { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpcie"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupts = ; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; - }; - - usbphy1: usbphy@020c9000 { - compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@020ca000 { - compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x60>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - }; - }; - - epit1: epit@020d0000 { - reg = <0x020d0000 0x4000>; - interrupts = ; - }; - - epit2: epit@020d4000 { - reg = <0x020d4000 0x4000>; - interrupts = ; - }; - - src: src@020d8000 { - compatible = "fsl,imx6sx-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: gpc@020dc000 { - compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - }; - - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6sx-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: iomuxc-gpr@020e4000 { - compatible = "fsl,imx6sx-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e4000 0x4000>; - }; - - sdma: sdma@020ec000 { - compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SDMA>, - <&clks IMX6SX_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - /* imx6sx reuses imx6q sdma firmware */ - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - }; - - aips2: aips-bus@02100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - crypto: caam@2100000 { - compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SX_CLK_CAAM_MEM>, - <&clks IMX6SX_CLK_CAAM_ACLK>, - <&clks IMX6SX_CLK_CAAM_IPG>, - <&clks IMX6SX_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - usbotg1: usb@02184000 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@02184200 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh: usb@02184400 { - compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBOH3>; - fsl,usbmisc = <&usbmisc 2>; - phy_type = "hsic"; - fsl,anatop = <&anatop>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@02184800 { - #index-cells = <1>; - compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6SX_CLK_USBOH3>; - }; - - fec1: ethernet@02188000 { - compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SX_CLK_ENET>, - <&clks IMX6SX_CLK_ENET_AHB>, - <&clks IMX6SX_CLK_ENET_PTP>, - <&clks IMX6SX_CLK_ENET_REF>, - <&clks IMX6SX_CLK_ENET_PTP>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - status = "disabled"; - }; - - mlb: mlb@0218c000 { - reg = <0x0218c000 0x4000>; - interrupts = , - , - ; - clocks = <&clks IMX6SX_CLK_MLB>; - status = "disabled"; - }; - - usdhc1: usdhc@02190000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC1>, - <&clks IMX6SX_CLK_USDHC1>, - <&clks IMX6SX_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@02194000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC2>, - <&clks IMX6SX_CLK_USDHC2>, - <&clks IMX6SX_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@02198000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC3>, - <&clks IMX6SX_CLK_USDHC3>, - <&clks IMX6SX_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: usdhc@0219c000 { - compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USDHC4>, - <&clks IMX6SX_CLK_USDHC4>, - <&clks IMX6SX_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@021a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@021a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@021a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C3>; - status = "disabled"; - }; - - mmdc: mmdc@021b0000 { - compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - }; - - fec2: ethernet@021b4000 { - compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; - reg = <0x021b4000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6SX_CLK_ENET>, - <&clks IMX6SX_CLK_ENET_AHB>, - <&clks IMX6SX_CLK_ENET_PTP>, - <&clks IMX6SX_CLK_ENET2_REF_125M>, - <&clks IMX6SX_CLK_ENET_PTP>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - status = "disabled"; - }; - - weim: weim@021b8000 { - compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_EIM_SLOW>; - }; - - ocotp: ocotp@021bc000 { - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - }; - - sai1: sai@021d4000 { - compatible = "fsl,imx6sx-sai"; - reg = <0x021d4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SAI1_IPG>, - <&clks IMX6SX_CLK_SAI1>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; - status = "disabled"; - }; - - audmux: audmux@021d8000 { - compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - - sai2: sai@021dc000 { - compatible = "fsl,imx6sx-sai"; - reg = <0x021dc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_SAI2_IPG>, - <&clks IMX6SX_CLK_SAI2>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; - status = "disabled"; - }; - - qspi1: qspi@021e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-qspi"; - reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6SX_CLK_QSPI1>, - <&clks IMX6SX_CLK_QSPI1>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - qspi2: qspi@021e4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-qspi"; - reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6SX_CLK_QSPI2>, - <&clks IMX6SX_CLK_QSPI2>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - uart2: serial@021e8000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; - reg = <0x021e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@021ec000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; - reg = <0x021ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@021f0000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; - reg = <0x021f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@021f4000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@021f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_I2C4>; - status = "disabled"; - }; - }; - - aips3: aips-bus@02200000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02200000 0x100000>; - ranges; - - spba-bus@02200000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02240000 0x40000>; - ranges; - - csi1: csi@02214000 { - reg = <0x02214000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, - <&clks IMX6SX_CLK_CSI>, - <&clks IMX6SX_CLK_DCIC1>; - clock-names = "disp-axi", "csi_mclk", "dcic"; - status = "disabled"; - }; - - pxp: pxp@02218000 { - reg = <0x02218000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PXP_AXI>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pxp-axi", "disp-axi"; - status = "disabled"; - }; - - csi2: csi@0221c000 { - reg = <0x0221c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, - <&clks IMX6SX_CLK_CSI>, - <&clks IMX6SX_CLK_DCIC2>; - clock-names = "disp-axi", "csi_mclk", "dcic"; - status = "disabled"; - }; - - lcdif1: lcdif@02220000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; - reg = <0x02220000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - lcdif2: lcdif@02224000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; - reg = <0x02224000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - vadc: vadc@02228000 { - reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; - reg-names = "vadc-vafe", "vadc-vdec"; - clocks = <&clks IMX6SX_CLK_VADC>, - <&clks IMX6SX_CLK_CSI>; - clock-names = "vadc", "csi"; - status = "disabled"; - }; - }; - - adc1: adc@02280000 { - compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; - reg = <0x02280000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - adc2: adc@02284000 { - compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; - reg = <0x02284000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_IPG>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - wdog3: wdog@02288000 { - compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; - reg = <0x02288000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; - status = "disabled"; - }; - - ecspi5: ecspi@0228c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; - reg = <0x0228c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_ECSPI5>, - <&clks IMX6SX_CLK_ECSPI5>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@022a0000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; - reg = <0x022a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_UART_IPG>, - <&clks IMX6SX_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm5: pwm@022a4000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM5>, - <&clks IMX6SX_CLK_PWM5>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm6: pwm@022a8000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM6>, - <&clks IMX6SX_CLK_PWM6>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm7: pwm@022ac000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x022ac000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM7>, - <&clks IMX6SX_CLK_PWM7>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - - pwm8: pwm@0022b0000 { - compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x0022b0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PWM8>, - <&clks IMX6SX_CLK_PWM8>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - }; - }; - - pcie: pcie@0x08000000 { - compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x4000>; /* DBI */ - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - /* configuration space */ - ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 - /* downstream I/O */ - 0x81000000 0 0 0x08f80000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; - num-lanes = <1>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_PCIE_AXI>, - <&clks IMX6SX_CLK_LVDS1_OUT>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie_ref_125m", "pcie_axi", - "lvds_gate", "display_axi"; - status = "disabled"; - }; - }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/software/linux/kernel/arch/arm/boot/dts/imx6ul-14x14-evk.dts deleted file mode 100644 index e281d5087..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ /dev/null @@ -1,499 +0,0 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "imx6ul.dtsi" - -/ { - model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_sd1_vmmc: sd1_regulator { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "mx6ul-wm8960"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Speaker", "SPK_LP", - "Speaker", "SPK_LN", - "Speaker", "SPK_RP", - "Speaker", "SPK_RN", - "LINPUT1", "Mic Jack", - "LINPUT3", "Mic Jack", - "RINPUT1", "Mic Jack", - "RINPUT2", "Mic Jack"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&cpu0 { - arm-supply = <®_arm>; - soc-supply = <®_soc>; -}; - -&i2c2 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: wm8960@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8960"; - reg = <0x1a>; - wlf,shared-lrclk; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - reg = <2>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - display = <&display0>; - status = "okay"; - - display0: display { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a"; - spi-max-frequency = <29000000>; - reg = <0>; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xffff>; - pre-charge-time = <0xfff>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_sd1_vmmc>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - - pinctrl_csi1: csi1grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 - MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 - MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 - MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 - MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 - MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 - MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 - MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 - MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 - MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 - MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 - MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - /* used for lcd reset */ - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_sim2: sim2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 - MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 - MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 - MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 - MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 - MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-geam-kit.dts b/software/linux/kernel/arch/arm/boot/dts/imx6ul-geam-kit.dts deleted file mode 100644 index 4c4af7614..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-geam-kit.dts +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include "imx6ul-geam.dtsi" - -/ { - model = "Engicam GEAM6UL"; - compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&lcdif { - display = <&display0>; - status = "okay"; - - display0: display { - bits-per-pixel = <16>; - bus-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <28000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <30>; - hback-porch = <30>; - hsync-len = <64>; - vback-porch = <5>; - vfront-porch = <5>; - vsync-len = <20>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - status = "okay"; -}; - -&tsc { - measure-delay-time = <0x1ffff>; - pre-charge-time = <0x1fff>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-geam.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6ul-geam.dtsi deleted file mode 100644 index 64eb9ed59..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-geam.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include "imx6ul.dtsi" - -/ { - memory { - reg = <0x80000000 0x08000000>; - }; - - chosen { - stdout-path = &uart1; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_3p3v>; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_3p3v>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - display = <&display0>; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pin = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/software/linux/kernel/arch/arm/boot/dts/imx6ul-pico-hobbit.dts deleted file mode 100644 index 827d9e8fc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ /dev/null @@ -1,549 +0,0 @@ -/* - * Copyright 2015 Technexion Ltd. - * - * Author: Wig Cheng - * Richard Hu - * Tapani Utriainen - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx6ul.dtsi" - -/ { - model = "Technexion Pico i.MX6UL Board"; - compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; - - memory { - reg = <0x80000000 0x10000000>; - }; - - chosen { - stdout-path = &uart6; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 6 0>; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6ul-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&codec>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - leds { - compatible = "gpio-leds"; - - hobbitled { - label = "hobbitled"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - max-speed = <100>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@08 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - /* VDD_ARM_SOC_IN*/ - sw1b_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* DRAM */ - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - /* DRAM */ - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: sgtl5000@0a { - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&sys_mclk>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; -}; - -&i2c3 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <33200000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <46>; - hsync-len = <1>; - vback-porch = <22>; - vfront-porch = <23>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { /* Wifi SDIO */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_brcm>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ - MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 - MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - /* LCD reset */ - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 - MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 - MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 - MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 - MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 - MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 - MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 - MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx6ul-pinfunc.h deleted file mode 100644 index 0034eeb84..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-pinfunc.h +++ /dev/null @@ -1,938 +0,0 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX6UL_PINFUNC_H -#define __DTS_IMX6UL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 -#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 - -#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 - -#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 -#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 -#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 -#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 -#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 -#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0 -#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0 -#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 -#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0 -#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 -#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 -#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 -#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 -#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 -#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 -#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 -#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 -#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 -#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 -#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 -#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 -#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 -#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 -#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 -#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 -#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 -#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 -#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 -#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 -#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 -#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 -#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 -#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 -#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 -#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 -#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 -#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 -#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 -#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 -#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 -#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 -#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 -#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 -#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 -#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 -#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 -#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 -#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 -#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 -#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 -#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 -#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 -#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 -#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 -#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 -#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 -#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 -#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 -#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 -#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 -#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 -#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 -#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 -#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 -#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 -#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 -#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 -#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 -#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 -#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 -#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 -#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 -#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 -#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 -#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 -#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 -#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 -#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 -#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 -#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 -#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 -#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 -#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 -#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 -#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 -#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 -#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 -#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 -#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 -#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 -#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 -#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 -#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 -#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 -#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 -#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 -#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 -#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 -#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 -#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 -#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 -#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 -#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 -#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 -#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 -#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 -#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 -#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 -#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 -#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 -#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 -#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 -#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 -#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 -#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 -#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0 -#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 -#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 -#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 -#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 -#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 -#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 -#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0 -#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 -#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 -#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 -#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 -#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0 -#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 -#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 -#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 -#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 -#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0 -#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 -#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0 -#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 -#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 -#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 -#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0 -#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 -#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 -#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0 -#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 -#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 -#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0 -#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 -#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0 -#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 -#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0 -#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0 -#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 -#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 -#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 -#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 -#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 -#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 -#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0 -#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 -#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 -#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 -#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 -#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 -#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 -#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 -#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 -#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 -#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 -#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0 -#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 -#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 -#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 -#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 -#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 -#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 -#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 -#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 -#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 -#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 -#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 -#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 -#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 -#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 -#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 -#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 -#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 -#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0 -#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 -#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 -#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 -#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 -#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 -#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 -#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 -#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 -#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 -#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 -#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 -#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 -#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 -#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 -#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 -#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 -#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 -#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 -#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 -#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 -#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 -#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 -#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 -#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 -#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 -#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 -#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 -#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 -#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 -#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 -#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 -#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 -#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 -#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 -#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 -#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 -#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 -#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 -#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 -#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 -#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 -#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0 -#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 -#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 -#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 -#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 -#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 -#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 -#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 -#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 -#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 -#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 -#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 -#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 -#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 -#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 -#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 -#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 -#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0 -#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 -#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 -#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 -#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 -#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 -#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 -#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 -#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 -#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 -#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 -#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 -#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 -#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 -#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 -#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 -#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 -#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 -#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0 -#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 -#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 -#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 -#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 -#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 -#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 -#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 -#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 -#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 -#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 -#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 -#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 -#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 -#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 -#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 -#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 -#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 -#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 -#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 -#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 -#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 -#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 -#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 -#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 -#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 -#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 -#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 -#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 -#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0 -#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 -#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 -#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 -#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 -#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 -#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 -#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0 -#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 -#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 -#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0 -#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 -#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 -#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 -#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 -#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 -#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 -#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 -#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 -#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 -#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 -#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 -#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 -#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 -#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 -#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 -#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 -#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 -#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 -#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 -#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 -#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 -#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 -#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 -#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 -#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 -#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 -#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 -#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 -#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 -#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 -#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 -#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 -#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 -#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 -#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 -#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 -#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 -#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 -#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 -#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 -#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 -#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 -#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 -#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 -#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 -#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 -#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 -#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 -#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 -#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 -#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 -#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0 -#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 -#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 -#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 -#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 -#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 -#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 -#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 -#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 -#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 -#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 -#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 -#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 -#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 -#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 -#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 -#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 -#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0 -#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 -#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 -#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 -#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 -#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 -#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 -#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 -#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 -#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 - -#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts b/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts deleted file mode 100644 index 8c2f3df79..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0010 Module"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - /delete-property/ mmc1; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts b/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts deleted file mode 100644 index d82698e7d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0011 Module"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - mmc0 = &usdhc2; - mmc1 = &usdhc1; - }; -}; - -&gpmi { - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - no-1-8-v; - non-removable; - fsl,wp-controller; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts deleted file mode 100644 index 7c5dd1b31..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx6ul.dtsi" -#include "imx6ul-tx6ul.dtsi" - -/ { - model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard"; - compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; - - aliases { - lcdif_24bit_pins_a = &pinctrl_disp0_3; - mmc0 = &usdhc1; - /delete-property/ mmc1; - serial2 = &uart3; - serial4 = &uart5; - }; - /delete-node/ sound; -}; - -&can1 { - xceiver-supply = <®_3v3>; -}; - -&can2 { - xceiver-supply = <®_3v3>; -}; - -&ds1339 { - status = "disabled"; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy0_int>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - - etnphy1: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy1_int>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - }; -}; - -&i2c_gpio { - status = "disabled"; -}; - -&i2c2 { - /delete-node/ codec@0a; - /delete-node/ touchscreen@48; - - rtc: mcp7940x@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&kpp { - status = "disabled"; -}; - -&lcdif { - pinctrl-0 = <&pinctrl_disp0_3>; -}; - -®_usbotg_vbus{ - status = "disabled"; -}; - -&usdhc1 { - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - /delete-property/ cd-gpios; - cap-sdio-irq; -}; - -&uart1 { - pinctrl-0 = <&pinctrl_uart1>; - /delete-property/ uart-has-rtscts; -}; - -&uart2 { - pinctrl-0 = <&pinctrl_uart2>; - /delete-property/ uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart7>; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart8>; - status = "disabled"; /* conflicts with LCDIF */ -}; - -&iomuxc { - hoggrp { - fsl,pins = < - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */ - >; - }; - - pinctrl_disp0_3: disp0grp-3 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - /* LCD_DATA08..09 not wired */ - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - /* LCD_DATA16..17 not wired */ - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x0b0b0 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x0b0b0 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart7: uart7grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0b0b0 - MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart8: uart8grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0b0b0 - MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x0b0b0 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul.dtsi deleted file mode 100644 index 530e9ca13..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ /dev/null @@ -1,973 +0,0 @@ -/* - * Copyright 2015 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - aliases { - can0 = &can2; - can1 = &can1; - display = &display; - i2c0 = &i2c2; - i2c1 = &i2c_gpio; - i2c2 = &i2c1; - i2c3 = &i2c3; - i2c4 = &i2c4; - lcdif_23bit_pins_a = &pinctrl_disp0_1; - lcdif_24bit_pins_a = &pinctrl_disp0_2; - pwm0 = &pwm5; - reg_can_xcvr = ®_can_xcvr; - serial2 = &uart5; - serial4 = &uart3; - spi0 = &ecspi2; - spi1 = &spi_gpio; - stk5led = &user_led; - usbh1 = &usbotg2; - usbotg = &usbotg1; - }; - - chosen { - stdout-path = &uart1; - }; - - memory { - reg = <0 0>; /* will be filled by U-Boot */ - }; - - clocks { - mclk: mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_rst>; - enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; - power-supply = <®_lcd_pwr>; - /* - * a poor man's way to create a 1:1 relationship between - * the PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - i2c_gpio: i2c-gpio { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio>; - gpios = < - &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ - &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ - >; - clock-frequency = <400000>; - status = "okay"; - - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - status = "disabled"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led: user { - label = "Heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_3v3_etn: regulator-3v3etn { - compatible = "regulator-fixed"; - regulator-name = "3V3_ETN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_power>; - gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_2v5: regulator-2v5 { - compatible = "regulator-fixed"; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_can_xcvr: regulator-canxcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - enable-active-low; - }; - - reg_lcd_pwr: regulator-lcdpwr { - compatible = "regulator-fixed"; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwr>; - gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; - - reg_usbh1_vbus: regulator-usbh1vbus { - compatible = "regulator-fixed"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg_vbus: regulator-usbotgvbus { - compatible = "regulator-fixed"; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - spi_gpio: spi-gpio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi_gpio>; - gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>; - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - num-chipselects = <2>; - cs-gpios = < - &gpio1 29 GPIO_ACTIVE_HIGH - &gpio1 10 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <660000>; - }; - - spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <660000>; - }; - }; - - sound { - compatible = "karo,imx6ul-tx6ul-sgtl5000", - "simple-audio-card"; - simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - codec_dai: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - fsl,spi-num-chipselects = <2>; - cs-gpios = < - &gpio1 29 GPIO_ACTIVE_HIGH - &gpio1 10 GPIO_ACTIVE_HIGH - >; - status = "disabled"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <60000000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <60000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - etnphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy0_int>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - - etnphy1: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy1_int>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; - phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - phy-supply = <®_3v3_etn>; - phy-handle = <&etnphy1>; - status = "disabled"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_2v5>; - VDDIO-supply = <®_3v3>; - clocks = <&mclk>; - }; - - polytouch: polytouch@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edt_ft5x06>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - touchscreen: touchscreen@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc2007>; - interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_NONE>; - gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <660>; - wakeup-source; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - /* sample keymap */ - /* row/col 0..3 are mapped to KPP row/col 4..7 */ - linux,keymap = < - MATRIX_KEY(4, 4, KEY_POWER) - MATRIX_KEY(4, 5, KEY_KP0) - MATRIX_KEY(4, 6, KEY_KP1) - MATRIX_KEY(4, 7, KEY_KP2) - MATRIX_KEY(5, 4, KEY_KP3) - MATRIX_KEY(5, 5, KEY_KP4) - MATRIX_KEY(5, 6, KEY_KP5) - MATRIX_KEY(5, 7, KEY_KP6) - MATRIX_KEY(6, 4, KEY_KP7) - MATRIX_KEY(6, 5, KEY_KP8) - MATRIX_KEY(6, 6, KEY_KP9) - >; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_disp0_1>; - lcd-supply = <®_lcd_pwr>; - display = <&display>; - status = "okay"; - - display: display@di0 { - bits-per-pixel = <32>; - bus-width = <24>; - status = "okay"; - - display-timings { - VGA { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <31>; - vsync-len = <2>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ETV570 { - clock-frequency = <25200000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0350 { - clock-frequency = <6413760>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0430 { - clock-frequency = <9009000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - - ET0500 { - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ET0700 { /* same as ET0500 */ - clock-frequency = <33264000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - ETQ570 { - clock-frequency = <6596040>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&pwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm5>; - #pwm-cells = <3>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usbotg_vbus>; - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - fsl,wp-controller; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ - >; - }; - - pinctrl_disp0_1: disp0grp-1 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */ - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_disp0_2: disp0grp-2 { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ - MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ - MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ - >; - }; - - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1 - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_etnphy_power: etnphy-pwrgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ - >; - }; - - pinctrl_etnphy0_int: etnphy-intgrp-0 { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ - >; - }; - - pinctrl_etnphy0_rst: etnphy-rstgrp-0 { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ - >; - }; - - pinctrl_etnphy1_int: etnphy-intgrp-1 { - fsl,pins = < - MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */ - >; - }; - - pinctrl_etnphy1_rst: etnphy-rstgrp-1 { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 - >; - }; - - pinctrl_flexcan_xcvr: flexcan-xcvrgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c_gpio: i2c-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 - MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 - >; - }; - - pinctrl_lcd_pwr: lcd-pwrgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ - >; - }; - - pinctrl_lcd_rst: lcd-rstgrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */ - >; - }; - - pinctrl_pwm5: pwm5grp { - fsl,pins = < - MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ - >; - }; - - pinctrl_spi_gpio: spi-gpiogrp { - fsl,pins = < - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ - >; - }; - - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart1_rtscts: uart1-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 - MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart2_rtscts: uart2-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 - MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 - MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 - >; - }; - - pinctrl_uart5_rtscts: uart5-rtsctsgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 - >; - }; - - pinctrl_usbh1_oc: usbh1-ocgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ - >; - }; - - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ - >; - }; - - pinctrl_usbotg_oc: usbotg-ocgrp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ - >; - }; - - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 - >; - }; - - pinctrl_usdhc1_cd: usdhc1cdgrp { - fsl,pins = < - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 - /* eMMC RESET */ - MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx6ul.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx6ul.dtsi deleted file mode 100644 index c5c05fdcc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx6ul.dtsi +++ /dev/null @@ -1,942 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include "imx6ul-pinfunc.h" -#include "skeleton.dtsi" - -/ { - aliases { - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - sai1 = &sai1; - sai2 = &sai2; - sai3 = &sai3; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clock-latency = <61036>; /* two CLK32 periods */ - operating-points = < - /* kHz uV */ - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; - clocks = <&clks IMX6UL_CLK_ARM>, - <&clks IMX6UL_CLK_PLL2_BUS>, - <&clks IMX6UL_CLK_PLL2_PFD2>, - <&clks IMX6UL_CA7_SECONDARY_SEL>, - <&clks IMX6UL_CLK_STEP>, - <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>, - <&clks IMX6UL_PLL1_BYPASS>, - <&clks IMX6UL_CLK_PLL1>, - <&clks IMX6UL_PLL1_BYPASS_SRC>, - <&clks IMX6UL_CLK_OSC>; - clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", - "secondary_sel", "step", "pll1_sw", - "pll1_sys", "pll1_bypass", "pll1", - "pll1_bypass_src", "osc"; - arm-supply = <®_arm>; - soc-supply = <®_soc>; - }; - }; - - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a02000 0x1000>, - <0x00a04000 0x2000>, - <0x00a06000 0x2000>; - }; - - ckil: clock-cli { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - ipp_di0: clock-di0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; - - ipp_di1: clock-di1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - status = "disabled"; - }; - - ocram: sram@00900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - }; - - dma_apbh: dma-apbh@01804000 { - compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x01804000 0x2000>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clks IMX6UL_CLK_APBHDMA>; - }; - - gpmi: gpmi-nand@01806000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01806000 0x2000>, <0x01808000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bch"; - clocks = <&clks IMX6UL_CLK_GPMI_IO>, - <&clks IMX6UL_CLK_GPMI_APB>, - <&clks IMX6UL_CLK_GPMI_BCH>, - <&clks IMX6UL_CLK_GPMI_BCH_APB>, - <&clks IMX6UL_CLK_PER_BCH>; - clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", - "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - aips1: aips-bus@02000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba-bus@02000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - ecspi1: ecspi@02008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI1>, - <&clks IMX6UL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: ecspi@0200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI2>, - <&clks IMX6UL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: ecspi@02010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI3>, - <&clks IMX6UL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: ecspi@02014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ECSPI4>, - <&clks IMX6UL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart7: serial@02018000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02018000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART7_IPG>, - <&clks IMX6UL_CLK_UART7_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@02020000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART1_IPG>, - <&clks IMX6UL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart8: serial@02024000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x02024000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART8_IPG>, - <&clks IMX6UL_CLK_UART8_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sai1: sai@02028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x02028000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI1_IPG>, - <&clks IMX6UL_CLK_SAI1>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 35 24 0>, - <&sdma 36 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai2: sai@0202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x0202c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI2_IPG>, - <&clks IMX6UL_CLK_SAI2>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 37 24 0>, - <&sdma 38 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@02030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; - reg = <0x02030000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SAI3_IPG>, - <&clks IMX6UL_CLK_SAI3>, - <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma 39 24 0>, - <&sdma 40 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - tsc: tsc@02040000 { - compatible = "fsl,imx6ul-tsc"; - reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_ADC2>; - clock-names = "tsc", "adc"; - status = "disabled"; - }; - - pwm1: pwm@02080000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM1>, - <&clks IMX6UL_CLK_PWM1>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@02084000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM2>, - <&clks IMX6UL_CLK_PWM2>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@02088000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM3>, - <&clks IMX6UL_CLK_PWM3>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@0208c000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM4>, - <&clks IMX6UL_CLK_PWM4>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - can1: flexcan@02090000 { - compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02090000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAN1_IPG>, - <&clks IMX6UL_CLK_CAN1_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can2: flexcan@02094000 { - compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; - reg = <0x02094000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_CAN2_IPG>, - <&clks IMX6UL_CLK_CAN2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt1: gpt@02098000 { - compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; - reg = <0x02098000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_GPT1_BUS>, - <&clks IMX6UL_CLK_GPT1_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@0209c000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, - <&iomuxc 16 33 16>; - }; - - gpio2: gpio@020a0000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; - }; - - gpio3: gpio@020a4000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 65 29>; - }; - - gpio4: gpio@020a8000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; - }; - - gpio5: gpio@020ac000 { - compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; - }; - - fec2: ethernet@020b4000 { - compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; - reg = <0x020b4000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET2_REF_125M>, - <&clks IMX6UL_CLK_ENET2_REF_125M>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<1>; - fsl,num-rx-queues=<1>; - status = "disabled"; - }; - - kpp: kpp@020b8000 { - compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_KPP>; - status = "disabled"; - }; - - wdog1: wdog@020bc000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG1>; - }; - - wdog2: wdog@020c0000 { - compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_WDOG2>; - status = "disabled"; - }; - - clks: ccm@020c4000 { - compatible = "fsl,imx6ul-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; - }; - - anatop: anatop@020c8000 { - compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", - "syscon", "simple-bus"; - reg = <0x020c8000 0x1000>; - interrupts = , - , - ; - - reg_3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2625000>; - regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "cpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - }; - - usbphy1: usbphy@020c9000 { - compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBPHY1>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@020ca000 { - compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBPHY2>; - phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x60>; - status = "disabled"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - }; - }; - - epit1: epit@020d0000 { - reg = <0x020d0000 0x4000>; - interrupts = ; - }; - - epit2: epit@020d4000 { - reg = <0x020d4000 0x4000>; - interrupts = ; - }; - - src: src@020d8000 { - compatible = "fsl,imx6ul-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = , - ; - #reset-cells = <1>; - }; - - gpc: gpc@020dc000 { - compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - interrupt-parent = <&intc>; - }; - - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6ul-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - gpr: iomuxc-gpr@020e4000 { - compatible = "fsl,imx6ul-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e4000 0x4000>; - }; - - gpt2: gpt@020e8000 { - compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; - reg = <0x020e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_GPT2_BUS>, - <&clks IMX6UL_CLK_GPT2_SERIAL>; - clock-names = "ipg", "per"; - }; - - sdma: sdma@020ec000 { - compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", - "fsl,imx35-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_SDMA>, - <&clks IMX6UL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pwm5: pwm@020f0000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM5>, - <&clks IMX6UL_CLK_PWM5>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@020f4000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM6>, - <&clks IMX6UL_CLK_PWM6>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm7: pwm@020f8000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM7>, - <&clks IMX6UL_CLK_PWM7>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm8: pwm@020fc000 { - compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; - reg = <0x020fc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_PWM8>, - <&clks IMX6UL_CLK_PWM8>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - }; - - aips2: aips-bus@02100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - usbotg1: usb@02184000 { - compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@02184200 { - compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@02184800 { - #index-cells = <1>; - compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - }; - - fec1: ethernet@02188000 { - compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; - reg = <0x02188000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET_REF>, - <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<1>; - fsl,num-rx-queues=<1>; - status = "disabled"; - }; - - usdhc1: usdhc@02190000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USDHC1>, - <&clks IMX6UL_CLK_USDHC1>, - <&clks IMX6UL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@02194000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_USDHC2>, - <&clks IMX6UL_CLK_USDHC2>, - <&clks IMX6UL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - adc1: adc@02198000 { - compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; - reg = <0x02198000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_ADC1>; - num-channels = <2>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - status = "disabled"; - }; - - i2c1: i2c@021a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@021a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@021a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C3>; - status = "disabled"; - }; - - mmdc: mmdc@021b0000 { - compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - }; - - lcdif: lcdif@021c8000 { - compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; - reg = <0x021c8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, - <&clks IMX6UL_CLK_LCDIF_APB>, - <&clks IMX6UL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - - qspi: qspi@021e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; - reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX6UL_CLK_QSPI>, - <&clks IMX6UL_CLK_QSPI>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - uart2: serial@021e8000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021e8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART2_IPG>, - <&clks IMX6UL_CLK_UART2_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@021ec000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021ec000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART3_IPG>, - <&clks IMX6UL_CLK_UART3_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart4: serial@021f0000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021f0000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART4_IPG>, - <&clks IMX6UL_CLK_UART4_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@021f4000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021f4000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART5_IPG>, - <&clks IMX6UL_CLK_UART5_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c4: i2c@021f8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; - reg = <0x021f8000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_I2C4>; - status = "disabled"; - }; - - uart6: serial@021fc000 { - compatible = "fsl,imx6ul-uart", - "fsl,imx6q-uart"; - reg = <0x021fc000 0x4000>; - interrupts = ; - clocks = <&clks IMX6UL_CLK_UART6_IPG>, - <&clks IMX6UL_CLK_UART6_SERIAL>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi deleted file mode 100644 index 373ee1919..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; -}; - -&adc1 { - status = "okay"; -}; - -&adc2 { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; -}; - -&lcdif { - display = <&display0>; - status = "okay"; - - display0: lcd-display { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing_vga>; - - /* Standard VGA timing */ - timing_vga: 640x480 { - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <24>; - vback-porch = <32>; - vfront-porch = <11>; - hsync-len = <96>; - vsync-len = <2>; - de-active = <1>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usdhc1 { - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7-colibri.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx7-colibri.dtsi deleted file mode 100644 index a9cc65725..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7-colibri.dtsi +++ /dev/null @@ -1,624 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - bl: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - }; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; -}; - -&cpu0 { - arm-supply = <®_DCDC2>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; - clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rmii"; - phy-supply = <®_LDO1>; - fsl,magic-packet; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; - status = "okay"; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1_mclk>; - VDDA-supply = <®_module_3v3_avdd>; - VDDIO-supply = <®_module_3v3>; - VDDD-supply = <®_DCDC3>; - }; - - ad7879@2c { - compatible = "adi,ad7879-1"; - reg = <0x2c>; - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - }; - - pmic@33 { - compatible = "ricoh,rn5t567"; - reg = <0x33>; - - regulators { - reg_DCDC1: DCDC1 { /* V1.0_SOC */ - regulator-min-microvolt = <975000>; - regulator-max-microvolt = <1125000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_DCDC2: DCDC2 { /* V1.1_ARM */ - regulator-min-microvolt = <975000>; - regulator-max-microvolt = <1125000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_DCDC3: DCDC3 { /* V1.8 */ - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <1825000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_DCDC4: DCDC4 { /* V1.35_DRAM */ - regulator-min-microvolt = <1325000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_LDO2: LDO2 { /* +V1.8_SD */ - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <3325000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */ - regulator-min-microvolt = <3275000>; - regulator-max-microvolt = <3325000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_LDO4: LDO4 { /* V1.8_LPSR */ - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <1825000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */ - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <1825000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -}; - -®_1p0d { - vin-supply = <®_DCDC3>; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; - fsl,dte-mode; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; - fsl,dte-mode; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - fsl,dte-mode; -}; - -&usbotg1 { - dr_mode = "host"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; - no-1-8-v; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - disable-wp; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; - - pinctrl_gpio1: gpio1-grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0X14 /* SODIMM 77 */ - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x14 /* SODIMM 91 */ - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ - MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x14 /* SODIMM 105 */ - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x14 /* SODIMM 107 */ - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ - MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ - MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ - MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ - MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ - >; - }; - - pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ - fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x14 /* SODIMM 69 */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ - MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ - MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ - MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ - >; - }; - - pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */ - fsl,pins = < - MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ - MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ - MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ - MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x14 /* SODIMM 146 */ - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x14 /* SODIMM 148 */ - >; - }; - - pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */ - fsl,pins = < - MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ - >; - }; - - pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */ - fsl,pins = < - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 - - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - >; - }; - - pinctrl_ecspi3_cs: ecspi3-cs-grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 - >; - }; - - pinctrl_ecspi3: ecspi3-grp { - fsl,pins = < - MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 - >; - }; - - pinctrl_flexcan2: flexcan2-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand-grp { - fsl,pins = < - MX7D_PAD_SD3_CLK__NAND_CLE 0x71 - MX7D_PAD_SD3_CMD__NAND_ALE 0x71 - MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 - MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 - MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 - MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 - MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 - MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 - MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 - MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 - MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 - MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 - MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 - MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 - MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 - >; - }; - - pinctrl_i2c4: i2c4-grp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f - MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_lcdif_dat: lcdif-dat-grp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - >; - }; - - pinctrl_lcdif_dat_24: lcdif-dat-24-grp { - fsl,pins = < - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdif-ctrl-grp { - fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - >; - }; - - pinctrl_pwm1: pwm1-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 - >; - }; - - pinctrl_pwm2: pwm2-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 - >; - }; - - pinctrl_pwm3: pwm3-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 - >; - }; - - pinctrl_pwm4: pwm4-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 - >; - }; - - pinctrl_uart1: uart1-grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 - MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 - MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 - >; - }; - - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { - fsl,pins = < - MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ - MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ - >; - }; - - pinctrl_uart2: uart2-grp { - fsl,pins = < - MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 - MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 - MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 - MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 - >; - }; - pinctrl_uart3: uart3-grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 - >; - }; - - pinctrl_usbotg2_reg: gpio-usbotg2-vbus { - fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ - >; - }; - - pinctrl_usdhc1: usdhc1-grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - >; - }; - - pinctrl_sai1: sai1-grp { - fsl,pins = < - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f - >; - }; - - pinctrl_sai1_mclk: sai1grp_mclk { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f - >; - }; -}; - -&iomuxc_lpsr { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_lpsr>; - - pinctrl_gpio_lpsr: gpio1-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x59 - MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x59 - MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x59 - >; - }; - - pinctrl_i2c1: i2c1-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f - MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_cd_usdhc1: usdhc1-cd-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ - >; - }; - - pinctrl_uart1_ctrl2: uart1-ctrl2-grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ - MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/software/linux/kernel/arch/arm/boot/dts/imx7d-cl-som-imx7.dts deleted file mode 100644 index 58b09bf1b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Support for CompuLab CL-SOM-iMX7 System-on-Module - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Ilya Ledvich - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "CompuLab CL-SOM-iMX7"; - compatible = "compulab,cl-som-imx7", "fsl,imx7d"; - - memory { - reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ - }; - - reg_usb_otg1_vbus: regulator-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/software/linux/kernel/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts deleted file mode 100644 index bd01d2cc6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx7d-colibri.dtsi" -#include "imx7-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d", - "fsl,imx7d"; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; - }; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7d-colibri.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx7d-colibri.dtsi deleted file mode 100644 index 3c2cb502b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7d-colibri.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx7d.dtsi" -#include "imx7-colibri.dtsi" - -/ { - memory { - reg = <0x80000000 0x20000000>; - }; -}; - -&usbotg2 { - dr_mode = "host"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7d-nitrogen7.dts b/software/linux/kernel/arch/arm/boot/dts/imx7d-nitrogen7.dts deleted file mode 100644 index ce08f180f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ /dev/null @@ -1,744 +0,0 @@ -/* - * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "Boundary Devices i.MX7 Nitrogen7 Board"; - compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; - - aliases { - fb_lcd = &lcdif; - t_lcd = &t_lcd; - }; - - memory { - reg = <0x80000000 0x40000000>; - }; - - backlight-j9 { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight_j9>; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - default-on; - }; - - backlight-j20 { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; - clock-names = "slow"; - regulator-name = "reg_wlan"; - startup-delay-us = <70000>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, - <&clks IMX7D_CLKO2_ROOT_DIV>; - assigned-clock-parents = <&clks IMX7D_CKIL>; - assigned-clock-rates = <0>, <32768>; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - }; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_3v3>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@08 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - rtc@68 { - compatible = "rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - touch@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_tsc2004>; - interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - clock-names = "mclk"; - wlf,shared-lrclk; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - lcd-supply = <®_vref_3v3>; - display = <&display0>; - status = "okay"; - - display0: lcd-display { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - /* default to Okaya display */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <48>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vgen3_reg>; - bus-width = <4>; - fsl,tuning-step = <2>; - wakeup-source; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wlan>; - cap-power-off-card; - keep-power-in-suspend; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = <38400000>; - }; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; - - pinctrl_hog_1: hoggrp-1 { - fsl,pins = < - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 - MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 - MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c2_rv4162: i2c2-rv4162grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c3_tsc2004: i2c3tsc2004grp { - fsl,pins = < - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 - MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_j2: j2grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d - MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d - MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d - MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d - MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d - MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d - MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 - MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 - >; - }; - - pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - >; - }; -}; - -&iomuxc_lpsr { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_2>; - - pinctrl_hog_2: hoggrp-2 { - fsl,pins = < - MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x7d - MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x7d - >; - }; - - pinctrl_backlight_j9: backlightj9grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x7d - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x7d - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x7d - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x75 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7d-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/imx7d-pinfunc.h deleted file mode 100644 index 3f9f0d9c8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7d-pinfunc.h +++ /dev/null @@ -1,1154 +0,0 @@ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX7D_PINFUNC_H -#define __DTS_IMX7D_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 -#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 -#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 -#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 -#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 -#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 -#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 -#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 -#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 -#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 -#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4 -#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 -#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 -#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5 -#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 -#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 -#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0 -#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0 -#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0 -#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1 -#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0 -#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0 -#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0 -#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0 -#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0 -#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0 -#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1 -#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0 -#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0 -#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0 -#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0 -#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0 -#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0 -#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0 -#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1 -#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0 -#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0 -#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0 -#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0 -#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0 -#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0 -#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0 -#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0 -#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0 -#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0 -#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0 -#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0 -#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0 -#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0 -#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0 -#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0 -#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0 -#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0 -#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0 -#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0 -#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0 -#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0 -#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0 -#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0 -#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0 -#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0 -#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0 -#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0 -#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0 -#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1 -#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1 -#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0 -#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0 -#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1 -#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1 -#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0 -#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1 -#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0 -#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0 -#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0 -#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0 -#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0 -#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1 -#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0 -#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0 -#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0 -#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1 -#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0 -#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0 -#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0 -#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0 -#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0 -#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1 -#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0 -#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1 -#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0 -#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0 -#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0 -#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1 -#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0 -#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0 -#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1 -#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1 -#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1 -#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0 -#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0 -#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1 -#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1 -#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0 -#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0 -#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1 -#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0 -#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1 -#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0 -#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1 -#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1 -#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1 -#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1 -#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1 -#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1 -#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0 -#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1 -#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1 -#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1 -#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0 -#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0 -#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0 -#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1 -#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0 -#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0 -#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2 -#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0 -#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1 -#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2 -#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2 -#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2 -#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2 -#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2 -#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0 -#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2 -#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0 -#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2 -#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0 -#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2 -#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2 -#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0 -#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2 -#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0 -#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2 -#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0 -#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2 -#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0 -#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2 -#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0 -#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1 -#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0 -#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1 -#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0 -#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1 -#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0 -#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2 -#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0 -#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2 -#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0 -#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2 -#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0 -#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2 -#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0 -#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1 -#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2 -#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0 -#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2 -#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0 -#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1 -#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2 -#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0 -#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1 -#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2 -#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0 -#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1 -#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0 -#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0 -#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0 -#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0 -#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0 -#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0 -#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0 -#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0 -#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0 -#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1 -#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0 -#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0 -#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0 -#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0 -#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0 -#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0 -#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 -#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 -#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0 -#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 -#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 -#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 -#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 -#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 -#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0 -#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2 -#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0 -#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0 -#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0 -#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3 -#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0 -#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0 -#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0 -#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2 -#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0 -#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0 -#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0 -#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3 -#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0 -#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0 -#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0 -#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0 -#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1 -#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0 -#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0 -#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1 -#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0 -#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0 -#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0 -#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1 -#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1 -#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0 -#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0 -#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0 -#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1 -#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0 -#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0 -#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1 -#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0 -#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0 -#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0 -#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0 -#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2 -#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0 -#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1 -#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1 -#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0 -#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1 -#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0 -#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0 -#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0 -#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0 -#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1 -#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2 -#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0 -#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0 -#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1 -#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1 -#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1 -#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0 -#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0 -#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2 -#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1 -#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0 -#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0 -#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1 -#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1 -#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0 -#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0 -#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2 -#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0 -#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0 -#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0 -#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1 -#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1 -#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0 -#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0 -#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2 -#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0 -#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1 -#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0 -#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0 -#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1 -#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0 -#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1 -#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2 -#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1 -#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1 -#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3 -#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1 -#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1 -#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1 -#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2 -#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1 -#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0 -#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1 -#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3 -#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1 -#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0 -#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2 -#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1 -#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2 -#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0 -#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3 -#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1 -#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2 -#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0 -#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2 -#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1 -#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2 -#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0 -#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3 -#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1 -#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0 -#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4 -#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1 -#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1 -#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5 -#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1 -#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1 -#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0 -#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4 -#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1 -#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1 -#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1 -#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5 -#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1 -#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1 -#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1 -#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1 -#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1 -#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4 -#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1 -#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1 -#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1 -#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5 -#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1 -#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1 -#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1 -#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4 -#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1 -#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1 -#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0 -#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5 -#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1 -#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1 -#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2 -#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2 -#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1 -#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2 -#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2 -#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2 -#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2 -#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0 -#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0 -#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1 -#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0 -#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2 -#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0 -#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3 -#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0 -#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2 -#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3 -#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1 -#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2 -#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2 -#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2 -#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2 -#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2 -#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2 -#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2 -#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2 -#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3 -#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2 -#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3 -#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4 -#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2 -#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5 -#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2 -#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4 -#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2 -#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5 -#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2 -#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0 -#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0 -#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2 -#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3 -#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1 -#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3 -#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2 -#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3 -#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0 -#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3 -#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1 -#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3 -#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1 -#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1 -#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3 -#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1 -#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0 -#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3 -#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1 -#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4 -#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5 -#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1 -#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1 -#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4 -#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2 -#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1 -#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1 -#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0 -#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1 -#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5 -#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3 -#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1 -#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4 -#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2 -#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4 -#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3 -#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4 -#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2 -#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3 -#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4 -#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4 -#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4 -#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2 -#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1 -#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1 -#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2 -#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0 -#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1 -#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2 -#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1 -#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2 -#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2 -#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0 - -#endif /* __DTS_IMX7D_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7d-sbc-imx7.dts b/software/linux/kernel/arch/arm/boot/dts/imx7d-sbc-imx7.dts deleted file mode 100644 index f8a868552..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7d-sbc-imx7.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Support for CompuLab SBC-iMX7 Single Board Computer - * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ - * Author: Ilya Ledvich - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - */ - -#include "imx7d-cl-som-imx7.dts" - -/ { - model = "CompuLab SBC-iMX7"; - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - status = "okay"; -}; - -&iomuxc { - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7d-sdb.dts b/software/linux/kernel/arch/arm/boot/dts/imx7d-sdb.dts deleted file mode 100644 index 2f33c463c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7d-sdb.dts +++ /dev/null @@ -1,645 +0,0 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "imx7d.dtsi" - -/ { - model = "Freescale i.MX7 SabreSD Board"; - compatible = "fsl,imx7d-sdb", "fsl,imx7d"; - - memory { - reg = <0x80000000 0x80000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_3v3: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - reg_vref_1v8: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&adc2 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; -}; - -&ecspi3 { - fsl,spi-num-chipselects = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - status = "okay"; - - tsc2046@0 { - compatible = "ti,tsc2046"; - reg = <0>; - spi-max-frequency = <1000000>; - pinctrl-names ="default"; - pinctrl-0 = <&pinctrl_tsc2046_pendown>; - interrupt-parent = <&gpio2>; - interrupts = <29 0>; - pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <0>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <0>; - ti,pressure-max = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <400>; - wakeup-source; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@08 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: wm8960@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - clock-names = "mclk"; - wlf,shared-lrclk; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - display = <&display0>; - status = "okay"; - - display0: display { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx7d-sdb { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 - MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 - MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 - MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f - MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - MX7D_PAD_LCD_RESET__LCD_RESET 0x79 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_tsc2046_pendown: tsc2046_pendown { - fsl,pins = < - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 - MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 - MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 - MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 - MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x59 - MX7D_PAD_SD2_CLK__SD2_CLK 0x19 - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */ - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5a - MX7D_PAD_SD2_CLK__SD2_CLK 0x1a - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { - fsl,pins = < - MX7D_PAD_SD2_CMD__SD2_CMD 0x5b - MX7D_PAD_SD2_CLK__SD2_CLK 0x1b - MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b - MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b - MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b - MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b - >; - }; - - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7d.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx7d.dtsi deleted file mode 100644 index f6dee41a0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7d.dtsi +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx7s.dtsi" - -/ { - cpus { - cpu0: cpu@0 { - operating-points = < - /* KHz uV */ - 996000 1075000 - 792000 975000 - >; - clock-frequency = <996000000>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clock-frequency = <996000000>; - }; - }; - - soc { - etm@3007d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007d000 0x1000>; - - /* - * System will hang if added nosmp in kernel command line - * without arm,primecell-periphid because amba bus try to - * read id and core1 power off at this time. - */ - arm,primecell-periphid = <0xbb956>; - cpu = <&cpu1>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etm1_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port1>; - }; - }; - }; - }; -}; - -&aips3 { - usbotg2: usb@30b20000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b20000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbmisc2: usbmisc@30b20200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b20200 0x200>; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY2_CLK>; - clock-names = "main_clk"; - }; - - fec2: ethernet@30bf0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30bf0000 0x10000>; - interrupts = , - , - ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - status = "disabled"; - }; -}; - -&ca_funnel_ports { - port@1 { - reg = <1>; - ca_funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&etm1_out_port>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/software/linux/kernel/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts deleted file mode 100644 index bd2a49c1a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "imx7s-colibri.dtsi" -#include "imx7-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s", - "fsl,imx7s"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7s-colibri.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx7s-colibri.dtsi deleted file mode 100644 index b81013455..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7s-colibri.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "imx7s.dtsi" -#include "imx7-colibri.dtsi" - -/ { - memory { - reg = <0x80000000 0x10000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7s-warp.dts b/software/linux/kernel/arch/arm/boot/dts/imx7s-warp.dts deleted file mode 100644 index 0345267f3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7s-warp.dts +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Copyright (C) 2016 NXP Semiconductors. - * Author: Fabio Estevam - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include "imx7s.dtsi" - -/ { - model = "Warp i.MX7 Board"; - compatible = "warp,imx7s-warp", "fsl,imx7s"; - - memory { - reg = <0x80000000 0x20000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_gpio>; - autorepeat; - - back { - label = "Back"; - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; - }; - - reg_bt: regulator-bt { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_reg>; - enable-active-high; - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - regulator-name = "bt_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - }; - }; -}; - -&clks { - assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <884736000>; -}; - -&cpu0 { - arm-supply = <&sw1a_reg>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@08 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - codec: sgtl5000@0a { - #sound-dai-cells = <0>; - reg = <0x0a>; - compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1_mclk>; - VDDA-supply = <&vgen4_reg>; - VDDIO-supply = <&vgen4_reg>; - VDDD-supply = <&vgen2_reg>; - }; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <36864000>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - keep-power-in-suspend; - no-1-8-v; - non-removable; - vmmc-supply = <®_brcm>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-step = <2>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ - >; - }; - - pinctrl_bt_reg: btreggrp { - fsl,pins = < - MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f - MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 - >; - }; - - pinctrl_sai1_mclk: sai1mclkgrp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x19 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x1a - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x1b - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/imx7s.dtsi b/software/linux/kernel/arch/arm/boot/dts/imx7s.dtsi deleted file mode 100644 index 2b6cb05bc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/imx7s.dtsi +++ /dev/null @@ -1,991 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include "imx7d-pinfunc.h" -#include "skeleton.dtsi" - -/ { - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <792000000>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX7D_CLK_ARM>; - }; - }; - - ckil: clock-cki { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - funnel@30041000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30041000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ca_funnel_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; - ca_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etm0_out_port>; - }; - }; - - /* funnel output port */ - port@2 { - reg = <0>; - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - - /* the other input ports are not connect to anything */ - }; - }; - - etm@3007c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007c000 0x1000>; - cpu = <&cpu0>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etm0_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port0>; - }; - }; - }; - - funnel@30083000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30083000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; - hugo_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ca_funnel_out_port0>; - }; - }; - - port@1 { - reg = <1>; - hugo_funnel_in_port1: endpoint { - slave-mode; /* M4 input */ - }; - }; - - port@2 { - reg = <0>; - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - - /* the other input ports are not connect to anything */ - }; - }; - - etf@30084000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30084000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - etf_in_port: endpoint { - slave-mode; - remote-endpoint = <&hugo_funnel_out_port0>; - }; - }; - - port@1 { - reg = <0>; - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - }; - - etr@30086000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30086000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - tpiu@30087000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x30087000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x31001000 0x1000>, - <0x31002000 0x2000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - aips1: aips-bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30000000 0x400000>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , /* GPIO1_INT15_0 */ - ; /* GPIO1_INT31_16 */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 13 32>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 45 29>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 74 24>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 98 18>; - }; - - gpio6: gpio@30250000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30250000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 116 23>; - }; - - gpio7: gpio@30260000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30260000 0x10000>; - interrupts = , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 139 16>; - }; - - wdog1: wdog@30280000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; - }; - - wdog2: wdog@30290000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; - status = "disabled"; - }; - - wdog3: wdog@302a0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; - status = "disabled"; - }; - - wdog4: wdog@302b0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; - status = "disabled"; - }; - - iomuxc_lpsr: iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; - }; - - gpt1: gpt@302d0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302d0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; - }; - - gpt2: gpt@302e0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302e0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt3: gpt@302f0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302f0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt4: gpt@30300000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x30300000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - iomuxc: iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - - ocotp: ocotp-ctrl@30350000 { - compatible = "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clks IMX7D_CLK_DUMMY>; - status = "disabled"; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", - "syscon", "simple-bus"; - reg = <0x30360000 0x10000>; - interrupts = , - ; - - reg_1p0d: regulator-vdd1p0d { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p0d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - anatop-reg-offset = <0x210>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <8>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1200000>; - anatop-enable-bit = <31>; - }; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x60>; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - linux,keycode = ; - wakeup-source; - }; - }; - - clks: ccm@30380000 { - compatible = "fsl,imx7d-ccm"; - reg = <0x30380000 0x10000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>; - clock-names = "ckil", "osc"; - }; - - src: src@30390000 { - compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - }; - - aips2: aips-bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30400000 0x400000>; - ranges; - - adc1: adc@30610000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30610000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - status = "disabled"; - }; - - adc2: adc@30620000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30620000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - status = "disabled"; - }; - - ecspi4: ecspi@30630000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30630000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, - <&clks IMX7D_ECSPI4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - pwm1: pwm@30660000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM1_ROOT_CLK>, - <&clks IMX7D_PWM1_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM2_ROOT_CLK>, - <&clks IMX7D_PWM2_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM3_ROOT_CLK>, - <&clks IMX7D_PWM3_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_PWM4_ROOT_CLK>, - <&clks IMX7D_PWM4_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - lcdif: lcdif@30730000 { - compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; - reg = <0x30730000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; - clock-names = "pix", "axi"; - status = "disabled"; - }; - }; - - aips3: aips-bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30800000 0x400000>; - ranges; - - ecspi1: ecspi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, - <&clks IMX7D_ECSPI1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: ecspi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, - <&clks IMX7D_ECSPI2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: ecspi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, - <&clks IMX7D_ECSPI3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART1_ROOT_CLK>, - <&clks IMX7D_UART1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART2_ROOT_CLK>, - <&clks IMX7D_UART2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART3_ROOT_CLK>, - <&clks IMX7D_UART3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sai1: sai@308a0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308a0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI1_IPG_CLK>, - <&clks IMX7D_SAI1_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; - status = "disabled"; - }; - - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308b0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI2_IPG_CLK>, - <&clks IMX7D_SAI2_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; - status = "disabled"; - }; - - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308c0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SAI3_IPG_CLK>, - <&clks IMX7D_SAI3_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; - status = "disabled"; - }; - - flexcan1: can@30a00000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a00000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - flexcan2: can@30a10000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a10000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C1_ROOT_CLK>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C2_ROOT_CLK>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C3_ROOT_CLK>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_I2C4_ROOT_CLK>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART4_ROOT_CLK>, - <&clks IMX7D_UART4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@30a70000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a70000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART5_ROOT_CLK>, - <&clks IMX7D_UART5_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@30a80000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a80000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART6_ROOT_CLK>, - <&clks IMX7D_UART6_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart7: serial@30a90000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a90000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_UART7_ROOT_CLK>, - <&clks IMX7D_UART7_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - usbotg1: usb@30b10000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b10000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbh: usb@30b30000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b30000 0x200>; - interrupts = ; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop3>; - fsl,usbmisc = <&usbmisc3 0>; - phy_type = "hsic"; - dr_mode = "host"; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbmisc1: usbmisc@30b10200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b10200 0x200>; - }; - - usbmisc3: usbmisc@30b30200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b30200 0x200>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY1_CLK>; - clock-names = "main_clk"; - }; - - usbphynop3: usbphynop3 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; - clock-names = "main_clk"; - }; - - usdhc1: usdhc@30b40000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC1_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: usdhc@30b50000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC2_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: usdhc@30b60000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC3_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - sdma: sdma@30bd0000 { - compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_SDMA_CORE_CLK>, - <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-BGA128M.dts b/software/linux/kernel/arch/arm/boot/dts/infinity2m-BGA128M.dts deleted file mode 100755 index fad48c178..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-BGA128M.dts +++ /dev/null @@ -1,71 +0,0 @@ -/* -* infinity2m-BGA128M.dts- Sigmastar -* -* Copyright (c) [2019~2020] SigmaStar Technology. -* -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License version 2 for more details. -* -*/ - -/dts-v1/; -#include "infinity2m.dtsi" - -/ { - model = "INFIITY2M SSC007A-S01A"; - compatible = "sstar,infinity2m"; - - memory { - reg = <0x20000000 0x07E00000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/mtdblock2 init=/linuxrc"; - }; - -/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - cma0 { - compatible = "shared-dma-pool"; - reg = <0x26E00000 0x01000000>; - reusable; - alignment = <0x1000>; - linux,cma-default; - }; - }; - - soc { - Sstar-ehci-1 { - compatible = "Sstar-ehci-1"; - dpdm_swap=<0>; - power-enable-pad = ; - }; - Sstar-ehci-2 { - compatible = "Sstar-ehci-2"; - dpdm_swap=<0>; - power-enable-pad = ; - }; - Sstar-ehci-3 { - compatible = "Sstar-ehci-3"; - dpdm_swap=<0>; - power-enable-pad = ; - }; - cpufreq { - vid_width = <1>; - vid_gpios = ; - vid_voltages = <900 1000>; //2b'00 2b'01 - vid_default = <0>; //2b'00 - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-clks_simple.dtsi b/software/linux/kernel/arch/arm/boot/dts/infinity2m-clks_simple.dtsi deleted file mode 100755 index 533591eca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-clks_simple.dtsi +++ /dev/null @@ -1,834 +0,0 @@ -/* -* infinity2m-clks_simple.dtsi- Sigmastar -* -* Copyright (c) [2019~2020] SigmaStar Technology. -* -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License version 2 for more details. -* -*/ -/* generated manually for fast booting */ - -CLK_VOID: CLK_VOID { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; -}; - -CLK_upll_384m: CLK_upll_384m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_upll>; - clock-div = <5>; - clock-mult = <4>; -}; - -CLK_upll_320m: CLK_upll_320m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_upll>; - clock-div = <3>; - clock-mult = <2>; -}; - -CLK_mpll_288m: CLK_mpll_288m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <288000000>; -}; - -CLK_utmi_240m: CLK_utmi_240m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_utmi>; - clock-div = <2>; - clock-mult = <1>; -}; - -CLK_mpll_216m: CLK_mpll_216m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <216000000>; -}; - -CLK_utmi_192m: CLK_utmi_192m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_utmi>; - clock-div = <5>; - clock-mult = <2>; -}; - -CLK_mpll_172m: CLK_mpll_172m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <172800000>; -}; - -CLK_utmi_160m: CLK_utmi_160m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_utmi>; - clock-div = <3>; - clock-mult = <1>; -}; - -CLK_mpll_123m: CLK_mpll_123m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <123400000>; -}; - -CLK_mpll_86m: CLK_mpll_86m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <86400000>; -}; - -CLK_mpll_288m_div2: CLK_mpll_288m_div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_288m>; - clock-div = <2>; - clock-mult = <1>; -}; - -CLK_mpll_288m_div4: CLK_mpll_288m_div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_288m>; - clock-div = <4>; - clock-mult = <1>; -}; - -CLK_mpll_288m_div8: CLK_mpll_288m_div8 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_288m>; - clock-div = <8>; - clock-mult = <1>; -}; -CLK_mpll_216m_div2: CLK_mpll_216m_div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_216m>; - clock-div = <2>; - clock-mult = <1>; -}; - -CLK_mpll_216m_div4: CLK_mpll_216m_div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_216m>; - clock-div = <4>; - clock-mult = <1>; -}; - -CLK_mpll_216m_div8: CLK_mpll_216m_div8 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_216m>; - clock-div = <8>; - clock-mult = <1>; -}; -CLK_mpll_86m_div2: CLK_mpll_86m_div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_86m>; - clock-div = <2>; - clock-mult = <1>; -}; -CLK_utmi_192m_div4: CLK_utmi_192m_div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_utmi_192m>; - clock-div = <4>; - clock-mult = <1>; -}; - -CLK_utmi_160m_div4: CLK_utmi_160m_div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_utmi_160m>; - clock-div = <4>; - clock-mult = <1>; -}; - -CLK_utmi_160m_div5: CLK_utmi_160m_div5 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_utmi_160m>; - clock-div = <5>; - clock-mult = <1>; -}; - -CLK_utmi_160m_div8: CLK_utmi_160m_div8 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_utmi_160m>; - clock-div = <8>; - clock-mult = <1>; -}; - -CLK_xtali_12m: CLK_xtali_12m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; -}; - -CLK_xtali_12m_div8: CLK_xtali_12m_div8 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_xtali_12m>; - clock-div = <8>; - clock-mult = <1>; -}; - -CLK_xtali_12m_div16: CLK_xtali_12m_div16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_xtali_12m>; - clock-div = <16>; - clock-mult = <1>; -}; - -CLK_xtali_12m_div40: CLK_xtali_12m_div40 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_xtali_12m>; - clock-div = <40>; - clock-mult = <1>; -}; -CLK_xtali_24m: CLK_xtali_24m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; -}; -CLK_miu_p: CLK_miu_p { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_miu>; - clock-div = <1>; - clock-mult = <1>; -}; - -CLK_mspi0_p: CLK_mspi0_p { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mspi0>; - clock-div = <1>; - clock-mult = <1>; -}; - -CLK_mspi1_p: CLK_mspi1_p { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mspi1>; - clock-div = <1>; - clock-mult = <1>; -}; - -CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_miu_sc_gp>; - clock-div = <1>; - clock-mult = <1>; -}; - -CLK_miu2x_p: CLK_miu2x_p { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_miu2x>; - clock-div = <1>; - clock-mult = <1>; -}; - -CLK_mcu_p: CLK_mcu_p { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mcu>; - clock-div = <1>; - clock-mult = <1>; -}; - -CLK_mcu_pm_p: CLK_mcu_pm_p { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mcu>; - clock-div = <1>; - clock-mult = <1>; -}; - -CLK_sdio_p: CLK_sdio_p { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_sdio>; - clock-div = <1>; - clock-mult = <1>; -}; - -CLK_fcie_p: CLK_fcie_p { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; -}; - - -CLK_eth_buf: CLK_eth_buf { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; -}; - -CLK_rmii_buf: CLK_rmii_buf { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; -}; - -CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; -}; -CLK_mpll_432m: CLK_mpll_432m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <432000000>; -}; - -CLK_hdmi_in: CLK_hdmi_in { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <432000000>; -}; - -CLK_dac_in: CLK_dac_in { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <432000000>; -}; -CLK_miu_sc_gp: CLK_miu_sc_gp { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_miu_p>; - clock-div = <1>; - clock-mult = <1>; -}; -CLK_miu2x: CLK_miu2x { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_ddrpll_clk>; - clock-div = <1>; - clock-mult = <1>; -}; -CLK_mpll_144m: CLK_mpll_144m { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <144000000>; -}; - -CLK_mpll_144m_div2: CLK_mpll_144m_div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_144m>; - clock-div = <2>; - clock-mult = <1>; -}; - -CLK_mpll_144m_div4: CLK_mpll_144m_div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_mpll_144m>; - clock-div = <4>; - clock-mult = <1>; -}; - -CLK_xtali_12m_div2: CLK_xtali_12m_div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_xtali_12m>; - clock-div = <2>; - clock-mult = <1>; -}; - -CLK_xtali_12m_div4: CLK_xtali_12m_div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_xtali_12m>; - clock-div = <4>; - clock-mult = <1>; -}; - -CLK_xtali_12m_div12: CLK_xtali_12m_div12 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_xtali_12m>; - clock-div = <12>; - clock-mult = <1>; -}; -CLK_rtc_32k: CLK_rtc_32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; -}; - -CLK_rtc_32k_div4: CLK_rtc_32k_div4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&CLK_rtc_32k>; - clock-div = <4>; - clock-mult = <1>; -}; - - -CLK_miupll_clk: CLK_miupll_clk { - #clock-cells = <0>; - compatible = "sstar,complex-clock"; - clocks = <&CLK_xtali_24m>; -}; - -CLK_ddrpll_clk: CLK_ddrpll_clk { - #clock-cells = <0>; - compatible = "sstar,complex-clock"; - clocks = <&CLK_ddr_syn>; -}; -CLK_cpupll_clk: CLK_cpupll_clk { - #clock-cells = <0>; - compatible = "sstar,complex-clock"; - clocks = <&CLK_mpll_432m>; -}; -CLK_utmi: CLK_utmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <480000000>; -}; - -CLK_upll: CLK_upll { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <480000000>; -}; - -CLK_fuart0_synth_out: CLK_fuart0_synth_out { - #clock-cells = <0>; - compatible = "sstar,complex-clock"; - clocks = <&CLK_fuart0_synth_in>; -}; - -CLK_miu: CLK_miu { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_ddrpll_clk>,<&CLK_VOID>,<&CLK_miupll_clk>,<&CLK_mpll_216m>; - reg = ; - mux-shift = <2>; //2+REG_CKG_MIU_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_MIU_OFFSET - glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET - auto-enable = <1>; -}; -CLK_bdma: CLK_bdma { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET -}; - -CLK_ddr_syn: CLK_ddr_syn { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET - auto-enable = <1>; -}; -CLK_mcu: CLK_mcu { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_432m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_216m_div2>; - reg = ; - mux-shift = <2>; //2+REG_CKG_MCU_OFFSET - mux-width = <3>; - gate-shift = <0>; //0+REG_CKG_MCU_OFFSET - glitch-shift = <5>; //5+REG_CKG_MCU_OFFSET - auto-enable = <1>; -}; - -CLK_riubrdg: CLK_riubrdg { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET - mux-width = <2>; - gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET - auto-enable = <1>; -}; - -CLK_spi: CLK_spi { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_SPI_OFFSET - mux-width = <3>; - gate-shift = <8>; //0+REG_CKG_SPI_OFFSET - auto-enable = <1>; -}; - -CLK_uart0: CLK_uart0 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_UART0_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_UART0_OFFSET -}; - -CLK_uart1: CLK_uart1 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_UART1_OFFSET - mux-width = <2>; - gate-shift = <8>; //0+REG_CKG_UART1_OFFSET -}; - -CLK_uart2: CLK_uart2 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; - reg = ; - mux-shift = <14>; //2+REG_CKG_UART2_OFFSET - mux-width = <2>; - gate-shift = <12>; //0+REG_CKG_UART2_OFFSET -}; - -CLK_fuart0_synth_in: CLK_fuart0_synth_in { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET - mux-width = <2>; - gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET -}; - -CLK_fuart: CLK_fuart { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; - reg = ; - mux-shift = <2>; //2+REG_CKG_FUART_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_FUART_OFFSET -}; - -CLK_mspi0: CLK_mspi0 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; - reg = ; - mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET -}; - -CLK_mspi1: CLK_mspi1 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_288m_div2>; - reg = ; - mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET - mux-width = <2>; - gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET -}; - -CLK_mspi: CLK_mspi { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mspi0_p>,<&CLK_mspi1_p>; - reg = ; - mux-shift = <14>; //2+REG_CKG_MSPI_OFFSET - mux-width = <1>; - gate-shift = <12>; //0+REG_CKG_MSPI_OFFSET -}; - -CLK_miic0: CLK_miic0 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET -}; - -CLK_miic1: CLK_miic1 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET - mux-width = <2>; - gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET -}; - -CLK_sata_phy_108: CLK_sata_phy_108 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_SATA_PHY_108_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_SATA_PHY_108_OFFSET -}; - -CLK_sata_phy_432: CLK_sata_phy_432 { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_432m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_SATA_PHY_432_OFFSET - mux-width = <2>; - gate-shift = <8>; //0+REG_CKG_SATA_PHY_432_OFFSET -}; -CLK_emac_ahb: CLK_emac_ahb { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; - reg = ; - mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET -}; - -CLK_jpe: CLK_jpe { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_upll_320m>,<&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; //max safe clock is 320m - reg = ; - mux-shift = <2>; //2+REG_CKG_JPE_OFFSET - mux-width = <3>; - gate-shift = <0>; //0+REG_CKG_JPE_OFFSET -}; - -CLK_aesdma: CLK_aesdma { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET - glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET -}; -CLK_sdio: CLK_sdio { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; - reg = ; - mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET - mux-width = <3>; - gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET -}; -CLK_sata_pm: CLK_sata_pm { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_216m_div2>,<&CLK_xtali_12m>,<&CLK_xtali_24m>,<&CLK_mpll_123m>; - reg = ; - mux-shift = <10>; //2+REG_CKG_SATA_PM_OFFSET - mux-width = <2>; - gate-shift = <8>; //0+REG_CKG_SATA_PM_OFFSET -}; - -CLK_sata_axi: CLK_sata_axi { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_utmi_240m>,<&CLK_mpll_288m>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_SATA_AXI_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_SATA_AXI_OFFSET -}; -CLK_dac: CLK_dac { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_dac_in>,<&CLK_hdmi_in>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_DAC_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_DAC_OFFSET -}; - -CLK_emac1_tx: CLK_emac1_tx { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; - reg = ; - mux-shift = <2>; //2+REG_CKG_EMAC1_TX_OFFSET - mux-width = <1>; - gate-shift = <0>; //0+REG_CKG_EMAC1_TX_OFFSET -}; - -CLK_emac1_rx: CLK_emac1_rx { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; - reg = ; - mux-shift = <2>; //2+REG_CKG_EMAC1_RX_OFFSET - mux-width = <1>; - gate-shift = <0>; //0+REG_CKG_EMAC1_RX_OFFSET -}; - -CLK_emac1_tx_ref: CLK_emac1_tx_ref { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_rmii_buf>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_EMAC1_TX_REF_OFFSET - mux-width = <1>; - gate-shift = <8>; //0+REG_CKG_EMAC1_TX_REF_OFFSET -}; - -CLK_emac1_rx_ref: CLK_emac1_rx_ref { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_rmii_buf>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_EMAC1_RX_REF_OFFSET - mux-width = <1>; - gate-shift = <8>; //0+REG_CKG_EMAC1_RX_REF_OFFSET -}; - -CLK_emac_tx: CLK_emac_tx { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; - reg = ; - mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET - mux-width = <1>; - gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET -}; - -CLK_emac_rx: CLK_emac_rx { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; - reg = ; - mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET - mux-width = <1>; - gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET -}; - -CLK_emac_tx_ref: CLK_emac_tx_ref { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_rmii_buf>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET - mux-width = <1>; - gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET -}; - -CLK_emac_rx_ref: CLK_emac_rx_ref { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_rmii_buf>,<&CLK_VOID>; - reg = ; - mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET - mux-width = <1>; - gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET -}; - -CLK_hemcu_216m: CLK_hemcu_216m { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_mpll_216m>; - reg = ; - gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET - auto-enable = <1>; -}; - -CLK_spi_pm: CLK_spi_pm { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; - reg = ; - mux-shift = <10>; //2+REG_CKG_SPI_OFFSET - mux-width = <4>; - gate-shift = <8>; //0+REG_CKG_SPI_OFFSET - glitch-shift = <14>; //6+REG_CKG_SPI_OFFSET - auto-enable = <1>; -}; - -CLK_pm_sleep: CLK_pm_sleep { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; - reg = ; - mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET - mux-width = <3>; - auto-enable = <1>; -}; - -CLK_pwm: CLK_pwm { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_mpll_86m>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; - reg = ; - mux-shift = <12>; //2+REG_CKG_PWM_OFFSET - mux-width = <3>; -}; - -CLK_sar: CLK_sar { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; - reg = ; - mux-shift = <7>; //2+REG_CKG_SAR_OFFSET - mux-width = <3>; - gate-shift = <5>; //0+REG_CKG_SAR_OFFSET -}; - -CLK_rtc: CLK_rtc { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>; - reg = ; - mux-shift = <2>; //2+REG_CKG_RTC_OFFSET - mux-width = <2>; - gate-shift = <0>; //0+REG_CKG_RTC_OFFSET -}; - -CLK_ir: CLK_ir { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; - reg = ; - mux-shift = <7>; //2+REG_CKG_IR_OFFSET - mux-width = <3>; - gate-shift = <5>; //0+REG_CKG_IR_OFFSET -}; -#ifdef CONFIG_MS_USCLK -usclk: usclk { - compatible = "usclk"; - clocks = <&CLK_RTC_CLK_32K>, <&CLK_VOID>, <&CLK_aesdma>, <&CLK_armpll_37p125m>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_dec_gp>, <&CLK_bist_sc_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_dac>, <&CLK_dac_in>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_dec_aclk>, <&CLK_dec_bclk>, <&CLK_dec_cclk>, <&CLK_dec_pclk>, <&CLK_dip>, <&CLK_disp_216>, <&CLK_disp_432>, <&CLK_emac1_rx>, <&CLK_emac1_rx_ref>, <&CLK_emac1_tx>, <&CLK_emac1_tx_ref>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_ref>, <&CLK_emac_testrx125_in_lan>, <&CLK_emac_tx>, <&CLK_emac_tx_ref>, <&CLK_eth_buf>, <&CLK_fcie_p>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_ge>, <&CLK_hdmi>, <&CLK_hdmi_in>, <&CLK_hemcu_216m>, <&CLK_ir>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_c>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_lpll_clk_div2>, <&CLK_lpll_clk_div4>, <&CLK_lpll_clk_div8>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_mipi_tx_dsi>, <&CLK_mipi_tx_dsi_apb>, <&CLK_mipi_tx_dsi_p>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_dec_gp>, <&CLK_miu_dig>, <&CLK_miu_dma0>, <&CLK_miu_ff>, <&CLK_miu_miic0>, <&CLK_miu_miic1>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_urdma>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mop>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div32>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi>, <&CLK_mspi0>, <&CLK_mspi0_p>, <&CLK_mspi1>, <&CLK_mspi1_p>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_pwm>, <&CLK_pwr_ctl>, <&CLK_riu>, <&CLK_riu_dec_gp>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_nogating>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_w_clk_dec_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rmii_buf>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sata_axi>, <&CLK_sata_phy_108>, <&CLK_sata_phy_432>, <&CLK_sata_pm>, <&CLK_sc_pixel>, <&CLK_sc_pixel_p>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_uart2>, <&CLK_upll>, <&CLK_upll_320m>, <&CLK_upll_384m>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_utmi_480m>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>; - clock-count = <167>; -}; -#endif diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-doublenet.dtsi b/software/linux/kernel/arch/arm/boot/dts/infinity2m-doublenet.dtsi index 121473098..e574fc722 100755 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-doublenet.dtsi +++ b/software/linux/kernel/arch/arm/boot/dts/infinity2m-doublenet.dtsi @@ -36,10 +36,8 @@ reg = <0x0>; operating-points = < /* kHz uV */ - /* 1200000 1000000 1100000 1000000 - */ 1000000 900000 /* 800000 900000 @@ -57,10 +55,8 @@ reg = <0x1>; operating-points = < /* kHz uV */ - /* 1200000 1000000 1100000 1000000 - */ 1000000 900000 /* 800000 900000 diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-fpga.dts b/software/linux/kernel/arch/arm/boot/dts/infinity2m-fpga.dts deleted file mode 100755 index 85b4bd4c9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-fpga.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* -* infinity2m-fpga.dts- Sigmastar -* -* Copyright (c) [2019~2020] SigmaStar Technology. -* -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License version 2 for more details. -* -*/ - - /* - * Memory Layout - * 0x20000000-0x24000000 64M Kernel - * 0x24000000-0x24800000 8M system - * 0x24800000-0x24900000 1M data - * 0x24900000-0x25000000 7M temp0 - * 0x25000000-0x28000000 48M temp1 - */ -/dts-v1/; -#include "infinity2m-fpga.dtsi" - -/ { - model = "INFINITY2M FPGA"; - compatible = "sstar,infinity2m"; - - memory { - reg = <0x20000000 0x06000000>; - }; - - chosen { - bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/mtdblock0 init=/linuxrc LX_MEM=0x6000000 mma_heap=mma_heap_name0,miu=0,sz=0x2000000"; - }; - - rootfsp:rammtd@0 { - compatible = "mtd-ram"; - reg= <0x27000000 0x00400000>; - bank-width = <1>; - linux,mtd-name = "ROOTFS"; - }; - - /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ - datap:rammtd@1 { - compatible = "mtd-ram"; - reg= <0x27400000 0x0400000>; - bank-width = <1>; - linux,mtd-name = "DATA"; - erase-size = <0x10000>; - }; - - extp:rammtd@2 { - compatible = "mtd-ram"; - reg= <0x27800000 0x0800000>; - bank-width = <1>; - linux,mtd-name = "EXT"; - erase-size = <0x10000>; - }; - -/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - cma0 { - compatible = "shared-dma-pool"; - reusable; - size = <0x01000000>; - alignment = <0x1000>; - linux,cma-default; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-fpga.dtsi b/software/linux/kernel/arch/arm/boot/dts/infinity2m-fpga.dtsi deleted file mode 100755 index c0035fa71..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-fpga.dtsi +++ /dev/null @@ -1,523 +0,0 @@ -/* -* infinity2m-fpga.dtsi- Sigmastar -* -* Copyright (c) [2019~2020] SigmaStar Technology. -* -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License version 2 for more details. -* -*/ - -#include <../../../../drivers/sstar/include/infinity2m/irqs.h> -#include <../../../../drivers/sstar/include/infinity2m/gpio.h> -#include -#include -#include "skeleton.dtsi" - - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - clocks = <&xtal>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - clocks = <&xtal>; - }; - - }; - - xtal: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - aliases { - console = &uart0; - serial0 = &uart0; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&ms_main_intc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gic: gic@16000000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - interrupt-parent = <&gic>; - reg = <0x16001000 0x1000>, - <0x16002000 0x1000>; - }; - - ms_main_intc: ms_main_intc { - compatible = "sstar,main-intc"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent=<&gic>; - interrupt-controller; - }; - - ms_pm_intc: ms_pm_intc { - compatible = "sstar,pm-intc"; - #interrupt-cells = <1>; - interrupt-parent=<&ms_main_intc>; - interrupt-controller; - }; - - arch_timer { - compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; - interrupt-parent=<&gic>; - interrupts = , - , - , - ; - clock-frequency = <24000000>; /* arch_timer must use clock-frequency*/ - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent=<&gic>; - interrupts = , - , - , - ; - }; - - clks: clocks{ - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - -/* - timer_clockevent: timer@1F006040 { - compatible = "sstar,piu-clockevent"; - reg = <0x1F006040 0x100>; - interrupts=; - clocks = <&CLK_xtali_12m>; - }; -*/ -/* - venc{ - compatible = "sstar,venc"; - reg = <0x1F264800 0x100>, <0x1F264A00 0x100>, <0x1F264C00 0x100>, - <0x1F264E00 0x100>, <0x1F265000 0x100>, - <0x1F265200 0x100>, <0x1F265400 0x100>, <0x1F265600 0x100>, <0x1F265800 0x100>; - reg-names = "mhe-0", "mhe-1", "mhe-2", "mfe-0", "mfe-1", "ven-0", "ven-1", "ven-2", "ven-3"; - interrupts = , ; - interrupt-parent = <&ms_main_intc>; - interrupt-names = "mhe-irq", "mfe-irq"; - clocks = <&CLK_vhe>, <&CLK_miu_vhe>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_vhe_gp>; - clock-names = "CKG_venc"; - status = "ok"; - }; - - hvsp1: hvsp1 { - compatible = "sstar,sclhvsp1_i6"; - //reg = <0x1F000000 0x100>; - //clk,chiptop,hvsp0,sc0,dnr,ldc - clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; - clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; - status = "ok"; - interrupts = , , , ; - }; - - hvsp2: hvsp2 { - compatible = "sstar,hvsp2"; - //reg = <0x1F000000 0x100>; - //clk,chiptop,hvsp0,sc0,dnr,ldc - clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; - clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; - status = "ok"; - interrupts = , ; - }; - - hvsp3: hvsp3 { - compatible = "sstar,hvsp3"; - //reg = <0x1F000000 0x100>; - //clk,chiptop,hvsp0,sc0,dnr,ldc - clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; - clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; - status = "ok"; - interrupts = , ; - }; - - scldma1: scldma1 { - compatible = "sstar,scldma1"; - //reg = <0x1F000000 0x100>; - //clk,chiptop,scldma - clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; - clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; - status = "ok"; - interrupts = ; - }; - scldma2: scldma2 { - compatible = "sstar,scldma2"; - //reg = <0x1F000000 0x100>; - //clk,chiptop,scldma - clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; - clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; - status = "ok"; - interrupts = ; - }; - scldma3: scldma3 { - compatible = "sstar,scldma3"; - //reg = <0x1F000000 0x100>; - //clk,chiptop,scldma - clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; - clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; - status = "ok"; - interrupts = ; - }; - scldma4: scldma4 { - compatible = "sstar,scldma4"; - //reg = <0x1F000000 0x100>; - //clk,chiptop,scldma - clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; - clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; - status = "ok"; - interrupts = ; - }; -*/ - vip: vip { - compatible = "sstar,vip"; - status = "ok"; - - //reg = <0x1F224000 0x200>; - }; - - pnl: pnl { - compatible = "sstar,pnl"; - status = "ok"; - - //Reg = <0x1F224000 0x200>; - }; - - disp: disp { - compatible = "sstar,disp"; - status = "ok"; - interrupts = , ; - //Reg = <0x1F224000 0x200>; - }; - - hdmitx: hdmitx { - compatible = "sstar,hdmitx"; - status = "ok"; - - //Reg = <0x1F224000 0x200>; - }; - - ge: ge { - compatible = "sstar,ge"; - status = "ok"; - interrupts = ; - //Reg = <0x1F224000 0x200>; - }; - - uart0: uart@1F221000 { - compatible = "sstar,uart"; - reg = <0x1F221000 0x100>; - interrupts= ; - status = "ok"; - clocks = <&xtal>; - }; - dip { - compatible = "sstar,dip"; - interrupts=; - status = "ok"; - }; - - emac0: emac0 { - compatible = "sstar-emac"; - interrupts = , ; - // clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; - // reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; - reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x00000000 0x000>; - pad = <0x1F203C38 0x0001 0x0001>; // pad selection from 0x0001 - phy-handle = <&phy0>; - max-speed = <10>; - mdio_path = <0>; // force internal mdio - status = "ok"; - mdio-bus { - phy0: ethernet-phy@0 { - // phy-mode = "rmii"; - phy-mode = "mii"; - }; - }; - }; - -/* - emac1: emac1 { - compatible = "sstar-emac"; - interrupts = , ; - // clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; - reg = <0x1F2A2800 0x800>, <0x1F344200 0x600>, <0x00000000 0x000>; - pad = <0x1F203C38 0x0F00 0x0100>; // pad selection from 0x0100/0x0200/0x0300/0x0400/0x0500/0x0600/0x0700/0x0800/0x0900 - phy-handle = <&phy1>; - max-speed = <10>; - status = "ok"; - mdio-bus { - phy1: ethernet-phy@1 { - // phy-mode = "rmii"; - phy-mode = "mii"; - }; - }; - }; -*/ - - flashisp { - compatible = "mtd-flashisp"; - clocks = <&CLK_bdma>; - quadread = <0>; - status = "disabled"; - }; -/* - isp: isp { - compatible = "isp"; - io_phy_addr = <0x1f000000>; - banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; - interrupts = ; - clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; - status = "ok"; - }; -*/ -/* - csi: csi { - compatible = "csi"; - io_phy_addr = <0x1f000000>; - banks = <0x1204>; - interrupts= ; - status = "ok"; - }; - vif: vif { - compatible = "sigma,vif"; - status = "ok"; - reg = <0x1F263200 0x600>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x0 0x0>, <0x1F203C00 0x200>, <0x1F226600 0x200>, <0x1F207000 0x200>, <0x1F000000 0x400000>; - clocks = <&CLK_sr_mclk>; - interrupts = ; - // Config sensor 0 pad mux - vif_sr0_par_mode = <2>; - vif_sr0_mipi_mode = <2>; - vif_sr0_bt656_mode = <2>; - // Config sensor 1 pad mux - vif_sr1_par_mode = <2>; - vif_sr1_mipi_mode = <2>; - vif_sr1_bt656_mode = <2>; - }; -*/ - ispalgo: ispalgo { - compatible = "sstar,ispalgo"; - status = "ok"; - }; - - ispmid: ispmid { - compatible = "sstar,ispmid"; - status = "ok"; - }; - - sensorif: sensorif { - compatible = "sigma,sensorif"; - status = "ok"; - sensorif_grp0_i2c = <1>; - }; - - jpe0: jpe@0x1F264000 { - compatible = "sstar,cedric-jpe"; - reg = <0x1F264000 0x100>; - interrupts = ; - clocks = <&CLK_jpe>; - clock-names = "CKG_jpe"; - clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz - status = "ok"; - }; -/* - ive0: ive@0x1F2A4000 { - compatible = "sstar,infinity3-ive"; - reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; - interrupts = ; - clocks = <&CLK_ive>,<&CLK_miu_ive>; - status = "ok"; - }; -*/ - i2c0@0{ - compatible = "sstar,i2c"; - reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&CLK_miic0>; - i2c-group = <0>; - status = "ok"; - /* - * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA - * 2 -> PAD_PWM0, PAD_PWM1 - * 3 -> PAD_SR_IO00, PAD_SR_IO01 - */ - i2c-padmux = <1>; - }; - - i2c1@1{ - compatible = "sstar,i2c"; - reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&CLK_miic1>; - i2c-group = <1>; - /* - * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA - * 2 -> PAD_PWM0, PAD_PWM1 - * 3 -> PAD_SR_IO00, PAD_SR_IO01 - */ - i2c-padmux = <1>; - status = "ok"; -// 24c512@54 { -// compatible = "sstar,24c512"; -// reg = <0x54>; -// }; - }; - - sound { - compatible = "sstar,infinity-audio"; -// reg = <0x1F000000 0x1000000>; - interrupts=; - playback-volume-level=<64>; //0~76 - capture-volume-level=<64>; - micin-gain-level=<0>; //0~5 - linein-gain-level=<1>;//0~6 - lineout-gain-level=<1>;//0~2 - }; - bdma0 { - compatible = "sstar,bdma0"; - interrupts=; - clocks = <&CLK_bdma>; - status = "ok"; - }; - - bdma1 { - compatible = "sstar,bdma1"; - interrupts=; - clocks = <&CLK_bdma>; - status = "ok"; - }; - - bdma2 { - compatible = "sstar,bdma2"; - interrupts=; - clocks = <&CLK_bdma>; - status = "ok"; - }; - - bdma3 { - compatible = "sstar,bdma3"; - interrupts=; - clocks = <&CLK_bdma>; - status = "ok"; - }; - - movdma { - compatible = "sstar,movdma"; - interrupts=; - clocks = <&CLK_miu>; - status = "ok"; - }; - /* - gop{ - compatible = "sstar,infinity-gop"; - clocks = <&CLK_gop0>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; - status = "ok"; - }; - - gop1{ - compatible = "sstar,infinity-gop1"; - clocks = <&CLK_gop1>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; - status = "ok"; - }; - - gop2{ - compatible = "sstar,infinity-gop2"; - clocks = <&CLK_gop2>,<&CLK_fclk2>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; - status = "ok"; - }; - */ - rtc { - compatible = "sstar,infinity-rtc"; - reg = <0x1F002400 0x40>; - interrupts=; - clocks = <&xtal>; - }; - - cpufreq { - compatible = "sstar,infinity-cpufreq"; - status = "ok"; - }; - - pwm { - compatible = "sstar,infinity-pwm"; - reg = <0x1F003400 0x600>; - clocks = <&CLK_xtali_12m>; - npwm = <4>; - pad-ctrl = ; - status = "ok"; - }; - - cmdq0 { - compatible = "sstar,cmdq0"; - clocks = <&CLK_mcu>; //for timeout tick - interrupts=; - status = "ok"; - }; -/* - Mstar-udc { - compatible = "sstar,infinity-udc"; - interrupts = ; - status = "ok"; - }; -*/ - miu { - compatible = "sstar,miu"; - interrupts=; - status = "ok"; - }; - - mmu { - compatible = "sstar,mmu"; - interrupts=; - status = "ok"; - }; - - dec { - compatible = "sstar,dec"; - banks = <0x1137>; - interrupts = ; - status = "ok"; - }; - - }; -}; - -&clks { - #include <../../../../drivers/sstar/include/infinity2m/reg_clks.h> - #include "infinity2m-clks.dtsi" - #include "infinity2m-gates.dtsi" -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-fusionx.dtsi b/software/linux/kernel/arch/arm/boot/dts/infinity2m-fusionx.dtsi index 12ca94499..21277cdb5 100755 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-fusionx.dtsi +++ b/software/linux/kernel/arch/arm/boot/dts/infinity2m-fusionx.dtsi @@ -36,13 +36,11 @@ reg = <0x0>; operating-points = < /* kHz uV */ - /* 1200000 1000000 1100000 1000000 - */ 1000000 900000 - /* 800000 900000 + /* 600000 900000 400000 900000 */ @@ -56,13 +54,11 @@ reg = <0x1>; operating-points = < /* kHz uV */ - /* 1200000 1000000 1100000 1000000 - */ 1000000 900000 - /* 800000 900000 + /* 600000 900000 400000 900000 */ @@ -217,7 +213,7 @@ interrupts=; status = "ok"; }; - +/* uart0: uart0@1F221000 { compatible = "sstar,uart"; reg = <0x1F221000 0x100>; @@ -225,6 +221,7 @@ clocks = <&CLK_uart0>; status = "ok"; }; +*/ uart1: uart1@1F221200 { compatible = "sstar,uart"; reg = <0x1F221200 0x100>; @@ -300,7 +297,6 @@ status = "ok"; }; - spi: spi { compatible = "sstar_spi"; io_phy_addr = <0x1f000000>; @@ -332,7 +328,7 @@ compatible = "spidev"; status = "ok"; }; - */ +*/ Sstar-ehci-1 { compatible = "Sstar-ehci-1"; @@ -414,7 +410,7 @@ slot-intcdzs = <1>,<1>,<1>; slot-fakecdzs = <0>,<0>,<0>; slot-cdzs-gpios = ,<0>,<0>; - //slot-pwr-gpios = ,<0>,<0>; // ssc010a:PAD_TTL0 P2_ssc011a: PAD_GPIO0 + slot-pwr-gpios = ,<0>,<0>; // ssc010a:PAD_TTL0 P2_ssc011a: PAD_GPIO0 slot-pwr-off-delay = <30>,<30>,<30>; slot-sdio-use = <0>,<0>,<0>; @@ -505,12 +501,9 @@ }; core_voltage { - //vid_width = <2>; - vid_width = <1>; - //vid_gpios = ; - vid_gpios = ; - //vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 - vid_voltages = <950 1000>; //2b'00 2b'01 2b'10 2b'11 + vid_width = <2>; + vid_gpios = ; + vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 }; /* core_voltage { diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-gates.dtsi b/software/linux/kernel/arch/arm/boot/dts/infinity2m-gates.dtsi deleted file mode 100755 index 1d1f8fe4f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-gates.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -/* -* infinity2m-gates.dtsi- Sigmastar -* -* Copyright (c) [2019~2020] SigmaStar Technology. -* -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License version 2 for more details. -* -*/ -GATE_MCM_vhe: GATE_MCM_vhe { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <0>; -}; - -GATE_MCM_mfe: GATE_MCM_mfe { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <0>; -}; - -GATE_MCM_jpe: GATE_MCM_jpe { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <8>; -}; - -GATE_MCM_aesdma: GATE_MCM_aesdma { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <8>; -}; - -GATE_MCM_emac: GATE_MCM_emac { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <8>; -}; - -GATE_MCM_gop: GATE_MCM_gop { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <8>; -}; - -GATE_MCM_bach: GATE_MCM_bach { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <0>; -}; - -GATE_MCM_usb: GATE_MCM_usb { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <0>; -}; - - -GATE_MCM_fcie: GATE_MCM_fcie { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <0>; -}; - -GATE_MCM_sdio: GATE_MCM_sdio { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <8>; -}; - -/* -GATE_MCM_urdma: GATE_MCM_urdma { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <8>; -}; -*/ - -GATE_SRAM_vhe: GATE_SRAM_vhe { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <0>; -}; - -GATE_SRAM_mfe: GATE_SRAM_mfe { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <9>; -}; - -GATE_SRAM_jpe: GATE_SRAM_jpe { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <8>; -}; - -GATE_SRAM_aesdma: GATE_SRAM_aesdma { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <1>; -}; - -GATE_SRAM_emac: GATE_SRAM_emac { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <3>; -}; - -GATE_SRAM_gop: GATE_SRAM_gop { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <5>; -}; - -GATE_SRAM_bach: GATE_SRAM_bach { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <0>; -}; - -GATE_SRAM_usb: GATE_SRAM_usb { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <11>; -}; - - -GATE_SRAM_fcie: GATE_SRAM_fcie { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <4>; -}; - -GATE_SRAM_sdio: GATE_SRAM_sdio { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <10>; -}; - - -GATE_SRAM_mailbox: GATE_SRAM_mailbox { - #clock-cells = <0>; - compatible = "sstar,composite-clock"; - reg = <0x1F200804 0x4>; - gate-shift = <2>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-ssc011a-s01a-fusionx.dtsi b/software/linux/kernel/arch/arm/boot/dts/infinity2m-ssc011a-s01a-fusionx.dtsi index e46879f2e..b854b6b7f 100755 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-ssc011a-s01a-fusionx.dtsi +++ b/software/linux/kernel/arch/arm/boot/dts/infinity2m-ssc011a-s01a-fusionx.dtsi @@ -78,19 +78,18 @@ */ i2c-speed = <3>; i2c-en-dma = <0>; // 0: disable; 1: enable; - status = "disabled"; - -// focaltech@38{ -// compatible = "focaltech,fts"; /* do not modify */ -// reg = <0x38>; /* do not modify */ -// interrupts-extended = <&ms_gpi_intc INT_GPI_FIQ_GPIO13>; -// focaltech,reset-gpio = ; /* RSTè„š */ -// focaltech,irq-gpio = ; /* INTè„š */ -// focaltech,max-touch-number = <10>; /* 最大触点数 */ -// //focaltech,display-coords = <0 0 720 720>; /* 分辨率 */ -// focaltech,display-coords = <0 0 480 480>; /* 分辨率 */ -// status = "ok"; -// }; + status = "ok"; + focaltech@38{ + compatible = "focaltech,fts"; /* do not modify */ + reg = <0x38>; /* do not modify */ + interrupts-extended = <&ms_gpi_intc INT_GPI_FIQ_GPIO13>; + focaltech,reset-gpio = ; /* RSTè„š */ + focaltech,irq-gpio = ; /* INTè„š */ + focaltech,max-touch-number = <10>; /* 最大触点数 */ + //focaltech,display-coords = <0 0 720 720>; /* 分辨率 */ + focaltech,display-coords = <0 0 480 480>; /* 分辨率 */ + status = "ok"; + }; /* goodix_gt911@5D{ //EVB i2c-padmux=2 SSD201_SZ_DEMO_BOARD i2c-padmux=1 compatible = "goodix,gt911"; diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-fusionx.dtsi b/software/linux/kernel/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-fusionx.dtsi index 73965f55d..7a7db51f6 100755 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-fusionx.dtsi +++ b/software/linux/kernel/arch/arm/boot/dts/infinity2m-ssc011a-s01a-padmux-fusionx.dtsi @@ -61,8 +61,10 @@ , // UART 0 - , - , + //, + //, + , // GPIO47 + , // GPIO48 // UART 1 , @@ -100,8 +102,8 @@ , , , - , // HSYNC_OUT: Used as GPIO - , // VSYNC_OUT: Used as GPIO + , // HSYNC_OUT: Used as GPIO85 + , // VSYNC_OUT: Used as GPIO86 , // SAR2: Used as GPIO ; // IR: Used as GPIO diff --git a/software/linux/kernel/arch/arm/boot/dts/infinity2m.dtsi b/software/linux/kernel/arch/arm/boot/dts/infinity2m.dtsi deleted file mode 100755 index a3b774dfc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/infinity2m.dtsi +++ /dev/null @@ -1,581 +0,0 @@ -/* -* infinity2m.dtsi- Sigmastar -* -* Copyright (c) [2019~2020] SigmaStar Technology. -* -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License version 2 for more details. -* -*/ - -#include <../../../../drivers/sstar/include/infinity2m/irqs.h> -#include <../../../../drivers/sstar/include/infinity2m/gpio.h> -#include <../../../../drivers/sstar/include/vcore_defs.h> -#include -#include -#include "skeleton.dtsi" - - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - clock-frequency = <1000000000>; - clocks = <&CLK_cpupll_clk>; - reg = <0x0>; - operating-points = < - /* kHz uV */ - /* - 1200000 1000000 - 1100000 1000000 - */ - 1000000 900000 - /* - 800000 900000 - 600000 900000 - 400000 900000 - */ - >; - }; -#ifndef __DTS_DCDO__ - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - clock-frequency = <1000000000>; - clocks = <&CLK_cpupll_clk>; - reg = <0x1>; - operating-points = < - /* kHz uV */ - /* - 1200000 1000000 - 1100000 1000000 - */ - 1000000 900000 - /* - 800000 900000 - 600000 900000 - 400000 900000 - */ - >; - }; -#endif - }; - - aliases { - console = &uart0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &fuart; - serial3 = &uart2; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&ms_main_intc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gic: gic@16000000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - interrupt-parent = <&gic>; - reg = <0x16001000 0x1000>, - <0x16002000 0x1000>; - }; - - ms_main_intc: ms_main_intc { - compatible = "sstar,main-intc"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent=<&gic>; - interrupt-controller; - }; - - ms_pm_intc: ms_pm_intc { - compatible = "sstar,pm-intc"; - #interrupt-cells = <1>; - interrupt-parent=<&ms_main_intc>; - interrupt-controller; - interrupts = ; - }; - - ms_gpi_intc: ms_gpi_intc { - compatible = "sstar,gpi-intc"; - #interrupt-cells = <1>; - interrupt-parent=<&ms_main_intc>; - interrupt-controller; - interrupts = ; - }; - - arch_timer { - compatible = "arm,armv7-timer"; - interrupt-parent=<&gic>; - interrupts = , - , - , - ; - clock-frequency = <6000000>; - always-on; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent=<&gic>; - interrupts = , - , - , - ; - }; - - clks: clocks{ - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - -/* - timer_clockevent: timer@1F006040 { - compatible = "sstar,piu-clocksource","sstar,piu-clockevent"; - reg = <0x1F006040 0x100>; - interrupts=<&ms_main_intc GIC_SPI INT_FIQ_TIMER_0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLK_xtali_12m>; - }; -*/ -#ifndef __DTS_DCDO__ - dec: dec { - compatible = "sstar,dec"; - banks = <0x1137>; - interrupts = ; - status = "ok"; - }; - - vip: vip { - compatible = "sstar,vip"; - status = "ok"; - CMDQ-mode = <1>; - //reg = <0x1F224000 0x200>; - }; - - pnl: pnl { - compatible = "sstar,pnl"; - status = "ok"; - clocks = <&CLK_hdmi>, <&CLK_dac>, <&CLK_sc_pixel>, <&CLK_mipi_tx_dsi>, <&CLK_mipi_tx_dsi_apb>; - clock-names = "CLK_hdmi", "CLK_dac", "CLK_sc_pixel", "CLK_mipi_tx_dsi", "CLK_mipi_tx_dsi_apb"; - //Reg = <0x1F224000 0x200>; - }; - - hdmitx: hdmitx { - compatible = "sstar,hdmitx"; - status = "ok"; - i2c_id = <0>; - hpd_gpio = <89>; - i2c_sw = <1>; - i2c_sda_gpio = <88>; - i2c_scl_gpio = <87>; - clocks = <&CLK_hdmi>, <&CLK_disp_432>, <&CLK_disp_216>; - clock-names = "CLK_hdmi", "CLK_disp_432", "CLK_disp_216"; - //Reg = <0x1F224000 0x200>; - }; - - ge: ge { - compatible = "sstar,ge"; - status = "ok"; - clocks = <&CLK_ge>; - interrupts = ; - //Reg = <0x1F224000 0x200>; - }; - - gop: gop { - compatible = "sstar,gop"; - status = "ok"; - - }; - - dip { - compatible = "sstar,dip"; - clocks = <&CLK_dip>; - interrupts=; - status = "ok"; - }; - cmdq0 { - compatible = "sstar,cmdq0"; - clocks = <&CLK_mcu>; //for timeout tick - interrupts=; - status = "ok"; - }; -#endif - uart0: uart0@1F221000 { - compatible = "sstar,uart"; - reg = <0x1F221000 0x100>; - interrupts = ; - clocks = <&CLK_uart0>; - status = "ok"; - }; - uart1: uart1@1F221200 { - compatible = "sstar,uart"; - reg = <0x1F221200 0x100>; - interrupts = ; - clocks = <&CLK_uart1>; - status = "ok"; - }; - fuart: uart2@1F220400 { - compatible = "sstar,uart"; - //reg = <0x1F220400 0x100>, <0x1F220600 0x100>; - //interrupts = , ; - reg = <0x1F220400 0x100>; - interrupts = , ; - clocks = <&CLK_fuart>; - dma = <0>; - sctp_enable = <0>;//rts cts enable - status = "ok"; - }; - uart2: uart2@1F221400 { - compatible = "sstar,uart"; - reg = <0x1F221400 0x100>; - interrupts = ; - clocks = <&CLK_uart2>; - status = "ok"; - }; - - emac0: emac0 { - compatible = "sstar-emac"; - interrupts = , ; - clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>; - reg = <0x1F2A2000 0x800>, <0x1F343C00 0x600>, <0x1F006200 0x600>; - pad = <0x1F203C38 0x0001 0x0000>; // pad selection from 0x0001 - phy-handle = <&phy0>; - status = "ok"; - mdio-bus@emac0 { - phy0: ethernet-phy@0 { - phy-mode = "mii"; - }; - }; - }; - - emac1: emac1 { - compatible = "sstar-emac"; - interrupts = , ; - clocks = <&CLK_emac_ahb>,<&CLK_emac1_tx>,<&CLK_emac1_rx>,<&CLK_emac1_tx_ref>,<&CLK_emac1_rx_ref>; - reg = <0x1F2A2800 0x800>, <0x1F344200 0x600>, <0x00000000 0x000>; - pad = <0x1F203C38 0x0F00 0x0300>; // pad selection from 0x0100/0x0200/0x0300/0x0400/0x0500/0x0600/0x0700/0x0800/0x0900 - status = "ok"; -#if 1 - phy-handle = <&phy1>; - mdio-bus@emac1 { - phy1: ethernet-phy@1 { - phy-mode = "rmii"; - }; - }; -#else - phy-mode = "rmii"; - fixed-link = <0 1 100 0 0>; -#endif - }; - - flashisp { - compatible = "mtd-flashisp"; - clocks = <&CLK_bdma>; - quadread = <0>; - status = "ok"; - }; - - spinandflash { - compatible = "ms-spinand"; - clocks =<&CLK_bdma>; - status = "ok"; - }; - - spi: spi { - compatible = "sstar_spi"; - io_phy_addr = <0x1f000000>; - banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>,<0x100B>; - clocks = <&CLK_mspi0>; - interrupts = ; - /* - * padmux: - * mode=1: PAD_PM_SD_CDZ,PAD_SD_D1,PAD_SD_D0,PAD_SD_CLK,PAD_SD_CMD - * mode=2: PAD_TTL16,PAD_TTL17,PAD_TTL18,PAD_TTL19 - * mode=3: PAD_GPIO4,PAD_GPIO5,PAD_GPIO6,PAD_GPIO7 - * mode=4: PAD_FUART_RX,PAD_FUART_TX,PAD_FUART_CTS,PAD_FUART_RTS - * mode=5: PAD_GPIO8,PAD_GPIO9,PAD_GPIO10,PAD_GPIO11 - * mode=6: PAD_GPIO0,PAD_GPIO1,PAD_GPIO2,PAD_GPIO3 - */ - dma = <1>; - spi0_mode = <2>; - status = "ok"; - }; - - spidev: spidev { - compatible = "spidev"; - status = "ok"; - }; - - Sstar-ehci-1 { - compatible = "Sstar-ehci-1"; - clocks = <&CLK_utmi>; - interrupts = ; - dpdm_swap=<0>; - //power-enable-pad = ; - status = "ok"; - }; - - Sstar-ehci-2 { - compatible = "Sstar-ehci-2"; - clocks = <&CLK_utmi>; - interrupts = ; - dpdm_swap=<0>; - //power-enable-pad = ; - status = "ok"; - }; - - - jpe0: jpe@0x1F264000 { - compatible = "sstar,cedric-jpe"; - reg = <0x1F264000 0x100>; - interrupts = ; - clocks = <&CLK_jpe>; - clock-names = "CKG_jpe"; - clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz - status = "ok"; - }; - - - gpio:gpio{ - compatible = "sstar,gpio"; - #gpio-cells = <2>; - gpio-controller; - }; -/* - sound { - compatible = "sstar,audio"; -// reg = <0x1F000000 0x1000000>; - interrupts=; - playback-volume-level=<64>; //0~94 - capture-volume-level=<64>; - // micin-pregain-level=<1>; //0~3 - micin-pregain-level=<0>; //0~3 - micin-gain-level=<3>; //0~7 - linein-gain-level=<2>; //0~7 - amp-gpio = ; - clocks = <&CLK_upll_384m>; - // playback-dma-buffer=<98304>; //512(ms)*48(kHz)*2(ch)*2(16bits) - // capture-dma-buffer=<122880>; //640(ms)*48(kHz)*2(ch)*2(16bits) - digmic-padmux = <1>; - i2s-padmux = <3>; - keep-i2s-clk = <0>; - status = "ok"; - }; -*/ - emmc { - compatible = "sstar_mci"; - clocks =<&CLK_sdio>, <&CLK_sdio>; - interrupts = ; - bus-width = <4>; - max-clks = <2>; // 0:48M 1:43M 2:40M 3:36M 4:32M 5:20M 6:12M 7:300K - clk-driving = <0>; - cmd-driving = <0>; - data-driving = <0>; - status = "ok"; - }; - - sdmmc { - compatible = "sstar,sdmmc"; - - slotnum = <1>; - revcdz = <0>; - - slot-ip-orders = <0>,<1>,<2>; - slot-pad-orders = <0>,<1>,<2>; - slot-max-clks = <48000000>,<48000000>,<48000000>; - slot-intcdzs = <1>,<1>,<1>; - slot-fakecdzs = <0>,<0>,<0>; - slot-cdzs-gpios = ,<0>,<0>; - slot-pwr-gpios = ,<0>,<0>; // ssc010a:PAD_TTL0 P2_ssc011a: PAD_GPIO0 - slot-pwr-off-delay = <30>,<30>,<30>; - slot-sdio-use = <0>,<0>,<0>; - - interrupts-extended = <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>,//was INT_IRQ_SDIO - <&ms_main_intc GIC_SPI INT_IRQ_SDIO IRQ_TYPE_LEVEL_HIGH>, - <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>, - <&ms_gpi_intc 42>, - <&ms_main_intc GIC_SPI INT_FIQ_SD_CDZ IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mie0_irq", "mie1_irq", "cdz_slot0_irq", "cdz_slot1_irq", "cdz_slot2_irq"; - - //clocks = <&CLK_sdio>,<&GATE_MCM_sdio>,<&GATE_SRAM_sdio>; - clocks = <&CLK_sdio>,<&CLK_sdio>,<&CLK_sdio>, - <&CLK_sdio>,<&CLK_sdio>,<&CLK_sdio>, - <&CLK_sdio>,<&CLK_sdio>,<&CLK_sdio>; - status = "ok"; - }; - - aesdma { - compatible = "sstar,infinity-aes"; - //clocks = <&CLK_aesdma>,<&GATE_MCM_aesdma>, <&GATE_SRAM_aesdma>; - clocks = <&CLK_aesdma>; - status = "ok"; - }; - - bdma0 { - compatible = "sstar,bdma0"; - interrupts=; - clocks = <&CLK_bdma>; - status = "ok"; - }; - - bdma1 { - compatible = "sstar,bdma1"; - interrupts=; - clocks = <&CLK_bdma>; - status = "ok"; - }; - - bdma2 { - compatible = "sstar,bdma2"; - interrupts=; - clocks = <&CLK_bdma>; - status = "ok"; - }; - - bdma3 { - compatible = "sstar,bdma3"; - interrupts=; - clocks = <&CLK_bdma>; - status = "ok"; - }; - - movdma { - compatible = "sstar,movdma"; - interrupts=; - clocks = <&CLK_miu>; - status = "ok"; - }; - - sata { - compatible = "sstar,sata", "sstar,sata-ahci"; - reg-names = "ahci", "ahci_port0", "ahci_misc"; - reg = <0x1F345000 0x100>, <0x1F345100 0x100>, <0x1F2A4A00 0x200>; - interrupts=; - clocks = <&CLK_sata_axi>,<&CLK_sata_pm>,<&CLK_sata_phy_108>,<&CLK_sata_phy_432>; - }; - - - rtc { - compatible = "sstar,infinity-rtc"; - reg = <0x1F002400 0x40>; - interrupts=; - clocks = <&CLK_rtc>; - status = "disabled"; - }; - - rtcpwc { - compatible = "sstar,infinity-rtcpwc"; - reg = <0x1F006800 0x200>; - interrupts=; //need to check - clocks = <&CLK_rtc>; - status = "ok"; - }; - - cpufreq { - compatible = "sstar,infinity-cpufreq"; - status = "ok"; - }; - - core_voltage { - vid_width = <2>; - vid_gpios = ; - vid_voltages = <850 900 950 1000>; //2b'00 2b'01 2b'10 2b'11 - }; -/* - core_voltage { - vid_width = <1>; - vid_gpios = ; - vid_voltages = <950 1000>; //2b'00 2b'01 - }; -*/ - watchdog: watchdog { - compatible = "sstar,infinity-wdt"; - reg = <0x1F006000 0x40>; - status = "ok"; - }; - - sar: sar { - compatible = "sstar,infinity-sar"; - reg = <0x1F002800 0x200>; - clocks = <&CLK_sar>; - status = "ok"; - }; - - ircut { - compatible = "sstar,infinity-ircut"; - ircut-gpio-num = ;///PM_GPIO_IRIN - interrupt-parent = <&ms_pm_intc>; - interrupts = ; - status = "ok"; - }; - - ir: ir@1F007A00 { - compatible = "sstar,infinity-ir"; - reg = <0x1F007A00 0x1000>; - clocks = <&CLK_ir>; - interrupts = ; - status = "ok"; - }; - - pwm { - compatible = "sstar,infinity-pwm"; - reg = <0x1F003400 0x600>; - clocks = <&CLK_xtali_12m>; - npwm = <4>; - pad-ctrl = ; - status = "disabled"; // no available pads - }; - - /* - pm { - compatible = "sstar,infinity-pm"; - interrupt-parent = <&ms_pm_intc>; - interrupts = ; - detect-gpio = ; - }; - */ - - miu { - compatible = "sstar,miu"; - interrupts=; - status = "ok"; - }; - - mmu { - compatible = "sstar,mmu"; - interrupts=; - status = "ok"; - }; - }; -}; - -&clks { - #include <../../../../drivers/sstar/include/infinity2m/reg_clks.h> -#ifndef __DTS_DCDO__ - #include "infinity2m-clks.dtsi" -#else - #include "infinity2m-clks_simple.dtsi" -#endif -/* #include "infinity2m-gates.dtsi"*/ -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/integrator.dtsi b/software/linux/kernel/arch/arm/boot/dts/integrator.dtsi deleted file mode 100644 index 6fe0dd1d3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/integrator.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -/* - * SoC core Device Tree for the ARM Integrator platforms - */ - -/include/ "skeleton.dtsi" - -/ { - core-module@10000000 { - compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; - reg = <0x10000000 0x200>; - - /* Use core module LED to indicate CPU load */ - led@0c.0 { - compatible = "register-bit-led"; - offset = <0x0c>; - mask = <0x01>; - label = "integrator:core_module"; - linux,default-trigger = "cpu0"; - default-state = "on"; - }; - }; - - ebi@12000000 { - compatible = "arm,external-bus-interface"; - reg = <0x12000000 0x100>; - }; - - timer@13000000 { - reg = <0x13000000 0x100>; - interrupt-parent = <&pic>; - interrupts = <5>; - }; - - timer@13000100 { - reg = <0x13000100 0x100>; - interrupt-parent = <&pic>; - interrupts = <6>; - }; - - timer@13000200 { - reg = <0x13000200 0x100>; - interrupt-parent = <&pic>; - interrupts = <7>; - }; - - pic@14000000 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x14000000 0x100>; - clear-mask = <0xffffffff>; - }; - - flash@24000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x24000000 0x02000000>; - bank-width = <4>; - }; - - fpga { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&pic>; - - /* - * These PrimeCells are in the same locations and using the - * same interrupts in all Integrators, however the silicon - * version deployed is different. - */ - rtc@15000000 { - reg = <0x15000000 0x1000>; - interrupts = <8>; - }; - - uart@16000000 { - reg = <0x16000000 0x1000>; - interrupts = <1>; - }; - - uart@17000000 { - reg = <0x17000000 0x1000>; - interrupts = <2>; - }; - - kmi@18000000 { - reg = <0x18000000 0x1000>; - interrupts = <3>; - }; - - kmi@19000000 { - reg = <0x19000000 0x1000>; - interrupts = <4>; - }; - - syscon { - /* Debug registers mapped as syscon */ - compatible = "syscon", "simple-mfd"; - reg = <0x1a000000 0x10>; - - led@04.0 { - compatible = "register-bit-led"; - offset = <0x04>; - mask = <0x01>; - label = "integrator:green0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@04.1 { - compatible = "register-bit-led"; - offset = <0x04>; - mask = <0x02>; - label = "integrator:yellow"; - default-state = "off"; - }; - led@04.2 { - compatible = "register-bit-led"; - offset = <0x04>; - mask = <0x04>; - label = "integrator:red"; - default-state = "off"; - }; - led@04.3 { - compatible = "register-bit-led"; - offset = <0x04>; - mask = <0x08>; - label = "integrator:green1"; - default-state = "off"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/integratorap.dts b/software/linux/kernel/arch/arm/boot/dts/integratorap.dts deleted file mode 100644 index 6f16d09dc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/integratorap.dts +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Device Tree for the ARM Integrator/AP platform - */ - -/dts-v1/; -/include/ "integrator.dtsi" - -/ { - model = "ARM Integrator/AP"; - compatible = "arm,integrator-ap"; - dma-ranges = <0x80000000 0x0 0x80000000>; - - aliases { - arm,timer-primary = &timer2; - arm,timer-secondary = &timer1; - }; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; - }; - - /* 24 MHz chrystal on the Integrator/AP development board */ - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - /* The UART clock is 14.74 MHz divided by an ICS525 */ - uartclk: uartclk@14.74M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <14745600>; - clocks = <&xtal24mhz>; - }; - - core-module@10000000 { - /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - /* Oscillator on the core module, clocks the CPU core */ - cmosc: cmosc@24M { - compatible = "arm,syscon-icst525-integratorap-cm"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Auxilary oscillator on the core module, 32.369MHz at boot */ - auxosc: auxosc@24M { - compatible = "arm,syscon-icst525"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x1c>; - clocks = <&cm24mhz>; - }; - }; - - syscon { - compatible = "arm,integrator-ap-syscon", "syscon"; - reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logical module IRQs */ - interrupts = <9>, <10>, <11>, <12>; - - /* - * SYSCLK clocks PCIv3 bridge, system controller and the - * logic modules. - */ - sysclk: apsys@24M { - compatible = "arm,syscon-icst525-integratorap-sys"; - #clock-cells = <0>; - lock-offset = <0x1c>; - vco-offset = <0x04>; - clocks = <&xtal24mhz>; - }; - - /* One-bit control for the PCI bus clock (33 or 25 MHz) */ - pciclk: pciclk@24M { - compatible = "arm,syscon-icst525-integratorap-pci"; - #clock-cells = <0>; - lock-offset = <0x1c>; - vco-offset = <0x04>; - clocks = <&xtal24mhz>; - }; - }; - - timer0: timer@13000000 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - timer1: timer@13000100 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - timer2: timer@13000200 { - compatible = "arm,integrator-timer"; - clocks = <&xtal24mhz>; - }; - - pic: pic@14000000 { - valid-mask = <0x003fffff>; - }; - - pci: pciv3@62000000 { - compatible = "v3,v360epc-pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x62000000 0x10000>; - interrupt-parent = <&pic>; - interrupts = <17>; /* Bus error IRQ */ - ranges = <0x00000000 0 0x61000000 /* config space */ - 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ - 0x01000000 0 0x0 /* I/O space */ - 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ - 0x02000000 0 0x00000000 /* non-prefectable memory */ - 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ - 0x42000000 0 0x10000000 /* prefetchable memory */ - 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = < - /* IDSEL 9 */ - 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ - 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ - 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ - 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ - /* IDSEL 10 */ - 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ - 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ - 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ - 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ - /* IDSEL 11 */ - 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ - 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ - 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ - 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ - /* IDSEL 12 */ - 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ - 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ - 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ - 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ - >; - }; - - fpga { - /* - * The Integator/AP predates the idea to have magic numbers - * identifying the PrimeCell in hardware, thus we have to - * supply these from the device tree. - */ - rtc: rtc@15000000 { - compatible = "arm,pl030", "arm,primecell"; - arm,primecell-periphid = <0x00041030>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - uart0: uart@16000000 { - compatible = "arm,pl010", "arm,primecell"; - arm,primecell-periphid = <0x00041010>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart1: uart@17000000 { - compatible = "arm,pl010", "arm,primecell"; - arm,primecell-periphid = <0x00041010>; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - kmi0: kmi@18000000 { - compatible = "arm,pl050", "arm,primecell"; - arm,primecell-periphid = <0x00041050>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi1: kmi@19000000 { - compatible = "arm,pl050", "arm,primecell"; - arm,primecell-periphid = <0x00041050>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/integratorcp.dts b/software/linux/kernel/arch/arm/boot/dts/integratorcp.dts deleted file mode 100644 index 1b5e4b006..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/integratorcp.dts +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Device Tree for the ARM Integrator/CP platform - */ - -/dts-v1/; -/include/ "integrator.dtsi" - -/ { - model = "ARM Integrator/CP"; - compatible = "arm,integrator-cp"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; - }; - - /* - * The Integrator/CP overall clocking architecture can be found in - * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which - * appear to illustrate the layout used in most configurations. - */ - - /* The codec chrystal operates at 24.576 MHz */ - xtal_codec: xtal24.576@24.576M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - /* The chrystal is divided by 2 by the codec for the AACI bit clock */ - aaci_bitclk: aaci_bitclk@12.288M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&xtal_codec>; - }; - - /* This is a 25MHz chrystal on the base board */ - xtal25mhz: xtal25mhz@25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ - uartclk: uartclk@14.74M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <14745600>; - }; - - /* Actually sysclk I think */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - core-module@10000000 { - /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - /* Oscillator on the core module, clocks the CPU core */ - cmcore: cmosc@24M { - compatible = "arm,syscon-icst525-integratorcp-cm-core"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Oscillator on the core module, clocks the memory bus */ - cmmem: cmosc@24M { - compatible = "arm,syscon-icst525-integratorcp-cm-mem"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x08>; - clocks = <&cm24mhz>; - }; - - /* Auxilary oscillator on the core module, clocks the CLCD */ - auxosc: auxosc@24M { - compatible = "arm,syscon-icst525"; - #clock-cells = <0>; - lock-offset = <0x14>; - vco-offset = <0x1c>; - clocks = <&cm24mhz>; - }; - - /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ - kmiclk: kmiclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <3>; - clock-mult = <1>; - clocks = <&cm24mhz>; - }; - - /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&cm24mhz>; - }; - }; - - syscon { - compatible = "arm,integrator-cp-syscon", "syscon"; - reg = <0xcb000000 0x100>; - }; - - timer0: timer@13000000 { - /* TIMER0 runs directly on the 25MHz chrystal */ - compatible = "arm,integrator-cp-timer"; - clocks = <&xtal25mhz>; - }; - - timer1: timer@13000100 { - /* TIMER1 runs @ 1MHz */ - compatible = "arm,integrator-cp-timer"; - clocks = <&timclk>; - }; - - timer2: timer@13000200 { - /* TIMER2 runs @ 1MHz */ - compatible = "arm,integrator-cp-timer"; - clocks = <&timclk>; - }; - - pic: pic@14000000 { - valid-mask = <0x1fc003ff>; - }; - - cic: cic@10000040 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x10000040 0x100>; - clear-mask = <0xffffffff>; - valid-mask = <0x00000007>; - }; - - /* The SIC is cascaded off IRQ 26 on the PIC */ - sic: sic@ca000000 { - compatible = "arm,versatile-fpga-irq"; - interrupt-parent = <&pic>; - interrupts = <26>; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0xca000000 0x100>; - clear-mask = <0x00000fff>; - valid-mask = <0x00000fff>; - }; - - ethernet@c8000000 { - compatible = "smsc,lan91c111"; - reg = <0xc8000000 0x10>; - interrupt-parent = <&pic>; - interrupts = <27>; - }; - - fpga { - /* - * These PrimeCells are at the same location and using - * the same interrupts in all Integrators, but in the CP - * slightly newer versions are deployed. - */ - rtc@15000000 { - compatible = "arm,pl031", "arm,primecell"; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - uart@16000000 { - compatible = "arm,pl011", "arm,primecell"; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart@17000000 { - compatible = "arm,pl011", "arm,primecell"; - clocks = <&uartclk>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - kmi@18000000 { - compatible = "arm,pl050", "arm,primecell"; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@19000000 { - compatible = "arm,pl050", "arm,primecell"; - clocks = <&kmiclk>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - /* - * These PrimeCells are only available on the Integrator/CP - */ - mmc@1c000000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x1c000000 0x1000>; - interrupts = <23 24>; - max-frequency = <515633>; - clocks = <&uartclk>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - - aaci@1d000000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x1d000000 0x1000>; - interrupts = <25>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - clcd@c0000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0xC0000000 0x1000>; - interrupts = <22>; - clocks = <&auxosc>, <&pclk>; - clock-names = "clcdclk", "apb_pclk"; - - port { - /* - * The VGA connected is implemented with a - * THS8134A triple DAC that can be run in 24bit - * or 16bit RGB mode. - */ - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <1 7 13>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-clocks.dtsi deleted file mode 100644 index 0c334b257..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-clocks.dtsi +++ /dev/null @@ -1,414 +0,0 @@ -/* - * Device Tree Source for Keystone 2 clock tree - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mainmuxclk: mainmuxclk@2310108 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-mux-clock"; - clocks = <&mainpllclk>, <&refclksys>; - reg = <0x02310108 4>; - bit-shift = <23>; - bit-mask = <1>; - clock-output-names = "mainmuxclk"; - }; - - chipclk1: chipclk1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1"; - }; - - chipclk1rstiso: chipclk1rstiso { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso"; - }; - - gemtraceclk: gemtraceclk@2310120 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310120 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "gemtraceclk"; - }; - - chipstmxptclk: chipstmxptclk { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310164 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "chipstmxptclk"; - }; - - chipclk12: chipclk12 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <2>; - clock-mult = <1>; - clock-output-names = "chipclk12"; - }; - - chipclk13: chipclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk13"; - }; - - paclk13: paclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&papllclk>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "paclk13"; - }; - - chipclk14: chipclk14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk14"; - }; - - chipclk16: chipclk16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk16"; - }; - - chipclk112: chipclk112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk112"; - }; - - chipclk124: chipclk124 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <24>; - clock-mult = <1>; - clock-output-names = "chipclk114"; - }; - - chipclk1rstiso13: chipclk1rstiso13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso13"; - }; - - chipclk1rstiso14: chipclk1rstiso14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso14"; - }; - - chipclk1rstiso16: chipclk1rstiso16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso16"; - }; - - chipclk1rstiso112: chipclk1rstiso112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso112"; - }; - - clkmodrst0: clkmodrst0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "modrst0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkusb: clkusb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb"; - reg = <0x02350008 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemifspi: clkaemifspi { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "aemif-spi"; - reg = <0x0235000c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkdebugsstrc: clkdebugsstrc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "debugss-trc"; - reg = <0x02350014 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clktetbtrc: clktetbtrc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tetb-trc"; - reg = <0x02350018 0xb00>, <0x02350004 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clkpa: clkpa { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&paclk13>; - clock-output-names = "pa"; - reg = <0x0235001c 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkcpgmac: clkcpgmac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "cpgmac"; - reg = <0x02350020 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clksa: clksa { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "sa"; - reg = <0x02350024 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkpcie: clkpcie { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x02350028 0xb00>, <0x0235000c 0x400>; - reg-names = "control", "domain"; - domain-id = <3>; - }; - - clksr: clksr { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso112>; - clock-output-names = "sr"; - reg = <0x02350034 0xb00>, <0x02350018 0x400>; - reg-names = "control", "domain"; - domain-id = <6>; - }; - - clkgem0: clkgem0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem0"; - reg = <0x0235003c 0xb00>, <0x02350020 0x400>; - reg-names = "control", "domain"; - domain-id = <8>; - }; - - clkddr30: clkddr30 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "ddr3-0"; - reg = <0x0235005c 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clkwdtimer0: clkwdtimer0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer1: clkwdtimer1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer2: clkwdtimer2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer3: clkwdtimer3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clktimer15: clktimer15 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer15"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart0: clkuart0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart1: clkuart1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemif: clkaemif { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "aemif"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkusim: clkusim { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "usim"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clki2c: clki2c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "i2c"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkspi: clkspi { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "spi"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkgpio: clkgpio { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "gpio"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkkeymgr: clkkeymgr { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "keymgr"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-clocks.dtsi deleted file mode 100644 index d56d68fe7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-clocks.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Edison SoC specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkusb1: clkusb1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb1"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkhyperlink0: clkhyperlink0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkpcie1: clkpcie1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie1"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkxge: clkxge { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-evm.dts b/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-evm.dts deleted file mode 100644 index ae1ebe7ee..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-evm.dts +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Edison EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2e.dtsi" - -/ { - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison EVM"; - - soc { - - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-pass"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&usb1_phy { - status = "okay"; -}; - -&keystone_usb1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1FE80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-netcp.dtsi deleted file mode 100644 index ac990f679..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Edison Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x24186000 0x100>, - <0x24187000 0x2a0>, - <0x24188000 0xb60>, - <0x24186100 0x80>, - <0x24189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@24000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x24000000 0x1000000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-9"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - port-4 { - slave-port = <4>; - link-interface = <2>; - }; - port-5 { - slave-port = <5>; - link-interface = <2>; - }; - port-6 { - slave-port = <6>; - link-interface = <2>; - }; - port-7 { - slave-port = <7>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 00]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2e.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2e.dtsi deleted file mode 100644 index 497c417db..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2e.dtsi +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Edison soc device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - soc { - /include/ "keystone-k2e-clocks.dtsi" - - usb: usb@2680000 { - interrupts = ; - dwc3@2690000 { - interrupts = ; - }; - }; - - usb1_phy: usb_phy@2620750 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620750 24>; - status = "disabled"; - }; - - keystone_usb1: usb@25000000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x25000000 0x10000>; - clocks = <&clkusb1>; - clock-names = "usb"; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - usb1: dwc3@25010000 { - compatible = "synopsys,dwc3"; - reg = <0x25010000 0x70000>; - interrupts = ; - usb-phy = <&usb1_phy>, <&usb1_phy>; - }; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - pcie1: pcie@21020000 { - compatible = "ti,keystone-pcie","snps,dw-pcie"; - clocks = <&clkpcie1>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; - ranges = <0x82000000 0 0x60000000 0x60000000 - 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - bus-range = <0x00 0xff>; - - /* error interrupt */ - interrupts = ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ - <0 0 0 2 &pcie_intc1 1>, /* INT B */ - <0 0 0 3 &pcie_intc1 2>, /* INT C */ - <0 0 0 4 &pcie_intc1 3>; /* INT D */ - - pcie_msi_intc1: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - - pcie_intc1: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x24200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2e-netcp.dtsi" - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2g-evm.dts b/software/linux/kernel/arch/arm/boot/dts/keystone-k2g-evm.dts deleted file mode 100644 index 692fcbb14..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2g-evm.dts +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Device Tree Source for K2G EVM - * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; - -#include "keystone-k2g.dtsi" - -/ { - compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone"; - model = "Texas Instruments K2G General Purpose EVM"; - - memory { - device_type = "memory"; - reg = <0x00000008 0x00000000 0x00000000 0x80000000>; - }; - -}; - -&k2g_pinctrl { - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2g.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2g.dtsi deleted file mode 100644 index 2919c5190..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2g.dtsi +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Device Tree Source for K2G SOC - * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "ti,k2g","ti,keystone"; - model = "Texas Instruments K2G SoC"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - }; - - gic: interrupt-controller@02561000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>, - <0x0 0x02564000 0x0 0x1000>, - <0x0 0x02566000 0x0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,keystone","simple-bus"; - ranges = <0x0 0x0 0x0 0xc0000000>; - dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - - k2g_pinctrl: pinmux@02621000 { - compatible = "pinctrl-single"; - reg = <0x02621000 0x410>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x001b0007>; - }; - - devctrl: device-state-control@02620000 { - compatible = "ti,keystone-devctrl", "syscon"; - reg = <0x02620000 0x1000>; - }; - - uart0: serial@02530c00 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - interrupts = ; - clock-frequency = <200000000>; - status = "disabled"; - }; - - kirq0: keystone_irq@026202a0 { - compatible = "ti,keystone-irq"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - msgmgr: msgmgr@02a00000 { - compatible = "ti,k2g-message-manager"; - #mbox-cells = <2>; - reg-names = "queue_proxy_region", - "queue_state_debug_region"; - reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; - interrupt-names = "rx_005", - "rx_057"; - interrupts = , - ; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi deleted file mode 100644 index af9b71905..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi +++ /dev/null @@ -1,425 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking SoC clock nodes - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkarm>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - ddr3bpllclk: ddr3bpllclk@2620368 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3b>; - clock-output-names = "ddr-3b-pll-clk"; - reg = <0x02620368 4>; - reg-names = "control"; - }; - - clktsip: clktsip { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "tsip"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clksrio: clksrio { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso13>; - clock-output-names = "srio"; - reg = <0x0235002c 0xb00>, <0x02350010 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkhyperlink0: clkhyperlink0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkgem1: clkgem1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clkgem4: clkgem4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem4"; - reg = <0x0235004c 0xb00>, <0x02350030 0x400>; - reg-names = "control", "domain"; - domain-id = <12>; - }; - - clkgem5: clkgem5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem5"; - reg = <0x02350050 0xb00>, <0x02350034 0x400>; - reg-names = "control", "domain"; - domain-id = <13>; - }; - - clkgem6: clkgem6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem6"; - reg = <0x02350054 0xb00>, <0x02350038 0x400>; - reg-names = "control", "domain"; - domain-id = <14>; - }; - - clkgem7: clkgem7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem7"; - reg = <0x02350058 0xb00>, <0x0235003c 0x400>; - reg-names = "control", "domain"; - domain-id = <15>; - }; - - clkddr31: clkddr31 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "ddr3-1"; - reg = <0x02350060 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clktac: clktac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac01: clkrac01 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-01"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac23: clkrac23 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-23"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc1: clkfftc1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x02350074 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc2: clkfftc2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-2"; - reg = <0x02350078 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc3: clkfftc3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-3"; - reg = <0x0235007c 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc4: clkfftc4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-4"; - reg = <0x02350080 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc5: clkfftc5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-5"; - reg = <0x02350084 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkaif: clkaif { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "aif"; - reg = <0x02350088 0xb00>, <0x02350054 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350090 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d2: clktcp3d2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-2"; - reg = <0x02350094 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clktcp3d3: clktcp3d3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-3"; - reg = <0x02350098 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp4: clkvcp4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-4"; - reg = <0x023500ac 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp5: clkvcp5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-5"; - reg = <0x023500b0 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp6: clkvcp6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-6"; - reg = <0x023500b4 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp7: clkvcp7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-7"; - reg = <0x023500b8 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkbcp: clkbcp { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdxb: clkdxb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dxb"; - reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkhyperlink1: clkhyperlink1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-1"; - reg = <0x023500c4 0xb00>, <0x02350070 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkxge: clkxge { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-evm.dts b/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-evm.dts deleted file mode 100644 index 2156ff92d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2hk.dtsi" - -/ { - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; - - soc { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-pass"; - }; - - refclkarm: refclkarm { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "refclk-arm"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - - refclkddr3b: refclkddr3b { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3b"; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - debug1_1 { - label = "keystone:green:debug1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ - }; - - debug1_2 { - label = "keystone:red:debug1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ - }; - - debug2 { - label = "keystone:blue:debug2"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ - }; - - debug3 { - label = "keystone:blue:debug3"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1fe80000>; - }; - }; - }; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi deleted file mode 100644 index f86d6ddb8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Hawking Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - - qmgr1 { - managed-queues = <0x2000 0x2000>; - reg = <0x2a60000 0x20000>, - <0x2a06400 0x400>, - <0x2a04000 0x1000>, - <0x2a05000 0x1000>, - <0x23aa0000 0x20000>, - <0x2aa0000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <8704 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <8720 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <640 9>; - qalloc-by-id; - }; - netcpx-tx { - qrange = <8752 8>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23aa0000 0x23ab0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x2004000 0x100>, - <0x2004400 0x120>, - <0x2004800 0x300>, - <0x2004c00 0x120>, - <0x2005000 0x400>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@2000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 22>, - <&dma_gbe 23>, - <&dma_gbe 8>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - ranges; - #address-cells = <1>; - #size-cells = <1>; - gbe@90000 { /* ETHSS */ - #address-cells = <1>; - #size-cells = <1>; - label = "netcp-gbe"; - compatible = "ti,netcp-gbe"; - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; - /* enable-ale; */ - tx-queue = <648>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8704>; - tx-completion-queue = <8706>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8705>; - tx-completion-queue = <8707>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 6f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk.dtsi deleted file mode 100644 index 8f67fa8df..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2hk.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking soc specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - soc { - /include/ "keystone-k2hk-clocks.dtsi" - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - dspgpio4: keystone_dsp_gpio@2620250 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x250>; - }; - - dspgpio5: keystone_dsp_gpio@2620254 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x254>; - }; - - dspgpio6: keystone_dsp_gpio@2620258 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x258>; - }; - - dspgpio7: keystone_dsp_gpio@262025c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x25c>; - }; - - mdio: mdio@02090300 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02090300 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2hk-netcp.dtsi" - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-clocks.dtsi deleted file mode 100644 index ef8464bb1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-clocks.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 lamarr SoC clock nodes - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkdfeiqnsys: clkdfeiqnsys { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "dfe"; - reg-names = "control", "domain"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - domain-id = <0>; - }; - - clkpcie1: clkpcie1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x0235002c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkgem1: clkgem1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clktac: clktac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac: clkrac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkdfepd0: clkdfepd0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd0"; - reg = <0x0235006c 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkosr: clkosr { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "osr"; - reg = <0x02350088 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350094 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkbcp: clkbcp { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdfepd1: clkdfepd1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd1"; - reg = <0x023500c0 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkfftc1: clkfftc1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkiqnail: clkiqnail { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "iqn-ail"; - reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - clkuart2: clkuart2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart3: clkuart3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-evm.dts b/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-evm.dts deleted file mode 100644 index 056b42f99..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-evm.dts +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Lamarr EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2l.dtsi" - -/ { - compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr EVM"; - - soc { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x7FE80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-netcp.dtsi deleted file mode 100644 index 5acbd0dcc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2l-netcp.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Lamarr Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; - -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x26186000 0x100>, - <0x26187000 0x2a0>, - <0x26188000 0xb60>, - <0x26186100 0x80>, - <0x26189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@26000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x26000000 0x1000000>; - - clocks = <&clkosr>, <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-5"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 7f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone-k2l.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone-k2l.dtsi deleted file mode 100644 index 2ee3d0ac2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone-k2l.dtsi +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Lamarr SoC specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - }; - - soc { - /include/ "keystone-k2l-clocks.dtsi" - - uart2: serial@02348400 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348400 0x100>; - clocks = <&clkuart2>; - interrupts = ; - }; - - uart3: serial@02348800 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348800 0x100>; - clocks = <&clkuart3>; - interrupts = ; - }; - - k2l_pmx: pinmux@02620690 { - compatible = "pinctrl-single"; - reg = <0x02620690 0xc>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - status = "disabled"; - - uart3_emifa_pins: pinmux_uart3_emifa_pins { - pinctrl-single,bits = < - /* UART3_EMIFA_SEL */ - 0x0 0x0 0xc0 - >; - }; - - uart2_emifa_pins: pinmux_uart2_emifa_pins { - pinctrl-single,bits = < - /* UART2_EMIFA_SEL */ - 0x0 0x0 0x30 - >; - }; - - uart01_spi2_pins: pinmux_uart01_spi2_pins { - pinctrl-single,bits = < - /* UART01_SPI2_SEL */ - 0x0 0x0 0x4 - >; - }; - - dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ - pinctrl-single,bits = < - /* DFESYNC_RP1_SEL */ - 0x0 0x0 0x2 - >; - }; - - avsif_pins: pinmux_avsif_pins { - pinctrl-single,bits = < - /* AVSIF_SEL */ - 0x0 0x0 0x1 - >; - }; - - gpio_emu_pins: pinmux_gpio_emu_pins { - pinctrl-single,bits = < - /* - * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 - * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 - * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 - * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 - * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 - * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 - * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 - * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 - * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 - * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 - * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 - * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 - * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 - * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 - * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 - */ - 0x4 0x0000 0xFFFE0000 - >; - }; - - gpio_timio_pins: pinmux_gpio_timio_pins { - pinctrl-single,bits = < - /* - * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 - * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 - * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 - * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 - * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 - * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 - * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 - * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 - * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 - * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 - * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 - * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 - */ - 0x4 0x0 0xFFF0 - >; - }; - - gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { - pinctrl-single,bits = < - /* - * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 - * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 - * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 - * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 - */ - 0x4 0x0 0xF - >; - }; - - gpio_dfeio_pins: pinmux_gpio_dfeio_pins { - pinctrl-single,bits = < - /* - * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 - * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 - * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 - * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 - * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 - * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 - * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 - * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 - * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 - * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 - * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 - * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 - * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 - * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 - * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 - * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 - */ - 0x8 0x0 0xFFFF0000 - >; - }; - - gpio_emifa_pins: pinmux_gpio_emifa_pins { - pinctrl-single,bits = < - /* - * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 - * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 - * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 - * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 - * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 - * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 - * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 - * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 - * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 - * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 - * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 - * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 - * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 - * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 - * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 - * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 - */ - 0x8 0x0 0xFFFF - >; - }; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x26200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2l-netcp.dtsi" - }; -}; - -&spi0 { - ti,davinci-spi-num-cs = <5>; -}; - -&spi1 { - ti,davinci-spi-num-cs = <3>; -}; - -&spi2 { - ti,davinci-spi-num-cs = <5>; - /* Pin muxed. Enabled and configured by Bootloader */ - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/keystone.dtsi b/software/linux/kernel/arch/arm/boot/dts/keystone.dtsi deleted file mode 100644 index 02708ba2d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/keystone.dtsi +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - -#include "skeleton.dtsi" - -/ { - compatible = "ti,keystone"; - model = "Texas Instruments Keystone 2 SoC"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - memory { - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; - }; - - gic: interrupt-controller { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>, - <0x0 0x02564000 0x0 0x1000>, - <0x0 0x02566000 0x0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,keystone","simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0x0 0x0 0xc0000000>; - dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - - pllctrl: pll-controller@02310000 { - compatible = "ti,keystone-pllctrl", "syscon"; - reg = <0x02310000 0x200>; - }; - - devctrl: device-state-control@02620000 { - compatible = "ti,keystone-devctrl", "syscon"; - reg = <0x02620000 0x1000>; - }; - - rstctrl: reset-controller { - compatible = "ti,keystone-reset"; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>; - }; - - /include/ "keystone-clocks.dtsi" - - uart0: serial@02530c00 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; - interrupts = ; - }; - - uart1: serial@02531000 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531000 0x100>; - clocks = <&clkuart1>; - interrupts = ; - }; - - i2c0: i2c@2530000 { - compatible = "ti,davinci-i2c"; - reg = <0x02530000 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@2530400 { - compatible = "ti,davinci-i2c"; - reg = <0x02530400 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@2530800 { - compatible = "ti,davinci-i2c"; - reg = <0x02530800 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@21000400 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@21000600 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000600 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi2: spi@21000800 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21000800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_phy: usb_phy@2620738 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620738 24>; - status = "disabled"; - }; - - keystone_usb0: usb@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - clocks = <&clkusb>; - clock-names = "usb"; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - usb0: dwc3@2690000 { - compatible = "synopsys,dwc3"; - reg = <0x2690000 0x70000>; - interrupts = ; - usb-phy = <&usb_phy>, <&usb_phy>; - }; - }; - - wdt: wdt@022f0080 { - compatible = "ti,keystone-wdt","ti,davinci-wdt"; - reg = <0x022f0080 0x80>; - clocks = <&clkwdtimer0>; - }; - - clock_event: timer@22f0000 { - compatible = "ti,keystone-timer"; - reg = <0x022f0000 0x80>; - interrupts = ; - clocks = <&clktimer15>; - }; - - gpio0: gpio@260bf00 { - compatible = "ti,keystone-gpio"; - reg = <0x0260bf00 0x100>; - gpio-controller; - #gpio-cells = <2>; - /* HW Interrupts mapped to GPIO pins */ - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clkgpio>; - clock-names = "gpio"; - ti,ngpio = <32>; - ti,davinci-gpio-unbanked = <32>; - }; - - aemif: aemif@21000A00 { - compatible = "ti,keystone-aemif", "ti,davinci-aemif"; - #address-cells = <2>; - #size-cells = <1>; - clocks = <&clkaemif>; - clock-names = "aemif"; - clock-ranges; - - reg = <0x21000A00 0x00000100>; - ranges = <0 0 0x30000000 0x10000000 - 1 0 0x21000A00 0x00000100>; - }; - - kirq0: keystone_irq@26202a0 { - compatible = "ti,keystone-irq"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - - pcie0: pcie@21800000 { - compatible = "ti,keystone-pcie", "snps,dw-pcie"; - clocks = <&clkpcie>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; - ranges = <0x82000000 0 0x50000000 0x50000000 - 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - bus-range = <0x00 0xff>; - - /* error interrupt */ - interrupts = ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ - <0 0 0 2 &pcie_intc0 1>, /* INT B */ - <0 0 0 3 &pcie_intc0 2>, /* INT C */ - <0 0 0 4 &pcie_intc0 3>; /* INT D */ - - pcie_msi_intc0: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - - pcie_intc0: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-6192.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-6192.dtsi deleted file mode 100644 index d573e03f3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-6192.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -/ { - mbus@f1000000 { - pciec: pcie-controller@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6192-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-6281.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-6281.dtsi deleted file mode 100644 index 748d0b62f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-6281.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -/ { - mbus@f1000000 { - pciec: pcie-controller@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6281-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-6282.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-6282.dtsi deleted file mode 100644 index bb63d2d50..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-6282.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -/ { - mbus@f1000000 { - pciec: pcie-controller@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - - pcie1: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 10>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 18>; - status = "disabled"; - }; - }; - }; - ocp@f1000000 { - - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6282-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - - /* - * Default I2C1 pinctrl setting on mpp36/mpp37, - * overwrite marvell,pins on board level if required. - */ - pmx_twsi1: pmx-twsi1 { - marvell,pins = "mpp36", "mpp37"; - marvell,function = "twsi1"; - }; - - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - thermal: thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - status = "okay"; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-98dx4122.dtsi deleted file mode 100644 index 720c210d4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/ { - mbus@f1000000 { - pciec: pcie-controller@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,98dx4122-pinctrl"; - - }; - }; -}; - -&sata_phy0 { - status = "disabled"; -}; - -&sata_phy1 { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-b3.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-b3.dts deleted file mode 100644 index d091ecb61..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-b3.dts +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Device Tree file for Excito Bubba B3 - * - * Copyright (C) 2013, Andrew Lunn - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Note: This requires a new'ish version of u-boot, which disables the - * L2 cache. If your B3 silently fails to boot, u-boot is probably too - * old. Either upgrade, or consider the following email: - * - * http://lists.debian.org/debian-arm/2012/08/msg00128.html - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Excito B3"; - compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - memory { /* 512 MB */ - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led-green { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_beeper: pmx-beeper { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - - m25p16@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p16", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0xc0000>; - label = "u-boot"; - }; - - partition@c0000 { - reg = <0xc0000 0x20000>; - label = "u-boot env"; - }; - - partition@e0000 { - reg = <0xe0000 0x120000>; - label = "data"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - /* - * There is something on the bus at address 0x64. - * Not yet identified what it is, maybe the eeprom - * for the Atheros WiFi chip? - */ - }; - - - serial@12000 { - /* Internal on test pins, 3.3v TTL - * UART0_RX = Testpoint 65 - * UART0_TX = Testpoint 66 - * See the Excito Wiki for more details. - */ - status = "okay"; - }; - - sata@80000 { - /* One internal, the second as eSATA */ - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-leds { - /* - * There is one LED "port" on the front and the colours - * mix together giving some interesting combinations. - */ - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_green &pmx_led_red - &pmx_led_blue >; - pinctrl-names = "default"; - - programming_led { - label = "bubba3:green:programming"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - error_led { - label = "bubba3:red:error"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - active_led { - label = "bubba3:blue:active"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power>; - pinctrl-names = "default"; - - power-button { - /* On the back */ - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - }; - - beeper: beeper { - /* 4KHz Piezoelectric buzzer */ - compatible = "gpio-beeper"; - pinctrl-0 = <&pmx_beeper>; - pinctrl-names = "default"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; - - ethphy1: ethernet-phy@24 { - device_type = "ethernet-phy"; - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -/* Wifi model has Atheros chipset on pcie port */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts deleted file mode 100644 index f16a73e49..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Device Tree file for Seagate Blackarmor NAS220 - * - * Copyright (C) 2014 Evgeni Dobrev - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; - -#include -#include -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "Seagate Blackarmor NAS220"; - compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - button { - label = "Power"; - linux,code = ; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-power { - label = "nas220:blue:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* - * Serial port routed to connector CN5 - * - * pin 1 - TX (CPU's TX) - * pin 4 - RX (CPU's RX) - * pin 6 - GND - */ -&uart0 { - status = "okay"; -}; - -&pinctrl { - pinctrl-0 = <&pmx_button_reset &pmx_button_power>; - pinctrl-names = "default"; - - pmx_act_sata0: pmx-act-sata0 { - marvell,pins = "mpp15"; - marvell,function = "sata0"; - }; - - pmx_act_sata1: pmx-act-sata1 { - marvell,pins = "mpp16"; - marvell,function = "sata1"; - }; - - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_button_power: pmx-button-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&i2c0 { - status = "okay"; - - adt7476: thermal@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; -}; - -&nand { - status = "okay"; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-cloudbox.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-cloudbox.dts deleted file mode 100644 index 555b7e4c5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ /dev/null @@ -1,102 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "LaCie CloudBox"; - compatible = "lacie,cloudbox", "marvell,kirkwood-88f6702", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_cloudbox_sata0: pmx-cloudbox-sata0 { - marvell,pins = "mpp15"; - marvell,function = "sata0"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - pinctrl-0 = <&pmx_cloudbox_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "cloudbox:red:fail"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - blue-sata { - label = "cloudbox:blue:sata"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-d2net.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-d2net.dts deleted file mode 100644 index e1c25c35e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-d2net.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Device Tree file for d2 Network v2 - * - * Copyright (C) 2014 Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -/dts-v1/; - -#include -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie d2 Network v2"; - compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "d2net_v2:blue:sata"; - slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - modes-map = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "d2net_v2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-db-88f6281.dts deleted file mode 100644 index aee6f02b1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-db-88f6281.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Marvell DB-88F6281-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood-db.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Marvell DB-88F6281-BP Development Board"; - compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-db-88f6282.dts deleted file mode 100644 index e8b23e13e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-db-88f6282.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Marvell DB-88F6282-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood-db.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Marvell DB-88F6282-BP Development Board"; - compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-db.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-db.dtsi deleted file mode 100644 index 812df691a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-db.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Marvell DB-{88F6281,88F6282}-BP Development Board Setup - * - * Saeed Bishara - * Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions that are common between the 6281 - * and 6282 variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pin-controller@10000 { - pmx_sdio_gpios: pmx-sdio-gpios { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <2>; - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio_gpios>; - pinctrl-names = "default"; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dir665.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-dir665.dts deleted file mode 100644 index 41acbb6dd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dir665.dts +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (C) 2014 Claudio Leite - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "D-Link DIR-665"; - compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 =< &pmx_led_usb - &pmx_led_internet_blue - &pmx_led_internet_amber - &pmx_led_5g &pmx_led_status_blue - &pmx_led_wps &pmx_led_status_amber - &pmx_led_24g - &pmx_btn_restart &pmx_btn_wps>; - pinctrl-names = "default"; - - pmx_led_usb: pmx-led-usb { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_led_internet_blue: pmx-led-internet-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_internet_amber: pmx-led-internet-amber { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_5g: pmx-led-5g { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_status_blue: pmx-led-status-blue { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_wps: pmx-led-wps { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_status_amber: pmx-led-status-amber { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_24g: pmx-led-24g { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_btn_restart: pmx-btn-restart { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_btn_wps: pmx-btn-wps { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "nvram"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "kernel"; - reg = <0x40000 0x180000>; - }; - - partition@1c0000 { - label = "rootfs"; - reg = <0x1c0000 0xe00000>; - }; - - cal_data: partition@fc0000 { - label = "cal_data"; - reg = <0xfc0000 0x10000>; - read-only; - }; - - partition@fd0000 { - label = "lang_pack"; - reg = <0xfd0000 0x30000>; - read-only; - }; - }; - }; - - serial@12000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-usb { - label = "dir665:blue:usb"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - blue-internet { - /* Can only be turned on if the Internet - * Ethernet port has Link - */ - label = "dir665:blue:internet"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - amber-internet { - label = "dir665:amber:internet"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - blue-wifi5g { - label = "dir665:blue:5g"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - blue-status { - label = "dir665:blue:status"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - blue-wps { - label = "dir665:blue:wps"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - amber-status { - label = "dir665:amber:status"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - blue-24g { - label = "dir665:blue:24g"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - reset { - label = "reset"; - linux,code = ; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; - - dsa { - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - }; - }; - }; -}; - -&mdio { - status = "okay"; -}; - -/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set - * fixed speed and duplex. */ -ð0 { - status = "okay"; - - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -/* eth1 is connected to the switch as well. However DSA only supports a - * single CPU port. So leave this port disabled to avoid confusion. */ - -ð1 { - status = "disabled"; -}; - -/* There is no battery on the boards, so the RTC does not keep time - * when there is no power, making it useless. */ -&rtc { - status = "disabled"; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dns320.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-dns320.dts deleted file mode 100644 index d85ef0a91..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dns320.dts +++ /dev/null @@ -1,58 +0,0 @@ -/dts-v1/; - -#include "kirkwood-dnskw.dtsi" - -/ { - model = "D-Link DNS-320 NAS (Rev A1)"; - compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320 - &pmx_led_red_left_hdd &pmx_led_red_right_hdd - &pmx_led_white_usb>; - pinctrl-names = "default"; - - blue-power { - label = "dns320:blue:power"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - blue-usb { - label = "dns320:blue:usb"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - orange-l_hdd { - label = "dns320:orange:l_hdd"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - orange-r_hdd { - label = "dns320:orange:r_hdd"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - orange-usb { - label = "dns320:orange:usb"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ - }; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dns325.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-dns325.dts deleted file mode 100644 index 5e586ed04..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dns325.dts +++ /dev/null @@ -1,62 +0,0 @@ -/dts-v1/; - -#include "kirkwood-dnskw.dtsi" - -/ { - model = "D-Link DNS-325 NAS (Rev A1)"; - compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 - &pmx_led_red_left_hdd &pmx_led_red_right_hdd - &pmx_led_white_usb>; - pinctrl-names = "default"; - - white-power { - label = "dns325:white:power"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - white-usb { - label = "dns325:white:usb"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ - }; - red-l_hdd { - label = "dns325:red:l_hdd"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - red-r_hdd { - label = "dns325:red:r_hdd"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - red-usb { - label = "dns325:red:usb"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - - lm75: lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - }; - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-dnskw.dtsi deleted file mode 100644 index d8fca9db4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "D-Link DNS NASes (kirkwood-based)"; - compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_power &pmx_button_unmount - &pmx_button_reset>; - pinctrl-names = "default"; - - power { - label = "Power button"; - linux,code = ; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - eject { - label = "USB unmount button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset button"; - linux,code = ; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; - pinctrl-names = "default"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW - &gpio1 13 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = <0 0 - 3000 1 - 6000 2>; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 - &pmx_present_sata1 &pmx_fan_tacho - &pmx_temp_alarm>; - pinctrl-names = "default"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - pmx_led_red_right_hdd: pmx-led-red-right-hdd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_led_red_left_hdd: pmx-led-red-left-hdd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_325: pmx-led-red-usb-325 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_button_power: pmx-button-power { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_320: pmx-led-red-usb-320 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_power_back_on: pmx-power-back-on { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_present_sata0: pmx-present-sata0 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_present_sata1: pmx-present-sata1 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_white_usb: pmx-led-white-usb { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_fan_tacho: pmx-fan-tacho { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_fan_high_speed: pmx-fan-high-speed { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_fan_low_speed: pmx-fan-low-speed { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_button_unmount: pmx-button-unmount { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_temp_alarm: pmx-temp-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 7 0>; - }; - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 8 0>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x500000>; - }; - - partition@600000 { - label = "ramdisk"; - reg = <0x0600000 0x500000>; - }; - - partition@b00000 { - label = "image"; - reg = <0x0b00000 0x6600000>; - }; - - partition@7100000 { - label = "mini firmware"; - reg = <0x7100000 0xa00000>; - }; - - partition@7b00000 { - label = "config"; - reg = <0x7b00000 0x500000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dockstar.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-dockstar.dts deleted file mode 100644 index 849736349..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dockstar.dts +++ /dev/null @@ -1,109 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate FreeAgent Dockstar"; - compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led-green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_orange>; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x0500000 0xfb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - compatible = "marvell,88e1116"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dreamplug.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-dreamplug.dts deleted file mode 100644 index e2abc8246..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ /dev/null @@ -1,126 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Dreamplug"; - compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_bluetooth: pmx-led-bluetooth { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wifi: pmx-led-wifi { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wifi_ap: pmx-led-wifi-ap { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - - partition@100000 { - reg = <0x100000 0x10000>; - label = "u-boot env"; - }; - - partition@180000 { - reg = <0x180000 0x10000>; - label = "dtb"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi - &pmx_led_wifi_ap >; - pinctrl-names = "default"; - - bluetooth { - label = "dreamplug:blue:bluetooth"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wifi { - label = "dreamplug:green:wifi"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wifi-ap { - label = "dreamplug:green:wifi_ap"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds109.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds109.dts deleted file mode 100644 index d4bcc1c7f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds109.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS109, DS110, DS110jv20"; - compatible = "synology,ds109", "synology,ds110jv20", - "synology,ds110", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds110jv10.dts deleted file mode 100644 index 95bf83b91..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds110jv10.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS110j v10 and v30"; - compatible = "synology,ds110jv10", "synology,ds110jv30", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds111.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds111.dts deleted file mode 100644 index a85a46644..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds111.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS111"; - compatible = "synology,ds111", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds112.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds112.dts deleted file mode 100644 index 6cef4bdbc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds112.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS112"; - compatible = "synology,ds111", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-21-2 { - status = "okay"; - }; - - regulators-hdd-30 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds209.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds209.dts deleted file mode 100644 index 6d25093a9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds209.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS209"; - compatible = "synology,ds209", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; - - regulators-hdd-31 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds210.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds210.dts deleted file mode 100644 index 2f1933efc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds210.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS210 v10, v20, v30, DS211j"; - compatible = "synology,ds210jv10", "synology,ds210jv20", - "synology,ds210jv30", "synology,ds211j", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; - - regulators-hdd-31 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds212.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds212.dts deleted file mode 100644 index 7f32e7abf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds212.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10"; - compatible = "synology,ds212", "synology,ds212pv10", - "synology,ds212pv10", "synology,ds212pv20", - "synology,ds213airv10", "synology,ds213v10", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds212j.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds212j.dts deleted file mode 100644 index f5c4213fc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds212j.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS212j v10, v20"; - compatible = "synology,ds212jv10", "synology,ds212jv20", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds409.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds409.dts deleted file mode 100644 index e80a962eb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds409.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS409, DS410j"; - compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - gpio-leds-alarm-12 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds409slim.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds409slim.dts deleted file mode 100644 index cae5af4b8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds409slim.dts +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology 409slim"; - compatible = "synology,ds409slim", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-20 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411.dts deleted file mode 100644 index 72e583074..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411, DS413jv10"; - compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - regulators-hdd-34 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411j.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411j.dts deleted file mode 100644 index 3348e330f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411j.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411j"; - compatible = "synology,ds411j", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; - - gpio-leds-alarm-12 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411slim.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411slim.dts deleted file mode 100644 index aaaf31b81..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ds411slim.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS411slim"; - compatible = "synology,ds411slim", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-1 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-goflexnet.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-goflexnet.dts deleted file mode 100644 index aa60a0b04..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ /dev/null @@ -1,189 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate GoFlex Net"; - compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_0: pmx-led_right_cap_0 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_1: pmx-led_right_cap_1 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_2: pmx-led_right_cap_2 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_3: pmx-led_right_cap_3 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_0: pmx-led_left_cap_0 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_1: pmx-led_left_cap_1 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_2: pmx-led_left_cap_2 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_3: pmx-led_left_cap_3 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led_green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led_orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_orange - &pmx_led_left_cap_0 &pmx_led_left_cap_1 - &pmx_led_left_cap_2 &pmx_led_left_cap_3 - &pmx_led_right_cap_0 &pmx_led_right_cap_1 - &pmx_led_right_cap_2 &pmx_led_right_cap_3 - >; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - left0 { - label = "status:white:left0"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - left1 { - label = "status:white:left1"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - left2 { - label = "status:white:left2"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - left3 { - label = "status:white:left3"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - right0 { - label = "status:white:right0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - right1 { - label = "status:white:right1"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - right2 { - label = "status:white:right2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - right3 { - label = "status:white:right3"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0xd800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts deleted file mode 100644 index b2d9834bf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ /dev/null @@ -1,132 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Guruplug Server Plus"; - compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_health_r: pmx-led-health-r { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_health_g: pmx-led-health-g { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wmode_r: pmx-led-wmode-r { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wmode_g: pmx-led-wmode-g { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - /* AzureWave AW-GH381 WiFi/BT */ - mvsdio@90000 { - status = "okay"; - non-removable; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g - &pmx_led_wmode_r &pmx_led_wmode_g >; - pinctrl-names = "default"; - - health-r { - label = "guruplug:red:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - health-g { - label = "guruplug:green:health"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wmode-r { - label = "guruplug:red:wmode"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wmode-g { - label = "guruplug:green:wmode"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x00100000 0x00400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x00500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - phy-connection-type = "rgmii-id"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ib62x0.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ib62x0.dts deleted file mode 100644 index 5bf628970..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ /dev/null @@ -1,145 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_os_red: pmx-led-os-red { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - pmx_led_os_green: pmx-led-os-green { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - pmx_led_usb_transfer: pmx-led-usb-transfer { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_button_usb_copy: pmx-button-usb-copy { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green - &pmx_led_usb_transfer>; - pinctrl-names = "default"; - - green-os { - label = "ib62x0:green:os"; - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - red-os { - label = "ib62x0:red:os"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - }; - usb-copy { - label = "ib62x0:red:usb_copy"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0xe0000>; - }; - - partition@e0000 { - label = "u-boot environment"; - reg = <0xe0000 0x20000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x600000>; - }; - - partition@700000 { - label = "root"; - reg = <0x0700000 0xf900000>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-iconnect.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-iconnect.dts deleted file mode 100644 index d25184ae4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-iconnect.dts +++ /dev/null @@ -1,194 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Iomega Iconnect"; - compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - linux,initrd-start = <0x4500040>; - linux,initrd-end = <0x4800000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_button_otb: pmx-button-otb { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_level: pmx-led-level { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_power_blue: pmx-led-power-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_power_red: pmx-power-red { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_usb1: pmx-led-usb1 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_usb2: pmx-led-usb2 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_usb3: pmx-led-usb3 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_usb4: pmx-led-usb4 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_otb: pmx-led-otb { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - i2c@11000 { - status = "okay"; - - lm63: lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; - }; - serial@12000 { - status = "ok"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_level &pmx_led_power_blue - &pmx_led_power_red &pmx_led_usb1 - &pmx_led_usb2 &pmx_led_usb3 - &pmx_led_usb4 &pmx_led_otb >; - pinctrl-names = "default"; - - led-level { - label = "led_level"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - power-blue { - label = "power:blue"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power-red { - label = "power:red"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - usb1 { - label = "usb1:blue"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - usb2 { - label = "usb2:blue"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - usb3 { - label = "usb3:blue"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - usb4 { - label = "usb4:blue"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - otb { - label = "otb:blue"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; - pinctrl-names = "default"; - - otb { - label = "OTB Button"; - linux,code = ; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0xc0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - }; - - partition@100000 { - label = "zImage"; - reg = <0x100000 0x300000>; - }; - - partition@540000 { - label = "initrd"; - reg = <0x540000 0x300000>; - }; - - partition@980000 { - label = "boot"; - reg = <0x980000 0x1f400000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts deleted file mode 100644 index 8474bffec..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ /dev/null @@ -1,225 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Iomega StorCenter ix2-200"; - compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 - &pmx_led_sata_brt_ctrl_2 - &pmx_led_backup_brt_ctrl_1 - &pmx_led_backup_brt_ctrl_2 - &pmx_led_power_brt_ctrl_1 - &pmx_led_power_brt_ctrl_2 - &pmx_led_health_brt_ctrl_1 - &pmx_led_health_brt_ctrl_2 - &pmx_led_rebuild_brt_ctrl_1 - &pmx_led_rebuild_brt_ctrl_2 >; - pinctrl-names = "default"; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_button_power: pmx-button-power { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - pmx_led_backup: pmx-led-backup { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_button_otb: pmx-button-otb { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_rebuild: pmx-led-rebuild { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_health: pmx-led_health { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - }; - i2c@11000 { - status = "okay"; - - lm63: lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; - }; - - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_backup &pmx_led_power - &pmx_led_rebuild &pmx_led_health >; - pinctrl-names = "default"; - - power_led { - label = "status:white:power_led"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - rebuild_led { - label = "status:white:rebuild_led"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - health_led { - label = "status:red:health_led"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - }; - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_reset &pmx_button_power - &pmx_button_otb>; - pinctrl-names = "default"; - - - Power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - Reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - OTB { - label = "OTB Button"; - linux,code = ; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - }; - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x300000>; - }; - - partition@400000 { - label = "rootfs"; - reg = <0x400000 0x1C00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-is2.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-is2.dts deleted file mode 100644 index 4121674ab..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-is2.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Internet Space v2"; - compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_common.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_common.dtsi deleted file mode 100644 index 7962bdefd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_common.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; - pinctrl-names = "default"; - - pmx_i2c_gpio_sda: pmx-gpio-sda { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_i2c_gpio_scl: pmx-gpio-scl { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - }; - - i2c { - compatible = "i2c-gpio"; - gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ - &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - }; -}; - -&nand { - status = "okay"; - chip-delay = <25>; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_fixedeth.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_fixedeth.dts deleted file mode 100644 index 9895f2b10..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_fixedeth.dts +++ /dev/null @@ -1,23 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-98dx4122.dtsi" -#include "kirkwood-km_common.dtsi" - -/ { - model = "Keymile Kirkwood Fixed Eth"; - compatible = "keymile,km_fixedeth", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; /* */ - duplex = <1>; /* */ - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_kirkwood.dts deleted file mode 100644 index 235bf382f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ /dev/null @@ -1,30 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-98dx4122.dtsi" -#include "kirkwood-km_common.dtsi" - -/ { - model = "Keymile Kirkwood Reference Design"; - compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-laplug.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-laplug.dts deleted file mode 100644 index 1b0f070c2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-laplug.dts +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2013 Maxime Hadjinlian - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "LaCie LaPlug"; - compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - i2c@11000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - }; - - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "laplug_v2:red:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - blue-power { - label = "laplug_v2:blue:power"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power_back1: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power Back 1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - - usb_power_back2: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "USB Power Back 2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - - usb_power_front: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "USB Power Front"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - /* Total size : 512MB */ - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; /* 1MB */ - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x1000000>; /* 16MB */ - }; - - partition@1100000 { - label = "rootfs"; - reg = <0x1100000 0x1EF00000>; /* 495MB */ - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi deleted file mode 100644 index 6548e68a2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Device Tree common file for kirkwood-6282 based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-linkstation.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - function-button { - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - power-on-switch { - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - red-alarm-led { - label = "linkstation:red:alarm"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - red-function-led { - label = "linkstation:red:function"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - amber-info-led { - label = "linkstation:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - - blue-function-led { - label = "linkstation:blue:function"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - - blue-power-led { - label = "linkstation:blue:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpios = <&gpio0 17 GPIO_ACTIVE_LOW - &gpio0 16 GPIO_ACTIVE_LOW>; - - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - - alarm-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - - regulators { - usb_power: regulator@1 { - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - - hdd_power0: regulator@2 { - gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi deleted file mode 100644 index cf2e69f0d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Device Tree common file for kirkwood-6281 based 2-Bay Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-linkstation.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_keys { - function-button { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - power-on-switch { - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - red-alarm-led { - label = "linkstation:red:alarm"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - - red-function-led { - label = "linkstation:red:function"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - amber-info-led { - label = "linkstation:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - blue-function-led { - label = "linkstation:blue:function"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - blue-power-led { - label = "linkstation:blue:power"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - usb_power: regulator@1 { - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - hdd_power0: regulator@2 { - gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; -}; - -ð1 { - status = "okay"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts deleted file mode 100644 index 6dc0df296..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-QVL - * - * Copyright (C) 2016, Mario Lange - * - * Based on kirkwood-linkstation-lswvl.dts, - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-QVL"; - compatible = "buffalo,lsqvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_hdderr2: pmx-led-hdderr2 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - pmx_led_hdderr3: pmx-led-hdderr3 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1 - &pmx_led_hdderr2 - &pmx_led_hdderr3>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - - red-hdderr2-led { - label = "linkstation:red:hdderr2"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - red-hdderr3-led { - label = "linkstation:red:hdderr3"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts deleted file mode 100644 index edcba5c44..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-VL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-VL"; - compatible = "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts deleted file mode 100644 index 4b6450186..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-WSXL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "kirkwood-linkstation-duo-6281.dtsi" - -/ { - model = "Buffalo Linkstation LS-WSXL"; - compatible = "buffalo,lswsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts deleted file mode 100644 index 954ec1d5b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-WVL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "kirkwood-linkstation-6282.dtsi" - -/ { - model = "Buffalo Linkstation LS-WVL"; - compatible = "buffalo,lswvl","marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd1: pmx-power-hdd1 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - }; - - sata@80000 { - nr-ports = <2>; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>; - - hdd_power1: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "HDD1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts deleted file mode 100644 index ecd5c12a8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-WXL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "kirkwood-linkstation-duo-6281.dtsi" - -/ { - model = "Buffalo Linkstation LS-WXL"; - compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_hdderr0: pmx-led-hdderr0 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_led_hdderr1: pmx-led-hdderr1 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_leds { - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue - &pmx_led_hdderr0 - &pmx_led_hdderr1>; - - red-hdderr0-led { - label = "linkstation:red:hdderr0"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - red-hdderr1-led { - label = "linkstation:red:hdderr1"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpios = <&gpio1 16 GPIO_ACTIVE_LOW - &gpio1 15 GPIO_ACTIVE_LOW>; - - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - - alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation.dtsi deleted file mode 100644 index 36c54c9df..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linkstation.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Device Tree common file for kirkwood based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd0: pmx-power-hdd0 { - marvell,function = "gpio"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function-red { - marvell,function = "gpio"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - function-button { - label = "Function Button"; - linux,code = ; - }; - - power-on-switch { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - }; - - power-auto-switch { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue>; - pinctrl-names = "default"; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd0 &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - hdd_power0: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-linksys-viper.dts deleted file mode 100644 index 345fcac48..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-linksys-viper.dts +++ /dev/null @@ -1,240 +0,0 @@ -/* - * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500) - * - * (c) 2013 Jonas Gorski - * (c) 2013 Deutsche Telekom Innovation Laboratories - * (c) 2014 Luka Perkov - * (c) 2014 Randy C. Will - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Linksys Viper (E4200v2 / EA4500)"; - compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; - pinctrl-names = "default"; - - wps { - label = "WPS Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; - pinctrl-names = "default"; - - white-health { - label = "viper:white:health"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - white-pulse { - label = "viper:white:pulse"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - }; - }; - - dsa { - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@16,0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <16 0>; /* MDIO address 16, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "ethernet1"; - }; - - port@1 { - reg = <1>; - label = "ethernet2"; - }; - - port@2 { - reg = <2>; - label = "ethernet3"; - }; - - port@3 { - reg = <3>; - label = "ethernet4"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; -}; - -&pinctrl { - pmx_led_white_health: pmx-led-white-health { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - pmx_led_white_pulse: pmx-led-white-pulse { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - pmx_btn_wps: pmx-btn-wps { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u_env"; - reg = <0x80000 0x20000>; - }; - - partition@A0000 { - label = "s_env"; - reg = <0xA0000 0x20000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x2A0000>; - }; - - partition@4A0000 { - label = "rootfs"; - reg = <0x4A0000 0x1760000>; - }; - - partition@1C00000 { - label = "alt_kernel"; - reg = <0x1C00000 0x2A0000>; - }; - - partition@1EA0000 { - label = "alt_rootfs"; - reg = <0x1EA0000 0x1760000>; - }; - - partition@3600000 { - label = "syscfg"; - reg = <0x3600000 0x4A00000>; - }; - - partition@C0000 { - label = "unused"; - reg = <0xC0000 0x140000>; - }; - - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&mdio { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set - * fixed speed and duplex. - */ -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -/* eth1 is connected to the switch at port 6. However DSA only supports a - * single CPU port. So leave this port disabled to avoid confusion. - */ -ð1 { - status = "disabled"; -}; - -/* There is no battery on the board, so the RTC does not keep - * time when there is no power, making it useless. - */ -&rtc { - status = "disabled"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-lschlv2.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-lschlv2.dts deleted file mode 100644 index e2fa368ae..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-lschlv2.dts +++ /dev/null @@ -1,19 +0,0 @@ -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-CHLv2"; - compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-lsxhl.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-lsxhl.dts deleted file mode 100644 index 8d89cdf8d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-lsxhl.dts +++ /dev/null @@ -1,19 +0,0 @@ -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-XHL"; - compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-lsxl.dtsi deleted file mode 100644 index 8b7c6ce79..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp19"; - marvell,function = "gpo"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function_red { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - }; - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - option { - label = "Function Button"; - linux,code = ; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - reserved { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - power { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue>; - pinctrl-names = "default"; - - func_blue { - label = "lsxl:blue:func"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - alarm { - label = "lsxl:red:alarm"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - info { - label = "lsxl:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - power { - label = "lsxl:blue:power"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - func_red { - label = "lsxl:red:func"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - gpios = <&gpio0 19 GPIO_ACTIVE_LOW - &gpio0 18 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 11 0>; - }; - hdd_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 0>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-mplcec4.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-mplcec4.dts deleted file mode 100644 index aa413b0bc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ /dev/null @@ -1,215 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "MPL CEC4"; - compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_health: pmx-led-health { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp34"; - marvell,function = "sata1"; - }; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp35"; - marvell,function = "sata0"; - }; - - pmx_led_user1o: pmx-led-user1o { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - pmx_led_user1g: pmx-led-user1g { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_user0o: pmx-led-user0o { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_led_user0g: pmx-led-user0g { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_led_misc: pmx-led-misc { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - i2c@11000 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - }; - - }; - - serial@12000 { - status = "okay"; - }; - - rtc@10300 { - status = "disabled"; - }; - - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - nr-ports = <2>; - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - /* No WP GPIO */ - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_health - &pmx_led_user1o - &pmx_led_user1g &pmx_led_user0o - &pmx_led_user0g &pmx_led_misc - >; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - }; - - user1o { - label = "user1:orange"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user1g { - label = "user1:green"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user0o { - label = "user0:orange"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user0g { - label = "user0:green"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - misc { - label = "status:orange:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "fdt"; - reg = <0x180000 0x80000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x400000>; - }; - - partition@600000 { - label = "rootfs"; - reg = <0x600000 0x1fa00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - - ethphy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts deleted file mode 100644 index 172a38c0b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Marvell 88F6281 GTW GE Board - * - * Lennert Buytenhek - * Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions that are common between the 6281 - * and 6282 variants of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Marvell 88F6281 GTW GE Board"; - compatible = "marvell,mv88f6281gtw-ge", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pin-controller@10000 { - pmx_usb_led: pmx-usb-led { - marvell,pins = "mpp12"; - marvell,function = "gpo"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp20", "mpp21"; - marvell,function = "gpio"; - }; - - pmx_keys: pmx-keys { - marvell,pins = "mpp46", "mpp47"; - marvell,function = "gpio"; - }; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - ehci@50000 { - status = "okay"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds &pmx_usb_led>; - pinctrl-names = "default"; - - green-status { - label = "gtw:green:Status"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - }; - - red-status { - label = "gtw:red:Status"; - gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - - green-usb { - label = "gtw:green:USB"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_keys>; - pinctrl-names = "default"; - - restart { - label = "SWR Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wps { - label = "WPS Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; - - dsa { - compatible = "marvell,dsa"; - #address-cells = <1>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; -}; - -&mdio { - status = "okay"; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nas2big.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-nas2big.dts deleted file mode 100644 index f53bcacf6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nas2big.dts +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Device Tree file for LaCie 2Big NAS - * - * Copyright (C) 2015 Seagate - * - * Author: Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -/dts-v1/; - -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 2Big NAS"; - compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - rtc@10300 { - /* The on-chip RTC is not powered (no supercap). */ - status = "disabled"; - }; - spi@10600 { - /* - * A NAND flash is used instead of an SPI flash for - * the other netxbig-compatible boards. - */ - status = "disabled"; - }; - }; - - fan { - /* - * An I2C fan controller (GMT G762) is used but alarm is - * wired to a separate GPIO. - */ - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - regulators: regulators { - status = "okay"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - /* - * An external I2C RTC (Dallas DS1337S+) is used. This allows - * to power-up the board on an RTC alarm. The external RTC can - * be kept powered, even when the SoC is off. - */ - rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - interrupts = <43>; - }; - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; - -&nand { - chip-delay = <50>; - status = "okay"; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x1000000>; - }; - - partition@1100000 { - label = "root"; - reg = <0x1100000 0x8000000>; - }; - - partition@9100000 { - label = "unused"; - reg = <0x9100000 0x6f00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-net2big.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-net2big.dts deleted file mode 100644 index 13a44773b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-net2big.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Device Tree file for LaCie 2Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 2Big Network v2"; - compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - fan { - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; -}; - -®ulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&i2c0 { - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-net5big.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-net5big.dts deleted file mode 100644 index d2d44df9c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-net5big.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Device Tree file for LaCie 5Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 5Big Network v2"; - compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - -}; - -®ulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - netxbig-leds { - blue-sata2 { - label = "netxbig:blue:sata2"; - mode-addr = <5>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata2 { - label = "netxbig:red:sata2"; - mode-addr = <5>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata3 { - label = "netxbig:blue:sata3"; - mode-addr = <6>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata3 { - label = "netxbig:red:sata3"; - mode-addr = <6>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata4 { - label = "netxbig:blue:sata4"; - mode-addr = <7>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata4 { - label = "netxbig:red:sata4"; - mode-addr = <7>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - }; -}; - -&mdio { - ethphy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - - -&i2c0 { - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts deleted file mode 100644 index c0413b63c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Device Tree file for NETGEAR ReadyNAS Duo v2 - * - * Copyright (C) 2013, Arnaud EBALARD - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "NETGEAR ReadyNAS Duo v2"; - compatible = "netgear,readynas-duo-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_button_backup: pmx-button-backup { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_blue_power: pmx-led-blue-power { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_led_blue_activity: pmx-led-blue-activity { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk1: pmx-led-blue-disk1 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk2: pmx-led-blue-disk2 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_blue_backup: pmx-led-blue-backup { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - i2c@11000 { - status = "okay"; - - rs5c372a: rs5c372a@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity - &pmx_led_blue_disk1 &pmx_led_blue_disk2 - &pmx_led_blue_backup >; - pinctrl-names = "default"; - - power_led { - label = "status:blue:power_led"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - activity_led { - label = "status:blue:activity_led"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - disk1_led { - label = "status:blue:disk1_led"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - disk2_led { - label = "status:blue:disk2_led"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power &pmx_button_backup - &pmx_button_reset>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb3_regulator: usb3-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB 3.0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "jffs2"; - reg = <0x1800000 0x6800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts deleted file mode 100644 index 2bfc6cfa1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Device Tree file for NETGEAR ReadyNAS NV+ v2 - * - * Copyright (C) 2013, Arnaud EBALARD - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "NETGEAR ReadyNAS NV+ v2"; - compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { /* 256 MB */ - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_power: pmx-button-power { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_button_backup: pmx-button-backup { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_blue_power: pmx-led-blue-power { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_led_blue_backup: pmx-led-blue-backup { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk1: pmx-led-blue-disk1 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk2: pmx-led-blue-disk2 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk3: pmx-led-blue-disk3 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_led_blue_disk4: pmx-led-blue-disk4 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_poweroff: pmx-poweroff { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - i2c@11000 { - status = "okay"; - - rs5c372a: rs5c372a@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */ - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup - &pmx_led_blue_disk1 &pmx_led_blue_disk2 - &pmx_led_blue_disk3 &pmx_led_blue_disk3 >; - pinctrl-names = "default"; - - power_led { - label = "status:blue:power_led"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - backup_led { - label = "status:blue:backup_led"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - disk1_led { - label = "status:blue:disk1_led"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - disk2_led { - label = "status:blue:disk2_led"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - disk3_led { - label = "status:blue:disk3_led"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - disk4_led { - label = "status:blue:disk4_led"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_button_power &pmx_button_backup - &pmx_button_reset>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - - reset-button { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - backup-button { - label = "Backup Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_poweroff>; - pinctrl-names = "default"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb3_regulator: usb3-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB 3.0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "jffs2"; - reg = <0x1800000 0x6800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -/* Connected to NEC uPD720200 USB 3.0 controller */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-netxbig.dtsi deleted file mode 100644 index 52b58fe0c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-netxbig.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Device Tree common file for LaCie 2Big and 5Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -#include -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - /* - * esc and power represent a three position rocker - * switch. Thus the conventional KEY_POWER does not fit - */ - exc { - label = "Back power switch (on|auto)"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - power { - label = "Back power switch (auto|off)"; - linux,code = ; - linux,input-type = <5>; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - option { - label = "Function button"; - linux,code = ; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - regulators: regulators { - status = "okay"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd0power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - }; - - netxbig_gpio_ext: netxbig-gpio-ext { - compatible = "lacie,netxbig-gpio-ext"; - - addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH - &gpio1 16 GPIO_ACTIVE_HIGH - &gpio1 17 GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH - &gpio1 14 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - netxbig-leds { - compatible = "lacie,netxbig-leds"; - - gpio-ext = <&netxbig_gpio_ext>; - - timers = ; - - blue-power { - label = "netxbig:blue:power"; - mode-addr = <0>; - mode-val = ; - bright-addr = <1>; - max-brightness = <7>; - }; - red-power { - label = "netxbig:red:power"; - mode-addr = <0>; - mode-val = ; - bright-addr = <1>; - max-brightness = <7>; - }; - blue-sata0 { - label = "netxbig:blue:sata0"; - mode-addr = <3>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata0 { - label = "netxbig:red:sata0"; - mode-addr = <3>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata1 { - label = "netxbig:blue:sata1"; - mode-addr = <4>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata1 { - label = "netxbig:red:sata1"; - mode-addr = <4>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - - pmx_button_function: pmx-button-function { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_button_power_off: pmx-button-power-off { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_button_power_on: pmx-button-power-on { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2-common.dtsi deleted file mode 100644 index 282605f4c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_ns2_sata0: pmx-ns2-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_ns2_sata1: pmx-ns2-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power push button"; - linux,code = ; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "ns2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2.dts deleted file mode 100644 index 190189d23..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2.dts +++ /dev/null @@ -1,39 +0,0 @@ -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space v2"; - compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2lite.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2lite.dts deleted file mode 100644 index 2c661add0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ /dev/null @@ -1,34 +0,0 @@ -/dts-v1/; - -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Lite v2"; - compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-sata { - label = "ns2:blue:sata"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2max.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2max.dts deleted file mode 100644 index 55cc41d9c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2max.dts +++ /dev/null @@ -1,58 +0,0 @@ -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Max v2"; - compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 1500 15 - 1700 14 - 1800 13 - 2100 12 - 3100 11 - 3300 10 - 4300 9 - 5500 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2mini.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2mini.dts deleted file mode 100644 index 9935f3ec2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ /dev/null @@ -1,59 +0,0 @@ -/dts-v1/; - -#include -#include "kirkwood-ns2-common.dtsi" - -/ { - /* This machine is embedded in the first LaCie CloudBox product. */ - model = "LaCie Network Space Mini v2"; - compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 3000 15 - 3180 14 - 4140 13 - 4570 12 - 6760 11 - 7140 10 - 7980 9 - 9200 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa310.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa310.dts deleted file mode 100644 index 0b69ee493..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa310.dts +++ /dev/null @@ -1,138 +0,0 @@ -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_unknown>; - pinctrl-names = "default"; - - pmx_led_esata_green: pmx-led-esata-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_esata_red: pmx-led-esata-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_led_usb_red: pmx-led-usb-red { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_green: pmx-led-hdd-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_red: pmx-led-hdd-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_unknown: pmx-unknown { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - }; - - i2c@11000 { - status = "okay"; - - adt7476: adt7476a@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red - &pmx_led_usb_green &pmx_led_usb_red - &pmx_led_sys_green &pmx_led_sys_red - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd_green &pmx_led_hdd_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa310:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - red-sys { - label = "nsa310:red:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd { - label = "nsa310:green:hdd"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd { - label = "nsa310:red:hdd"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-esata { - label = "nsa310:green:esata"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-esata { - label = "nsa310:red:esata"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa310:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - red-usb { - label = "nsa310:red:usb"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa310:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa310:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa310a.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa310a.dts deleted file mode 100644 index 3d2b3d494..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ /dev/null @@ -1,114 +0,0 @@ -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/* - * There are at least two different NSA310 designs. This variant does - * not have the red USB Led. - */ - -/ { - compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_led_esata_green: pmx-led-esata-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_esata_red: pmx-led-esata-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_green: pmx-led-hdd-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd_red: pmx-led-hdd-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - }; - - i2c@11000 { - status = "okay"; - - lm85: lm85@2e { - compatible = "national,lm85"; - reg = <0x2e>; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green-sys { - label = "nsa310:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - red-sys { - label = "nsa310:red:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd { - label = "nsa310:green:hdd"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd { - label = "nsa310:red:hdd"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-esata { - label = "nsa310:green:esata"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-esata { - label = "nsa310:red:esata"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa310:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa310:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa310:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa320.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa320.dts deleted file mode 100644 index 6ab104b4b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa320.dts +++ /dev/null @@ -1,222 +0,0 @@ -/* Device tree file for the Zyxel NSA 320 NAS box. - * - * Copyright (c) 2014, Adam Baker - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Based upon the board setup file created by Peter Schildmann */ - -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - model = "Zyxel NSA320"; - compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - /* SATA Activity and Present pins are not connected */ - pmx_sata0: pmx-sata0 { - marvell,pins ; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins ; - marvell,function = "sata1"; - }; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_mcu_data: pmx-mcu-data { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_mcu_clk: pmx-mcu-clk { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_mcu_act: pmx-mcu-act { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_htp: pmx-htp { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - /* Buzzer needs to be switched at around 1kHz so is - not compatible with the gpio-beeper driver. */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_vid_b1: pmx-vid-b1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_resume_data: pmx-power-resume-data { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_power_resume_clk: pmx-power-resume-clk { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - - i2c@11000 { - status = "okay"; - - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - regulators { - usb0_power: regulator@1 { - enable-active-high; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa320:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - orange-sys { - label = "nsa320:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa320:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa320:red:hdd1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa320:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa320:red:hdd2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa320:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa320:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa320:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - }; - - hwmon { - compatible = "zyxel,nsa320-mcu"; - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; - pinctrl-names = "default"; - - data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - - /* The following pins are currently not assigned to a driver, - some of them should be configured as inputs. - pinctrl-0 = <&pmx_htp &pmx_vid_b1 - &pmx_power_resume_data &pmx_power_resume_clk>; */ -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa325.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa325.dts deleted file mode 100644 index 36c64816b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa325.dts +++ /dev/null @@ -1,235 +0,0 @@ -/* Device tree file for the Zyxel NSA 325 NAS box. - * - * Copyright (c) 2015, Hans Ulli Kroll - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Based upon the board setup file created by Peter Schildmann - */ - -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - model = "ZyXEL NSA325"; - compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_mcu_data: pmx-mcu-data { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_mcu_clk: pmx-mcu-clk { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_mcu_act: pmx-mcu-act { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_htp: pmx-htp { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - /* - * Buzzer needs to be switched at around 1kHz so is - * not compatible with the gpio-beeper driver. - */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_vid_b1: pmx-vid-b1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_resume_data: pmx-power-resume-data { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_power_resume_clk: pmx-power-resume-clk { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - - pmx_pwr_sata1: pmx-pwr-sata1 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - /* This board uses the pcf8563 RTC instead of the SoC RTC */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - status = "okay"; - - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_pwr_sata1>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - enable-active-high; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa325:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - orange-sys { - label = "nsa325:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa325:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa325:red:hdd1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa325:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa325:red:hdd2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa325:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa325:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa325:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - /* The following pins are currently not assigned to a driver, - some of them should be configured as inputs. - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act - &pmx_htp &pmx_vid_b1 - &pmx_power_resume_data &pmx_power_resume_clk>; */ - }; - - -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi deleted file mode 100644 index e09b79ac7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "ZyXEL NSA310"; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - copy { - label = "Copy Button"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - read-only; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-openblocks_a6.dts deleted file mode 100644 index 94e49f32d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ /dev/null @@ -1,183 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Plat'Home OpenBlocksA6"; - compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <1>; - status = "okay"; - }; - - i2c@11100 { - status = "okay"; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches>; - pinctrl-names = "default"; - - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11", "mpp15", - "mpp16"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14", "mpp8", - "mpp9"; - marvell,function = "uart1"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_dip_switches: pmx-dip-switches { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "gpio"; - }; - - pmx_gpio_header: pmx-gpio-header { - marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27", - "mpp28", "mpp29", "mpp30", "mpp31"; - marvell,function = "gpio"; - }; - - pmx_gpio_init: pmx-init { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_usb_oc: pmx-usb-oc { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp41", "mpp42", "mpp43"; - marvell,function = "gpio"; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-red { - label = "obsa6:red:stat"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - led-green { - label = "obsa6:green:stat"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - led-yellow { - label = "obsa6:yellow:stat"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_gpio_init>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x90000>; - }; - - partition@90000 { - label = "env"; - reg = <0x90000 0x44000>; - }; - - partition@d4000 { - label = "test"; - reg = <0xd4000 0x24000>; - }; - - partition@f4000 { - label = "conf"; - reg = <0xf4000 0x400000>; - }; - - partition@4f4000 { - label = "linux"; - reg = <0x4f4000 0x1d20000>; - }; - - partition@2214000 { - label = "user"; - reg = <0x2214000 0x1dec000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&gpio0 { - status = "okay"; - - pinctrl-0 = <&pmx_gpio_header>; - pinctrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-openblocks_a7.dts deleted file mode 100644 index 27cc913ca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Device Tree file for OpenBlocks A7 board - * - * Copyright (C) 2013 Free Electrons - * - * Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Plat'Home OpenBlocksA7"; - compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - sata@80000 { - nr-ports = <1>; - status = "okay"; - }; - - i2c@11100 { - status = "okay"; - - s24c02: s24c02@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header - &pmx_gpio_header_gpo>; - pinctrl-names = "default"; - - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11", "mpp15", - "mpp16"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14", "mpp8", - "mpp9"; - marvell,function = "uart1"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_dip_switches: pmx-dip-switches { - marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47"; - marvell,function = "gpio"; - }; - - /* - * Accessible on connector J202. The MPP - * listed below are pin 1-7, pin 8 is unused, - * pin 9 is external reset input and pin 10 is - * ground. - */ - pmx_gpio_header: pmx-gpio-header { - marvell,pins = "mpp17", "mpp29", "mpp28", - "mpp35", "mpp34", "mpp40"; - marvell,function = "gpio"; - }; - - pmx_gpio_header_gpo: pxm-gpio-header-gpo { - marvell,pins = "mpp7"; - marvell,function = "gpo"; - }; - - pmx_gpio_init: pmx-init { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_usb_oc: pmx-usb-oc { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp41", "mpp42", "mpp43"; - marvell,function = "gpio"; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-red { - label = "obsa7:red:stat"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - led-green { - label = "obsa7:green:stat"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - led-yellow { - label = "obsa7:yellow:stat"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_gpio_init>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - button { - label = "Init Button"; - linux,code = ; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x1c0000>; - }; - - partition@1c0000 { - label = "env"; - reg = <0x1c0000 0x2c0000>; - }; - - partition@480000 { - label = "test"; - reg = <0x480000 0x160000>; - }; - - partition@5e0000 { - label = "conf"; - reg = <0x5e0000 0x540000>; - }; - - partition@b20000 { - label = "linux"; - reg = <0xb20000 0x3d40000>; - }; - - partition@4860000 { - label = "user"; - reg = <0x4860000 0xb7a0000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-base.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-base.dts deleted file mode 100644 index 8af589996..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-base.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Marvell OpenRD Base Board Description - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions that are specific to OpenRD - * base variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Base"; - compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - serial@12100 { - status = "okay"; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-client.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-client.dts deleted file mode 100644 index 96ff59d68..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-client.dts +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Marvell OpenRD Client Board Description - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions that are specific to OpenRD - * client variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Client"; - compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - audio-controller@a0000 { - status = "okay"; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio0 0>; - }; - - simple-audio-card,codec { - sound-dai = <&cs42l51>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; - ethphy1: ethernet-phy@24 { - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts deleted file mode 100644 index 9f12f8b53..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Marvell OpenRD Ultimate Board Description - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions that are specific to OpenRD - * ultimate variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Ultimate"; - compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd.dtsi deleted file mode 100644 index 7175511a9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-openrd.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Marvell OpenRD (Base|Client|Ultimate) Board Description - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; - pinctrl-names = "default"; - - pmx_select28: pmx-select-rs232-rs485 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_select34: pmx-select-uart-sd { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - - }; - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - status = "okay"; - cd-gpios = <&gpio0 29 9>; - }; - gpio@10100 { - p28 { - gpio-hog; - gpios = <28 GPIO_ACTIVE_HIGH>; - /* - * SelRS232or485 selects between RS-232 or RS-485 - * mode for the second UART. - * - * Low: RS-232 - * High: RS-485 - * - * To use the second UART, you need to change also - * the SelUARTorSD. - */ - output-low; - line-name = "SelRS232or485"; - }; - }; - gpio@10140 { - p2 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - /* - * SelUARTorSD selects between the second UART - * (serial@12100) and SD (mvsdio@90000). - * - * Low: UART - * High: SD - * - * When changing this line make sure the newly - * selected device node is enabled and the - * previously selected device node is disabled. - */ - output-high; /* Select SD by default */ - line-name = "SelUARTorSD"; - }; - }; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@600000 { - label = "root"; - reg = <0x0600000 0x1FA00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-pogo_e02.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-pogo_e02.dts deleted file mode 100644 index a190080c9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-pogo_e02.dts +++ /dev/null @@ -1,134 +0,0 @@ -/* - * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 - * - * Copyright (C) 2015 Christoph Junghans - * - * based on information of dts files from - * Arch Linux ARM by Oleg Rakhmanov - * OpenWrt by Felix Kaechele - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Cloud Engines Pogoplug E02"; - compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - - health { - label = "pogo_e02:green:health"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "pogo_e02:orange:fault"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange - &pmx_led_green >; - pinctrl-names = "default"; - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0x5b00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts deleted file mode 100644 index b2f26239d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 - * inspired by the board files made by Kevin Mihelich for ArchLinux, - * and their DTS file. - * - * Copyright (C) 2015 Linus Walleij - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" -#include - -/ { - model = "Cloud Engines PogoPlug Series 4"; - compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - chosen { - stdout-path = "uart0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_eject>; - pinctrl-names = "default"; - - eject { - debounce_interval = <50>; - wakeup-source; - linux,code = ; - label = "Eject Button"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "pogoplugv4:green:health"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - fault { - label = "pogoplugv4:red:fault"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pinctrl { - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_eject: pmx-button-eject { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_red: pmx-led-red { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* - * This PCIE controller has a USB 3.0 XHCI controller at 1,0 - */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&sata { - status = "okay"; - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - nr-ports = <1>; -}; - -&sdio { - status = "okay"; - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; - pinctrl-names = "default"; - cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; -}; - -&nand { - /* 128 MiB of NAND flash */ - chip-delay = <40>; - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x200000>; - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x00200000 0x300000>; - }; - - partition@500000 { - label = "uImage2"; - reg = <0x00500000 0x300000>; - }; - - partition@800000 { - label = "failsafe"; - reg = <0x00800000 0x800000>; - }; - - partition@1000000 { - label = "root"; - reg = <0x01000000 0x7000000>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6192.dts deleted file mode 100644 index b8af90724..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Marvell RD88F6192 Board descrition - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "Marvell RD88F6192 reference design"; - compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; - }; - - serial@12000 { - status = "okay"; - - }; - - spi@10600 { - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts deleted file mode 100644 index 6f771a99c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Marvell RD88F6181 A Board descrition - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions for the board with the A0 or - * higher stepping of the SoC. The ethernet switch does not have a - * "wan" port. - */ - -/dts-v1/; -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with A0 or higher SoC"; - compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - - dsa { - switch@0 { - reg = <10 0>; /* MDIO address 10, switch 0 in tree */ - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð1 { - status = "okay"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts deleted file mode 100644 index 1a797381d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Marvell RD88F6181 Z0 stepping descrition - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions for the board using the Z0 - * stepping of the SoC. The ethernet switch has a "wan" port. -*/ - -/dts-v1/; - -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with Z0 SoC"; - compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - - dsa { - switch@0 { - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - port@4 { - reg = <4>; - label = "wan"; - }; - }; - }; -}; - -ð1 { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi deleted file mode 100644 index d5aacf137..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Marvell RD88F6181 Common Board descrition - * - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions that are common between the two - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - /* No WP GPIO */ - }; - }; - - dsa { - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x200000>; - }; - - partition@300000 { - label = "rootfs"; - reg = <0x0300000 0x500000>; - }; -}; - -&mdio { - status = "okay"; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs212.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs212.dts deleted file mode 100644 index 2c722ecd5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs212.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS212"; - compatible = "synology,rs212", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-3 { - status = "okay"; - }; - - gpio-leds-hdd-38 { - status = "okay"; - }; - - regulators-hdd-30-2 { - status = "okay"; - }; -}; - -&s35390a { - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs409.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs409.dts deleted file mode 100644 index 921ca49e8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs409.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS409"; - compatible = "synology,rs409", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-15-18 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs411.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs411.dts deleted file mode 100644 index 02852b0c8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-rs411.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology RS411 RS812"; - compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-100-15-35-3 { - status = "okay"; - }; - - gpio-leds-hdd-36 { - status = "okay"; - }; -}; - -ð1 { - status = "okay"; -}; - -&s35390a { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi deleted file mode 100644 index 7196c7f3e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs - * - * Copyright (C) 2013 Simon Baatz - * - * Licensed under GPLv2 - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x0500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts deleted file mode 100644 index e2b4ea4f9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts +++ /dev/null @@ -1,43 +0,0 @@ -/* - * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug - * - * Copyright (C) 2013 Simon Baatz - * - * Licensed under GPLv2 - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies eSATA SheevaPlug"; - compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; - pinctrl-names = "default"; - status = "okay"; - cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug.dts deleted file mode 100644 index 82f6abf12..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-sheevaplug.dts +++ /dev/null @@ -1,43 +0,0 @@ -/* - * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug - * - * Copyright (C) 2013 Simon Baatz - * - * Licensed under GPLv2 - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies SheevaPlug"; - compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - misc { - label = "sheevaplug:red:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-synology.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-synology.dtsi deleted file mode 100644 index 65e9524e8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-synology.dtsi +++ /dev/null @@ -1,857 +0,0 @@ -/* - * Nodes for Marvell 628x Synology devices - * - * Andrew Lunn - * Ben Peddell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_alarmled_12: pmx-alarmled-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_15: pmx-fanctrl-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_16: pmx-fanctrl-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_17: pmx-fanctrl-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_18: pmx-fanalarm-18 { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - - pmx_hddled_20: pmx-hddled-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_hddled_21: pmx-hddled-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_hddled_22: pmx-hddled-22 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_hddled_23: pmx-hddled-23 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_hddled_24: pmx-hddled-24 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_hddled_25: pmx-hddled-25 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_hddled_26: pmx-hddled-26 { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - pmx_hddled_27: pmx-hddled-27 { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_hddled_28: pmx-hddled-28 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_32: pmx-fanctrl-32 { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_33: pmx-fanctrl-33 { - marvell,pins = "mpp33"; - marvell,function = "gpo"; - }; - - pmx_fanctrl_34: pmx-fanctrl-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_35: pmx-fanalarm-35 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - pmx_hddled_36: pmx-hddled-36 { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_hddled_37: pmx-hddled-37 { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_hddled_38: pmx-hddled-38 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_hddled_39: pmx-hddled-39 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_hddled_40: pmx-hddled-40 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - pmx_hddled_41: pmx-hddled-41 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_hddled_42: pmx-hddled-42 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_hddled_43: pmx-hddled-43 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - pmx_hddled_44: pmx-hddled-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hddled_45: pmx-hddled-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_44: pmx-fanalarm-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_45: pmx-fanalarm-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - }; - - rtc@10300 { - status = "disabled"; - }; - - spi@10600 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@00000000 { - reg = <0x00000000 0x00080000>; - label = "RedBoot"; - }; - - partition@00080000 { - reg = <0x00080000 0x00200000>; - label = "zImage"; - }; - - partition@00280000 { - reg = <0x00280000 0x00140000>; - label = "rd.gz"; - }; - - partition@003c0000 { - reg = <0x003c0000 0x00010000>; - label = "vendor"; - }; - - partition@003d0000 { - reg = <0x003d0000 0x00020000>; - label = "RedBoot config"; - }; - - partition@003f0000 { - reg = <0x003f0000 0x00010000>; - label = "FIS directory"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - rs5c372: rs5c372@32 { - status = "disabled"; - compatible = "ricoh,rs5c372"; - reg = <0x32>; - }; - - s35390a: s35390a@30 { - status = "disabled"; - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&gate_clk 7>; - }; - - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-fan-150-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-150-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-100-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-1 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-3 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH - &gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-leds-alarm-12 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_alarmled_12>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:alarm"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-20 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 - &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 - &pmx_hddled_26 &pmx_hddled_27>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-1 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-2 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-36 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 - &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 - &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 - &pmx_hddled_45>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - - hdd5-green { - label = "synology:green:hdd5"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - - hdd5-amber { - label = "synology:amber:hdd5"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-38 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; - - regulators-hdd-29 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-1 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-2 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-4 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 - &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-31 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-34 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 - &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - reg = <9>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "disabled"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-t5325.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-t5325.dts deleted file mode 100644 index 3500f4738..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-t5325.dts +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Device Tree file for HP t5325 Thin Client" - * - * Copyright (C) 2014 - * - * Thomas Petazzoni - * Andrew Lunn - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "HP t5325 Thin Client"; - compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_i2s &pmx_sysrst>; - pinctrl-names = "default"; - - pmx_button_power: pmx-button_power { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_off: pmx-power-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_led: pmx-led { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_usb_sata_power_enable: pmx-usb-sata-power-enable { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_spi: pmx-spi { - marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; - marvell,function = "spi"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_i2s: pmx-i2s { - marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", - "mpp43"; - marvell,function = "audio"; - }; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - spi-max-frequency = <86000000>; - reg = <0>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - - partition@1 { - reg = <0x80000 0x40000>; - label = "SSD firmware"; - }; - - partition@2 { - reg = <0xc0000 0x10000>; - label = "u-boot env"; - }; - - partition@3 { - reg = <0xd0000 0x10000>; - label = "permanent u-boot env"; - }; - - partition@4 { - reg = <0xd0000 0x10000>; - label = "permanent u-boot env"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - - alc5621: alc5621@1a { - compatible = "realtek,alc5621"; - reg = <0x1a>; - #sound-dai-cells = <0>; - add-ctrl = <0x3700>; - jack-det-ctrl = <0x4810>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - audio: audio-controller@a0000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_sata_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB-SATA Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_power>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Speaker", "SPKOUT", - "Speaker", "SPKOUTN", - "MIC1", "Mic Jack", - "MIC2", "Mic Jack"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Speaker", "Speaker", - "Microphone", "Mic Jack"; - - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio>; - }; - - simple-audio-card,codec { - sound-dai = <&alc5621>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - device_type = "ethernet-phy"; - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-topkick.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-topkick.dts deleted file mode 100644 index 1e9a72100..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-topkick.dts +++ /dev/null @@ -1,215 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Univeral Scientific Industrial Co. Topkick-1281P2"; - compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - /* - * Switch positions - * - * /-SW_LEFT(2) - * | - * | /-SW_IDLE - * | | - * | | /-SW_RIGHT - * | | | - * PS [L] [I] [R] LEDS - */ - pinctrl-0 = <&pmx_sw_left &pmx_sw_right - &pmx_sw_idle &pmx_sw_left2>; - pinctrl-names = "default"; - - pmx_led_disk_yellow: pmx-led-disk-yellow { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_sata0_pwr_enable: pmx-sata0-pwr-enable { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_led_sys_red: pmx-led-sys-red { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_led_sys_blue: pmx-led-sys-blue { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_led_wifi_green: pmx-led-wifi-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_sw_left: pmx-sw-left { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - pmx_sw_right: pmx-sw-right { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_sw_idle: pmx-sw-idle { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_sw_left2: pmx-sw-left2 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_wifi_yellow: pmx-led-wifi-yellow { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - i2c@11000 { - status = "okay"; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - /* - * GPIO LED layout - * - * /-SYS_LED(2) - * | - * | /-DISK_LED - * | | - * | | /-WLAN_LED(2) - * | | | - * [SW] [*] [*] [*] - */ - - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red - &pmx_led_sys_blue &pmx_led_wifi_green - &pmx_led_wifi_yellow>; - pinctrl-names = "default"; - - disk { - label = "topkick:yellow:disk"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - system2 { - label = "topkick:red:system"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - system { - label = "topkick:blue:system"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - wifi { - label = "topkick:green:wifi"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "topkick:yellow:wifi"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_pwr_enable>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 4 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - }; - - partition@180000 { - label = "u-boot env"; - reg = <0x0180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "uInitrd"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "rootfs"; - reg = <0x1800000 0xe800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219-6281.dts deleted file mode 100644 index ee62204e4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ /dev/null @@ -1,55 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-ts219.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_ram_size &pmx_board_id>; - pinctrl-names = "default"; - - pmx_ram_size: pmx-ram-size { - /* RAM: 0: 256 MB, 1: 512 MB */ - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - pmx_board_id: pmx-board-id { - /* 0: TS-11x, 1: TS-21x */ - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219-6282.dts deleted file mode 100644 index 3437bb396..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ /dev/null @@ -1,57 +0,0 @@ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-ts219.dtsi" - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_ram_size &pmx_board_id>; - pinctrl-names = "default"; - - pmx_ram_size: pmx-ram-size { - /* RAM: 0: 256 MB, 1: 512 MB */ - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_board_id: pmx-board-id { - /* 0: TS-11x, 1: TS-21x */ - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ðphy0 { reg = <0>; }; - -&pcie1 { status = "okay"; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219.dtsi deleted file mode 100644 index 62e5e2d5c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/ { - model = "QNAP TS219 family"; - compatible = "qnap,ts219", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "s35390a"; - reg = <0x30>; - }; - }; - serial@12000 { - status = "okay"; - }; - serial@12100 { - status = "okay"; - }; - poweroff@12100 { - compatible = "qnap,power-off"; - reg = <0x12100 0x100>; - clocks = <&gate_clk 7>; - }; - spi@10600 { - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0000000 { - reg = <0x00000000 0x00080000>; - label = "U-Boot"; - }; - - partition@00200000 { - reg = <0x00200000 0x00200000>; - label = "Kernel"; - }; - - partition@00400000 { - reg = <0x00400000 0x00900000>; - label = "RootFS1"; - }; - partition@00d00000 { - reg = <0x00d00000 0x00300000>; - label = "RootFS2"; - }; - partition@00040000 { - reg = <0x00080000 0x00040000>; - label = "U-Boot Config"; - }; - partition@000c0000 { - reg = <0x000c0000 0x00140000>; - label = "NAS Config"; - }; - }; - }; - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419-6281.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419-6281.dts deleted file mode 100644 index aa22aa862..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419-6281.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Device Tree file for QNAP TS41X with 6281 SoC - * - * Copyright (C) 2013, Andrew Lunn - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-ts219.dtsi" -#include "kirkwood-ts419.dtsi" - -ðphy0 { reg = <8>; }; -ðphy1 { reg = <0>; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419-6282.dts deleted file mode 100644 index e3e71f48a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419-6282.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Device Tree file for QNAP TS41X with 6282 SoC - * - * Copyright (C) 2013, Andrew Lunn - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" -#include "kirkwood-ts219.dtsi" -#include "kirkwood-ts419.dtsi" - -ðphy0 { reg = <0>; }; -ðphy1 { reg = <1>; }; - -&pciec { status = "okay"; }; -&pcie1 { status = "okay"; }; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419.dtsi deleted file mode 100644 index 02bd53762..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood-ts419.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Device Tree include file for QNAP TS41X - * - * Copyright (C) 2013, Andrew Lunn - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/ { - model = "QNAP TS419 family"; - compatible = "qnap,ts419", "marvell,kirkwood"; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_USB_copy_button: pmx-USB-copy-button { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - /* - * JP1 indicates if an LCD module is installed - * on the serial port (0), or if the port is used - * as a console (1). - */ - pmx_jumper_jp1: pmx-jumper_jp1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = ; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - /* overwrite reg property in board file */ - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/kirkwood.dtsi b/software/linux/kernel/arch/arm/boot/dts/kirkwood.dtsi deleted file mode 100644 index 29b8bd7e0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/kirkwood.dtsi +++ /dev/null @@ -1,392 +0,0 @@ -/include/ "skeleton.dtsi" -#include -#include - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - compatible = "marvell,kirkwood"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,feroceon"; - reg = <0>; - clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; - clock-names = "cpu_clk", "ddrclk", "powersave"; - }; - }; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - i2c0 = &i2c0; - }; - - mbus@f1000000 { - compatible = "marvell,kirkwood-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - /* If a board file needs to change this ranges it must replace it completely */ - ranges = ; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ - pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - - nand: nand@012f { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - compatible = "marvell,orion-nand"; - reg = ; - chip-delay = <25>; - /* set partition map and/or chip-delay in board dts */ - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "disabled"; - }; - - crypto_sram: sa-sram@0301 { - compatible = "mmio-sram"; - reg = ; - clocks = <&gate_clk 17>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - ocp@f1000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x0100000>; - #address-cells = <1>; - #size-cells = <1>; - - pinctrl: pin-controller@10000 { - /* set compatible property in SoC file */ - reg = <0x10000 0x20>; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", "mpp27", - "mpp30", "mpp31", "mpp32", "mpp33"; - marvell,function = "ge1"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", "mpp19"; - marvell,function = "nand"; - }; - - /* - * Default SPI0 pinctrl setting with CSn on mpp0, - * overwrite marvell,pins on board level if required. - */ - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - - /* - * Default UART pinctrl setting without RTS/CTS, - * overwrite marvell,pins on board level if required. - */ - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,kirkwood-core-clock"; - reg = <0x10030 0x4>; - #clock-cells = <1>; - }; - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <23>; - reg = <0x10600 0x28>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <35>, <36>, <37>, <38>; - clocks = <&gate_clk 7>; - }; - - gpio1: gpio@10140 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10140 0x40>; - ngpios = <18>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <39>, <40>, <41>; - clocks = <&gate_clk 7>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <29>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x1500 0x20>; - }; - - sysc: system-controller@20000 { - compatible = "marvell,orion-system-controller"; - reg = <0x20000 0x120>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <1>; - marvell,#interrupts = <6>; - }; - - gate_clk: clock-gating-control@2011c { - compatible = "marvell,kirkwood-gating-clock"; - reg = <0x2011c 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - wdt: watchdog-timer@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&gate_clk 7>; - status = "okay"; - }; - - cesa: crypto@30000 { - compatible = "marvell,kirkwood-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <22>; - clocks = <&gate_clk 17>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - usb0: ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - clocks = <&gate_clk 3>; - status = "okay"; - }; - - dma0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - status = "okay"; - clocks = <&gate_clk 8>; - - xor00 { - interrupts = <5>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <6>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - dma1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60B00 0x100>; - status = "okay"; - clocks = <&gate_clk 16>; - - xor00 { - interrupts = <7>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <8>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - eth0: ethernet-controller@72000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 0>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - eth0port: ethernet0-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <11>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <46>; - clocks = <&gate_clk 0>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - - eth1: ethernet-controller@76000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76000 0x4000>; - clocks = <&gate_clk 19>; - marvell,tx-checksum-limit = <1600>; - pinctrl-0 = <&pmx_ge1>; - pinctrl-names = "default"; - status = "disabled"; - - eth1port: ethernet1-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <15>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - sata_phy0: sata-phy@82000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x82000 0x0334>; - clocks = <&gate_clk 14>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - sata_phy1: sata-phy@84000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x84000 0x0334>; - clocks = <&gate_clk 15>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - audio0: audio-controller@a0000 { - compatible = "marvell,kirkwood-audio"; - #sound-dai-cells = <1>; - reg = <0xa0000 0x2210>; - interrupts = <24>; - clocks = <&gate_clk 9>; - clock-names = "internal"; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/software/linux/kernel/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts deleted file mode 100644 index 2fa5eb4bd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts +++ /dev/null @@ -1,264 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "logicpd-som-lv.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - - sysboot2 { - label = "gpio3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &led_pins_wkup>; - - led1 { - label = "led1"; - gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ - linux,default-trigger = "none"; - }; - }; -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ - reg = <1 0 0xff>; - }; -}; - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&video_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - video_reg: video_reg { - compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lcd0: display@0 { - compatible = "panel-dpi"; - label = "28"; - status = "okay"; - /* default-on; */ - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_pin>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <2>; - vsync-len = <11>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&twl_pwm 0 5000000>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ - >; - }; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ - >; - }; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ - >; - }; - - lcd_enable_pin: pinmux_lcd_enable_pin { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - >; - }; -}; - -&omap3_pmx_wkup { - led_pins_wkup: pinmux_led_pins_wkup { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ - >; - }; -}; - - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/logicpd-som-lv.dtsi b/software/linux/kernel/arch/arm/boot/dts/logicpd-som-lv.dtsi deleted file mode 100644 index 4f2c5ec75..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ /dev/null @@ -1,275 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 3 0>; /* gpio_3 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f4g16abbda3w"; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - /* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */ - - x-loader@0 { - label = "x-loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "u-boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "u-boot-env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "fs"; - reg = <0x680000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; - pinctrl-0 = <&mmc3_pins &wl127x_gpio>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1273"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */ - ref-clock-frequency = <26000000>; - }; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; - - mmc3_pins: pinmux_mm3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ - >; - }; - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ - >; - }; - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - hsusb_otg_pins: pinmux_hsusb_otg_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - - -}; - -&omap3_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_reset_pin>; - hsusb2_reset_pin: pinmux_hsusb1_reset_pin { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ - >; - }; - wl127x_gpio: pinmux_wl127x_gpio_pin { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,use-leds; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/software/linux/kernel/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts deleted file mode 100644 index b4575bbaf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ /dev/null @@ -1,404 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "logicpd-torpedo-som.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit"; - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; - - sysboot2 { - label = "sysboot2"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ - linux,code = ; - wakeup-source; - }; - - sysboot5 { - label = "sysboot5"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ - linux,code = ; - wakeup-source; - }; - - gpio1 { - label = "gpio1"; - gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ - linux,code = ; - wakeup-source; - }; - - gpio2 { - label = "gpio2"; - gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - label = "led1"; - gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ - linux,default-trigger = "none"; - }; - }; - - pwm10: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - ti,timers = <&timer10>; - #pwm-cells = <3>; - }; - -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ - reg = <1 0 0xff>; - }; -}; - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&video_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - video_reg: video_reg { - pinctrl-names = "default"; - pinctrl-0 = <&panel_pwr_pins>; - compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ - }; - - lcd0: display { - compatible = "panel-dpi"; - label = "15"; - status = "okay"; - /* default-on; */ - pinctrl-names = "default"; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <4>; - vsync-len = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&pwm10 0 5000000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1_cd>; - cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ - >; - }; - - pwm_pins: pinmux_pwm_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ - >; - }; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ - >; - }; - - isp_pins: pinmux_isp_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ - - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ - >; - }; - - panel_pwr_pins: pinmux_panel_pwr_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; -}; - -&omap3_pmx_wkup { - gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ - >; - }; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ - >; - }; - - mmc1_cd: pinmux_mmc1_cd { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ - >; - }; -}; - -&i2c2 { - mt9p031@48 { - compatible = "aptina,mt9p031"; - reg = <0x48>; - clocks = <&isp 0>; - vaa-supply = <&vaux4>; - vdd-supply = <&vaux4>; - vdd_io-supply = <&vaux4>; - port { - mt9p031_out: endpoint { - input-clock-frequency = <24000000>; - pixel-clock-frequency = <72000000>; - remote-endpoint = <&ccdc_ep>; - }; - }; - }; -}; - -&i2c3 { - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vaux1>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mcspi1 { - at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; -}; - -&isp { - pinctrl-names = "default"; - pinctrl-0 = <&isp_pins>; - ports { - port@0 { - reg = <0>; - ccdc_ep: endpoint { - remote-endpoint = <&mt9p031_out>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/software/linux/kernel/arch/arm/boot/dts/logicpd-torpedo-som.dtsi deleted file mode 100644 index efe53998c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - leds { - compatible = "gpio-leds"; - user0 { - label = "user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - linux,default-trigger = "none"; - }; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 29 0>; /* gpio157 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f4g16abbda3w"; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - /* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */ - - x-loader@0 { - label = "x-loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "u-boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "u-boot-env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "fs"; - reg = <0x680000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - at24@50 { - compatible = "atmel,24c64"; - readonly; - reg = <0x50>; - }; -}; - -/* - * Only found on the wireless SOM. For the SOM without wireless, the pins for - * MMC3 can be routed with jumpers to the second MMC slot on the devkit and - * gpio157 is not connected. So this should be OK to keep common for now, - * probably device tree overlays is the way to go with the various SOM and - * jumpering combinations for the long run. - */ -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; - pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1283"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&omap3_pmx_core { - mmc3_pins: pinmux_mm3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ - >; - }; - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ - >; - }; - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -&omap3_pmx_core2 { - mmc3_core2_pins: pinmux_mmc3_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - >; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,use-leds; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc18xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/lpc18xx.dtsi deleted file mode 100644 index 7cae9c5e2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc18xx.dtsi +++ /dev/null @@ -1,538 +0,0 @@ -/* - * Common base for NXP LPC18xx and LPC43xx devices. - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -#include "armv7-m.dtsi" - -#include "dt-bindings/clock/lpc18xx-cgu.h" -#include "dt-bindings/clock/lpc18xx-ccu.h" - -#define LPC_PIN(port, pin) (0x##port * 32 + pin) -#define LPC_GPIO(port, pin) (port * 32 + pin) - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-m3"; - device_type = "cpu"; - reg = <0x0>; - clocks = <&ccu1 CLK_CPU_CORE>; - }; - }; - - clocks { - xtal: xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - xtal32: xtal32 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - enet_rx_clk: enet_rx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "enet_rx_clk"; - }; - - enet_tx_clk: enet_tx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "enet_tx_clk"; - }; - - gp_clkin: gp_clkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "gp_clkin"; - }; - }; - - soc { - sct_pwm: pwm@40000000 { - compatible = "nxp,lpc1850-sct-pwm"; - reg = <0x40000000 0x1000>; - clocks =<&ccu1 CLK_CPU_SCT>; - clock-names = "pwm"; - resets = <&rgu 37>; - #pwm-cells = <3>; - status = "disabled"; - }; - - dmac: dma-controller@40002000 { - compatible = "arm,pl080", "arm,primecell"; - arm,primecell-periphid = <0x00041080>; - reg = <0x40002000 0x1000>; - interrupts = <2>; - clocks = <&ccu1 CLK_CPU_DMA>; - clock-names = "apb_pclk"; - resets = <&rgu 19>; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <16>; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb1; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - }; - - spifi: flash-controller@40003000 { - compatible = "nxp,lpc1773-spifi"; - reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; - reg-names = "spifi", "flash"; - interrupts = <30>; - clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; - clock-names = "spifi", "reg"; - resets = <&rgu 53>; - status = "disabled"; - }; - - mmcsd: mmcsd@40004000 { - compatible = "snps,dw-mshc"; - reg = <0x40004000 0x1000>; - interrupts = <6>; - num-slots = <1>; - clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; - clock-names = "ciu", "biu"; - resets = <&rgu 20>; - status = "disabled"; - }; - - usb0: ehci@40006100 { - compatible = "nxp,lpc1850-ehci", "generic-ehci"; - reg = <0x40006100 0x100>; - interrupts = <8>; - clocks = <&ccu1 CLK_CPU_USB0>; - resets = <&rgu 17>; - phys = <&usb0_otg_phy>; - phy-names = "usb"; - has-transaction-translator; - status = "disabled"; - }; - - usb1: ehci@40007100 { - compatible = "nxp,lpc1850-ehci", "generic-ehci"; - reg = <0x40007100 0x100>; - interrupts = <9>; - clocks = <&ccu1 CLK_CPU_USB1>; - resets = <&rgu 18>; - status = "disabled"; - }; - - emc: memory-controller@40005000 { - compatible = "arm,pl172", "arm,primecell"; - reg = <0x40005000 0x1000>; - clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; - clock-names = "mpmcclk", "apb_pclk"; - resets = <&rgu 21>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x1c000000 0x1000000 - 1 0 0x1d000000 0x1000000 - 2 0 0x1e000000 0x1000000 - 3 0 0x1f000000 0x1000000>; - status = "disabled"; - }; - - lcdc: lcd-controller@40008000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x40008000 0x1000>; - interrupts = <7>; - interrupt-names = "combined"; - clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; - clock-names = "clcdclk", "apb_pclk"; - resets = <&rgu 16>; - status = "disabled"; - }; - - eeprom: eeprom@4000e000 { - compatible = "nxp,lpc1857-eeprom"; - reg = <0x4000e000 0x1000>, <0x20040000 0x4000>; - reg-names = "reg", "mem"; - clocks = <&ccu1 CLK_CPU_EEPROM>; - clock-names = "eeprom"; - resets = <&rgu 27>; - interrupts = <4>; - status = "disabled"; - }; - - mac: ethernet@40010000 { - compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; - reg = <0x40010000 0x2000>; - interrupts = <5>; - interrupt-names = "macirq"; - clocks = <&ccu1 CLK_CPU_ETHERNET>; - clock-names = "stmmaceth"; - resets = <&rgu 22>; - reset-names = "stmmaceth"; - rx-fifo-depth = <256>; - tx-fifo-depth = <256>; - snps,pbl = <4>; /* 32 (8x mode) */ - snps,force_thresh_dma_mode; - status = "disabled"; - }; - - creg: syscon@40043000 { - compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; - reg = <0x40043000 0x1000>; - clocks = <&ccu1 CLK_CPU_CREG>; - resets = <&rgu 5>; - - creg_clk: clock-controller { - compatible = "nxp,lpc1850-creg-clk"; - clocks = <&xtal32>; - #clock-cells = <1>; - }; - - usb0_otg_phy: phy { - compatible = "nxp,lpc1850-usb-otg-phy"; - clocks = <&ccu1 CLK_USB0>; - #phy-cells = <0>; - }; - - dmamux: dma-mux { - compatible = "nxp,lpc1850-dmamux"; - #dma-cells = <3>; - dma-requests = <64>; - dma-masters = <&dmac>; - }; - }; - - rtc: rtc@40046000 { - compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc"; - reg = <0x40046000 0x1000>; - interrupts = <47>; - clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; - clock-names = "rtc", "reg"; - }; - - cgu: clock-controller@40050000 { - compatible = "nxp,lpc1850-cgu"; - reg = <0x40050000 0x1000>; - #clock-cells = <1>; - clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; - }; - - ccu1: clock-controller@40051000 { - compatible = "nxp,lpc1850-ccu"; - reg = <0x40051000 0x1000>; - #clock-cells = <1>; - clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, - <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, - <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, - <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; - clock-names = "base_apb3_clk", "base_apb1_clk", - "base_spifi_clk", "base_cpu_clk", - "base_periph_clk", "base_usb0_clk", - "base_usb1_clk", "base_spi_clk"; - }; - - ccu2: clock-controller@40052000 { - compatible = "nxp,lpc1850-ccu"; - reg = <0x40052000 0x1000>; - #clock-cells = <1>; - clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, - <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, - <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, - <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; - clock-names = "base_audio_clk", "base_uart3_clk", - "base_uart2_clk", "base_uart1_clk", - "base_uart0_clk", "base_ssp1_clk", - "base_ssp0_clk", "base_sdio_clk"; - }; - - rgu: reset-controller@40053000 { - compatible = "nxp,lpc1850-rgu"; - reg = <0x40053000 0x1000>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; - clock-names = "delay", "reg"; - #reset-cells = <1>; - }; - - watchdog@40080000 { - compatible = "nxp,lpc1850-wwdt"; - reg = <0x40080000 0x24>; - interrupts = <49>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; - clock-names = "wdtclk", "reg"; - }; - - uart0: serial@40081000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x40081000 0x1000>; - reg-shift = <2>; - interrupts = <24>; - clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; - clock-names = "uartclk", "reg"; - resets = <&rgu 44>; - dmas = <&dmamux 1 1 2 - &dmamux 2 1 2 - &dmamux 11 2 2 - &dmamux 12 2 2>; - dma-names = "tx", "rx", "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@40082000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x40082000 0x1000>; - reg-shift = <2>; - interrupts = <25>; - clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; - clock-names = "uartclk", "reg"; - resets = <&rgu 45>; - dmas = <&dmamux 3 1 2 - &dmamux 4 1 2>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - ssp0: spi@40083000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x40083000 0x1000>; - interrupts = <22>; - clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; - clock-names = "sspclk", "apb_pclk"; - resets = <&rgu 50>; - dmas = <&dmamux 9 0 2 - &dmamux 10 0 2>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer0: timer@40084000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40084000 0x1000>; - interrupts = <12>; - clocks = <&ccu1 CLK_CPU_TIMER0>; - clock-names = "timerclk"; - resets = <&rgu 32>; - }; - - timer1: timer@40085000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40085000 0x1000>; - interrupts = <13>; - clocks = <&ccu1 CLK_CPU_TIMER1>; - clock-names = "timerclk"; - resets = <&rgu 33>; - }; - - pinctrl: pinctrl@40086000 { - compatible = "nxp,lpc1850-scu"; - reg = <0x40086000 0x1000>; - clocks = <&ccu1 CLK_CPU_SCU>; - }; - - i2c0: i2c@400a1000 { - compatible = "nxp,lpc1788-i2c"; - reg = <0x400a1000 0x1000>; - interrupts = <18>; - clocks = <&ccu1 CLK_APB1_I2C0>; - resets = <&rgu 48>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can1: can@400a4000 { - compatible = "bosch,c_can"; - reg = <0x400a4000 0x1000>; - interrupts = <43>; - clocks = <&ccu1 CLK_APB1_CAN1>; - resets = <&rgu 54>; - status = "disabled"; - }; - - uart2: serial@400c1000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x400c1000 0x1000>; - reg-shift = <2>; - interrupts = <26>; - clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; - clock-names = "uartclk", "reg"; - resets = <&rgu 46>; - dmas = <&dmamux 5 1 2 - &dmamux 6 1 2>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@400c2000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x400c2000 0x1000>; - reg-shift = <2>; - interrupts = <27>; - clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; - clock-names = "uartclk", "reg"; - resets = <&rgu 47>; - dmas = <&dmamux 7 1 2 - &dmamux 8 1 2 - &dmamux 13 3 2 - &dmamux 14 3 2>; - dma-names = "tx", "rx", "rx", "tx"; - status = "disabled"; - }; - - timer2: timer@400c3000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x400c3000 0x1000>; - interrupts = <14>; - clocks = <&ccu1 CLK_CPU_TIMER2>; - clock-names = "timerclk"; - resets = <&rgu 34>; - }; - - timer3: timer@400c4000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x400c4000 0x1000>; - interrupts = <15>; - clocks = <&ccu1 CLK_CPU_TIMER3>; - clock-names = "timerclk"; - resets = <&rgu 35>; - }; - - ssp1: spi@400c5000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x400c5000 0x1000>; - interrupts = <23>; - clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; - clock-names = "sspclk", "apb_pclk"; - resets = <&rgu 51>; - dmas = <&dmamux 11 2 2 - &dmamux 12 2 2 - &dmamux 3 3 2 - &dmamux 4 3 2 - &dmamux 5 2 2 - &dmamux 6 2 2 - &dmamux 13 2 2 - &dmamux 14 2 2>; - dma-names = "rx", "tx", "tx", "rx", - "tx", "rx", "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@400e0000 { - compatible = "nxp,lpc1788-i2c"; - reg = <0x400e0000 0x1000>; - interrupts = <19>; - clocks = <&ccu1 CLK_APB3_I2C1>; - resets = <&rgu 49>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dac: dac@400e1000 { - compatible = "nxp,lpc1850-dac"; - reg = <0x400e1000 0x1000>; - interrupts = <0>; - clocks = <&ccu1 CLK_APB3_DAC>; - resets = <&rgu 42>; - status = "disabled"; - }; - - can0: can@400e2000 { - compatible = "bosch,c_can"; - reg = <0x400e2000 0x1000>; - interrupts = <51>; - clocks = <&ccu1 CLK_APB3_CAN0>; - resets = <&rgu 55>; - status = "disabled"; - }; - - adc0: adc@400e3000 { - compatible = "nxp,lpc1850-adc"; - reg = <0x400e3000 0x1000>; - interrupts = <17>; - clocks = <&ccu1 CLK_APB3_ADC0>; - resets = <&rgu 40>; - status = "disabled"; - }; - - adc1: adc@400e4000 { - compatible = "nxp,lpc1850-adc"; - reg = <0x400e4000 0x1000>; - interrupts = <21>; - clocks = <&ccu1 CLK_APB3_ADC1>; - resets = <&rgu 41>; - status = "disabled"; - }; - - gpio: gpio@400f4000 { - compatible = "nxp,lpc1850-gpio"; - reg = <0x400f4000 0x4000>; - clocks = <&ccu1 CLK_CPU_GPIO>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, - <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, - <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, - <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, - <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, - <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, - <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, - <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, - <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, - <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, - <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, - <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, - <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, - <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, - <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, - <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, - <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, - <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, - <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, - <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, - <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, - <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, - <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, - <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, - <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, - <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, - <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, - <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, - <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, - <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, - <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, - <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, - <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, - <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, - <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, - <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, - <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, - <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, - <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, - <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc3250-ea3250.dts b/software/linux/kernel/arch/arm/boot/dts/lpc3250-ea3250.dts deleted file mode 100644 index e2bc73107..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc3250-ea3250.dts +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Embedded Artists LPC3250 board - * - * Copyright 2012 Roland Stigge - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "Embedded Artists LPC3250 board based on NXP LPC3250"; - compatible = "ea,ea3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@21 { - label = "Interrupt Key"; - linux,code = <103>; - gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ - }; - key1 { - label = "KEY1"; - linux,code = <1>; - gpios = <&pca9532 0 0>; - }; - key2 { - label = "KEY2"; - linux,code = <2>; - gpios = <&pca9532 1 0>; - }; - key3 { - label = "KEY3"; - linux,code = <3>; - gpios = <&pca9532 2 0>; - }; - key4 { - label = "KEY4"; - linux,code = <4>; - gpios = <&pca9532 3 0>; - }; - joy0 { - label = "Joystick Key 0"; - linux,code = <10>; - gpios = <&gpio 2 0 0>; /* P2.0 */ - }; - joy1 { - label = "Joystick Key 1"; - linux,code = <11>; - gpios = <&gpio 2 1 0>; /* P2.1 */ - }; - joy2 { - label = "Joystick Key 2"; - linux,code = <12>; - gpios = <&gpio 2 2 0>; /* P2.2 */ - }; - joy3 { - label = "Joystick Key 3"; - linux,code = <13>; - gpios = <&gpio 2 3 0>; /* P2.3 */ - }; - joy4 { - label = "Joystick Key 4"; - linux,code = <14>; - gpios = <&gpio 2 4 0>; /* P2.4 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - /* LEDs on OEM Board */ - - led1 { - gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ - linux,default-trigger = "timer"; - default-state = "off"; - }; - - led2 { - gpios = <&gpio 2 10 1>; /* P2.10, active low */ - default-state = "off"; - }; - - led3 { - gpios = <&gpio 2 11 1>; /* P2.11, active low */ - default-state = "off"; - }; - - led4 { - gpios = <&gpio 2 12 1>; /* P2.12, active low */ - default-state = "off"; - }; - - /* LEDs on Base Board */ - - lede1 { - gpios = <&pca9532 8 0>; - default-state = "off"; - }; - lede2 { - gpios = <&pca9532 9 0>; - default-state = "off"; - }; - lede3 { - gpios = <&pca9532 10 0>; - default-state = "off"; - }; - lede4 { - gpios = <&pca9532 11 0>; - default-state = "off"; - }; - lede5 { - gpios = <&pca9532 12 0>; - default-state = "off"; - }; - lede6 { - gpios = <&pca9532 13 0>; - default-state = "off"; - }; - lede7 { - gpios = <&pca9532 14 0>; - default-state = "off"; - }; - lede8 { - gpios = <&pca9532 15 0>; - default-state = "off"; - }; - }; -}; - -/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ -&adc { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 3 10 0>; - reset-gpio = <&gpio 3 2 0>; - dac-clk = "wspll"; - }; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x60>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2d { - compatible = "nxp,isp1301"; - reg = <0x2d>; - }; -}; - -&mac { - phy-mode = "rmii"; - use-iram; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&sd { - wp-gpios = <&pca9532 5 0>; - cd-gpios = <&pca9532 4 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; -}; - -/* 128MB Flash via SLC NAND controller */ -&slc { - status = "okay"; - - nxp,wdr-clks = <14>; - nxp,wwidth = <260000000>; - nxp,whold = <104000000>; - nxp,wsetup = <200000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <34666666>; - nxp,rhold = <104000000>; - nxp,rsetup = <200000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - mtd0@00000000 { - label = "ea3250-boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - mtd1@00080000 { - label = "ea3250-uboot"; - reg = <0x00080000 0x000c0000>; - read-only; - }; - - mtd2@00140000 { - label = "ea3250-kernel"; - reg = <0x00140000 0x00400000>; - }; - - mtd3@00540000 { - label = "ea3250-rootfs"; - reg = <0x00540000 0x07ac0000>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&uart6 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc3250-phy3250.dts b/software/linux/kernel/arch/arm/boot/dts/lpc3250-phy3250.dts deleted file mode 100644 index b7bd3a110..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc3250-phy3250.dts +++ /dev/null @@ -1,226 +0,0 @@ -/* - * PHYTEC phyCORE-LPC3250 board - * - * Copyright 2012 Roland Stigge - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; - compatible = "phytec,phy3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - regulators { - backlight_reg: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "backlight_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 4 0>; - enable-active-high; - regulator-boot-on; - }; - - lcd_reg: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "lcd_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 0 0>; - enable-active-high; - regulator-boot-on; - }; - - sd_reg: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "sd_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 5 0>; - enable-active-high; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { /* red */ - gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ - default-state = "off"; - }; - - led1 { /* green */ - gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&clcd { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 3 10 0>; - reset-gpio = <&gpio 3 2 0>; - dac-clk = "wspll"; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; -}; - -&key { - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - status = "okay"; -}; - -&mac { - phy-mode = "rmii"; - use-iram; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&sd { - wp-gpios = <&gpio 3 0 0>; - cd-gpios = <&gpio 3 1 0>; - cd-inverted; - bus-width = <4>; - vmmc-supply = <&sd_reg>; - status = "okay"; -}; - -/* 64MB Flash via SLC NAND controller */ -&slc { - status = "okay"; - - nxp,wdr-clks = <14>; - nxp,wwidth = <40000000>; - nxp,whold = <100000000>; - nxp,wsetup = <100000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <40000000>; - nxp,rhold = <66666666>; - nxp,rsetup = <100000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - mtd0@00000000 { - label = "phy3250-boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; - - mtd1@00064000 { - label = "phy3250-uboot"; - reg = <0x00064000 0x00190000>; - read-only; - }; - - mtd2@001f4000 { - label = "phy3250-ubt-prms"; - reg = <0x001f4000 0x00010000>; - }; - - mtd3@00204000 { - label = "phy3250-kernel"; - reg = <0x00204000 0x00400000>; - }; - - mtd4@00604000 { - label = "phy3250-rootfs"; - reg = <0x00604000 0x039fc000>; - }; - }; -}; - -&ssp0 { - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - cs-gpios = <&gpio 3 5 0>; - status = "okay"; - - eeprom: at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - - pl022,interface = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - }; -}; - -&tsc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc32xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/lpc32xx.dtsi deleted file mode 100644 index b5841fab5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc32xx.dtsi +++ /dev/null @@ -1,502 +0,0 @@ -/* - * NXP LPC32xx SoC - * - * Copyright 2012 Roland Stigge - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" - -#include -#include - -/ { - compatible = "nxp,lpc3220"; - interrupt-parent = <&mic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0x0>; - }; - }; - - clocks { - xtal_32k: xtal_32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xtal_32k"; - }; - - xtal: xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <13000000>; - clock-output-names = "xtal"; - }; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x00000000 0x00000000 0x10000000>, - <0x20000000 0x20000000 0x30000000>, - <0xe0000000 0xe0000000 0x04000000>; - - iram: sram@08000000 { - compatible = "mmio-sram"; - reg = <0x08000000 0x20000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x08000000 0x20000>; - }; - - /* - * Enable either SLC or MLC - */ - slc: flash@20020000 { - compatible = "nxp,lpc3220-slc"; - reg = <0x20020000 0x1000>; - clocks = <&clk LPC32XX_CLK_SLC>; - status = "disabled"; - }; - - mlc: flash@200a8000 { - compatible = "nxp,lpc3220-mlc"; - reg = <0x200a8000 0x11000>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_MLC>; - status = "disabled"; - }; - - dma: dma@31000000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x31000000 0x1000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_DMA>; - clock-names = "apb_pclk"; - }; - - usb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x31020000 0x00001000>; - - /* - * Enable either ohci or usbd (gadget)! - */ - ohci: ohci@0 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_HOST>; - status = "disabled"; - }; - - usbd: usbd@0 { - compatible = "nxp,lpc3220-udc"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, - <30 IRQ_TYPE_LEVEL_HIGH>, - <28 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_LOW>; - clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; - status = "disabled"; - }; - - i2cusb: i2c@300 { - compatible = "nxp,pnx-i2c"; - reg = <0x300 0x100>; - interrupt-parent = <&sic1>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_I2C>; - #address-cells = <1>; - #size-cells = <0>; - pnx,timeout = <0x64>; - }; - - usbclk: clock-controller@f00 { - compatible = "nxp,lpc3220-usb-clk"; - reg = <0xf00 0x100>; - #clock-cells = <1>; - }; - }; - - clcd: clcd@31040000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x31040000 0x1000>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_LCD>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - mac: ethernet@31060000 { - compatible = "nxp,lpc-eth"; - reg = <0x31060000 0x1000>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_MAC>; - }; - - emc: memory-controller@31080000 { - compatible = "arm,pl175", "arm,primecell"; - reg = <0x31080000 0x1000>; - clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; - clock-names = "mpmcclk", "apb_pclk"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe0000000 0x01000000>, - <1 0xe1000000 0x01000000>, - <2 0xe2000000 0x01000000>, - <3 0xe3000000 0x01000000>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>; - - /* - * ssp0 and spi1 are shared pins; - * enable one in your board dts, as needed. - */ - ssp0: ssp@20084000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x20084000 0x1000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP0>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - spi1: spi@20088000 { - compatible = "nxp,lpc3220-spi"; - reg = <0x20088000 0x1000>; - clocks = <&clk LPC32XX_CLK_SPI1>; - status = "disabled"; - }; - - /* - * ssp1 and spi2 are shared pins; - * enable one in your board dts, as needed. - */ - ssp1: ssp@2008c000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x2008c000 0x1000>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - spi2: spi@20090000 { - compatible = "nxp,lpc3220-spi"; - reg = <0x20090000 0x1000>; - clocks = <&clk LPC32XX_CLK_SPI2>; - status = "disabled"; - }; - - i2s0: i2s@20094000 { - compatible = "nxp,lpc3220-i2s"; - reg = <0x20094000 0x1000>; - }; - - sd: sd@20098000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x20098000 0x1000>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SD>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2s1: i2s@2009C000 { - compatible = "nxp,lpc3220-i2s"; - reg = <0x2009C000 0x1000>; - }; - - /* UART5 first since it is the default console, ttyS0 */ - uart5: serial@40090000 { - /* actually, ns16550a w/ 64 byte fifos! */ - compatible = "nxp,lpc3220-uart"; - reg = <0x40090000 0x1000>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART5>; - status = "disabled"; - }; - - uart3: serial@40080000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40080000 0x1000>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART3>; - status = "disabled"; - }; - - uart4: serial@40088000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40088000 0x1000>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART4>; - status = "disabled"; - }; - - uart6: serial@40098000 { - compatible = "nxp,lpc3220-uart"; - reg = <0x40098000 0x1000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - clocks = <&clk LPC32XX_CLK_UART6>; - status = "disabled"; - }; - - i2c1: i2c@400A0000 { - compatible = "nxp,pnx-i2c"; - reg = <0x400A0000 0x100>; - interrupt-parent = <&sic1>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - #address-cells = <1>; - #size-cells = <0>; - pnx,timeout = <0x64>; - clocks = <&clk LPC32XX_CLK_I2C1>; - }; - - i2c2: i2c@400A8000 { - compatible = "nxp,pnx-i2c"; - reg = <0x400A8000 0x100>; - interrupt-parent = <&sic1>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - #address-cells = <1>; - #size-cells = <0>; - pnx,timeout = <0x64>; - clocks = <&clk LPC32XX_CLK_I2C2>; - }; - - mpwm: mpwm@400E8000 { - compatible = "nxp,lpc3220-motor-pwm"; - reg = <0x400E8000 0x78>; - status = "disabled"; - #pwm-cells = <2>; - }; - }; - - fab { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x20000000 0x20000000 0x30000000>; - - /* System Control Block */ - scb { - compatible = "simple-bus"; - ranges = <0x0 0x040004000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - clk: clock-controller@0 { - compatible = "nxp,lpc3220-clk"; - reg = <0x00 0x114>; - #clock-cells = <1>; - - clocks = <&xtal_32k>, <&xtal>; - clock-names = "xtal_32k", "xtal"; - - assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; - assigned-clock-rates = <208000000>; - }; - }; - - mic: interrupt-controller@40008000 { - compatible = "nxp,lpc3220-mic"; - reg = <0x40008000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sic1: interrupt-controller@4000c000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x4000c000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>, - <30 IRQ_TYPE_LEVEL_LOW>; - }; - - sic2: interrupt-controller@40010000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x40010000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - }; - - uart1: serial@40014000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40014000 0x1000>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart2: serial@40018000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40018000 0x1000>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart7: serial@4001c000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x4001c000 0x1000>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - rtc: rtc@40024000 { - compatible = "nxp,lpc3220-rtc"; - reg = <0x40024000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_RTC>; - }; - - gpio: gpio@40028000 { - compatible = "nxp,lpc3220-gpio"; - reg = <0x40028000 0x1000>; - gpio-controller; - #gpio-cells = <3>; /* bank, pin, flags */ - }; - - timer4: timer@4002C000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x4002C000 0x1000>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER4>; - clock-names = "timerclk"; - status = "disabled"; - }; - - timer5: timer@40030000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40030000 0x1000>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER5>; - clock-names = "timerclk"; - status = "disabled"; - }; - - watchdog: watchdog@4003C000 { - compatible = "nxp,pnx4008-wdt"; - reg = <0x4003C000 0x1000>; - clocks = <&clk LPC32XX_CLK_WDOG>; - }; - - timer0: timer@40044000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40044000 0x1000>; - clocks = <&clk LPC32XX_CLK_TIMER0>; - clock-names = "timerclk"; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; - - /* - * TSC vs. ADC: Since those two share the same - * hardware, you need to choose from one of the - * following two and do 'status = "okay";' for one of - * them - */ - - adc: adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_ADC>; - status = "disabled"; - }; - - tsc: tsc@40048000 { - compatible = "nxp,lpc3220-tsc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_ADC>; - status = "disabled"; - }; - - timer1: timer@4004C000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x4004C000 0x1000>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER1>; - clock-names = "timerclk"; - }; - - key: key@40050000 { - compatible = "nxp,lpc3220-key"; - reg = <0x40050000 0x1000>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer2: timer@40058000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40058000 0x1000>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER2>; - clock-names = "timerclk"; - status = "disabled"; - }; - - pwm1: pwm@4005C000 { - compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C000 0x4>; - clocks = <&clk LPC32XX_CLK_PWM1>; - status = "disabled"; - }; - - pwm2: pwm@4005C004 { - compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C004 0x4>; - clocks = <&clk LPC32XX_CLK_PWM2>; - status = "disabled"; - }; - - timer3: timer@40060000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40060000 0x1000>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk LPC32XX_CLK_TIMER3>; - clock-names = "timerclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc4337-ciaa.dts b/software/linux/kernel/arch/arm/boot/dts/lpc4337-ciaa.dts deleted file mode 100644 index 7c16d639a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc4337-ciaa.dts +++ /dev/null @@ -1,221 +0,0 @@ -/* - * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar) - * - * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4357.dtsi" - -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "CIAA NXP LPC4337"; - compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350"; - - aliases { - serial0 = &uart2; - serial1 = &uart3; - }; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = &uart2; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x0800000>; /* 8 MB */ - }; -}; - -&pinctrl { - enet_rmii_pins: enet-rmii-pins { - enet_rmii_rxd_cfg { - pins = "p1_15", "p0_0"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_txd_cfg { - pins = "p1_18", "p1_20"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_rx_dv_cfg { - pins = "p1_16"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_tx_en_cfg { - pins = "p0_1"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_ref_clk_cfg { - pins = "p1_19"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdc_cfg { - pins = "p7_7"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - ssp_pins: ssp-pins { - ssp1_cs { - pins = "p6_7"; - function = "gpio"; - bias-pull-up; - bias-disable; - }; - - ssp1_miso_mosi { - pins = "p1_3", "p1_4"; - function = "ssp1"; - slew-rate = <1>; - bias-pull-down; - input-enable; - input-schmitt-disable; - }; - - ssp1_sck { - pins = "pf_4"; - function = "ssp1"; - slew-rate = <1>; - bias-disable; - }; - }; - - uart2_pins: uart2-pins { - uart2_rx_cfg { - pins = "p7_2"; - function = "uart2"; - bias-disable; - input-enable; - }; - - uart2_tx_cfg { - pins = "p7_1"; - function = "uart2"; - bias-disable; - }; - }; - - uart3_pins: uart3-pins { - uart3_rx_cfg { - pins = "p2_4"; - function = "uart3"; - bias-disable; - input-enable; - }; - - uart3_tx_cfg { - pins = "p2_3"; - function = "uart3"; - bias-disable; - }; - }; -}; - -&enet_tx_clk { - clock-frequency = <50000000>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "microchip,24c512"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "microchip,24c02"; - reg = <0x51>; - }; - - eeprom@54 { - compatible = "microchip,24c512"; - reg = <0x54>; - }; -}; - -&mac { - status = "okay"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_rmii_pins>; -}; - -&sct_pwm { - status = "okay"; -}; - -&ssp1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp_pins>; - cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>; - num-cs = <1>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/software/linux/kernel/arch/arm/boot/dts/lpc4350-hitex-eval.dts deleted file mode 100644 index 874c75d44..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ /dev/null @@ -1,483 +0,0 @@ -/* - * Hitex LPC4350 Evaluation Board - * - * Copyright 2015 Ariel D'Alessandro - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4350.dtsi" - -#include "dt-bindings/input/input.h" -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "Hitex LPC4350 Evaluation Board"; - compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart0; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x800000>; /* 8 MB */ - }; - - pca_buttons { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - autorepeat; - - button0 { - label = "joy:right"; - linux,code = ; - gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; - }; - - button1 { - label = "joy:up"; - linux,code = ; - gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; - }; - - - button2 { - label = "joy:enter"; - linux,code = ; - gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; - }; - - button3 { - label = "joy:left"; - linux,code = ; - gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; - }; - - button4 { - label = "joy:down"; - linux,code = ; - gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; - }; - - button5 { - label = "user:sw3"; - linux,code = ; - gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; - }; - - button6 { - label = "user:sw4"; - linux,code = ; - gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; - }; - - button7 { - label = "user:sw5"; - linux,code = ; - gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; - }; - }; - - pca_leds { - compatible = "gpio-leds"; - - led0 { - label = "ext:led0"; - gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "ext:led1"; - gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>; - }; - - led2 { - label = "ext:led2"; - gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>; - }; - - led3 { - label = "ext:led3"; - gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>; - }; - }; - - vcc: vcc_fixed { - compatible = "regulator-fixed"; - regulator-name = "3v3io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&pinctrl { - adc1_pins: adc1-pins { - adc1_pins_cfg { - pins = "pf_9"; - function = "adc"; - input-disable; - bias-disable; - }; - }; - - emc_pins: emc-pins { - emc_addr0_23_cfg { - pins = "p2_9", "p2_10", "p2_11", "p2_12", - "p2_13", "p1_0", "p1_1", "p1_2", - "p2_8", "p2_7", "p2_6", "p2_2", - "p2_1", "p2_0", "p6_8", "p6_7", - "pd_16", "pd_15", "pe_0", "pe_1", - "pe_2", "pe_3", "pe_4", "pa_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_data0_15_cfg { - pins = "p1_7", "p1_8", "p1_9", "p1_10", - "p1_11", "p1_12", "p1_13", "p1_14", - "p5_4", "p5_5", "p5_6", "p5_7", - "p5_0", "p5_1", "p5_2", "p5_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_we_oe_cfg { - pins = "p1_6", "p1_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_bls0_3_cfg { - pins = "p1_4", "p6_6", "pd_13", "pd_10"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_cs0_cs2_cfg { - pins = "p1_5", "pd_12"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dqm0_3_cfg { - pins = "p6_12", "p6_10", "pd_0", "pe_13"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_ras_cas_cfg { - pins = "p6_5", "p6_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dycs0_cfg { - pins = "p6_9"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_cke_cfg { - pins = "p6_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_clock_cfg { - pins = "clk0", "clk1", "clk2", "clk3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - enet_mii_pins: enet-mii-pins { - enet_mii_rxd0_3_cfg { - pins = "p1_15", "p0_0", "p9_3", "p9_2"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_txd0_3_cfg { - pins = "p1_18", "p1_20", "p9_4", "p9_5"; - function = "enet"; - bias-disable; - }; - - enet_mii_crs_col_cfg { - pins = "p9_0", "p9_6"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_rx_clk_dv_er_cfg { - pins = "pc_0", "p1_16", "p9_1"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mii_tx_clk_en_cfg { - pins = "p1_19", "p0_1"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - }; - - enet_mdc_cfg { - pins = "pc_1"; - function = "enet"; - bias-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - spifi_pins: spifi-pins { - spifi_clk_cfg { - pins = "p3_3"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_mosi_miso_sio2_3_cfg { - pins = "p3_7", "p3_6", "p3_5", "p3_4"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_cs_cfg { - pins = "p3_8"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - uart0_pins: uart0-pins { - uart0_rx_cfg { - pins = "pf_11"; - function = "uart0"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart0_tx_cfg { - pins = "pf_10"; - function = "uart0"; - bias-pull-down; - }; - }; -}; - -&adc1 { - status = "okay"; - vref-supply = <&vcc>; - pinctrl-names = "default"; - pinctrl-0 = <&adc1_pins>; -}; - -&emc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emc_pins>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-access-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - flash@0,0 { - compatible = "sst,sst39vf320", "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2C0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x100000>; /* 1 MiB */ - }; - }; - }; - - cs2 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <2>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <30>; - mpmc,read-access-delay = <90>; - mpmc,page-mode-read-delay = <55>; - mpmc,write-access-delay = <55>; - mpmc,turn-round-delay = <55>; - - ext_sram: sram@2,0 { - compatible = "mmio-sram"; - reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ - }; - }; -}; - -&enet_tx_clk { - clock-frequency = <25000000>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - /* NXP SE97BTP with temperature sensor + eeprom */ - sensor@18 { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; - reg = <0x18>; - }; - - eeprom@50 { - compatible = "nxp,24c02"; - reg = <0x50>; - }; - - pca_gpio: gpio@24 { - compatible = "nxp,pca9673"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mac { - status = "okay"; - phy-mode = "mii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_mii_pins>; -}; - -&spifi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifi_pins>; - - flash { - compatible = "jedec,spi-nor"; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2c0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x500000>; /* 5 MiB */ - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc4350.dtsi b/software/linux/kernel/arch/arm/boot/dts/lpc4350.dtsi deleted file mode 100644 index c4422f587..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc4350.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * NXP LPC4350 and LPC4330 SoC - * - * Copyright 2015 Ariel D'Alessandro - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -/ { - compatible = "nxp,lpc4350", "nxp,lpc4330"; - - cpus { - cpu@0 { - compatible = "arm,cortex-m4"; - }; - }; - - soc { - sram0: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ - }; - - sram1: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ - }; - - sram2: sram@20000000 { - compatible = "mmio-sram"; - reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/software/linux/kernel/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts deleted file mode 100644 index 9b5fad622..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ /dev/null @@ -1,625 +0,0 @@ -/* - * Embedded Artist LPC4357 Developer's Kit - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ -/dts-v1/; - -#include "lpc18xx.dtsi" -#include "lpc4357.dtsi" - -#include "dt-bindings/input/input.h" -#include "dt-bindings/gpio/gpio.h" - -/ { - model = "Embedded Artists' LPC4357 Developer's Kit"; - compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart0; - }; - - memory@28000000 { - device_type = "memory"; - reg = <0x28000000 0x2000000>; /* 32 MB */ - }; - - vcc: vcc_fixed { - compatible = "regulator-fixed"; - regulator-name = "3v3-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* vmmc is controlled by sdmmc host internally */ - vmmc: vmmc_fixed { - compatible = "regulator-fixed"; - regulator-name = "vmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - gpio_joystick { - compatible = "gpio-keys-polled"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_joystick_pins>; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - autorepeat; - - button0 { - label = "joy_enter"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; - }; - - button1 { - label = "joy_left"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; - }; - - button2 { - label = "joy_up"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; - }; - - button3 { - label = "joy_right"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; - }; - - button4 { - label = "joy_down"; - linux,code = ; - gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; - }; - }; - - leds_mmio { - compatible = "gpio-leds"; - - led1 { - gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>; - }; - - led3 { - gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>; - }; - - led4 { - gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>; - }; - - led5 { - gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>; - }; - - led6 { - gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>; - }; - - led7 { - gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>; - }; - - led8 { - gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>; - }; - - led9 { - gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>; - }; - - led10 { - gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>; - }; - - led11 { - gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>; - }; - - led12 { - gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>; - }; - - led13 { - gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>; - }; - - led14 { - gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>; - }; - - led15 { - gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>; - }; - - led16 { - gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - emc_pins: emc-pins { - emc_addr0_23_cfg { - pins = "p2_9", "p2_10", "p2_11", "p2_12", - "p2_13", "p1_0", "p1_1", "p1_2", - "p2_8", "p2_7", "p2_6", "p2_2", - "p2_1", "p2_0", "p6_8", "p6_7", - "pd_16", "pd_15", "pe_0", "pe_1", - "pe_2", "pe_3", "pe_4", "pa_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_data0_31_cfg { - pins = "p1_7", "p1_8", "p1_9", "p1_10", - "p1_11", "p1_12", "p1_13", "p1_14", - "p5_4", "p5_5", "p5_6", "p5_7", - "p5_0", "p5_1", "p5_2", "p5_3", - "pd_2", "pd_3", "pd_4", "pd_5", - "pd_6", "pd_7", "pd_8", "pd_9", - "pe_5", "pe_6", "pe_7", "pe_8", - "pe_9", "pe_10", "pe_11", "pe_12"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_we_oe_cfg { - pins = "p1_6", "p1_3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_bls0_3_cfg { - pins = "p1_4", "p6_6", "pd_13", "pd_10"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_cs0_3_cfg { - pins = "p1_5", "p6_3", "pd_12", "pd_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dqm0_3_cfg { - pins = "p6_12", "p6_10", "pd_0", "pe_13"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_ras_cas_cfg { - pins = "p6_5", "p6_4"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_dycs0_cfg { - pins = "p6_9"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_cke_cfg { - pins = "p6_11"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - emc_sdram_clock_cfg { - pins = "clk0", "clk1", "clk2", "clk3"; - function = "emc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - enet_rmii_pins: enet-rmii-pins { - enet_rmii_rxd_cfg { - pins = "p1_15", "p0_0"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_txd_cfg { - pins = "p1_18", "p1_20"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_rx_dv_cfg { - pins = "p1_16"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_rmii_tx_en_cfg { - pins = "p0_1"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_ref_clk_cfg { - pins = "p1_19"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdio_cfg { - pins = "p1_17"; - function = "enet"; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - enet_mdc_cfg { - pins = "pc_1"; - function = "enet"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - }; - - gpio_joystick_pins: gpio-joystick-pins { - gpio_joystick_cfg { - pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; - function = "gpio"; - input-enable; - bias-disable; - }; - }; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - sdmmc_pins: sdmmc-pins { - sdmmc_clk_cfg { - pins = "pc_0"; - function = "sdmmc"; - slew-rate = <1>; - bias-pull-down; - }; - - sdmmc_cmd_dat0_3_cfg { - pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; - function = "sdmmc"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - sdmmc_cd_cfg { - pins = "pc_8"; - function = "sdmmc"; - bias-pull-down; - input-enable; - }; - - sdmmc_pow_cfg { - pins = "pc_9"; - function = "sdmmc"; - bias-pull-down; - }; - }; - - spifi_pins: spifi-pins { - spifi_clk_cfg { - pins = "p3_3"; - function = "spifi"; - slew-rate = <1>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_mosi_miso_sio2_3_cfg { - pins = "p3_7", "p3_6", "p3_5", "p3_4"; - function = "spifi"; - slew-rate = <0>; - bias-disable; - input-enable; - input-schmitt-disable; - }; - - spifi_cs_cfg { - pins = "p3_8"; - function = "spifi"; - bias-disable; - }; - }; - - ssp0_pins: ssp0-pins { - ssp0_sck_miso_mosi { - pins = "pf_0", "pf_2", "pf_3"; - function = "ssp0"; - slew-rate = <1>; - bias-pull-down; - input-enable; - input-schmitt-disable; - }; - - ssp0_ssel { - pins = "pf_1"; - function = "ssp0"; - bias-pull-up; - }; - }; - - uart0_pins: uart0-pins { - uart0_rx_cfg { - pins = "pf_11"; - function = "uart0"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart0_tx_cfg { - pins = "pf_10"; - function = "uart0"; - bias-pull-down; - }; - }; - - uart3_pins: uart3-pins { - uart3_rx_cfg { - pins = "p2_4"; - function = "uart3"; - input-schmitt-disable; - bias-disable; - input-enable; - }; - - uart3_tx_cfg { - pins = "p9_3"; - function = "uart3"; - bias-pull-down; - }; - }; - - usb0_pins: usb0-pins { - usb0_pwr_enable { - pins = "p2_3"; - function = "usb0"; - }; - - usb0_pwr_fault { - pins = "p8_0"; - function = "usb0"; - bias-disable; - input-enable; - }; - }; -}; - -&adc0 { - status = "okay"; - vref-supply = <&vcc>; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - - mma7455@1d { - compatible = "fsl,mma7455"; - reg = <0x1d>; - }; - - lm75@48 { - compatible = "nxp,lm75"; - reg = <0x48>; - }; - - eeprom@57 { - compatible = "microchip,24c64"; - reg = <0x57>; - }; -}; - -&dac { - status = "okay"; - vref-supply = <&vcc>; -}; - -&emc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&emc_pins>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-access-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - flash@0,0 { - compatible = "sst,sst39vf320", "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x040000>; /* 256 KiB */ - }; - - partition@1 { - label = "kernel"; - reg = <0x040000 0x2c0000>; /* 2.75 MiB */ - }; - - partition@2 { - label = "rootfs"; - reg = <0x300000 0x100000>; /* 1 MiB */ - }; - }; - }; - - cs2 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <2>; - mpmc,memory-width = <16>; - - mmio_leds: gpio@2,0 { - compatible = "ti,7416374"; - reg = <2 0 0x2>; - gpio-controller; - #gpio-cells = <2>; - }; - - }; -}; - -&enet_tx_clk { - clock-frequency = <50000000>; -}; - -&mac { - status = "okay"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&enet_rmii_pins>; -}; - -&mmcsd { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vmmc>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pins>; -}; - -&spifi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifi_pins>; - - flash { - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "data"; - reg = <0 0x200000>; - }; - }; -}; - -&ssp0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_pins>; - num-cs = <1>; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&usb0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/lpc4357.dtsi b/software/linux/kernel/arch/arm/boot/dts/lpc4357.dtsi deleted file mode 100644 index 72f12db8d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/lpc4357.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -/* - * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC - * - * Copyright 2015 Joachim Eastwood - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -/ { - compatible = "nxp,lpc4357"; - - cpus { - cpu@0 { - compatible = "arm,cortex-m4"; - }; - }; - - soc { - sram0: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ - }; - - sram1: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ - }; - - sram2: sram@20000000 { - compatible = "mmio-sram"; - reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ - }; - }; -}; - -&eeprom { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ls1021a-qds.dts b/software/linux/kernel/arch/arm/boot/dts/ls1021a-qds.dts deleted file mode 100644 index 940875316..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ls1021a-qds.dts +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "LS1021A QDS Board"; - - aliases { - enet0_rgmii_phy = &rgmii_phy1; - enet1_rgmii_phy = &rgmii_phy2; - enet2_rgmii_phy = &rgmii_phy3; - enet0_sgmii_phy = &sgmii_phy1c; - enet1_sgmii_phy = &sgmii_phy1d; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - dspiflash: at45db021d@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&enet0 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy1c>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy1d>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet2 { - phy-handle = <&rgmii_phy3>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9547: mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - ds3232: rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - interrupts = ; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - - adt7461a@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - codec: sgtl5000@2a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x2a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk 1>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x2 0x0 0x0 0x7e800000 0x00010000 - 0x3 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - reg = <0x3 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; - ranges = <0 3 0 0x100>; - - mdio-mux-emi1 { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x54 1>; /* BRDCFG4 */ - mux-mask = <0xe0>; /* EMI1[2:0] */ - - /* Onboard PHYs */ - ls1021amdio0: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - }; - - ls1021amdio1: mdio@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - }; - - ls1021amdio2: mdio@40 { - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy3: ethernet-phy@3 { - reg = <0x3>; - }; - }; - - ls1021amdio3: mdio@60 { - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy1c: ethernet-phy@1c { - reg = <0x1c>; - }; - }; - - ls1021amdio4: mdio@80 { - reg = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy1d: ethernet-phy@1d { - reg = <0x1d>; - }; - }; - }; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - tbi0: tbi-phy@8 { - reg = <0x8>; - device_type = "tbi-phy"; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ls1021a-twr.dts b/software/linux/kernel/arch/arm/boot/dts/ls1021a-twr.dts deleted file mode 100644 index a8b148ad1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ls1021a-twr.dts +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "LS1021A TWR Board"; - - aliases { - enet2_rgmii_phy = &rgmii_phy1; - enet0_sgmii_phy = &sgmii_phy2; - enet1_sgmii_phy = &sgmii_phy0; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; - - panel: panel { - compatible = "nec,nl4827hc19-05b"; - - port { - panel_in: endpoint { - remote-endpoint = <&dcu_out>; - }; - }; - }; -}; - -&dcu { - status = "okay"; - - port { - dcu_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&dspi1 { - bus-num = <0>; - status = "okay"; - - dspiflash: s25fl064k@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl064k"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&enet0 { - tbi-handle = <&tbi1>; - phy-handle = <&sgmii_phy2>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet1 { - tbi-handle = <&tbi1>; - phy-handle = <&sgmii_phy0>; - phy-connection-type = "sgmii"; - status = "okay"; -}; - -&enet2 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - -}; - -&i2c1 { - status = "okay"; - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk 1>; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR Flash on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - sgmii_phy0: ethernet-phy@0 { - reg = <0x0>; - }; - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - sgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - tbi1: tbi-phy@1f { - reg = <0x1f>; - device_type = "tbi-phy"; - }; -}; - -&sai1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ls1021a.dtsi b/software/linux/kernel/arch/arm/boot/dts/ls1021a.dtsi deleted file mode 100644 index 368e21934..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ls1021a.dtsi +++ /dev/null @@ -1,678 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton64.dtsi" -#include - -/ { - compatible = "fsl,ls1021a"; - interrupt-parent = <&gic>; - - aliases { - crypto = &crypto; - ethernet0 = &enet0; - ethernet1 = &enet1; - ethernet2 = &enet2; - serial0 = &lpuart0; - serial1 = &lpuart1; - serial2 = &lpuart2; - serial3 = &lpuart3; - serial4 = &lpuart4; - serial5 = &lpuart5; - sysclk = &sysclk; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; - clocks = <&cluster1_clk>; - }; - - cpu@f01 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf01>; - clocks = <&cluster1_clk>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - device_type = "soc"; - interrupt-parent = <&gic>; - ranges; - - gic: interrupt-controller@1400000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1401000 0x0 0x1000>, - <0x0 0x1402000 0x0 0x1000>, - <0x0 0x1404000 0x0 0x2000>, - <0x0 0x1406000 0x0 0x2000>; - interrupts = ; - - }; - - msi1: msi-controller@1570e00 { - compatible = "fsl,1s1021a-msi"; - reg = <0x0 0x1570e00 0x0 0x8>; - msi-controller; - interrupts = ; - }; - - msi2: msi-controller@1570e08 { - compatible = "fsl,1s1021a-msi"; - reg = <0x0 0x1570e08 0x0 0x8>; - msi-controller; - interrupts = ; - }; - - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = ; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1021a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - big-endian; - }; - - esdhc: esdhc@1560000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = ; - clock-frequency = <0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - status = "disabled"; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1021a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20220520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&platform_clk 1>; - dma-coherent; - status = "disabled"; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1021a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <7>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x1700000 0x0 0x100000>; - ranges = <0x0 0x0 0x1700000 0x100000>; - interrupts = ; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - - }; - - clockgen: clocking@1ee1000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1ee1000 0x10000>; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "sysclk"; - }; - - cga_pll1: pll@800 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0x800 0x10>; - clocks = <&sysclk>; - clock-output-names = "cga-pll1", "cga-pll1-div2", - "cga-pll1-div4"; - }; - - platform_clk: pll@c00 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0xc00 0x10>; - clocks = <&sysclk>; - clock-output-names = "platform-clk", "platform-clk-div2"; - }; - - cluster1_clk: clk0c0@0 { - compatible = "fsl,qoriq-core-mux-2.0"; - #clock-cells = <0>; - reg = <0x0 0x10>; - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; - clock-output-names = "cluster1-clk"; - }; - }; - - dspi0: dspi@2100000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&platform_clk 1>; - spi-num-chipselects = <6>; - big-endian; - status = "disabled"; - }; - - dspi1: dspi@2110000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&platform_clk 1>; - spi-num-chipselects = <6>; - big-endian; - status = "disabled"; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&platform_clk 1>; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&platform_clk 1>; - status = "disabled"; - }; - - i2c2: i2c@21a0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&platform_clk 1>; - status = "disabled"; - }; - - uart0: serial@21c0500 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart1: serial@21c0600 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart2: serial@21d0500 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - uart3: serial@21d0600 { - compatible = "fsl,16550-FIFO64", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = ; - clock-frequency = <0>; - fifo-size = <15>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = ; - clocks = <&sysclk>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart1: serial@2960000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = ; - clocks = <&platform_clk 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart2: serial@2970000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = ; - clocks = <&platform_clk 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart3: serial@2980000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = ; - clocks = <&platform_clk 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@2990000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = ; - clocks = <&platform_clk 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@29a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = ; - clocks = <&platform_clk 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - wdog0: watchdog@2ad0000 { - compatible = "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = ; - clocks = <&platform_clk 1>; - clock-names = "wdog-en"; - big-endian; - }; - - sai1: sai@2b50000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b50000 0x0 0x10000>; - interrupts = ; - clocks = <&platform_clk 1>, <&platform_clk 1>, - <&platform_clk 1>, <&platform_clk 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 47>, - <&edma0 1 46>; - status = "disabled"; - }; - - sai2: sai@2b60000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b60000 0x0 0x10000>; - interrupts = ; - clocks = <&platform_clk 1>, <&platform_clk 1>, - <&platform_clk 1>, <&platform_clk 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 45>, - <&edma0 1 44>; - status = "disabled"; - }; - - edma0: edma@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&platform_clk 1>, - <&platform_clk 1>; - }; - - dcu: dcu@2ce0000 { - compatible = "fsl,ls1021a-dcu"; - reg = <0x0 0x2ce0000 0x0 0x10000>; - interrupts = ; - clocks = <&platform_clk 0>, - <&platform_clk 0>; - clock-names = "dcu", "pix"; - big-endian; - status = "disabled"; - }; - - mdio0: mdio@2d24000 { - compatible = "gianfar"; - device_type = "mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2d24000 0x0 0x4000>; - }; - - ptp_clock@2d10e00 { - compatible = "fsl,etsec-ptp"; - reg = <0x0 0x2d10e00 0x0 0xb0>; - interrupts = ; - fsl,tclk-period = <5>; - fsl,tmr-prsc = <2>; - fsl,tmr-add = <0xaaaaaaab>; - fsl,tmr-fiper1 = <999999990>; - fsl,tmr-fiper2 = <99990>; - fsl,max-adj = <499999999>; - }; - - enet0: ethernet@2d10000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - fsl,magic-packet; - ranges; - dma-coherent; - - queue-group@2d10000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d10000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d14000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d14000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - enet1: ethernet@2d50000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - ranges; - dma-coherent; - - queue-group@2d50000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d50000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d54000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d54000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - enet2: ethernet@2d90000 { - compatible = "fsl,etsec2"; - device_type = "network"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - model = "eTSEC"; - ranges; - dma-coherent; - - queue-group@2d90000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d90000 0x0 0x1000>; - interrupts = , - , - ; - }; - - queue-group@2d94000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x2d94000 0x0 0x1000>; - interrupts = , - , - ; - }; - }; - - usb@8600000 { - compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; - reg = <0x0 0x8600000 0x0 0x1000>; - interrupts = ; - dr_mode = "host"; - phy_type = "ulpi"; - }; - - usb3@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - }; - - pcie@3400000 { - compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ - fsl,pcie-scfg = <&scfg 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - }; - - pcie@3500000 { - compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = ; - fsl,pcie-scfg = <&scfg 1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/meson.dtsi b/software/linux/kernel/arch/arm/boot/dts/meson.dtsi deleted file mode 100644 index 8c77c8766..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/meson.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright 2014 Carlo Caione - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - L2: l2-cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - gic: interrupt-controller@c4301000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xc4301000 0x1000>, - <0xc4300100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - timer@c1109940 { - compatible = "amlogic,meson6-timer"; - reg = <0xc1109940 0x18>; - interrupts = <0 10 1>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - wdt: watchdog@c1109900 { - compatible = "amlogic,meson6-wdt"; - reg = <0xc1109900 0x8>; - interrupts = <0 0 1>; - }; - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x18>; - interrupts = <0 90 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_A: serial@c11084c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc11084c0 0x18>; - interrupts = <0 26 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_B: serial@c11084dc { - compatible = "amlogic,meson-uart"; - reg = <0xc11084dc 0x18>; - interrupts = <0 75 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_C: serial@c1108700 { - compatible = "amlogic,meson-uart"; - reg = <0xc1108700 0x18>; - interrupts = <0 93 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - i2c_AO: i2c@c8100500 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc8100500 0x20>; - interrupts = <0 92 1>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_A: i2c@c1108500 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc1108500 0x20>; - interrupts = <0 21 1>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_B: i2c@c11087c0 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc11087c0 0x20>; - interrupts = <0 128 1>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ir_receiver: ir-receiver@c8100480 { - compatible= "amlogic,meson6-ir"; - reg = <0xc8100480 0x20>; - interrupts = <0 15 1>; - status = "disabled"; - }; - - spifc: spi@c1108c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0xc1108c80 0x80>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk81>; - status = "disabled"; - }; - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson6-dwmac", "snps,dwmac"; - reg = <0xc9410000 0x10000 - 0xc1108108 0x4>; - interrupts = <0 8 1>; - interrupt-names = "macirq"; - clocks = <&clk81>; - clock-names = "stmmaceth"; - status = "disabled"; - }; - }; -}; /* end of / */ diff --git a/software/linux/kernel/arch/arm/boot/dts/meson6-atv1200.dts b/software/linux/kernel/arch/arm/boot/dts/meson6-atv1200.dts deleted file mode 100644 index 1237faa63..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/meson6-atv1200.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2014 Carlo Caione - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "meson6.dtsi" - -/ { - model = "Geniatech ATV1200"; - compatible = "geniatech,atv1200", "amlogic,meson6"; - - aliases { - serial0 = &uart_AO; - }; - - memory { - reg = <0x40000000 0x80000000>; - }; -}; - -&uart_AO { - status = "okay"; -}; - -ðmac { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/meson6.dtsi b/software/linux/kernel/arch/arm/boot/dts/meson6.dtsi deleted file mode 100644 index 8b33be15a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/meson6.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2014 Carlo Caione - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "meson.dtsi" - -/ { - model = "Amlogic Meson6 SoC"; - compatible = "amlogic,meson6"; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x200>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x201>; - }; - }; - - clk81: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; -}; /* end of / */ diff --git a/software/linux/kernel/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/software/linux/kernel/arch/arm/boot/dts/meson8-minix-neo-x8.dts deleted file mode 100644 index 8bceb8d34..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright 2014 Beniamino Galvani - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "meson8.dtsi" - -/ { - model = "MINIX NEO-X8"; - compatible = "minix,neo-x8", "amlogic,meson8"; - - aliases { - serial0 = &uart_AO; - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue { - label = "x8:blue:power"; - gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_pins>; - pinctrl-names = "default"; - - pmic@32 { - compatible = "ricoh,rn5t618"; - reg = <0x32>; - system-power-controller; - - regulators { - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&spi_nor_pins>; - pinctrl-names = "default"; - - spi-flash@0 { - compatible = "mxicy,mx25l1606e"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <30000000>; - - partition@0 { - label = "boot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x10000>; - }; - }; -}; - -&ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; - pinctrl-names = "default"; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_pins>; - pnictrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/meson8.dtsi b/software/linux/kernel/arch/arm/boot/dts/meson8.dtsi deleted file mode 100644 index 45619f616..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/meson8.dtsi +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright 2014 Carlo Caione - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -/include/ "meson.dtsi" - -/ { - model = "Amlogic Meson8 SoC"; - compatible = "amlogic,meson8"; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x200>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x201>; - }; - - cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x202>; - }; - - cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x203>; - }; - }; - - clk81: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <141666666>; - }; - - pinctrl_cbus: pinctrl@c1109880 { - compatible = "amlogic,meson8-cbus-pinctrl"; - reg = <0xc1109880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@c11080b0 { - reg = <0xc11080b0 0x28>, - <0xc11080e8 0x18>, - <0xc1108120 0x18>, - <0xc1108030 0x30>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - spi_nor_pins: nor { - mux { - groups = "nor_d", "nor_q", "nor_c", "nor_cs"; - function = "nor"; - }; - }; - - ir_recv_pins: remote { - mux { - groups = "remote_input"; - function = "remote"; - }; - }; - - eth_pins: ethernet { - mux { - groups = "eth_tx_clk_50m", "eth_tx_en", - "eth_txd1", "eth_txd0", - "eth_rx_clk_in", "eth_rx_dv", - "eth_rxd1", "eth_rxd0", "eth_mdio", - "eth_mdc"; - function = "ethernet"; - }; - }; - }; - - pinctrl_aobus: pinctrl@c8100084 { - compatible = "amlogic,meson8-aobus-pinctrl"; - reg = <0xc8100084 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@c1108030 { - reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - }; - }; - - i2c_ao_pins: i2c_mst_ao { - mux { - groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; - function = "i2c_mst_ao"; - }; - }; - }; -}; /* end of / */ diff --git a/software/linux/kernel/arch/arm/boot/dts/meson8b-mxq.dts b/software/linux/kernel/arch/arm/boot/dts/meson8b-mxq.dts deleted file mode 100644 index c7fdaeabb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/meson8b-mxq.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "meson8b.dtsi" - -/ { - model = "TRONFY MXQ S805"; - compatible = "tronfy,mxq", "amlogic,meson8b"; - - aliases { - serial0 = &uart_AO; - }; - - memory { - reg = <0x40000000 0x40000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/meson8b-odroidc1.dts b/software/linux/kernel/arch/arm/boot/dts/meson8b-odroidc1.dts deleted file mode 100644 index e50f1a1fd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/meson8b-odroidc1.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "meson8b.dtsi" -#include - -/ { - model = "Hardkernel ODROID-C1"; - compatible = "hardkernel,odroid-c1", "amlogic,meson8b"; - - aliases { - serial0 = &uart_AO; - }; - - memory { - reg = <0x40000000 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - blue { - label = "c1:blue:alive"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/meson8b.dtsi b/software/linux/kernel/arch/arm/boot/dts/meson8b.dtsi deleted file mode 100644 index 41fd53671..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/meson8b.dtsi +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2015 Endless Mobile, Inc. - * Author: Carlo Caione - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x200>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x201>; - }; - - cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x202>; - }; - - cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - next-level-cache = <&L2>; - reg = <0x203>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - L2: l2-cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - gic: interrupt-controller@c4301000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xc4301000 0x1000>, - <0xc4300100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - reset: reset-controller@c1104404 { - compatible = "amlogic,meson8b-reset"; - reg = <0xc1104404 0x20>; - #reset-cells = <1>; - }; - - wdt: watchdog@c1109900 { - compatible = "amlogic,meson8b-wdt"; - reg = <0xc1109900 0x8>; - interrupts = <0 0 1>; - }; - - timer@c1109940 { - compatible = "amlogic,meson6-timer"; - reg = <0xc1109940 0x18>; - interrupts = <0 10 1>; - }; - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x18>; - interrupts = <0 90 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; - - uart_A: serial@c11084c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc11084c0 0x18>; - interrupts = <0 26 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; - - uart_B: serial@c11084dc { - compatible = "amlogic,meson-uart"; - reg = <0xc11084dc 0x18>; - interrupts = <0 75 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; - - uart_C: serial@c1108700 { - compatible = "amlogic,meson-uart"; - reg = <0xc1108700 0x18>; - interrupts = <0 93 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; - - clkc: clock-controller@c1104000 { - #clock-cells = <1>; - compatible = "amlogic,meson8b-clkc"; - reg = <0xc1108000 0x4>, <0xc1104000 0x460>; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc1108550 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc1108650 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc11086c0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pinctrl_cbus: pinctrl@c1109880 { - compatible = "amlogic,meson8b-cbus-pinctrl"; - reg = <0xc1109880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@c11080b0 { - reg = <0xc11080b0 0x28>, - <0xc11080e8 0x18>, - <0xc1108120 0x18>, - <0xc1108030 0x38>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - pinctrl_aobus: pinctrl@c8100084 { - compatible = "amlogic,meson8b-aobus-pinctrl"; - reg = <0xc8100084 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@c1108030 { - reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - }; - }; - }; - }; -}; /* end of / */ diff --git a/software/linux/kernel/arch/arm/boot/dts/mmp2-brownstone.dts b/software/linux/kernel/arch/arm/boot/dts/mmp2-brownstone.dts deleted file mode 100644 index 350208c5e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mmp2-brownstone.dts +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; -#include "mmp2.dtsi" - -/ { - model = "Marvell MMP2 Brownstone Development Board"; - compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; - - chosen { - bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - soc { - apb@d4000000 { - uart3: uart@d4018000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - pmic: max8925@3c { - compatible = "maxium,max8925"; - reg = <0x3c>; - interrupts = <1>; - interrupt-parent = <&intcmux4>; - interrupt-controller; - #interrupt-cells = <1>; - maxim,tsc-irq = <0>; - - regulators { - SDV1 { - regulator-min-microvolt = <637500>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - regulator-always-on; - }; - SDV2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2225000>; - regulator-boot-on; - regulator-always-on; - }; - SDV3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - }; - LDO11 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO15 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO16 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO17 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO18 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO19 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO20 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - }; - backlight { - maxim,max8925-dual-string = <0>; - }; - charger { - batt-detect = <0>; - topoff-threshold = <1>; - fast-charge = <7>; - no-temp-support = <0>; - no-insert-detect = <0>; - }; - }; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mmp2.dtsi b/software/linux/kernel/arch/arm/boot/dts/mmp2.dtsi deleted file mode 100644 index 766bbb849..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mmp2.dtsi +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - intcmux4: interrupt-controller@d4282150 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <4>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x150 0x4>, <0x168 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - intcmux5: interrupt-controller@d4282154 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <5>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x154 0x4>, <0x16c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - mrvl,clr-mfp-irq = <1>; - }; - - intcmux9: interrupt-controller@d4282180 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <9>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x180 0x4>, <0x17c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <3>; - }; - - intcmux17: interrupt-controller@d4282158 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <17>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x158 0x4>, <0x170 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <5>; - }; - - intcmux35: interrupt-controller@d428215c { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <35>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x15c 0x4>, <0x174 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <15>; - }; - - intcmux51: interrupt-controller@d4282160 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <51>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x160 0x4>, <0x178 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - intcmux55: interrupt-controller@d4282188 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <55>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x188 0x4>, <0x184 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - uart1: uart@d4030000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4030000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks MMP2_CLK_UART0>; - resets = <&soc_clocks MMP2_CLK_UART0>; - status = "disabled"; - }; - - uart2: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks MMP2_CLK_UART1>; - resets = <&soc_clocks MMP2_CLK_UART1>; - status = "disabled"; - }; - - uart3: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <24>; - clocks = <&soc_clocks MMP2_CLK_UART2>; - resets = <&soc_clocks MMP2_CLK_UART2>; - status = "disabled"; - }; - - uart4: uart@d4016000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4016000 0x1000>; - interrupts = <46>; - clocks = <&soc_clocks MMP2_CLK_UART3>; - resets = <&soc_clocks MMP2_CLK_UART3>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp2-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks MMP2_CLK_GPIO>; - resets = <&soc_clocks MMP2_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <1>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - - gcb4: gpio@d4019104 { - reg = <0xd4019104 0x4>; - }; - - gcb5: gpio@d4019108 { - reg = <0xd4019108 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks MMP2_CLK_TWSI0>; - resets = <&soc_clocks MMP2_CLK_TWSI0>; - #address-cells = <1>; - #size-cells = <0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4025000 0x1000>; - interrupts = <58>; - clocks = <&soc_clocks MMP2_CLK_TWSI1>; - resets = <&soc_clocks MMP2_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <1 0>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - interrupt-parent = <&intcmux5>; - clocks = <&soc_clocks MMP2_CLK_RTC>; - resets = <&soc_clocks MMP2_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,mmp2-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/moxart-uc7112lx.dts b/software/linux/kernel/arch/arm/boot/dts/moxart-uc7112lx.dts deleted file mode 100644 index 10d088df0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/moxart-uc7112lx.dts +++ /dev/null @@ -1,117 +0,0 @@ -/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX - * - * Copyright (C) 2013 Jonas Jensen - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; -/include/ "moxart.dtsi" - -/ { - model = "MOXA UC-7112-LX"; - compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"; - - memory { - device_type = "memory"; - reg = <0x0 0x2000000>; - }; - - clocks { - ref12: ref12M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - }; - - flash@80000000,0 { - compatible = "numonyx,js28f128", "cfi-flash"; - reg = <0x80000000 0x1000000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "bootloader"; - reg = <0x0 0x40000>; - }; - partition@40000 { - label = "linux kernel"; - reg = <0x40000 0x1C0000>; - }; - partition@200000 { - label = "root filesystem"; - reg = <0x200000 0x800000>; - }; - partition@a00000 { - label = "user filesystem"; - reg = <0xa00000 0x600000>; - }; - }; - - leds { - compatible = "gpio-leds"; - user-led { - label = "ready-led"; - gpios = <&gpio 27 0x1>; - default-state = "on"; - linux,default-trigger = "default-on"; - }; - }; - - gpio_keys_polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <500>; - button@25 { - label = "GPIO Reset"; - linux,code = <116>; - gpios = <&gpio 25 1>; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait"; - }; -}; - -&clk_pll { - clocks = <&ref12>; -}; - -&sdhci { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - ethphy0: ethernet-phy@1 { - device_type = "ethernet-phy"; - compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mdio1 { - status = "okay"; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mac0 { - status = "okay"; -}; - -&mac1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/moxart.dtsi b/software/linux/kernel/arch/arm/boot/dts/moxart.dtsi deleted file mode 100644 index 1fd27ed65..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/moxart.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC - * - * Copyright (C) 2013 Jonas Jensen - * - * Licensed under GPLv2 or later. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "moxa,moxart"; - model = "MOXART"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "faraday,fa526"; - reg = <0>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x90000000 0x10000000>; - ranges; - - intc: interrupt-controller@98800000 { - compatible = "moxa,moxart-ic"; - reg = <0x98800000 0x38>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-mask = <0x00080000>; - }; - - clk_pll: clk_pll@98100000 { - compatible = "moxa,moxart-pll-clock"; - #clock-cells = <0>; - reg = <0x98100000 0x34>; - }; - - clk_apb: clk_apb@98100000 { - compatible = "moxa,moxart-apb-clock"; - #clock-cells = <0>; - reg = <0x98100000 0x34>; - clocks = <&clk_pll>; - }; - - timer: timer@98400000 { - compatible = "moxa,moxart-timer"; - reg = <0x98400000 0x42>; - interrupts = <19 1>; - clocks = <&clk_apb>; - }; - - gpio: gpio@98700000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "moxa,moxart-gpio"; - reg = <0x98700000 0xC>; - }; - - rtc: rtc { - compatible = "moxa,moxart-rtc"; - gpio-rtc-sclk = <&gpio 5 0>; - gpio-rtc-data = <&gpio 6 0>; - gpio-rtc-reset = <&gpio 7 0>; - }; - - dma: dma@90500000 { - compatible = "moxa,moxart-dma"; - reg = <0x90500080 0x40>; - interrupts = <24 0>; - #dma-cells = <1>; - }; - - watchdog: watchdog@98500000 { - compatible = "moxa,moxart-watchdog"; - reg = <0x98500000 0x10>; - clocks = <&clk_apb>; - }; - - sdhci: sdhci@98e00000 { - compatible = "moxa,moxart-sdhci"; - reg = <0x98e00000 0x5C>; - interrupts = <5 0>; - clocks = <&clk_apb>; - dmas = <&dma 5>, - <&dma 5>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mdio0: mdio@90900090 { - compatible = "moxa,moxart-mdio"; - reg = <0x90900090 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mdio1: mdio@92000090 { - compatible = "moxa,moxart-mdio"; - reg = <0x92000090 0x8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mac0: mac@90900000 { - compatible = "moxa,moxart-mac"; - reg = <0x90900000 0x90>; - interrupts = <25 0>; - phy-handle = <ðphy0>; - phy-mode = "mii"; - status = "disabled"; - }; - - mac1: mac@92000000 { - compatible = "moxa,moxart-mac"; - reg = <0x92000000 0x90>; - interrupts = <27 0>; - phy-handle = <ðphy1>; - phy-mode = "mii"; - status = "disabled"; - }; - - uart0: uart@98200000 { - compatible = "ns16550a"; - reg = <0x98200000 0x20>; - interrupts = <31 8>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <14745600>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mpa1600.dts b/software/linux/kernel/arch/arm/boot/dts/mpa1600.dts deleted file mode 100644 index 116ce78be..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mpa1600.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * mpa1600.dts - Device Tree file for Phontech MPA 1600 - * - * Copyright (C) 2013 Joachim Eastwood - * - * Licensed under GPLv2 only - */ -/dts-v1/; -#include "at91rm9200.dtsi" - -/ { - model = "Phontech MPA 1600"; - compatible = "phontech,mpa1600", "atmel,at91rm9200"; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - ssc0: ssc@fffd0000 { - status = "okay"; - }; - - ssc1: ssc@fffd4000 { - status = "okay"; - }; - }; - - usb0: ohci@00300000 { - num-ports = <1>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - monitor_mute { - label = "Monitor mute"; - gpios = <&pioC 1 GPIO_ACTIVE_LOW>; - linux,code = <113>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mps2-an385.dts b/software/linux/kernel/arch/arm/boot/dts/mps2-an385.dts deleted file mode 100644 index 31c374d72..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mps2-an385.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "mps2.dtsi" - -/ { - model = "ARM MPS2 Application Note 385/386"; - compatible = "arm,mps2"; - - aliases { - serial0 = &uart0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:9600n8"; - }; - - memory { - device_type = "memory"; - reg = <0x21000000 0x1000000>; - }; - - smb { - ethernet@0,0 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0 0x0 0x10000>; - interrupts = <13>; - interrupt-parent = <&nvic>; - smsc,irq-active-high; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mps2-an399.dts b/software/linux/kernel/arch/arm/boot/dts/mps2-an399.dts deleted file mode 100644 index 5e7e5ca2e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mps2-an399.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "mps2.dtsi" - -/ { - model = "ARM MPS2 Application Note 399/400"; - compatible = "arm,mps2"; - - aliases { - serial0 = &uart0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:9600n8"; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x1000000>; - }; - - smb { - ethernet@1,0 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <1 0x0 0x10000>; - interrupts = <13>; - interrupt-parent = <&nvic>; - smsc,irq-active-high; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mps2.dtsi b/software/linux/kernel/arch/arm/boot/dts/mps2.dtsi deleted file mode 100644 index efb8a03cb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mps2.dtsi +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include "armv7-m.dtsi" - -/ { - oscclk0: clk-osc0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - oscclk1: clk-osc1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - oscclk2: clk-osc2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - cfgclk: clk-cfg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <5000000>; - }; - - spicfgclk: clk-spicfg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <75000000>; - }; - - sysclk: clk-sys { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - audmclk: clk-audm { - compatible = "fixed-factor-clock"; - clocks = <&oscclk1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - audsclk: clk-auds { - compatible = "fixed-factor-clock"; - clocks = <&oscclk1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - - spiclcd: clk-cpiclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - spicon: clk-spicon { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2cclcd: clk-i2cclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2caud: clk-i2caud { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - soc { - compatible = "simple-bus"; - ranges; - - apb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x10000>; - - timer0: mps2-timer0@0 { - compatible = "arm,mps2-timer"; - reg = <0x0 0x1000>; - interrupts = <8>; - clocks = <&sysclk>; - status = "disabled"; - }; - - timer1: mps2-timer1@1000 { - compatible = "arm,mps2-timer"; - reg = <0x1000 0x1000>; - interrupts = <9>; - clocks = <&sysclk>; - status = "disabled"; - }; - - timer2: dual-timer@2000 { - compatible = "arm,sp804"; - reg = <0x2000 0x1000>; - clocks = <&sysclk>; - interrupts = <10>; - status = "disabled"; - }; - - uart0: serial@4000 { - compatible = "arm,mps2-uart"; - reg = <0x4000 0x1000>; - interrupts = <0 1 12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - uart1: serial@5000 { - compatible = "arm,mps2-uart"; - reg = <0x5000 0x1000>; - interrupts = <2 3 12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - uart2: serial@6000 { - compatible = "arm,mps2-uart"; - reg = <0x6000 0x1000>; - interrupts = <4 5 12>; - clocks = <&sysclk>; - status = "disabled"; - }; - - wdt: watchdog@8000 { - compatible = "arm,sp805", "arm,primecell"; - arm,primecell-periphid = <0x00141805>; - reg = <0x8000 0x1000>; - interrupts = <0>; - clocks = <&sysclk>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - }; - }; - - fpga@40020000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x10000>; - - fpgaio@8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x8000 0x10>; - - led0 { - compatible = "register-bit-led"; - offset = <0x0>; - mask = <0x01>; - label = "userled:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - led1 { - compatible = "register-bit-led"; - offset = <0x0>; - mask = <0x02>; - label = "userled:1"; - linux,default-trigger = "usr"; - default-state = "off"; - }; - }; - }; - - smb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40200000 0x10000>, - <1 0 0xa0000000 0x10000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt2701-evb.dts b/software/linux/kernel/arch/arm/boot/dts/mt2701-evb.dts deleted file mode 100644 index 082ca8807..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt2701-evb.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Erin Lo - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "mt2701.dtsi" - -/ { - model = "MediaTek MT2701 evaluation board"; - compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; - - memory { - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt2701-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/mt2701-pinfunc.h deleted file mode 100644 index e24ebc8d9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt2701-pinfunc.h +++ /dev/null @@ -1,735 +0,0 @@ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Biao Huang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DTS_MT2701_PINFUNC_H -#define __DTS_MT2701_PINFUNC_H - -#include - -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) -#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) - -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) -#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) - -#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) - -#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) - -#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) - -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) -#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) - -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) -#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7) - -#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) -#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4) -#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7) - -#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) -#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) -#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4) -#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7) - -#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) -#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) -#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) -#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4) -#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7) - -#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) - -#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) - -#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) - -#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) - -#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1) -#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2) -#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) -#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7) - -#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1) -#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2) -#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7) - -#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) -#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) -#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) -#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) -#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6) -#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7) - -#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) -#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) -#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) -#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6) -#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7) - -#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1) -#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2) -#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3) -#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4) -#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) -#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6) -#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7) - -#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1) -#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2) -#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3) -#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4) -#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) -#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6) -#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7) - -#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1) -#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3) -#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) -#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) -#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7) -#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10) - -#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1) -#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3) -#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) -#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) -#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7) -#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10) - -#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1) -#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3) -#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) -#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7) -#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10) - -#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1) -#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3) -#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) -#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7) - -#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1) -#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) -#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3) -#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) -#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) -#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) -#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7) - -#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1) -#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) -#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3) -#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) -#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) -#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7) - -#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) -#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3) -#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) -#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) -#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7) - -#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1) -#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) -#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3) -#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) -#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) -#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7) -#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14) - -#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) -#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) -#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3) -#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) -#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) -#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6) -#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7) - -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6) -#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7) - -#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) -#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) -#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) -#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6) -#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7) - -#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6) -#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7) - -#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) -#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7) - -#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1) -#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) -#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) -#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) - -#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1) -#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) -#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) -#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) - -#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1) -#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) -#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) - -#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1) -#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) -#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) - -#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1) -#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) - -#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1) -#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2) - -#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1) -#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) - -#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1) - -#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1) -#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) - -#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1) -#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) - -#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) -#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) -#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3) -#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6) -#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7) - -#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) -#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3) -#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4) -#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5) -#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7) - -#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) -#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) -#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) -#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7) - -#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) -#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) -#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) -#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4) -#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5) -#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7) - -#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) -#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) -#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7) - -#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1) - -#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1) - -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6) -#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7) - -#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6) -#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7) - -#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) -#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) -#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6) -#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7) - -#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1) - -#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1) - -#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1) - -#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1) - -#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1) -#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2) -#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5) - -#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1) -#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2) - -#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1) -#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2) - -#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1) -#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2) - -#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1) -#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) -#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7) - -#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1) -#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7) - -#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0) -#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1) - -#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) -#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1) - -#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0) -#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1) - -#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0) -#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1) - -#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0) -#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1) - -#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0) -#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1) - -#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0) -#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1) - -#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0) -#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1) - -#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0) -#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1) - -#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0) -#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1) - -#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) -#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3) -#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4) - -#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) -#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) -#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3) -#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4) - -#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) -#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) -#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3) -#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4) - -#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) -#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3) -#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4) - -#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) -#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7) - -#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) -#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7) - -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) -#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7) - -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6) -#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7) - -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6) -#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7) - -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6) -#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7) - -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) -#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4) - -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) -#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4) - -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) -#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4) - -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) -#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4) - -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) -#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4) - -#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) -#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4) - -#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) -#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4) - -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) -#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4) - -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) -#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4) - -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) -#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4) - -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4) -#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) - -#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1) -#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4) -#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5) - -#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1) -#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4) -#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5) - -#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1) -#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4) -#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5) - -#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1) -#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4) -#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5) - -#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6) -#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7) - -#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) -#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3) -#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4) -#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7) - -#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6) -#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7) - -#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6) -#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7) - -#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1) - -#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) -#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1) -#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) -#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5) -#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7) -#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9) - -#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) -#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1) -#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2) -#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5) -#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7) -#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9) - -#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) -#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1) -#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2) -#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5) -#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7) - -#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) -#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1) -#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2) -#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3) -#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5) -#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7) - -#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) -#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1) -#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2) -#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3) -#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5) -#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7) - -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7) -#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11) - -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7) -#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11) - -#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2) -#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7) - -#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) -#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) -#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) - -#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) -#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) -#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2) - -#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) -#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) -#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2) - -#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) -#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) - -#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) -#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) - -#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) -#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1) -#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2) -#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3) -#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4) -#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7) - -#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) -#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1) -#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2) -#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3) -#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4) -#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7) - -#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) -#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1) - -#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) -#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1) - -#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) - -#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) -#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1) - -#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) -#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1) - -#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9) - -#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9) -#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14) - -#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9) -#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14) - -#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9) -#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14) - -#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9) -#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14) - -#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9) -#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14) - -#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9) -#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14) - -#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9) - -#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9) - -#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9) - -#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9) - -#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9) - -#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) -#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) -#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7) - -#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0) -#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) - -#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0) -#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) -#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6) - -#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0) -#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) -#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6) - -#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0) -#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) -#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6) - -#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0) -#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) -#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6) - -#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0) -#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1) - -#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0) -#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1) - -#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0) -#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) - -#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0) -#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) - -#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0) -#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) - -#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0) -#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) - -#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0) -#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) - -#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0) -#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1) -#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6) - -#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0) -#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1) -#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6) - -#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0) -#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) - -#endif /* __DTS_MT2701_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/mt2701.dtsi b/software/linux/kernel/arch/arm/boot/dts/mt2701.dtsi deleted file mode 100644 index 23fe0497f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt2701.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Erin.Lo - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "skeleton64.dtsi" -#include "mt2701-pinfunc.h" - -/ { - compatible = "mediatek,mt2701"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt2701-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - ; - }; - - syscfg_pctl_a: syscfg@10005000 { - compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt2701-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt2701-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt2701-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x1000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt2701-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt2701-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt2701-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt2701-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - hifsys: syscon@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt2701-ethsys", "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - bdpsys: syscon@1c000000 { - compatible = "mediatek,mt2701-bdpsys", "syscon"; - reg = <0 0x1c000000 0 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt6580-evbp1.dts b/software/linux/kernel/arch/arm/boot/dts/mt6580-evbp1.dts deleted file mode 100644 index 17daeae6b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt6580-evbp1.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "mt6580.dtsi" - -/ { - model = "MediaTek MT6580 evaluation board"; - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt6580.dtsi b/software/linux/kernel/arch/arm/boot/dts/mt6580.dtsi deleted file mode 100644 index 06fdf6c2d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt6580.dtsi +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "mediatek,mt6580"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt6580-timer", - "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6580-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x1000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; - - uart0: serial@11005000 { - compatible = "mediatek,mt6580-uart", - "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11006000 { - compatible = "mediatek,mt6580-uart", - "mediatek,mt6577-uart"; - reg = <0x11006000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt6589-aquaris5.dts b/software/linux/kernel/arch/arm/boot/dts/mt6589-aquaris5.dts deleted file mode 100644 index 594a6f3be..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt6589-aquaris5.dts +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Matthias Brugger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "mt6589.dtsi" - -/ { - model = "bq Aquaris5"; - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; - - chosen { - bootargs = "console=ttyS0,921600n8 earlyprintk"; - stdout-path = &uart0; - }; - - memory { - reg = <0x80000000 0x40000000>; - }; - -}; - -&uart0 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt6589.dtsi b/software/linux/kernel/arch/arm/boot/dts/mt6589.dtsi deleted file mode 100644 index 88b3cb128..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt6589.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Matthias Brugger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "mediatek,mt6589"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - timer: timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6589-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x1000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; - - uart0: serial@11006000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11006000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11007000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11007000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11008000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11008000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11009000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11009000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - wdt: watchdog@010000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x44>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt6592-evb.dts b/software/linux/kernel/arch/arm/boot/dts/mt6592-evb.dts deleted file mode 100644 index b57237e63..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt6592-evb.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Howard Chen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "mt6592.dtsi" - -/ { - model = "mt6592 evb"; - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; - - memory { - reg = <0x80000000 0x40000000>; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/mt6592.dtsi b/software/linux/kernel/arch/arm/boot/dts/mt6592.dtsi deleted file mode 100644 index c69201fff..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt6592.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Howard Chen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "mediatek,mt6592"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x4>; - }; - cpu@5 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x5>; - }; - cpu@6 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x6>; - }; - cpu@7 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x7>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200220 { - compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200220 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x1000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11002000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11003000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11004000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt7623-evb.dts b/software/linux/kernel/arch/arm/boot/dts/mt7623-evb.dts deleted file mode 100644 index a9ee2d64c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt7623-evb.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2016 MediaTek Inc. - * Author: John Crispin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "mt7623.dtsi" - -/ { - model = "MediaTek MT7623 evaluation board"; - compatible = "mediatek,mt7623-evb", "mediatek,mt7623"; - - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -&uart2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt7623.dtsi b/software/linux/kernel/arch/arm/boot/dts/mt7623.dtsi deleted file mode 100644 index fd2b614ae..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt7623.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2016 MediaTek Inc. - * Author: John Crispin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "skeleton64.dtsi" - -/ { - compatible = "mediatek,mt7623"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt6589-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt7623-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt7623-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt7623-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x1000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt7623-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt8127-moose.dts b/software/linux/kernel/arch/arm/boot/dts/mt8127-moose.dts deleted file mode 100644 index 073e295a1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt8127-moose.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "mt8127.dtsi" - -/ { - model = "MediaTek MT8127 Moose Board"; - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; - - memory { - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt8127.dtsi b/software/linux/kernel/arch/arm/boot/dts/mt8127.dtsi deleted file mode 100644 index 52086c801..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt8127.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "skeleton64.dtsi" - -/ { - compatible = "mediatek,mt8127"; - interrupt-parent = <&sysirq>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - timer: timer@10008000 { - compatible = "mediatek,mt8127-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt8127-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x1000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt8135-evbp1.dts b/software/linux/kernel/arch/arm/boot/dts/mt8135-evbp1.dts deleted file mode 100644 index 460db6d05..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt8135-evbp1.dts +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "mt8135.dtsi" - -/ { - model = "MediaTek MT8135 evaluation board"; - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; - - memory { - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -&pwrap { - pmic: mt6397 { - compatible = "mediatek,mt6397"; - - mt6397regulator: mt6397regulator { - compatible = "mediatek,mt6397-regulator"; - - mt6397_vpca15_reg: buck_vpca15 { - regulator-name = "vpca15"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vpca7_reg: buck_vpca7 { - regulator-name = "vpca7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca15_reg: buck_vsramca15 { - regulator-name = "vsramca15"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca7_reg: buck_vsramca7 { - regulator-name = "vsramca7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vcore_reg: buck_vcore { - regulator-name = "vcore"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vgpu_reg: buck_vgpu { - regulator-name = "vgpu"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vdrm_reg: buck_vdrm { - regulator-name = "vdrm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vio18_reg: buck_vio18 { - regulator-name = "vio18"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vtcxo_reg: ldo_vtcxo { - regulator-name = "vtcxo"; - regulator-always-on; - }; - - mt6397_va28_reg: ldo_va28 { - regulator-name = "va28"; - regulator-always-on; - }; - - mt6397_vcama_reg: ldo_vcama { - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vio28_reg: ldo_vio28 { - regulator-name = "vio28"; - regulator-always-on; - }; - - mt6397_vusb_reg: ldo_vusb { - regulator-name = "vusb"; - }; - - mt6397_vmc_reg: ldo_vmc { - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vmch_reg: ldo_vmch { - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-name = "vemc_3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp1_reg: ldo_vgp1 { - regulator-name = "vcamd"; - regulator-min-microvolt = <1220000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - mt6397_vgp2_reg: ldo_vgp2 { - regulator-name = "vcamio"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp3_reg: ldo_vgp3 { - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp4_reg: ldo_vgp4 { - regulator-name = "vgp4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp5_reg: ldo_vgp5 { - regulator-name = "vgp5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp6_reg: ldo_vgp6 { - regulator-name = "vgp6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vibr_reg: ldo_vibr { - regulator-name = "vibr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - }; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mt8135-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/mt8135-pinfunc.h deleted file mode 100644 index 5a609875c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt8135-pinfunc.h +++ /dev/null @@ -1,1302 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Hongzhou.Yang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DTS_MT8135_PINFUNC_H -#define __DTS_MT8135_PINFUNC_H - -#include - -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) -#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7) - -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) -#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7) - -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) -#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7) - -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) -#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7) - -#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6) -#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7) - -#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6) -#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7) - -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6) -#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7) - -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6) -#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7) - -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6) -#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7) - -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5) -#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6) - -#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1) -#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2) -#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7) - -#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1) -#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2) -#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6) -#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7) - -#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1) -#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2) -#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3) -#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7) - -#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1) -#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2) -#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3) -#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4) -#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6) -#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7) - -#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1) -#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2) -#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3) -#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4) -#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5) -#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6) -#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7) - -#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1) -#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2) -#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3) -#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4) -#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5) -#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7) - -#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1) -#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2) -#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3) -#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4) -#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5) -#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7) - -#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1) -#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2) -#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3) -#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4) -#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5) -#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6) -#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7) - -#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1) -#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2) -#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3) -#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4) -#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5) -#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6) -#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7) - -#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1) -#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2) -#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3) -#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4) -#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5) -#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6) -#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7) - -#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1) -#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2) -#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3) -#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4) -#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7) - -#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1) -#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2) -#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3) -#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4) -#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7) - -#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1) -#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2) -#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3) -#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4) -#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7) - -#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1) -#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2) -#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3) -#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4) -#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7) - -#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1) -#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2) -#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3) -#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4) -#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7) - -#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1) -#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2) -#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4) - -#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1) -#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2) -#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4) -#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5) - -#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1) -#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2) -#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4) -#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5) - -#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1) -#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2) -#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4) -#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5) - -#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1) -#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2) -#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3) -#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4) -#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5) - -#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1) -#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2) -#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3) -#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4) -#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5) - -#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1) -#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2) -#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3) -#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4) -#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5) - -#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1) -#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2) -#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3) -#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4) -#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5) - -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6) -#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7) - -#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1) -#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2) - -#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1) -#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2) -#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3) -#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4) - -#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1) -#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2) - -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5) -#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7) - -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5) -#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7) - -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5) -#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7) - -#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1) -#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2) -#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3) -#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5) -#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7) - -#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1) -#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2) -#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3) -#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5) -#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7) - -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5) -#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7) - -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1) -#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2) - -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1) -#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2) - -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1) -#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2) - -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1) -#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2) - -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2) -#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7) - -#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1) - -#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1) -#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2) - -#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1) -#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2) - -#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1) -#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2) - -#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1) -#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2) -#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3) -#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4) -#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5) -#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7) - -#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1) -#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2) -#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4) -#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5) -#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7) - -#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1) -#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2) -#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4) -#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5) -#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7) - -#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1) -#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2) -#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5) -#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7) - -#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1) -#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2) -#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5) -#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7) - -#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1) -#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2) -#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3) - -#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1) -#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2) -#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3) - -#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1) -#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2) -#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3) - -#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1) -#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2) -#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3) - -#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1) -#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2) -#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3) - -#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1) -#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2) -#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3) - -#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5) -#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7) - -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5) -#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7) - -#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5) -#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7) - -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2) -#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5) - -#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1) -#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2) -#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3) -#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6) -#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7) - -#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1) -#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2) -#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) -#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6) -#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7) - -#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1) -#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2) -#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3) -#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6) -#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7) - -#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1) -#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2) -#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3) -#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6) -#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7) - -#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1) -#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2) -#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5) -#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6) -#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7) - -#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1) -#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2) -#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5) -#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6) -#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7) - -#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1) -#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2) -#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) -#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) -#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7) - -#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1) -#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2) -#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3) -#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4) -#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5) -#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) -#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7) - -#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1) -#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2) -#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3) -#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4) -#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) -#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) -#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7) - -#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1) -#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2) -#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3) -#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4) -#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) -#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7) - -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6) -#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7) - -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6) -#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7) - -#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6) -#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7) - -#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6) -#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7) - -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5) -#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6) - -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5) -#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6) - -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5) -#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7) - -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5) -#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7) - -#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5) -#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7) - -#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4) -#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7) - -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5) -#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7) - -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5) -#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7) - -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6) -#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7) - -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6) -#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7) - -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6) -#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7) - -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6) -#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7) - -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6) -#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7) - -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6) -#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7) - -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6) -#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7) - -#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6) -#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7) - -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6) -#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7) - -#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5) -#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7) - -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6) -#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7) - -#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1) -#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2) -#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3) -#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4) -#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7) - -#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1) -#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2) -#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3) -#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4) -#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7) - -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6) -#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7) - -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6) -#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7) - -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6) -#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7) - -#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1) -#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2) -#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3) -#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4) -#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5) -#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6) -#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7) - -#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1) -#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2) -#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3) -#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4) -#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5) -#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6) -#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7) - -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6) -#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7) - -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6) -#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7) - -#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1) -#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2) -#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3) -#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4) -#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) -#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6) -#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7) - -#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1) -#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2) -#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3) -#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4) -#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) -#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6) -#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7) - -#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1) -#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2) -#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3) -#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4) -#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) -#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6) -#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7) - -#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1) -#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2) -#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3) -#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4) -#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) -#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6) -#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7) - -#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1) -#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4) -#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5) -#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6) -#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7) - -#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1) -#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2) -#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5) -#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6) -#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7) - -#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1) -#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2) -#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5) -#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6) -#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7) - -#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1) -#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2) -#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5) -#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7) - -#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1) -#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2) -#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3) -#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5) -#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7) - -#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1) -#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2) -#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3) -#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5) -#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6) -#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7) - -#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1) -#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5) -#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6) -#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7) - -#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1) -#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2) -#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5) -#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7) - -#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1) -#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2) -#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3) -#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4) -#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5) -#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6) - -#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1) -#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2) -#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3) -#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5) -#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6) - -#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1) -#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2) -#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4) -#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5) - -#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1) -#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2) -#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4) -#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5) - -#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1) -#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2) -#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4) - -#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1) -#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2) -#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5) - -#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1) -#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2) -#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3) -#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4) -#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5) - -#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1) -#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2) -#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3) -#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4) -#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5) -#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6) - -#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1) -#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2) -#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4) -#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5) - -#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1) -#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2) -#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3) -#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4) -#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5) - -#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1) -#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2) -#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3) -#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4) -#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5) - -#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1) -#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2) -#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3) -#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4) -#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5) - -#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1) -#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2) -#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3) -#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4) -#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5) - -#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1) -#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2) -#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3) -#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4) -#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5) - -#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1) -#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2) -#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3) -#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4) -#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5) - -#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1) -#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2) -#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3) -#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4) -#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5) - -#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1) -#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2) -#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5) - -#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1) -#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2) -#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5) - -#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1) -#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2) -#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5) - -#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1) -#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2) -#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4) - -#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1) -#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2) -#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4) - -#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1) -#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2) -#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4) - -#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1) -#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2) -#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4) - -#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1) -#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2) -#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4) - -#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1) -#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2) -#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4) - -#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1) -#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2) -#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4) - -#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1) -#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2) -#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4) - -#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1) -#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2) -#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4) - -#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2) - -#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2) - -#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2) - -#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2) - -#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2) - -#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2) - -#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2) - -#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2) - -#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2) - -#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2) - -#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2) - -#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2) - -#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2) - -#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2) - -#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2) - -#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2) - -#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) - -#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) - -#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) - -#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) - -#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1) -#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2) - -#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1) -#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2) - -#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1) -#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2) - -#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1) -#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2) - -#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1) -#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2) - -#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1) -#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2) - -#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1) -#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2) -#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3) - -#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) -#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1) -#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2) -#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3) - -#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) -#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1) -#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2) - -#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) -#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1) -#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2) - -#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) -#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1) -#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2) -#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3) - -#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) -#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1) -#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2) -#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3) - -#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) -#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1) -#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2) -#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3) -#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4) -#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5) -#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6) -#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7) - -#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) -#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1) -#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2) -#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5) -#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7) - -#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) -#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1) -#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2) -#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5) -#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7) - -#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) -#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1) -#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2) -#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5) -#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7) - -#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) -#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1) -#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2) -#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3) -#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6) -#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7) - -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6) -#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7) - -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4) -#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6) - -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6) -#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7) - -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4) -#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6) - -#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) -#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1) - -#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) -#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1) -#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2) -#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3) -#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5) -#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6) - -#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) -#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1) -#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2) -#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3) -#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5) -#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6) - -#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) -#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1) -#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2) -#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3) -#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4) -#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5) - -#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) -#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1) -#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2) -#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3) -#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4) -#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5) - -#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) -#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1) -#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2) -#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3) -#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4) -#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5) - -#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) -#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1) -#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2) -#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3) -#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4) -#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5) - -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5) -#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6) - -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5) -#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6) - -#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5) -#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6) - -#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4) -#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5) - -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4) -#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5) - -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4) -#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5) - -#endif /* __DTS_MT8135_PINFUNC_H */ diff --git a/software/linux/kernel/arch/arm/boot/dts/mt8135.dtsi b/software/linux/kernel/arch/arm/boot/dts/mt8135.dtsi deleted file mode 100644 index 1d7f92bdc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mt8135.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "skeleton64.dtsi" -#include "mt8135-pinfunc.h" - -/ { - compatible = "mediatek,mt8135"; - interrupt-parent = <&sysirq>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x001>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - clk26m: clk26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - topckgen: topckgen@10000000 { - compatible = "mediatek,mt8135-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: infracfg@10001000 { - #reset-cells = <1>; - #clock-cells = <1>; - compatible = "mediatek,mt8135-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - }; - - pericfg: pericfg@10003000 { - #reset-cells = <1>; - #clock-cells = <1>; - compatible = "mediatek,mt8135-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - }; - - /* - * Pinctrl access register at 0x10005000 and 0x1020c000 through - * regmap. Register 0x1000b000 is used by EINT. - */ - pio: pinctrl@10005000 { - compatible = "mediatek,mt8135-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - ; - }; - - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt8135-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; - reg = <0 0x1000f000 0 0x1000>, - <0 0x11017000 0 0x1000>; - reg-names = "pwrap", "pwrap-bridge"; - interrupts = ; - resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, - <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; - reset-names = "pwrap", "pwrap-bridge"; - clocks = <&clk26m>, <&clk26m>; - clock-names = "spi", "wrap"; - }; - - sysirq: interrupt-controller@10200030 { - compatible = "mediatek,mt8135-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200030 0 0x1c>; - }; - - apmixedsys: apmixedsys@10209000 { - compatible = "mediatek,mt8135-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - syscfg_pctl_b: syscfg_pctl_b@1020c000 { - compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; - reg = <0 0x1020c000 0 0x1000>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x1000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11006000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11006000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11007000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11007000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11008000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11008000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11009000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11009000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mvebu-linkstation-fan.dtsi b/software/linux/kernel/arch/arm/boot/dts/mvebu-linkstation-fan.dtsi deleted file mode 100644 index e211a3c47..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mvebu-linkstation-fan.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Device Tree common file for gpio-fan on Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - - gpio-fan,speed-map = - <0 3 - 1500 2 - 3250 1 - 5000 0>; - }; -}; - -&pinctrl { - pmx_fan_low: pmx-fan-low { - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi b/software/linux/kernel/arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi deleted file mode 100644 index 68d75e79a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Device Tree common file for gpio-{keys,leds} on Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_switch>; - pinctrl-names = "default"; - - power-on-switch { - label = "Power-on Switch"; - linux,code = ; - linux,input-type = <5>; - }; - - power-auto-switch { - label = "Power-auto Switch"; - linux,code = ; - linux,input-type = <5>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info>; - pinctrl-names = "default"; - - blue-power-led { - label = "linkstation:blue:power"; - default-state = "keep"; - }; - - red-alarm-led { - label = "linkstation:red:alarm"; - }; - - amber-info-led { - label = "linkstation:amber:info"; - }; - }; -}; - -&pinctrl { - pmx_power_switch: pmx-power-switch { - marvell,function = "gpio"; - }; - - pmx_led_power: pmx-leds { - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,function = "gpio"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/mxs-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/mxs-pinfunc.h deleted file mode 100644 index c6da987b2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/mxs-pinfunc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ -#define __DT_BINDINGS_MXS_PINCTRL_H__ - -/* fsl,drive-strength property */ -#define MXS_DRIVE_4mA 0 -#define MXS_DRIVE_8mA 1 -#define MXS_DRIVE_12mA 2 -#define MXS_DRIVE_16mA 3 - -/* fsl,voltage property */ -#define MXS_VOLTAGE_LOW 0 -#define MXS_VOLTAGE_HIGH 1 - -/* fsl,pull-up property */ -#define MXS_PULL_DISABLE 0 -#define MXS_PULL_ENABLE 1 - -#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ diff --git a/software/linux/kernel/arch/arm/boot/dts/nspire-classic.dtsi b/software/linux/kernel/arch/arm/boot/dts/nspire-classic.dtsi deleted file mode 100644 index 4907c5085..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/nspire-classic.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -/* - * linux/arch/arm/boot/nspire-classic.dts - * - * Copyright (C) 2013 Daniel Tang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ - -/include/ "nspire.dtsi" - -&lcd { - lcd-type = "classic"; -}; - -&fast_timer { - /* compatible = "lsi,zevio-timer"; */ - reg = <0x90010000 0x1000>, <0x900A0010 0x8>; -}; - -&uart { - compatible = "ns16550"; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb_pclk>; - no-loopback-test; -}; - -&timer0 { - /* compatible = "lsi,zevio-timer"; */ - reg = <0x900C0000 0x1000>, <0x900A0018 0x8>; -}; - -&timer1 { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; -}; - -&keypad { - active-low; - -}; - -&base_clk { - compatible = "lsi,nspire-classic-clock"; -}; - -&ahb_clk { - compatible = "lsi,nspire-classic-ahb-divider"; -}; - - -&vbus_reg { - gpio = <&gpio 5 0>; -}; - -/ { - memory { - device_type = "memory"; - reg = <0x10000000 0x2000000>; /* 32 MB */ - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - - intc: interrupt-controller@DC000000 { - compatible = "lsi,zevio-intc"; - interrupt-controller; - reg = <0xDC000000 0x1000>; - #interrupt-cells = <1>; - }; - }; - chosen { - bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/nspire-clp.dts b/software/linux/kernel/arch/arm/boot/dts/nspire-clp.dts deleted file mode 100644 index fa5a04465..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/nspire-clp.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * linux/arch/arm/boot/nspire-clp.dts - * - * Copyright (C) 2013 Daniel Tang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ -/dts-v1/; - -/include/ "nspire-classic.dtsi" - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00020039 - 0x0004002c 0x00050034 0x00060015 - 0x0007000b 0x0008002d 0x01000033 - 0x0101004e 0x01020011 0x01030004 - 0x0104002f 0x01050003 0x01060016 - 0x01070002 0x01080014 0x02000062 - 0x0201000c 0x0202001f 0x02030007 - 0x02040013 0x02050006 0x02060010 - 0x02070005 0x02080019 0x03000027 - 0x03010037 0x03020018 0x0303000a - 0x03040031 0x03050009 0x03060032 - 0x03070008 0x03080026 0x04000028 - 0x04010035 0x04020025 0x04040024 - 0x04060017 0x04080023 0x05000028 - 0x05020022 0x0503001b 0x05040021 - 0x0505001a 0x05060012 0x0507006f - 0x05080020 0x0509002a 0x0601001c - 0x0602002e 0x06030068 0x06040030 - 0x0605006d 0x0606001e 0x06070001 - 0x0608002b 0x0609000f 0x07000067 - 0x0702006a 0x0704006c 0x07060069 - 0x0707000e 0x0708001d 0x070a000d - >; -}; - -/ { - model = "TI-NSPIRE Clickpad"; - compatible = "ti,nspire-clp"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/nspire-cx.dts b/software/linux/kernel/arch/arm/boot/dts/nspire-cx.dts deleted file mode 100644 index 08e0b81b3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/nspire-cx.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * linux/arch/arm/boot/nspire-cx.dts - * - * Copyright (C) 2013 Daniel Tang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ -/dts-v1/; - -/include/ "nspire.dtsi" - -&lcd { - lcd-type = "cx"; -}; - -&fast_timer { - /* compatible = "arm,sp804", "arm,primecell"; */ -}; - -&uart { - compatible = "arm,pl011", "arm,primecell"; - - clocks = <&uart_clk>, <&apb_pclk>; - clock-names = "uart_clk", "apb_pclk"; -}; - -&timer0 { - compatible = "arm,sp804", "arm,primecell"; -}; - -&timer1 { - compatible = "arm,sp804", "arm,primecell"; -}; - -&base_clk { - compatible = "lsi,nspire-cx-clock"; -}; - -&ahb_clk { - compatible = "lsi,nspire-cx-ahb-divider"; -}; - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; -}; - -&vbus_reg { - gpio = <&gpio 2 0>; -}; - -/ { - model = "TI-NSPIRE CX"; - compatible = "ti,nspire-cx"; - - memory { - device_type = "memory"; - reg = <0x10000000 0x4000000>; /* 64 MB */ - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - - intc: interrupt-controller@DC000000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xDC000000 0x1000>; - #interrupt-cells = <1>; - }; - - apb@90000000 { - #address-cells = <1>; - #size-cells = <1>; - - i2c@90050000 { - compatible = "snps,designware-i2c"; - reg = <0x90050000 0x1000>; - interrupts = <20>; - }; - }; - }; - chosen { - bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/nspire-tp.dts b/software/linux/kernel/arch/arm/boot/dts/nspire-tp.dts deleted file mode 100644 index 621391ce6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/nspire-tp.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* - * linux/arch/arm/boot/nspire-tp.dts - * - * Copyright (C) 2013 Daniel Tang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ -/dts-v1/; - -/include/ "nspire-classic.dtsi" - -&keypad { - linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; -}; - -/ { - model = "TI-NSPIRE Touchpad"; - compatible = "ti,nspire-tp"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/nspire.dtsi b/software/linux/kernel/arch/arm/boot/dts/nspire.dtsi deleted file mode 100644 index ee5a0bb22..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/nspire.dtsi +++ /dev/null @@ -1,196 +0,0 @@ -/* - * linux/arch/arm/boot/nspire.dtsi - * - * Copyright (C) 2013 Daniel Tang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ - -/include/ "skeleton.dtsi" - -/ { - interrupt-parent = <&intc>; - - cpus { - cpu@0 { - compatible = "arm,arm926ej-s"; - }; - }; - - bootrom: bootrom@00000000 { - reg = <0x00000000 0x80000>; - }; - - sram: sram@A4000000 { - device = "memory"; - reg = <0xA4000000 0x20000>; - }; - - timer_clk: timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - base_clk: base_clk { - #clock-cells = <0>; - reg = <0x900B0024 0x4>; - }; - - ahb_clk: ahb_clk { - #clock-cells = <0>; - reg = <0x900B0024 0x4>; - clocks = <&base_clk>; - }; - - apb_pclk: apb_pclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&ahb_clk>; - }; - - usb_phy: usb_phy { - compatible = "usb-nop-xceiv"; - }; - - vbus_reg: vbus_reg { - compatible = "regulator-fixed"; - - regulator-name = "USB VBUS output"; - regulator-type = "voltage"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - spi: spi@A9000000 { - reg = <0xA9000000 0x1000>; - }; - - usb0: usb@B0000000 { - compatible = "lsi,zevio-usb"; - reg = <0xB0000000 0x1000>; - interrupts = <8>; - - usb-phy = <&usb_phy>; - vbus-supply = <&vbus_reg>; - }; - - usb1: usb@B4000000 { - reg = <0xB4000000 0x1000>; - interrupts = <9>; - status = "disabled"; - }; - - lcd: lcd@C0000000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0xC0000000 0x1000>; - interrupts = <21>; - - clocks = <&apb_pclk>; - clock-names = "apb_pclk"; - }; - - adc: adc@C4000000 { - reg = <0xC4000000 0x1000>; - interrupts = <11>; - }; - - tdes: crypto@C8010000 { - reg = <0xC8010000 0x1000>; - }; - - sha256: crypto@CC000000 { - reg = <0xCC000000 0x1000>; - }; - - apb@90000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - clock-ranges; - ranges; - - gpio: gpio@90000000 { - compatible = "lsi,zevio-gpio"; - reg = <0x90000000 0x1000>; - interrupts = <7>; - gpio-controller; - #gpio-cells = <2>; - }; - - fast_timer: timer@90010000 { - reg = <0x90010000 0x1000>; - interrupts = <17>; - }; - - uart: serial@90020000 { - reg = <0x90020000 0x1000>; - interrupts = <1>; - }; - - timer0: timer@900C0000 { - reg = <0x900C0000 0x1000>; - - clocks = <&timer_clk>; - }; - - timer1: timer@900D0000 { - reg = <0x900D0000 0x1000>; - interrupts = <19>; - - clocks = <&timer_clk>; - }; - - watchdog: watchdog@90060000 { - compatible = "arm,amba-primecell"; - reg = <0x90060000 0x1000>; - interrupts = <3>; - }; - - rtc: rtc@90090000 { - reg = <0x90090000 0x1000>; - interrupts = <4>; - }; - - misc: misc@900A0000 { - reg = <0x900A0000 0x1000>; - }; - - pwr: pwr@900B0000 { - reg = <0x900B0000 0x1000>; - interrupts = <15>; - }; - - keypad: input@900E0000 { - compatible = "ti,nspire-keypad"; - reg = <0x900E0000 0x1000>; - interrupts = <16>; - - scan-interval = <1000>; - row-delay = <200>; - - clocks = <&apb_pclk>; - }; - - contrast: contrast@900F0000 { - reg = <0x900F0000 0x1000>; - }; - - led: led@90110000 { - reg = <0x90110000 0x1000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi deleted file mode 100644 index 445fafc73..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Common file for GPMC connected smsc911x on omaps - * - * Note that the board specifc DTS file needs to specify - * ranges, pinctrl, reg, interrupt parent and interrupts. - */ - -/ { - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&gpmc { - ethernet@gpmc { - compatible = "smsc,lan9221", "smsc,lan9115"; - bank-width = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <150>; - gpmc,cs-wr-off-ns = <150>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <15>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <140>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <140>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <120>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <75>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi deleted file mode 100644 index 73e272fad..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Common file for GPMC connected smsc9221 on omaps - * - * Compared to smsc911x, smsc9221 (and others like smsc9217 - * or smsc 9218) has faster timings, leading to higher - * bandwidth. - * - * Note that the board specifc DTS file needs to specify - * ranges, pinctrl, reg, interrupt parent and interrupts. - */ - -/ { - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&gpmc { - ethernet@gpmc { - compatible = "smsc,lan9221","smsc,lan9115"; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <42>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <42>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <36>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <54>; - gpmc,access-ns = <36>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wr-data-mux-bus-ns = <18>; - gpmc,wr-access-ns = <42>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap-zoom-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap-zoom-common.dtsi deleted file mode 100644 index 46ef3e443..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap-zoom-common.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Common features on the Zoom debug board - */ - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */ - <7 0 0x2c000000 0x01000000>; - - /* - * Four port TL16CP754C serial port on GPMC, - * they probably share the same GPIO IRQ - * REVISIT: Add timing support from slls644g.pdf - */ - uart@3,0 { - compatible = "ns16550a"; - reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - gpmc,mux-add-data = <0>; - gpmc,device-width = <1>; - gpmc,wait-pin = <1>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <155>; - gpmc,cs-wr-off-ns = <155>; - gpmc,adv-on-ns = <15>; - gpmc,adv-rd-off-ns = <40>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <145>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <145>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <145>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <20>; - gpmc,cycle2cycle-delay-ns = <20>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <45>; - gpmc,wr-access-ns = <145>; - }; - uart@3,1 { - compatible = "ns16550a"; - reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - uart@3,2 { - compatible = "ns16550a"; - reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - uart@3,3 { - compatible = "ns16550a"; - reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - - ethernet@gpmc { - reg = <7 0 0xff>; - interrupt-parent = <&gpio5>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */ - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap2.dtsi deleted file mode 100644 index f1d6de8b3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2.dtsi +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Device Tree Source for OMAP2 SoC - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include - -/ { - compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &i2c1; - i2c1 = &i2c2; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - }; - }; - - pmu { - compatible = "arm,arm1136-pmu"; - interrupts = <3>; - }; - - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap2-mpu"; - ti,hwmods = "mpu"; - }; - }; - - ocp { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - aes: aes@480a6000 { - compatible = "ti,omap2-aes"; - ti,hwmods = "aes"; - reg = <0x480a6000 0x50>; - dmas = <&sdma 9 &sdma 10>; - dma-names = "tx", "rx"; - }; - - hdq1w: 1w@480b2000 { - compatible = "ti,omap2420-1w"; - ti,hwmods = "hdq1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - }; - - intc: interrupt-controller@1 { - compatible = "ti,omap2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x480FE000 0x1000>; - }; - - sdma: dma-controller@48056000 { - compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; - ti,hwmods = "dma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <64>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap2-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48070000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap2-i2c"; - ti,hwmods = "i2c2"; - reg = <0x48072000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; - }; - - mcspi1: mcspi@48098000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi1"; - reg = <0x48098000 0x100>; - interrupts = <65>; - dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 - &sdma 39 &sdma 40 &sdma 41 &sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: mcspi@4809a000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi2"; - reg = <0x4809a000 0x100>; - interrupts = <66>; - dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - rng: rng@480a0000 { - compatible = "ti,omap2-rng"; - ti,hwmods = "rng"; - reg = <0x480a0000 0x50>; - interrupts = <52>; - }; - - sham: sham@480a4000 { - compatible = "ti,omap2-sham"; - ti,hwmods = "sham"; - reg = <0x480a4000 0x64>; - interrupts = <51>; - dmas = <&sdma 13>; - dma-names = "rx"; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart1"; - reg = <0x4806a000 0x2000>; - interrupts = <72>; - dmas = <&sdma 49 &sdma 50>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart2"; - reg = <0x4806c000 0x400>; - interrupts = <73>; - dmas = <&sdma 51 &sdma 52>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - uart3: serial@4806e000 { - compatible = "ti,omap2-uart"; - ti,hwmods = "uart3"; - reg = <0x4806e000 0x400>; - interrupts = <74>; - dmas = <&sdma 53 &sdma 54>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - timer2: timer@4802a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4802a000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48078000 { - compatible = "ti,omap2420-timer"; - reg = <0x48078000 0x400>; - interrupts = <39>; - ti,hwmods = "timer3"; - }; - - timer4: timer@4807a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807a000 0x400>; - interrupts = <40>; - ti,hwmods = "timer4"; - }; - - timer5: timer@4807c000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807c000 0x400>; - interrupts = <41>; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@4807e000 { - compatible = "ti,omap2420-timer"; - reg = <0x4807e000 0x400>; - interrupts = <42>; - ti,hwmods = "timer6"; - ti,timer-dsp; - }; - - timer7: timer@48080000 { - compatible = "ti,omap2420-timer"; - reg = <0x48080000 0x400>; - interrupts = <43>; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@48082000 { - compatible = "ti,omap2420-timer"; - reg = <0x48082000 0x400>; - interrupts = <44>; - ti,hwmods = "timer8"; - ti,timer-dsp; - }; - - timer9: timer@48084000 { - compatible = "ti,omap2420-timer"; - reg = <0x48084000 0x400>; - interrupts = <45>; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap2420-timer"; - reg = <0x48086000 0x400>; - interrupts = <46>; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap2420-timer"; - reg = <0x48088000 0x400>; - interrupts = <47>; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - timer12: timer@4808a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4808a000 0x400>; - interrupts = <48>; - ti,hwmods = "timer12"; - ti,timer-pwm; - }; - - dss: dss@48050000 { - compatible = "ti,omap2-dss"; - reg = <0x48050000 0x400>; - status = "disabled"; - ti,hwmods = "dss_core"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@48050400 { - compatible = "ti,omap2-dispc"; - reg = <0x48050400 0x400>; - interrupts = <25>; - ti,hwmods = "dss_dispc"; - }; - - rfbi: encoder@48050800 { - compatible = "ti,omap2-rfbi"; - reg = <0x48050800 0x400>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - }; - - venc: encoder@48050c00 { - compatible = "ti,omap2-venc"; - reg = <0x48050c00 0x400>; - status = "disabled"; - ti,hwmods = "dss_venc"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2420-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap2420-clocks.dtsi deleted file mode 100644 index f8e5bd3cc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2420-clocks.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Device Tree Source for OMAP2420 clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -&prcm_clocks { - sys_clkout2_src_gate: sys_clkout2_src_gate@70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <15>; - reg = <0x0070>; - }; - - sys_clkout2_src_mux: sys_clkout2_src_mux@70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; - ti,bit-shift = <8>; - reg = <0x0070>; - }; - - sys_clkout2_src: sys_clkout2_src { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; - }; - - sys_clkout2: sys_clkout2@70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkout2_src>; - ti,bit-shift = <11>; - ti,max-div = <64>; - reg = <0x0070>; - ti,index-power-of-two; - }; - - dsp_gate_ick: dsp_gate_ick@810 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <1>; - reg = <0x0810>; - }; - - dsp_div_ick: dsp_div_ick@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0840>; - ti,index-starts-at-one; - }; - - dsp_ick: dsp_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dsp_gate_ick>, <&dsp_div_ick>; - }; - - iva1_gate_ifck: iva1_gate_ifck@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <10>; - reg = <0x0800>; - }; - - iva1_div_ifck: iva1_div_ifck@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <8>; - reg = <0x0840>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; - }; - - iva1_ifck: iva1_ifck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>; - }; - - iva1_ifck_div: iva1_ifck_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&iva1_ifck>; - clock-mult = <1>; - clock-div = <2>; - }; - - iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&iva1_ifck_div>; - ti,bit-shift = <8>; - reg = <0x0800>; - }; - - wdt3_ick: wdt3_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <28>; - reg = <0x0210>; - }; - - wdt3_fck: wdt3_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <28>; - reg = <0x0200>; - }; - - mmc_ick: mmc_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <26>; - reg = <0x0210>; - }; - - mmc_fck: mmc_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <26>; - reg = <0x0200>; - }; - - eac_ick: eac_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <24>; - reg = <0x0210>; - }; - - eac_fck: eac_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <24>; - reg = <0x0200>; - }; - - i2c1_fck: i2c1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <19>; - reg = <0x0200>; - }; - - i2c2_fck: i2c2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <20>; - reg = <0x0200>; - }; - - vlynq_ick: vlynq_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <3>; - reg = <0x0210>; - }; - - vlynq_gate_fck: vlynq_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <3>; - reg = <0x0200>; - }; - - core_d18_ck: core_d18_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <18>; - }; - - vlynq_mux_fck: vlynq_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>; - ti,bit-shift = <15>; - reg = <0x0240>; - }; - - vlynq_fck: vlynq_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>; - }; -}; - -&prcm_clockdomains { - gfx_clkdm: gfx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_ick>; - }; - - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, - <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, - <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>; - }; - - iva1_clkdm: iva1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&iva1_mpu_int_ifck>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_ick>, <&dss_54m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, - <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, - <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, - <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>, - <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, - <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, - <&uart3_ick>, <&uart3_fck>, <&cam_ick>, - <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>, - <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>, - <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>, - <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>, - <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>, - <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, - <&pka_ick>; - }; -}; - -&func_96m_ck { - compatible = "fixed-factor-clock"; - clocks = <&apll96_ck>; - clock-mult = <1>; - clock-div = <1>; -}; - -&dsp_div_fck { - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; -}; - -&ssi_ssr_sst_div_fck { - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2420-h4.dts b/software/linux/kernel/arch/arm/boot/dts/omap2420-h4.dts deleted file mode 100644 index 9265c0b9c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2420-h4.dts +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap2420.dtsi" - -/ { - model = "TI OMAP2420 H4 board"; - compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x4000000>; /* 64 MB */ - }; -}; - -&gpmc { - ranges = <0 0 0x08000000 0x04000000>; - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,ge28f256l18b85"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x04000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <20>; - gpmc,adv-rd-off-ns = <50>; - gpmc,adv-wr-off-ns = <50>; - gpmc,oe-on-ns = <60>; - gpmc,oe-off-ns = <120>; - gpmc,we-on-ns = <60>; - gpmc,we-off-ns = <120>; - gpmc,rd-cycle-ns = <170>; - gpmc,wr-cycle-ns = <170>; - gpmc,access-ns = <150>; - gpmc,page-burst-access-ns = <10>; - - partition@0 { - label = "bootloader"; - reg = <0 0x20000>; - }; - partition@20000 { - label = "params"; - reg = <0x20000 0x20000>; - }; - partition@40000 { - label = "kernel"; - reg = <0x40000 0x200000>; - }; - partition@240000 { - label = "file-system"; - reg = <0x240000 0x3dc0000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2420-n800.dts b/software/linux/kernel/arch/arm/boot/dts/omap2420-n800.dts deleted file mode 100644 index d8c1b4236..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2420-n800.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N800"; - compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2420-n810-wimax.dts b/software/linux/kernel/arch/arm/boot/dts/omap2420-n810-wimax.dts deleted file mode 100644 index 6b25b0359..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2420-n810-wimax.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N810 WiMax"; - compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2420-n810.dts b/software/linux/kernel/arch/arm/boot/dts/omap2420-n810.dts deleted file mode 100644 index b604d26bd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2420-n810.dts +++ /dev/null @@ -1,15 +0,0 @@ -/dts-v1/; - -#include "omap2420-n8x0-common.dtsi" - -/ { - model = "Nokia N810"; - compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; -}; - -&i2c2 { - aic3x@18 { - compatible = "tlv320aic3x"; - reg = <0x18>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap2420-n8x0-common.dtsi deleted file mode 100644 index 7e5ffc583..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -#include "omap2420.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - ocp { - i2c0 { - compatible = "i2c-cbus-gpio"; - gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */ - &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */ - &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */ - >; - #address-cells = <1>; - #size-cells = <0>; - retu_mfd: retu@1 { - compatible = "retu-mfd"; - interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - reg = <0x1>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - pmic@72 { - compatible = "menelaus"; - reg = <0x72>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - - /* gpio-irq for dma: 26 */ - - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <127>; - gpmc,cs-wr-off-ns = <109>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <18>; - gpmc,oe-on-ns = <27>; - gpmc,oe-off-ns = <127>; - gpmc,we-on-ns = <27>; - gpmc,we-off-ns = <72>; - gpmc,rd-cycle-ns = <145>; - gpmc,wr-cycle-ns = <136>; - gpmc,access-ns = <118>; - gpmc,page-burst-access-ns = <27>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <9>; - gpmc,sync-clk-ps = <27000>; - - /* MTD partition table corresponding to old board-n8x0 file. */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@1 { - label = "config"; - reg = <0x00020000 0x00060000>; - }; - partition@2 { - label = "kernel"; - reg = <0x00080000 0x00200000>; - }; - partition@3 { - label = "initfs"; - reg = <0x00280000 0x00400000>; - }; - partition@4 { - label = "rootfs"; - reg = <0x00680000 0x0f980000>; - }; - partition@5 { - label = "omap2-onenand"; - reg = <0x00000000 0x10000000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2420.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap2420.dtsi deleted file mode 100644 index fb712b9aa..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2420.dtsi +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Device Tree Source for OMAP2420 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "omap2.dtsi" - -/ { - compatible = "ti,omap2420", "ti,omap2"; - - ocp { - l4: l4@48000000 { - compatible = "ti,omap2-l4", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x100000>; - - prcm: prcm@8000 { - compatible = "ti,omap2-prcm"; - reg = <0x8000 0x1000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@0 { - compatible = "ti,omap2-scm", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x1000>; - - omap2420_pmx: pinmux@30 { - compatible = "ti,omap2420-padconf", - "pinctrl-single"; - reg = <0x30 0x0113>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon"; - reg = <0x270 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - scm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x20>; - ti,hwmods = "counter_32k"; - }; - }; - - gpio1: gpio@48018000 { - compatible = "ti,omap2-gpio"; - reg = <0x48018000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@4801a000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801a000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@4801c000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801c000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@4801e000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801e000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpmc: gpmc@6800a000 { - compatible = "ti,omap2420-gpmc"; - reg = <0x6800a000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap2420-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <59>, /* TX interrupt */ - <60>; /* RX interrupt */ - interrupt-names = "tx", "rx"; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@48076000 { - compatible = "ti,omap2420-mcbsp"; - reg = <0x48076000 0xff>; - reg-names = "mpu"; - interrupts = <62>, /* TX interrupt */ - <63>; /* RX interrupt */ - interrupt-names = "tx", "rx"; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - msdi1: mmc@4809c000 { - compatible = "ti,omap2420-mmc"; - ti,hwmods = "msdi1"; - reg = <0x4809c000 0x80>; - interrupts = <83>; - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap2-mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>, <34>; - interrupt-names = "dsp", "iva"; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <6>; - mbox_dsp: dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_iva: iva { - ti,mbox-tx = <2 1 3>; - ti,mbox-rx = <3 1 3>; - }; - }; - - timer1: timer@48028000 { - compatible = "ti,omap2420-timer"; - reg = <0x48028000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - wd_timer2: wdt@48022000 { - compatible = "ti,omap2-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x48022000 0x80>; - }; - }; -}; - -&i2c1 { - compatible = "ti,omap2420-i2c"; -}; - -&i2c2 { - compatible = "ti,omap2420-i2c"; -}; - -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2420-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2430-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap2430-clocks.dtsi deleted file mode 100644 index a5aa7d619..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2430-clocks.dtsi +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Device Tree Source for OMAP2430 clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -&scm_clocks { - mcbsp3_mux_fck: mcbsp3_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - reg = <0x78>; - }; - - mcbsp3_fck: mcbsp3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; - }; - - mcbsp4_mux_fck: mcbsp4_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x78>; - }; - - mcbsp4_fck: mcbsp4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; - }; - - mcbsp5_mux_fck: mcbsp5_mux_fck@78 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x78>; - }; - - mcbsp5_fck: mcbsp5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; - }; -}; - -&prcm_clocks { - iva2_1_gate_ick: iva2_1_gate_ick@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <0>; - reg = <0x0800>; - }; - - iva2_1_div_ick: iva2_1_div_ick@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dsp_fck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0840>; - ti,index-starts-at-one; - }; - - iva2_1_ick: iva2_1_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; - }; - - mdm_gate_ick: mdm_gate_ick@c10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0c10>; - }; - - mdm_div_ick: mdm_div_ick@c40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - reg = <0x0c40>; - ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>; - }; - - mdm_ick: mdm_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mdm_gate_ick>, <&mdm_div_ick>; - }; - - mdm_osc_ck: mdm_osc_ck@c00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&osc_ck>; - ti,bit-shift = <1>; - reg = <0x0c00>; - }; - - mcbsp3_ick: mcbsp3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <3>; - reg = <0x0214>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <3>; - reg = <0x0204>; - }; - - mcbsp4_ick: mcbsp4_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x0214>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x0204>; - }; - - mcbsp5_ick: mcbsp5_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <5>; - reg = <0x0214>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <5>; - reg = <0x0204>; - }; - - mcspi3_ick: mcspi3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <9>; - reg = <0x0214>; - }; - - mcspi3_fck: mcspi3_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <9>; - reg = <0x0204>; - }; - - icr_ick: icr_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0410>; - }; - - i2chs1_fck: i2chs1_fck@204 { - #clock-cells = <0>; - compatible = "ti,omap2430-interface-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <19>; - reg = <0x0204>; - }; - - i2chs2_fck: i2chs2_fck@204 { - #clock-cells = <0>; - compatible = "ti,omap2430-interface-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <20>; - reg = <0x0204>; - }; - - usbhs_ick: usbhs_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <6>; - reg = <0x0214>; - }; - - mmchs1_ick: mmchs1_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <7>; - reg = <0x0214>; - }; - - mmchs1_fck: mmchs1_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <7>; - reg = <0x0204>; - }; - - mmchs2_ick: mmchs2_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <8>; - reg = <0x0214>; - }; - - mmchs2_fck: mmchs2_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <8>; - reg = <0x0204>; - }; - - gpio5_ick: gpio5_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <10>; - reg = <0x0214>; - }; - - gpio5_fck: gpio5_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <10>; - reg = <0x0204>; - }; - - mdm_intc_ick: mdm_intc_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <11>; - reg = <0x0214>; - }; - - mmchsdb1_fck: mmchsdb1_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <16>; - reg = <0x0204>; - }; - - mmchsdb2_fck: mmchsdb2_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <17>; - reg = <0x0204>; - }; -}; - -&prcm_clockdomains { - gfx_clkdm: gfx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_ick>; - }; - - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, - <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, - <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>, - <&icr_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_ick>, <&dss_54m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, - <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, - <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, - <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>, - <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, - <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>, - <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>, - <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>, - <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>, - <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>, - <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>, - <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, - <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>, - <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>, - <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>, - <&mmchsdb2_fck>; - }; - - mdm_clkdm: mdm_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mdm_osc_ck>; - }; -}; - -&func_96m_ck { - compatible = "ti,mux-clock"; - clocks = <&apll96_ck>, <&alt_ck>; - ti,bit-shift = <4>; - reg = <0x0540>; -}; - -&dsp_div_fck { - ti,max-div = <4>; - ti,index-starts-at-one; -}; - -&ssi_ssr_sst_div_fck { - ti,max-div = <5>; - ti,index-starts-at-one; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2430-sdp.dts b/software/linux/kernel/arch/arm/boot/dts/omap2430-sdp.dts deleted file mode 100644 index 4f7d9d7c0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2430-sdp.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap2430.dtsi" - -/ { - model = "TI OMAP2430 SDP"; - compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; -}; - -&i2c2 { - clock-frequency = <100000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - }; -}; - -#include "twl4030.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - bus-width = <4>; -}; - -&gpmc { - ranges = <5 0 0x08000000 0x01000000>; - ethernet@gpmc { - compatible = "smsc,lan91c94"; - interrupt-parent = <&gpio5>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ - reg = <5 0x300 0xf>; - bank-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,mux-add-data = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <6>; - gpmc,cs-rd-off-ns = <187>; - gpmc,cs-wr-off-ns = <187>; - gpmc,adv-on-ns = <18>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <60>; - gpmc,oe-off-ns = <169>; - gpmc,we-on-ns = <66>; - gpmc,we-off-ns = <169>; - gpmc,rd-cycle-ns = <187>; - gpmc,wr-cycle-ns = <187>; - gpmc,access-ns = <187>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <24>; - gpmc,cycle2cycle-delay-ns = <24>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap2430.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap2430.dtsi deleted file mode 100644 index 455aaea40..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap2430.dtsi +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Device Tree Source for OMAP243x SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "omap2.dtsi" - -/ { - compatible = "ti,omap2430", "ti,omap2"; - - ocp { - l4_wkup: l4_wkup@49000000 { - compatible = "ti,omap2-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x49000000 0x31000>; - - prcm: prcm@6000 { - compatible = "ti,omap2-prcm"; - reg = <0x6000 0x1000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@2000 { - compatible = "ti,omap2-scm", "simple-bus"; - reg = <0x2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x1000>; - - omap2430_pmx: pinmux@30 { - compatible = "ti,omap2430-padconf", - "pinctrl-single"; - reg = <0x30 0x0154>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon", - "simple-bus"; - reg = <0x270 0x240>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x270 0x240>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - pbias_regulator: pbias_regulator@230 { - compatible = "ti,pbias-omap2", "ti,pbias-omap"; - reg = <0x230 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - - scm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@20000 { - compatible = "ti,omap-counter32k"; - reg = <0x20000 0x20>; - ti,hwmods = "counter_32k"; - }; - }; - - gpio1: gpio@4900c000 { - compatible = "ti,omap2-gpio"; - reg = <0x4900c000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@4900e000 { - compatible = "ti,omap2-gpio"; - reg = <0x4900e000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@49010000 { - compatible = "ti,omap2-gpio"; - reg = <0x49010000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@49012000 { - compatible = "ti,omap2-gpio"; - reg = <0x49012000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio5: gpio@480b6000 { - compatible = "ti,omap2-gpio"; - reg = <0x480b6000 0x200>; - interrupts = <33>; - ti,hwmods = "gpio5"; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpmc: gpmc@6e000000 { - compatible = "ti,omap2430-gpmc"; - reg = <0x6e000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <64>, /* OCP compliant interrupt */ - <59>, /* TX interrupt */ - <60>, /* RX interrupt */ - <61>; /* RX overflow interrupt */ - interrupt-names = "common", "tx", "rx", "rx_overflow"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@48076000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48076000 0xff>; - reg-names = "mpu"; - interrupts = <16>, /* OCP compliant interrupt */ - <62>, /* TX interrupt */ - <63>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp3: mcbsp@4808c000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x4808c000 0xff>; - reg-names = "mpu"; - interrupts = <17>, /* OCP compliant interrupt */ - <89>, /* TX interrupt */ - <90>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp4: mcbsp@4808e000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x4808e000 0xff>; - reg-names = "mpu"; - interrupts = <18>, /* OCP compliant interrupt */ - <54>, /* TX interrupt */ - <55>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp5: mcbsp@48096000 { - compatible = "ti,omap2430-mcbsp"; - reg = <0x48096000 0xff>; - reg-names = "mpu"; - interrupts = <19>, /* OCP compliant interrupt */ - <81>, /* TX interrupt */ - <82>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp5"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap2-hsmmc"; - reg = <0x4809c000 0x200>; - interrupts = <83>; - ti,hwmods = "mmc1"; - ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap2-hsmmc"; - reg = <0x480b4000 0x200>; - interrupts = <86>; - ti,hwmods = "mmc2"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap2-mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <6>; - mbox_dsp: dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - }; - - timer1: timer@49018000 { - compatible = "ti,omap2420-timer"; - reg = <0x49018000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - mcspi3: mcspi@480b8000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi3"; - reg = <0x480b8000 0x100>; - interrupts = <91>; - dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - usb_otg_hs: usb_otg_hs@480ac000 { - compatible = "ti,omap2-musb"; - ti,hwmods = "usb_otg_hs"; - reg = <0x480ac000 0x1000>; - interrupts = <93>; - }; - - wd_timer2: wdt@49016000 { - compatible = "ti,omap2-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x49016000 0x80>; - }; - }; -}; - -&i2c1 { - compatible = "ti,omap2430-i2c"; -}; - -&i2c2 { - compatible = "ti,omap2430-i2c"; -}; - -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2430-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap24xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap24xx-clocks.dtsi deleted file mode 100644 index 769a346de..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap24xx-clocks.dtsi +++ /dev/null @@ -1,1244 +0,0 @@ -/* - * Device Tree Source for OMAP24xx clock data - * - * Copyright (C) 2014 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&scm_clocks { - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x4>; - }; - - mcbsp1_fck: mcbsp1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; - }; - - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_96m_ck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x4>; - }; - - mcbsp2_fck: mcbsp2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; - }; -}; - -&prcm_clocks { - func_32k_ck: func_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - secure_32k_ck: secure_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12m_ck: virt_12m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13m_ck: virt_13m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26m_ck: virt_26m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - aplls_clkin_ck: aplls_clkin_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>; - ti,bit-shift = <23>; - reg = <0x0540>; - }; - - aplls_clkin_x2_ck: aplls_clkin_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&aplls_clkin_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - osc_ck: osc_ck@60 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>; - ti,bit-shift = <6>; - reg = <0x0060>; - ti,index-starts-at-one; - }; - - sys_ck: sys_ck@60 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&osc_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x0060>; - ti,index-starts-at-one; - }; - - alt_ck: alt_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <54000000>; - }; - - mcbsp_clks: mcbsp_clks { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - dpll_ck: dpll_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-dpll-core-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0500>, <0x0540>; - }; - - apll96_ck: apll96_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-apll-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <2>; - ti,idlest-shift = <8>; - ti,clock-frequency = <96000000>; - reg = <0x0500>, <0x0530>, <0x0520>; - }; - - apll54_ck: apll54_ck@500 { - #clock-cells = <0>; - compatible = "ti,omap2-apll-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - ti,idlest-shift = <9>; - ti,clock-frequency = <54000000>; - reg = <0x0500>, <0x0530>, <0x0520>; - }; - - func_54m_ck: func_54m_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&apll54_ck>, <&alt_ck>; - ti,bit-shift = <5>; - reg = <0x0540>; - }; - - core_ck: core_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - func_96m_ck: func_96m_ck@540 { - #clock-cells = <0>; - }; - - apll96_d2_ck: apll96_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&apll96_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_48m_ck: func_48m_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&apll96_d2_ck>, <&alt_ck>; - ti,bit-shift = <3>; - reg = <0x0540>; - }; - - func_12m_ck: func_12m_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&func_48m_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - sys_clkout_src_gate: sys_clkout_src_gate@70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0070>; - }; - - sys_clkout_src_mux: sys_clkout_src_mux@70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; - reg = <0x0070>; - }; - - sys_clkout_src: sys_clkout_src { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>; - }; - - sys_clkout: sys_clkout@70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkout_src>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0070>; - ti,index-power-of-two; - }; - - emul_ck: emul_ck@78 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_54m_ck>; - ti,bit-shift = <0>; - reg = <0x0078>; - }; - - mpu_ck: mpu_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <31>; - reg = <0x0140>; - ti,index-starts-at-one; - }; - - dsp_gate_fck: dsp_gate_fck@800 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0800>; - }; - - dsp_div_fck: dsp_div_fck@840 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - reg = <0x0840>; - }; - - dsp_fck: dsp_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dsp_gate_fck>, <&dsp_div_fck>; - }; - - core_l3_ck: core_l3_ck@240 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <31>; - reg = <0x0240>; - ti,index-starts-at-one; - }; - - gfx_3d_gate_fck: gfx_3d_gate_fck@300 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <2>; - reg = <0x0300>; - }; - - gfx_3d_div_fck: gfx_3d_div_fck@340 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,max-div = <4>; - reg = <0x0340>; - ti,index-starts-at-one; - }; - - gfx_3d_fck: gfx_3d_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>; - }; - - gfx_2d_gate_fck: gfx_2d_gate_fck@300 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <1>; - reg = <0x0300>; - }; - - gfx_2d_div_fck: gfx_2d_div_fck@340 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,max-div = <4>; - reg = <0x0340>; - ti,index-starts-at-one; - }; - - gfx_2d_fck: gfx_2d_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>; - }; - - gfx_ick: gfx_ick@310 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <0>; - reg = <0x0310>; - }; - - l4_ck: l4_ck@240 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <5>; - ti,max-div = <3>; - reg = <0x0240>; - ti,index-starts-at-one; - }; - - dss_ick: dss_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <0>; - reg = <0x0210>; - }; - - dss1_gate_fck: dss1_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <0>; - reg = <0x0200>; - }; - - core_d2_ck: core_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - core_d3_ck: core_d3_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - core_d4_ck: core_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - core_d5_ck: core_d5_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <5>; - }; - - core_d6_ck: core_d6_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <6>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - core_d8_ck: core_d8_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - core_d9_ck: core_d9_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <9>; - }; - - core_d12_ck: core_d12_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <12>; - }; - - core_d16_ck: core_d16_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dss1_mux_fck: dss1_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>; - ti,bit-shift = <8>; - reg = <0x0240>; - }; - - dss1_fck: dss1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dss1_gate_fck>, <&dss1_mux_fck>; - }; - - dss2_gate_fck: dss2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <1>; - reg = <0x0200>; - }; - - dss2_mux_fck: dss2_mux_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&func_48m_ck>; - ti,bit-shift = <13>; - reg = <0x0240>; - }; - - dss2_fck: dss2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dss2_gate_fck>, <&dss2_mux_fck>; - }; - - dss_54m_fck: dss_54m_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_54m_ck>; - ti,bit-shift = <2>; - reg = <0x0200>; - }; - - ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <1>; - reg = <0x0204>; - }; - - ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <20>; - reg = <0x0240>; - }; - - ssi_ssr_sst_fck: ssi_ssr_sst_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@214 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <0>; - reg = <0x0214>; - }; - - usb_l4_div_ick: usb_l4_div_ick@240 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&core_l3_ck>; - ti,bit-shift = <25>; - reg = <0x0240>; - ti,dividers = <0>, <1>, <2>, <0>, <4>; - }; - - usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; - }; - - ssi_l4_ick: ssi_l4_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <1>; - reg = <0x0214>; - }; - - gpt1_ick: gpt1_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0410>; - }; - - gpt1_gate_fck: gpt1_gate_fck@400 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <0>; - reg = <0x0400>; - }; - - gpt1_mux_fck: gpt1_mux_fck@440 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - reg = <0x0440>; - }; - - gpt1_fck: gpt1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; - }; - - gpt2_ick: gpt2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x0210>; - }; - - gpt2_gate_fck: gpt2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <4>; - reg = <0x0200>; - }; - - gpt2_mux_fck: gpt2_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <2>; - reg = <0x0244>; - }; - - gpt2_fck: gpt2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; - }; - - gpt3_ick: gpt3_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <5>; - reg = <0x0210>; - }; - - gpt3_gate_fck: gpt3_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <5>; - reg = <0x0200>; - }; - - gpt3_mux_fck: gpt3_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <4>; - reg = <0x0244>; - }; - - gpt3_fck: gpt3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; - }; - - gpt4_ick: gpt4_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <6>; - reg = <0x0210>; - }; - - gpt4_gate_fck: gpt4_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <6>; - reg = <0x0200>; - }; - - gpt4_mux_fck: gpt4_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <6>; - reg = <0x0244>; - }; - - gpt4_fck: gpt4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; - }; - - gpt5_ick: gpt5_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <7>; - reg = <0x0210>; - }; - - gpt5_gate_fck: gpt5_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <7>; - reg = <0x0200>; - }; - - gpt5_mux_fck: gpt5_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <8>; - reg = <0x0244>; - }; - - gpt5_fck: gpt5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; - }; - - gpt6_ick: gpt6_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <8>; - reg = <0x0210>; - }; - - gpt6_gate_fck: gpt6_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0200>; - }; - - gpt6_mux_fck: gpt6_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <10>; - reg = <0x0244>; - }; - - gpt6_fck: gpt6_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; - }; - - gpt7_ick: gpt7_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <9>; - reg = <0x0210>; - }; - - gpt7_gate_fck: gpt7_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <9>; - reg = <0x0200>; - }; - - gpt7_mux_fck: gpt7_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <12>; - reg = <0x0244>; - }; - - gpt7_fck: gpt7_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; - }; - - gpt8_ick: gpt8_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <10>; - reg = <0x0210>; - }; - - gpt8_gate_fck: gpt8_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <10>; - reg = <0x0200>; - }; - - gpt8_mux_fck: gpt8_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <14>; - reg = <0x0244>; - }; - - gpt8_fck: gpt8_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; - }; - - gpt9_ick: gpt9_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <11>; - reg = <0x0210>; - }; - - gpt9_gate_fck: gpt9_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <11>; - reg = <0x0200>; - }; - - gpt9_mux_fck: gpt9_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <16>; - reg = <0x0244>; - }; - - gpt9_fck: gpt9_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; - }; - - gpt10_ick: gpt10_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <12>; - reg = <0x0210>; - }; - - gpt10_gate_fck: gpt10_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <12>; - reg = <0x0200>; - }; - - gpt10_mux_fck: gpt10_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <18>; - reg = <0x0244>; - }; - - gpt10_fck: gpt10_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; - }; - - gpt11_ick: gpt11_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <13>; - reg = <0x0210>; - }; - - gpt11_gate_fck: gpt11_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <13>; - reg = <0x0200>; - }; - - gpt11_mux_fck: gpt11_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <20>; - reg = <0x0244>; - }; - - gpt11_fck: gpt11_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; - }; - - gpt12_ick: gpt12_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <14>; - reg = <0x0210>; - }; - - gpt12_gate_fck: gpt12_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <14>; - reg = <0x0200>; - }; - - gpt12_mux_fck: gpt12_mux_fck@244 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; - ti,bit-shift = <22>; - reg = <0x0244>; - }; - - gpt12_fck: gpt12_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>; - }; - - mcbsp1_ick: mcbsp1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <15>; - reg = <0x0210>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <15>; - reg = <0x0200>; - }; - - mcbsp2_ick: mcbsp2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <16>; - reg = <0x0210>; - }; - - mcbsp2_gate_fck: mcbsp2_gate_fck@200 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <16>; - reg = <0x0200>; - }; - - mcspi1_ick: mcspi1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <17>; - reg = <0x0210>; - }; - - mcspi1_fck: mcspi1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <17>; - reg = <0x0200>; - }; - - mcspi2_ick: mcspi2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <18>; - reg = <0x0210>; - }; - - mcspi2_fck: mcspi2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <18>; - reg = <0x0200>; - }; - - uart1_ick: uart1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <21>; - reg = <0x0210>; - }; - - uart1_fck: uart1_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <21>; - reg = <0x0200>; - }; - - uart2_ick: uart2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <22>; - reg = <0x0210>; - }; - - uart2_fck: uart2_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <22>; - reg = <0x0200>; - }; - - uart3_ick: uart3_ick@214 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - uart3_fck: uart3_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <2>; - reg = <0x0204>; - }; - - gpios_ick: gpios_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x0410>; - }; - - gpios_fck: gpios_fck@400 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <2>; - reg = <0x0400>; - }; - - mpu_wdt_ick: mpu_wdt_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x0410>; - }; - - mpu_wdt_fck: mpu_wdt_fck@400 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <3>; - reg = <0x0400>; - }; - - sync_32k_ick: sync_32k_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x0410>; - }; - - wdt1_ick: wdt1_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x0410>; - }; - - omapctrl_ick: omapctrl_ick@410 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x0410>; - }; - - cam_fck: cam_fck@200 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <31>; - reg = <0x0200>; - }; - - cam_ick: cam_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <31>; - reg = <0x0210>; - }; - - mailboxes_ick: mailboxes_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <30>; - reg = <0x0210>; - }; - - wdt4_ick: wdt4_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <29>; - reg = <0x0210>; - }; - - wdt4_fck: wdt4_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_32k_ck>; - ti,bit-shift = <29>; - reg = <0x0200>; - }; - - mspro_ick: mspro_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <27>; - reg = <0x0210>; - }; - - mspro_fck: mspro_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_96m_ck>; - ti,bit-shift = <27>; - reg = <0x0200>; - }; - - fac_ick: fac_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <25>; - reg = <0x0210>; - }; - - fac_fck: fac_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <25>; - reg = <0x0200>; - }; - - hdq_ick: hdq_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <23>; - reg = <0x0210>; - }; - - hdq_fck: hdq_fck@200 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_12m_ck>; - ti,bit-shift = <23>; - reg = <0x0200>; - }; - - i2c1_ick: i2c1_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <19>; - reg = <0x0210>; - }; - - i2c2_ick: i2c2_ick@210 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <20>; - reg = <0x0210>; - }; - - gpmc_fck: gpmc_fck@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <1>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - sdma_fck: sdma_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_l3_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sdma_ick: sdma_ick@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <0>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - sdrc_ick: sdrc_ick@238 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&core_l3_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <2>; - reg = <0x0238>; - ti,clock-mult = <1>; - }; - - des_ick: des_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <0>; - reg = <0x021c>; - }; - - sha_ick: sha_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <1>; - reg = <0x021c>; - }; - - rng_ick: rng_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; - - aes_ick: aes_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <3>; - reg = <0x021c>; - }; - - pka_ick: pka_ick@21c { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l4_ck>; - ti,bit-shift = <4>; - reg = <0x021c>; - }; - - usb_fck: usb_fck@204 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&func_48m_ck>; - ti,bit-shift = <0>; - reg = <0x0204>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-beagle-xm-ab.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-beagle-xm-ab.dts deleted file mode 100644 index 7ac3bcf59..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-beagle-xm-ab.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-beagle-xm.dts" - -/ { - /* HS USB Port 2 Power enable was inverted with the xM C */ - hsusb2_power: hsusb2_power_reg { - enable-active-high; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-beagle-xm.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-beagle-xm.dts deleted file mode 100644 index 85e297ed0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-beagle-xm.dts +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - model = "TI OMAP3 BeagleBoard xM"; - compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "beagleboard::usr0"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "beagleboard::usr1"; - gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ - linux,default-trigger = "mmc0"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - pmu_stat { - label = "beagleboard::pmu_stat"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - linux,code = <0x114>; - wakeup-source; - }; - - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ - vcc-supply = <&hsusb2_power>; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; - - /* XXX pinctrl from twl */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - etb@5401b000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x5401b000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - port { - etb_in: endpoint { - slave-mode; - remote-endpoint = <&etm_out>; - }; - }; - }; - - etm@54010000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x54010000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; -}; - -&omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ - >; - }; - - dss_dpi_pins2: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ - >; - }; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins2 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - - twl_power: power { - compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; - ti,use_poweroff; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&vaux2 { - regulator-name = "usb_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mcbsp2 { - status = "okay"; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-beagle.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-beagle.dts deleted file mode 100644 index 4be85ce59..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-beagle.dts +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TI OMAP3 BeagleBoard"; - compatible = "ti,omap3-beagle", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; - - leds { - compatible = "gpio-leds"; - pmu_stat { - label = "beagleboard::pmu_stat"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - }; - - heartbeat { - label = "beagleboard::usr0"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "beagleboard::usr1"; - gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ - linux,default-trigger = "mmc0"; - }; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ - vcc-supply = <&hsusb2_power>; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,code = <0x114>; - wakeup-source; - }; - - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ - - pinctrl-names = "default"; - pinctrl-0 = <&tfp410_pins>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - etb@540000000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x5401b000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - port { - etb_in: endpoint { - slave-mode; - remote-endpoint = <&etm_out>; - }; - }; - }; - - etm@54010000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x54010000 0x1000>; - - clocks = <&emu_src_ck>; - clock-names = "apb_pclk"; - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; -}; - -&omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c3 { - clock-frequency = <100000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&vaux2 { - regulator-name = "vdd_ehci"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&mcbsp2 { - status = "okay"; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&gpmc { - status = "ok"; - ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ - - /* Chip select 0 */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* NAND I/O window, 4 bytes */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "ham1"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - nand-bus-width = <16>; - #address-cells = <1>; - #size-cells = <1>; - - gpmc,device-width = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - partition@1c0000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x680000 0xf980000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3517.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3517.dts deleted file mode 100644 index 53ae04f91..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3517.dts +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Support for CompuLab CM-T3517 - */ -/dts-v1/; - -#include "am3517.dtsi" -#include "omap3-cm-t3x.dtsi" - -/ { - model = "CompuLab CM-T3517"; - compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; - - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vw1271"; - pinctrl-names = "default"; - pinctrl-0 = < - &wl12xx_wkup_pins - &wl12xx_core_pins - >; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */ - startup-delay-us = <20000>; - enable-active-high; - }; - - wl12xx_vaux2: wl12xx_vaux2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271_vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&omap3_pmx_wkup { - - wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ - >; - }; -}; - -&omap3_pmx_core { - - phy1_reset_pins: pinmux_hsusb1_phy_reset_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ - >; - }; - - phy2_reset_pins: pinmux_hsusb2_phy_reset_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ - >; - }; - - otg_drv_vbus: pinmux_otg_drv_vbus { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - wl12xx_core_pins: pinmux_wl12xx_core_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ - OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - usb_hub_pins: pinmux_usb_hub_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ - >; - }; -}; - -&hsusb1_phy { - pinctrl-names = "default"; - pinctrl-0 = <&phy1_reset_pins>; - reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; -}; - -&hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&phy2_reset_pins>; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; -}; - -&davinci_emac { - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&am35x_otg_hs { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&otg_drv_vbus>; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - vmmc_aux-supply = <&wl12xx_vaux2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 145 */ - ref-clock-frequency = <38400000>; - }; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t35x - >; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3530.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3530.dts deleted file mode 100644 index 8dd14fcf6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3530.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Support for CompuLab CM-T3530 - */ -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-cm-t3x30.dtsi" - -/ { - model = "CompuLab CM-T3530"; - compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; - - /* Regulator to trigger the reset signal of the Wifi module */ - mmc2_sdio_reset: regulator-mmc2-sdio-reset { - compatible = "regulator-fixed"; - regulator-name = "regulator-mmc2-sdio-reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&omap3_pmx_core { - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&mmc2_sdio_reset>; - non-removable; - bus-width = <4>; - cap-power-off-card; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t35x - >; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3730.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3730.dts deleted file mode 100644 index 2294f5b0a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3730.dts +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Support for CompuLab CM-T3730 - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-cm-t3x30.dtsi" - -/ { - model = "CompuLab CM-T3730"; - compatible = "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vw1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; /* gpio73 */ - startup-delay-us = <20000>; - enable-active-high; - }; - - wl12xx_vaux2: wl12xx_vaux2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271_vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vaux2>; - }; -}; - -&omap3_pmx_wkup { - dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&omap3_pmx_core { - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - vmmc_aux-supply = <&wl12xx_vaux2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ - ref-clock-frequency = <38400000>; - }; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins_common - &dss_dpi_pins_cm_t3730 - >; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3x.dtsi deleted file mode 100644 index 57b9a028a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Common support for CompuLab CM-T3x CoMs - */ - -/ { - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&green_led_pins>; - ledb { - label = "cm-t3x:green"; - gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */ - linux,default-trigger = "heartbeat"; - }; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&hsusb1_power>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&hsusb2_power>; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - tv0: connector { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; -}; - -&omap3_pmx_core { - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - green_led_pins: pinmux_green_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ - >; - }; - - dss_dpi_pins_common: pinmux_dss_dpi_pins_common { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - >; - }; - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; -}; - -&mmc3 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "at24,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy &hsusb2_phy>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio2>; - interrupts = <25 0>; /* gpio_57 */ - pendown-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&venc { - status = "ok"; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&mcbsp2 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <8>; - gpmc,device-width = <1>; - ti,nand-ecc-opt = "sw"; - - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <120>; - gpmc,cs-wr-off-ns = <120>; - - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <120>; - gpmc,adv-wr-off-ns = <120>; - - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <90>; - - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <90>; - - gpmc,page-burst-access-ns = <6>; - gpmc,access-ns = <72>; - gpmc,cycle2cycle-delay-ns = <60>; - - gpmc,rd-cycle-ns = <120>; - gpmc,wr-cycle-ns = <120>; - gpmc,wr-access-ns = <186>; - gpmc,wr-data-mux-bus-ns = <90>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "xloader"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "uboot"; - reg = <0x80000 0x1e0000>; - }; - partition@0x260000 { - label = "uboot environment"; - reg = <0x260000 0x40000>; - }; - partition@0x2a0000 { - label = "linux"; - reg = <0x2a0000 0x400000>; - }; - partition@0x6a0000 { - label = "rootfs"; - reg = <0x6a0000 0x1f880000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3x30.dtsi deleted file mode 100644 index 046cd7733..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-cm-t3x30.dtsi +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Common support for CompuLab CM-T3x30 CoMs - */ - -#include "omap3-cm-t3x.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "cm-t35"; - - ti,mcbsp = <&mcbsp2>; - }; -}; - -&omap3_pmx_core { - - smsc1_pins: pinmux_smsc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ - >; - }; - - hsusb0_pins: pinmux_hsusb0_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; -}; - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ - - smsc1: ethernet@gpmc { - compatible = "smsc,lan9221", "smsc,lan9115"; - pinctrl-names = "default"; - pinctrl-0 = <&smsc1_pins>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - reg = <5 0 0xff>; - }; -}; - -&i2c1 { - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include - -&venc { - vdda-supply = <&vdac>; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(0) */ - ti,pullups = <0x000001>; -}; - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(0x00, 0x01, KEY_A) - MATRIX_KEY(0x00, 0x02, KEY_B) - MATRIX_KEY(0x00, 0x03, KEY_LEFT) - - MATRIX_KEY(0x01, 0x01, KEY_UP) - MATRIX_KEY(0x01, 0x02, KEY_ENTER) - MATRIX_KEY(0x01, 0x03, KEY_DOWN) - - MATRIX_KEY(0x02, 0x01, KEY_RIGHT) - MATRIX_KEY(0x02, 0x02, KEY_C) - MATRIX_KEY(0x02, 0x03, KEY_D) - >; -}; - -&hsusb1_phy { - reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; -}; - -&hsusb2_phy { - reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb0_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-common.dtsi deleted file mode 100644 index f330c69cc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Author: Anil Kumar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -#include "omap34xx.dtsi" -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "devkit8000::led1"; - gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "devkit8000::led2"; - gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ - default-state = "on"; - linux,default-trigger = "none"; - }; - - usr { - label = "devkit8000::led3"; - gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ - default-state = "on"; - linux,default-trigger = "usr"; - }; - - pmu_stat { - label = "devkit8000::pmu_stat"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "devkit8000"; - - ti,mcbsp = <&mcbsp2>; - ti,audio-routing = - "Ext Spk", "PREDRIVEL", - "Ext Spk", "PREDRIVER", - "MAINMIC", "Main Mic", - "Main Mic", "Mic Bias 1"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user { - label = "user"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_dvi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c2>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tv0: connector1 { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - status = "disabled"; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&twl_gpio { - ti,use-leds; - /* - * pulldowns: - * BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c6>; -}; - -&twl_keypad { - linux,keymap = ; -}; - -&wdt2 { - status = "disabled"; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "sw"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; -}; - -&gpmc { - ranges = <6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ - - ethernet@0,0 { - compatible = "davicom,dm9000"; - reg = <6 0x000 2 - 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ - bank-width = <2>; - interrupt-parent = <&gpio1>; - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - davicom,no-eeprom; - - gpmc,mux-add-data = <0>; - gpmc,device-width = <1>; - gpmc,wait-pin = <0>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - - gpmc,cs-on-ns = <6>; - gpmc,cs-rd-off-ns = <180>; - gpmc,cs-wr-off-ns = <180>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <144>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <90>; - gpmc,cycle2cycle-delay-ns = <90>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - }; -}; - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -&vpll1 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - vdds_dsi-supply = <&vpll1>; - vdda_dac-supply = <&vdac>; - - port { - dpi_dvi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi deleted file mode 100644 index 2d64bcffa..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Author: Anthoine Bourgeois - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-devkit8000-common.dtsi" -/ { - aliases { - display0 = &lcd0; - display1 = &dvi0; - display2 = &tv0; - }; - - lcd0: display { - compatible = "panel-dpi"; - label = "lcd"; - - enable-gpios = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - }; - }; - }; -}; - -&dss { - port { - dpi_lcd_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&vio { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcspi2 { - - /* touch controller */ - ads7846@0 { - compatible = "ti,ads7846"; - vcc-supply = <&vio>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <27 0>; /* gpio_27 */ - pendown-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - ti,debounce-max = /bits/ 16 <10>; - ti,debounce-tol = /bits/ 16 <5>; - ti,debounce-rep = /bits/ 16 <1>; - ti,keep-vref-on = <1>; - ti,settle-delay-usec = /bits/ 16 <150>; - - wakeup-source; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts deleted file mode 100644 index d8b16398b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Author: Anthoine Bourgeois - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/* - * 4.3'' LCD panel sold with devkit8000 board - */ - -#include "omap3-devkit8000-lcd-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel"; - compatible = "timll,omap3-devkit8000", "ti,omap3"; - - lcd0: display { - panel-timing { - clock-frequency = <10164705>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <2>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts deleted file mode 100644 index edb37ba80..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Author: Anthoine Bourgeois - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/* - * 7.0'' LCD panel sold with some devkit8000 board - */ - -#include "omap3-devkit8000-lcd-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel"; - compatible = "timll,omap3-devkit8000", "ti,omap3"; - - lcd0: display { - panel-timing { - clock-frequency = <40000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <1>; - hback-porch = <1>; - hsync-len = <48>; - vback-porch = <25>; - vfront-porch = <12>; - vsync-len = <3>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000.dts deleted file mode 100644 index 40ac89482..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-devkit8000.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Author: Anthoine Bourgeois - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap3-devkit8000-common.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000"; - compatible = "timll,omap3-devkit8000", "ti,omap3"; - - aliases { - display1 = &dvi0; - display2 = &tv0; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-evm-37xx.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-evm-37xx.dts deleted file mode 100644 index 4f9a76544..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-evm-37xx.dts +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-evm-common.dtsi" - - -/ { - model = "TI OMAP37XX EVM (TMDSEVM3730)"; - compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; -}; - -&omap3_pmx_core { - dss_dpi_pins1: pinmux_dss_dpi_pins2 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ - >; - }; - - smsc911x_pins: pinmux_smsc911x_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; -}; - -&omap3_pmx_wkup { - dss_dpi_pins2: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "hynix,h8kds0un0mer-4em"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@0x1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@0x280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@0x780000 { - label = "Filesystem"; - reg = <0x780000 0x1f880000>; - }; - }; - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc911x_pins>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-evm-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-evm-common.dtsi deleted file mode 100644 index 090475083..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-evm-common.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Common support for omap3 EVM boards - */ - -#include -#include "omap-gpmc-smsc911x.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - leds { - compatible = "gpio-leds"; - ledb { - label = "omap3evm::ledb"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - linux,default-trigger = "default-on"; - }; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio150 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include "omap3-panel-sharp-ls037v7dw01.dtsi" - -&backlight0 { - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; -}; - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&lcd_3v3 { - gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */ - enable-active-low; -}; - -&lcd0 { - enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ - reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ - mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ - &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ - &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ -}; - -&mcspi1 { - tsc2046@0 { - interrupt-parent = <&gpio6>; - interrupts = <15 0>; /* gpio175 */ - pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */ - ref-clock-frequency = <38400000>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(2, 2, KEY_1) - MATRIX_KEY(1, 1, KEY_2) - MATRIX_KEY(0, 0, KEY_3) - MATRIX_KEY(3, 2, KEY_4) - MATRIX_KEY(2, 1, KEY_5) - MATRIX_KEY(1, 0, KEY_6) - MATRIX_KEY(1, 3, KEY_7) - MATRIX_KEY(3, 1, KEY_8) - MATRIX_KEY(2, 0, KEY_9) - MATRIX_KEY(2, 3, KEY_KPASTERISK) - MATRIX_KEY(0, 2, KEY_0) - MATRIX_KEY(3, 0, KEY_KPDOT) - /* s4 not wired */ - MATRIX_KEY(1, 2, KEY_BACKSPACE) - MATRIX_KEY(0, 1, KEY_ENTER) - >; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ethernet@gpmc { - interrupt-parent = <&gpio6>; - interrupts = <16 8>; - reg = <5 0 0xff>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-evm.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-evm.dts deleted file mode 100644 index 99b2bfcd1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-evm.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-evm-common.dtsi" - -/ { - model = "TI OMAP35XX EVM (TMDSEVM3530)"; - compatible = "ti,omap3-evm", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-gta04.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-gta04.dtsi deleted file mode 100644 index b3a8b1f24..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-gta04.dtsi +++ /dev/null @@ -1,620 +0,0 @@ -/* - * Copyright (C) 2013 Marek Belisko - * - * Based on omap3-beagle-xm.dts - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - model = "OMAP3 GTA04"; - compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - aliases { - display0 = &lcd; - }; - - gpio-keys { - compatible = "gpio-keys"; - - aux-button { - label = "aux"; - linux,code = <169>; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "gta04"; - - ti,mcbsp = <&mcbsp2>; - }; - - /* GSM audio */ - sound_telephony { - compatible = "simple-audio-card"; - simple-audio-card,name = "GTA04 voice"; - simple-audio-card,bitclock-master = <&telephony_link_master>; - simple-audio-card,frame-master = <&telephony_link_master>; - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&mcbsp4>; - }; - - telephony_link_master: simple-audio-card,codec { - sound-dai = <>m601_codec>; - }; - }; - - gtm601_codec: gsm_codec { - compatible = "option,gtm601"; - #sound-dai-cells = <0>; - }; - - spi_lcd { - compatible = "spi-gpio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_pins>; - - gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 18 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 20 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - /* lcd panel */ - lcd: td028ttec1@0 { - compatible = "toppoly,td028ttec1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm11 0 12000000 0>; - pwm-names = "backlight"; - brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <9>; /* => 90 */ - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - }; - - pwm11: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer11>; - #pwm-cells = <3>; - }; - - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - }; - - tv0: connector { - compatible = "svideo-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&opa_out>; - }; - }; - }; - - tv_amp: opa362 { - compatible = "ti,opa362"; - enable-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - opa_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - - port@1 { - reg = <1>; - opa_out: endpoint { - remote-endpoint = <&tv_connector_in>; - }; - }; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - backlight_pins: backlight_pins_pimnux { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - hdq_pins: hdq_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ - >; - }; - - bma180_pins: pinmux_bma180_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ - >; - }; - - itg3200_pins: pinmux_itg3200_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ - >; - }; - - hmc5843_pins: pinmux_hmc5843_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - spi_gpio_pins: spi_gpio_pinmux { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - codec { - ti,ramp_delay_value = <3>; - }; - }; - - twl_power: power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; - - /* pressure sensor */ - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - interrupt-parent = <&gpio4>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */ - }; - - /* accelerometer */ - bma180@41 { - compatible = "bosch,bma180"; - reg = <0x41>; - pinctrl-names = "default"; - pintcrl-0 = <&bma180_pins>; - interrupt-parent = <&gpio4>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */ - }; - - /* gyroscope */ - itg3200@68 { - compatible = "invensense,itg3200"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&itg3200_pins>; - interrupt-parent = <&gpio2>; - interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */ - }; - - /* leds + gpios */ - tca6507: tca6507@45 { - compatible = "ti,tca6507"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x45>; - - gpio-controller; - #gpio-cells = <2>; - - gta04_led0: red_aux@0 { - label = "gta04:red:aux"; - reg = <0x0>; - }; - - gta04_led1: green_aux@1 { - label = "gta04:green:aux"; - reg = <0x1>; - }; - - gta04_led3: red_power@3 { - label = "gta04:red:power"; - reg = <0x3>; - linux,default-trigger = "default-on"; - }; - - gta04_led4: green_power@4 { - label = "gta04:green:power"; - reg = <0x4>; - }; - - wifi_reset: wifi_reset@6 { - reg = <0x6>; - compatible = "gpio"; - }; - }; - - /* compass aka magnetometer */ - hmc5843@1e { - compatible = "honeywell,hmc5883l"; - reg = <0x1e>; - pinctrl-names = "default"; - pinctrl-0 = <&hmc5843_pins>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */ - }; - - /* touchscreen */ - tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - interrupt-parent = <&gpio6>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */ - gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <600>; - }; - - /* RFID EEPROM */ - m24lr64@50 { - compatible = "at,24c64"; - reg = <0x50>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc2 { - vmmc-supply = <&vaux4>; - bus-width = <4>; - ti,non-removable; - cap-power-off-card; - mmc-pwrseq = <&wifi_pwrseq>; -}; - -&mmc3 { - status = "disabled"; -}; - -&twl_keypad { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -/* spare */ -&vaux1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; -}; - -/* sensors */ -&vaux2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; -}; - -/* camera */ -&vaux3 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; -}; - -/* WLAN/BT */ -&vaux4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -/* GPS LNA */ -&vsim { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < &dss_dpi_pins >; - - status = "okay"; - vdds_dsi-supply = <&vpll2>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&venc { - status = "okay"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&opa_in>; - ti,channels = <2>; - ti,invert-polarity; - }; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; -}; - -&mcbsp2 { - status = "okay"; -}; - -&hdqw1w { - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - -&mcbsp4 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a3.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a3.dts deleted file mode 100644 index 3099a892c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a3.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2014 H. Nikolaus Schaller - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A3"; -}; - -&i2c2 { - - /* alternate accelerometer that might be installed on some GTA04A3 boards */ - lis302@1d { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x1d>; - interrupt-parent = <&gpio3>; - interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; - Vdd-supply = <&vaux2>; - Vdd_IO-supply = <&vaux2>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <8>; - st,click-thresh-y = <8>; - st,click-thresh-z = <10>; - st,click-click-time-limit = <9>; - st,click-latency = <50>; - st,irq1-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <32>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - st,max-limit-x = <3>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a4.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a4.dts deleted file mode 100644 index c918bb1f0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a4.dts +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2014 Marek Belisko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A4"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a5.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a5.dts deleted file mode 100644 index 600b6ca5a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-gta04a5.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2014 H. Nikolaus Schaller - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-gta04.dtsi" - -/ { - model = "Goldelico GTA04A5"; - - sound { - ti,jack-det-gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>; /* GTA04A5 only */ - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-ha-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-ha-common.dtsi deleted file mode 100644 index bd66545ef..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-ha-common.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-tao3530.dtsi" - -/ { - gpio_poweroff { - pinctrl-names = "default"; - pinctrl-0 = <&poweroff_pins>; - - compatible = "gpio-poweroff"; - gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */ - }; -}; - -&omap3_pmx_core { - sound2_pins: pinmux_sound2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ - >; - }; - - led_blue_pins: pinmux_led_blue_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ - >; - }; - - led_green_pins: pinmux_led_green_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ - >; - }; - - led_red_pins: pinmux_led_red_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ - >; - }; - - poweroff_pins: pinmux_poweroff_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ - >; - }; - - powerdown_input_pins: pinmux_powerdown_input_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ - >; - }; - - fpga_boot0_pins: fpga_boot0_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */ - >; - }; - - fpga_boot1_pins: fpga_boot1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */ - >; - }; -}; - -/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-ha-lcd.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-ha-lcd.dts deleted file mode 100644 index 60af7c235..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-ha-lcd.dts +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-ha-common.dtsi" - -/ { - model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; - compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - &powerdown_input_pins - &fpga_boot0_pins - &fpga_boot1_pins - &led_blue_pins - &led_green_pins - &led_red_pins - &touchscreen_wake_pins - >; - - touchscreen_irq_pins: pinmux_touchscreen_irq_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ - >; - }; - - touchscreen_wake_pins: pinmux_touchscreen_wake_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: pinmux_lte430_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; -}; - -/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <31250000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <86>; - hsync-len = <1>; - vback-porch = <30>; - vfront-porch = <13>; - vsync-len = <3>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ - - default-on; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-ha.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-ha.dts deleted file mode 100644 index fde325688..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-ha.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-ha-common.dtsi" - -/ { - model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM"; - compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - &powerdown_input_pins - &fpga_boot0_pins - &fpga_boot1_pins - &led_blue_pins - &led_green_pins - &led_red_pins - >; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-igep.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-igep.dtsi deleted file mode 100644 index 54c4c07bb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-igep.dtsi +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Common device tree for IGEP boards based on AM/DM37x - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - chosen { - stdout-path = &uart3; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "igep2"; - ti,mcbsp = <&mcbsp2>; - }; - - vdd33: regulator-vdd33 { - compatible = "regulator-fixed"; - regulator-name = "vdd33"; - regulator-always-on; - }; - -}; - -&omap3_pmx_core { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; -}; - -&gpmc { - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29c4g96maz"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0 0x100000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x100000 0x180000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x280000 0x100000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x380000 0x300000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x680000 0x1f980000>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <4>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020-common.dtsi deleted file mode 100644 index 667f96245..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Common Device Tree Source for IGEPv2 - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-igep.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - compatible = "gpio-leds"; - - boot { - label = "omap3:green:boot"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user1 { - label = "omap3:red:user1"; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user2 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; - }; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ - vcc-supply = <&hsusb1_power>; - }; - - tfp410: encoder { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &tfp410_pins - &dss_dpi_pins - >; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - >; - }; - - smsc9221_pins: pinmux_smsc9221_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - >; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ - >; - }; - - mmc1_wp_pins: pinmux_mmc1_cd_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ - >; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc9221_pins>; - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&vpll2 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; -}; - -&dss { - status = "ok"; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&mmc1 { - pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>; - wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */ -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020-rev-f.dts deleted file mode 100644 index 321c2b7a4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x) - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-igep0020-common.dtsi" - -/ { - model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3"; - - /* Regulator to trigger the WL_EN signal of the Wifi module */ - lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { - compatible = "regulator-fixed"; - regulator-name = "regulator-lbep5clwmc-wlen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ - enable-active-high; - }; -}; - -&omap3_pmx_core { - lbep5clwmc_pins: pinmux_lbep5clwmc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ - >; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; - vmmc-supply = <&lbep5clwmc_wlen>; - bus-width = <4>; - non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 177 */ - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020.dts deleted file mode 100644 index 33d6b4ead..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0020.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-igep0020-common.dtsi" - -/ { - model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ - <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ - }; -}; - -&omap3_pmx_core { - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ - >; - }; -}; - -/* On board Wifi module */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030-common.dtsi deleted file mode 100644 index e94d94274..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030-common.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Common Device Tree Source for IGEP COM MODULE - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-igep.dtsi" - -/ { - leds: gpio_leds { - compatible = "gpio-leds"; - - user0 { - label = "omap3:red:user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - default-state = "off"; - }; - - user1 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ - default-state = "off"; - }; - - user2 { - label = "omap3:red:user1"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */ - default-state = "off"; - }; - }; - - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_core2_pins>; - - hsusb2_core2_pins: pinmux_hsusb2_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - leds_core2_pins: pinmux_leds_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030-rev-g.dts deleted file mode 100644 index 76dc08868..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x) - * - * Copyright (C) 2014 Javier Martinez Canillas - * Copyright (C) 2014 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-igep0030-common.dtsi" - -/ { - model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3"; - - /* Regulator to trigger the WL_EN signal of the Wifi module */ - lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { - compatible = "regulator-fixed"; - regulator-name = "regulator-lbep5clwmc-wlen"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ - enable-active-high; - }; -}; - -&omap3_pmx_core { - lbep5clwmc_pins: pinmux_lbep5clwmc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ - >; - }; - -}; - -&i2c2 { - status = "disabled"; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins &leds_core2_pins>; - - boot { - label = "omap3:green:boot"; - gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; - vmmc-supply = <&lbep5clwmc_wlen>; - bus-width = <4>; - non-removable; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030.dts deleted file mode 100644 index 55b0cc4f5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-igep0030.dts +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x) - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-igep0030-common.dtsi" - -/ { - model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3"; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>, /* gpio_139 - RESET_N_W */ - <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 - WIFI_PDN */ - }; -}; - -&omap3_pmx_core { - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ - >; - }; -}; - -&leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_core2_pins>; - - boot { - label = "omap3:green:boot"; - gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */ - default-state = "on"; - }; -}; - -/* On board Wifi module */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-ldp.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-ldp.dts deleted file mode 100644 index e28fe13cb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-ldp.dts +++ /dev/null @@ -1,308 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include -#include "omap34xx.dtsi" -#include "omap-gpmc-smsc911x.dtsi" - -/ { - model = "TI OMAP3430 LDP (Zoom1 Labrador)"; - compatible = "ti,omap3-ldp", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - - key_enter { - label = "enter"; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */ - linux,code = ; - wakeup-source; - }; - - key_f1 { - label = "f1"; - gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */ - linux,code = ; - wakeup-source; - }; - - key_f2 { - label = "f2"; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */ - linux,code = ; - wakeup-source; - }; - - key_f3 { - label = "f3"; - gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */ - linux,code = ; - wakeup-source; - }; - - key_f4 { - label = "f4"; - gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */ - linux,code = ; - wakeup-source; - }; - - key_left { - label = "left"; - gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ - linux,code = ; - wakeup-source; - }; - - key_right { - label = "right"; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */ - linux,code = ; - wakeup-source; - }; - - key_up { - label = "up"; - gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */ - linux,code = ; - wakeup-source; - }; - - key_down { - label = "down"; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */ - linux,code = ; - wakeup-source; - }; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */ - <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,nand"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x140000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x1c0000 0x40000>; - }; - partition@200000 { - label = "Kernel"; - reg = <0x200000 0x1e00000>; - }; - partition@2000000 { - label = "Filesystem"; - reg = <0x2000000 0x6000000>; - }; - }; - - ethernet@gpmc { - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - reg = <1 0 0xff>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_power: power { - compatible = "ti,twl4030-power-idle"; - ti,use_poweroff; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include "omap3-panel-sharp-ls037v7dw01.dtsi" - -&backlight0 { - gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -/* tps61130rsa enabled by twl4030 regen */ -&lcd_3v3 { - regulator-always-on; -}; - -&lcd0 { - enable-gpios = <&twl_gpio 15 GPIO_ACTIVE_HIGH>; /* lcd INI */ - reset-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; /* gpio55, lcd RESB */ - mode-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio56, lcd MO */ -}; - -&mcspi1 { - tsc2046@0 { - interrupt-parent = <&gpio2>; - interrupts = <22 0>; /* gpio54 */ - pendown-gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - /* See 35xx errata 2.1.1.128 in SPRZ278F */ - compatible = "ti,omap3-pre-es3-hsmmc"; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - status="disabled"; -}; - -&mmc3 { - status="disabled"; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* cam_d4.gpio_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* cam_d5.gpio_104 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* cam_d6.gpio_105 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* cam_d7.gpio_106 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* cam_d8.gpio_107 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* cam_d9.gpio_108 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ - >; - }; - - musb_pins: pinmux_musb_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ - >; - }; -}; - -&twl_keypad { - linux,keymap = ; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&musb_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - mode = <3>; - power = <50>; -}; - -&vaux1 { - /* Needed for ads7846 */ - regulator-name = "vcc"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-lilly-a83x.dtsi deleted file mode 100644 index fa611a5e4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ /dev/null @@ -1,462 +0,0 @@ -/* - * Copyright (C) 2014 Christoph Fritz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include "omap36xx.dtsi" - -/ { - model = "INCOstartec LILLY-A83X module (DM3730)"; - compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; - - chosen { - bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x8000000>; /* 128 MB */ - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "lilly-a83x::led1"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "lilly-a83x"; - - ti,mcbsp = <&mcbsp2>; - }; - - reg_vcc3: vcc3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_vcc3>; - }; -}; - -&omap3_pmx_wkup { - pinctrl-names = "default"; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ - >; - }; - - tsc2048_pins: pinmux_tsc2048_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ - >; - }; - - mmc1cd_pins: pinmux_mmc1cd_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ - >; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - hsusb1_pins: pinmux_hsusb1_pins { - pinctrl-single,pins = < - - /* GPIO 182 controls USB-Hub reset. But USB-Phy its - * reset can't be controlled. So we clamp this GPIO to - * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub. - */ - - OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ - >; - }; - - hsusb_otg_pins: pinmux_hsusb_otg_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - spi2_pins: pinmux_spi2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ - >; - }; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - - hsusb1_2_pins: pinmux_hsusb1_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - >; - }; - - gpio1_pins: pinmux_gpio1_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ - >; - }; - -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_pins>; -}; - -&gpio6 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>; -}; - -&i2c1 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl { - vmmc1: regulator-vmmc1 { - regulator-always-on; - }; - - vdd1: regulator-vdd1 { - regulator-always-on; - }; - - vdd2: regulator-vdd2 { - regulator-always-on; - }; -}; - -&i2c2 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; -}; - -&i2c3 { - clock-frequency = <2600000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - gpiom1: gpio@20 { - compatible = "mcp,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - status = "disabled"; -}; - -&mmc1 { - cd-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; - cd-inverted; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1cd_pins>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mcspi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins>; - - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - interrupt-parent = <&gpio1>; - interrupts = <8 0>; /* boot6 / gpio_8 */ - spi-max-frequency = <1000000>; - pendown-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - vcc-supply = <®_vcc3>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2048_pins>; - - ti,x-min = /bits/ 16 <300>; - ti,x-max = /bits/ 16 <3000>; - ti,y-min = /bits/ 16 <600>; - ti,y-max = /bits/ 16 <3600>; - ti,x-plate-ohms = /bits/ 16 <80>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy; - - wakeup-source; - }; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&usbhshost { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_2_pins>; - num-ports = <2>; - port1-mode = "ehci-phy"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, - <7 0 0x15000000 0x01000000>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - /* no elm on omap3 */ - - gpmc,mux-add-data = <0>; - gpmc,device-width = <2>; - gpmc,wait-pin = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,burst-length= <4>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <100>; - gpmc,cs-wr-off-ns = <100>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <100>; - gpmc,adv-wr-off-ns = <100>; - gpmc,oe-on-ns = <5>; - gpmc,oe-off-ns = <75>; - gpmc,we-on-ns = <5>; - gpmc,we-off-ns = <75>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <60>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-delay-ns = <50>; - gpmc,wr-data-mux-bus-ns = <75>; - gpmc,wr-access-ns = <155>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "MLO"; - reg = <0 0x80000>; - }; - - partition@0x80000 { - label = "u-boot"; - reg = <0x80000 0x1e0000>; - }; - - partition@0x260000 { - label = "u-boot-environment"; - reg = <0x260000 0x20000>; - }; - - partition@0x280000 { - label = "kernel"; - reg = <0x280000 0x500000>; - }; - - partition@0x780000 { - label = "filesystem"; - reg = <0x780000 0xf880000>; - }; - }; - - ethernet@7,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - bank-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <60>; - gpmc,cs-wr-off-ns = <60>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <60>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <50>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wr-data-mux-bus-ns = <15>; - gpmc,wr-access-ns = <75>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <®_vcc3>; - vdd33a-supply = <®_vcc3>; - reg-io-width = <4>; - interrupt-parent = <&gpio5>; - interrupts = <1 0x2>; - reg = <7 0 0xff>; - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - phy-mode = "mii"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-lilly-dbb056.dts deleted file mode 100644 index 0e3c9812f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-lilly-dbb056.dts +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2014 Christoph Fritz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -/dts-v1/; - -#include "omap3-lilly-a83x.dtsi" - -/ { - model = "INCOstartec LILLY-DBB056 (DM3730)"; - compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3"; -}; - -&twl { - vaux2: regulator-vaux2 { - compatible = "ti,twl4030-vaux2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - lan9117_pins: pinmux_lan9117_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ - >; - }; - - gpio4_pins: pinmux_gpio4_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ - >; - }; - - gpio5_pins: pinmux_gpio5_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ - >; - }; - - lcd_pins: pinmux_lcd_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ - OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ - >; - }; - - spi1_pins: pinmux_spi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio4_pins>; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio5_pins>; -}; - -&mmc2 { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vmmc1>; - cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */ - wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */ - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - ti,dual-volt; -}; - -&mcspi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ - <4 0 0x20000000 0x01000000>, - <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ - - ethernet@4,0 { - compatible = "smsc,lan9117", "smsc,lan9115"; - bank-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <65>; - gpmc,cs-wr-off-ns = <65>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <10>; - gpmc,oe-off-ns = <65>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <65>; - gpmc,rd-cycle-ns = <100>; - gpmc,wr-cycle-ns = <100>; - gpmc,access-ns = <60>; - gpmc,page-burst-access-ns = <5>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wr-data-mux-bus-ns = <15>; - gpmc,wr-access-ns = <75>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <®_vcc3>; - vdd33a-supply = <®_vcc3>; - reg-io-width = <4>; - interrupt-parent = <&gpio4>; - interrupts = <2 0x2>; - reg = <4 0 0xff>; - pinctrl-names = "default"; - pinctrl-0 = <&lan9117_pins>; - phy-mode = "mii"; - smsc,force-internal-phy; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-n9.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-n9.dts deleted file mode 100644 index b9e58c536..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-n9.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * omap3-n9.dts - Device Tree file for Nokia N9 - * - * Written by: Aaro Koskinen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "omap3-n950-n9.dtsi" - -/ { - model = "Nokia N9"; - compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3"; -}; - -&i2c2 { - smia_1: camera@10 { - compatible = "nokia,smia"; - reg = <0x10>; - /* No reset gpio */ - vana-supply = <&vaux3>; - clocks = <&isp 0>; - clock-frequency = <9600000>; - nokia,nvm-size = <(16 * 64)>; - port { - smia_1_1: endpoint { - link-frequencies = /bits/ 64 <199200000 210000000 499200000>; - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi2a_ep>; - }; - }; - }; -}; - -&isp { - vdd-csiphy1-supply = <&vaux2>; - vdd-csiphy2-supply = <&vaux2>; - ports { - port@2 { - reg = <2>; - csi2a_ep: endpoint { - remote-endpoint = <&smia_1_1>; - clock-lanes = <2>; - data-lanes = <1 3>; - crc = <1>; - lane-polarities = <1 1 1>; - }; - }; - }; -}; - -&modem { - compatible = "nokia,n9-modem"; -}; - -&lis302 { - st,axis-x = <1>; /* LIS3_DEV_X */ - st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-46)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - - st,max-limit-x = <(-3)>; - st,max-limit-y = <46>; - st,max-limit-z = <46>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-n900.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-n900.dts deleted file mode 100644 index 4d448f145..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-n900.dts +++ /dev/null @@ -1,1029 +0,0 @@ -/* - * Copyright (C) 2013 Pavel Machek - * Copyright (C) 2013-2014 Aaro Koskinen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 (or later) as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "omap34xx.dtsi" -#include - -/* - * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall - * for omap AES HW crypto support. When linux kernel try to access memory of AES - * blocks then kernel receive "Unhandled fault: external abort on non-linefetch" - * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no - * crash anymore) omap AES support will be disabled for all Nokia N900 devices. - * There is "unofficial" version of bootloader which enables AES in L3 firewall - * but it is not widely used and to prevent kernel crash rather AES is disabled. - * There is also no runtime detection code if AES is disabled in L3 firewall... - */ -&aes { - status = "disabled"; -}; - -/ { - model = "Nokia N900"; - compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; - - aliases { - i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat { - label = "debug::sleep"; - gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio162 */ - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&debug_leds>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - gpio_keys { - compatible = "gpio-keys"; - - camera_lens_cover { - label = "Camera Lens Cover"; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - - camera_focus { - label = "Camera Focus"; - gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ - linux,code = ; - linux,can-disable; - }; - - camera_capture { - label = "Camera Capture"; - gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ - linux,code = ; - linux,can-disable; - }; - - lock_button { - label = "Lock Button"; - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ - linux,code = ; - linux,can-disable; - }; - - keypad_slide { - label = "Keypad Slide"; - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - - proximity_sensor { - label = "Proximity Sensor"; - gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - }; - - isp1707: isp1707 { - compatible = "nxp,isp1707"; - nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; - usb-phy = <&usb2_phy>; - }; - - tv: connector { - compatible = "composite-video-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - sound: n900-audio { - compatible = "nokia,n900-audio"; - - nokia,cpu-dai = <&mcbsp2>; - nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; - nokia,headphone-amplifier = <&tpa6130a2>; - - tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ - jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ - eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ - speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; - }; - - battery: n900-battery { - compatible = "nokia,n900-battery"; - io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; - io-channel-names = "temp", "bsi", "vbat"; - }; - - pwm9: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer9>; - ti,clock-source = <0x00>; /* timer_sys_ck */ - }; - - ir: n900-ir { - compatible = "nokia,n900-ir"; - pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ - >; - }; - - ethernet_pins: pinmux_ethernet_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ - >; - }; - - gpmc_pins: pinmux_gpmc_pins { - pinctrl-single,pins = < - - /* address lines */ - OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ - OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ - - /* data lines, gpmc_d0..d7 not muxable according to TRM */ - OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ - OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ - OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ - OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ - - /* - * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable - * according to TRM. OneNAND seems to require PIN_INPUT on clock. - */ - OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - debug_leds: pinmux_debug_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ - >; - }; - - mcspi4_pins: pinmux_mcspi4_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ - >; - }; - - acx565akm_pins: pinmux_acx565akm_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ - >; - }; - - dss_sdi_pins: pinmux_dss_sdi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */ - - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ - >; - }; - - wl1251_pins: pinmux_wl1251 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ - OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ - >; - }; - - ssi_pins: pinmux_ssi { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ - >; - }; - - modem_pins: pinmux_modem { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <2200000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&vaux1 { - regulator-name = "V28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; /* due to battery cover sensor */ -}; - -&vaux2 { - regulator-name = "VCSI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vaux3 { - regulator-name = "VMMC2_30"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vaux4 { - regulator-name = "VCAM_ANA_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vmmc1 { - regulator-name = "VMMC1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vmmc2 { - regulator-name = "V28_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; /* due VIO leak to AIC34 VDDs */ -}; - -&vpll1 { - regulator-name = "VPLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; -}; - -&vpll2 { - regulator-name = "VSDI_CSI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ - regulator-always-on; -}; - -&vsim { - regulator-name = "VMMC2_IO_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ -}; - -&vio { - regulator-name = "VIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vintana1 { - regulator-name = "VINTANA1"; - /* fixed to 1500000 */ - regulator-always-on; -}; - -&vintana2 { - regulator-name = "VINTANA2"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; -}; - -&vintdig { - regulator-name = "VINTDIG"; - /* fixed to 1500000 */ - regulator-always-on; -}; - -&twl { - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - }; - - twl_power: power { - compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; - ti,use_poweroff; - }; -}; - -&twl_keypad { - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) - MATRIX_KEY(0x00, 0x01, KEY_O) - MATRIX_KEY(0x00, 0x02, KEY_P) - MATRIX_KEY(0x00, 0x03, KEY_COMMA) - MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) - MATRIX_KEY(0x00, 0x06, KEY_A) - MATRIX_KEY(0x00, 0x07, KEY_S) - - MATRIX_KEY(0x01, 0x00, KEY_W) - MATRIX_KEY(0x01, 0x01, KEY_D) - MATRIX_KEY(0x01, 0x02, KEY_F) - MATRIX_KEY(0x01, 0x03, KEY_G) - MATRIX_KEY(0x01, 0x04, KEY_H) - MATRIX_KEY(0x01, 0x05, KEY_J) - MATRIX_KEY(0x01, 0x06, KEY_K) - MATRIX_KEY(0x01, 0x07, KEY_L) - - MATRIX_KEY(0x02, 0x00, KEY_E) - MATRIX_KEY(0x02, 0x01, KEY_DOT) - MATRIX_KEY(0x02, 0x02, KEY_UP) - MATRIX_KEY(0x02, 0x03, KEY_ENTER) - MATRIX_KEY(0x02, 0x05, KEY_Z) - MATRIX_KEY(0x02, 0x06, KEY_X) - MATRIX_KEY(0x02, 0x07, KEY_C) - MATRIX_KEY(0x02, 0x08, KEY_F9) - - MATRIX_KEY(0x03, 0x00, KEY_R) - MATRIX_KEY(0x03, 0x01, KEY_V) - MATRIX_KEY(0x03, 0x02, KEY_B) - MATRIX_KEY(0x03, 0x03, KEY_N) - MATRIX_KEY(0x03, 0x04, KEY_M) - MATRIX_KEY(0x03, 0x05, KEY_SPACE) - MATRIX_KEY(0x03, 0x06, KEY_SPACE) - MATRIX_KEY(0x03, 0x07, KEY_LEFT) - - MATRIX_KEY(0x04, 0x00, KEY_T) - MATRIX_KEY(0x04, 0x01, KEY_DOWN) - MATRIX_KEY(0x04, 0x02, KEY_RIGHT) - MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) - MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) - MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) - MATRIX_KEY(0x04, 0x08, KEY_F10) - - MATRIX_KEY(0x05, 0x00, KEY_Y) - MATRIX_KEY(0x05, 0x08, KEY_F11) - - MATRIX_KEY(0x06, 0x00, KEY_U) - - MATRIX_KEY(0x07, 0x00, KEY_I) - MATRIX_KEY(0x07, 0x01, KEY_F7) - MATRIX_KEY(0x07, 0x02, KEY_F8) - >; -}; - -&twl_gpio { - ti,pullups = <0x0>; - ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <100000>; - - tlv320aic3x: tlv320aic3x@18 { - compatible = "ti,tlv320aic3x"; - reg = <0x18>; - gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ - ai3x-gpio-func = < - 0 /* AIC3X_GPIO1_FUNC_DISABLED */ - 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ - >; - - AVDD-supply = <&vmmc2>; - DRVDD-supply = <&vmmc2>; - IOVDD-supply = <&vio>; - DVDD-supply = <&vio>; - - ai3x-micbias-vg = <1>; - }; - - tlv320aic3x_aux: tlv320aic3x@19 { - compatible = "ti,tlv320aic3x"; - reg = <0x19>; - gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ - - AVDD-supply = <&vmmc2>; - DRVDD-supply = <&vmmc2>; - IOVDD-supply = <&vio>; - DVDD-supply = <&vio>; - - ai3x-micbias-vg = <2>; - }; - - tsl2563: tsl2563@29 { - compatible = "amstaos,tsl2563"; - reg = <0x29>; - - amstaos,cover-comp-gain = <16>; - }; - - adp1653: led-controller@30 { - compatible = "adi,adp1653"; - reg = <0x30>; - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ - - flash { - flash-timeout-us = <500000>; - flash-max-microamp = <320000>; - led-max-microamp = <50000>; - }; - indicator { - led-max-microamp = <17500>; - }; - }; - - lp5523: lp5523@32 { - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ - - chan0 { - chan-name = "lp5523:kb1"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan1 { - chan-name = "lp5523:kb2"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan2 { - chan-name = "lp5523:kb3"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan3 { - chan-name = "lp5523:kb4"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan4 { - chan-name = "lp5523:b"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan5 { - chan-name = "lp5523:g"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan6 { - chan-name = "lp5523:r"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan7 { - chan-name = "lp5523:kb5"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan8 { - chan-name = "lp5523:kb6"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - }; - - bq27200: bq27200@55 { - compatible = "ti,bq27200"; - reg = <0x55>; - }; - - tpa6130a2: tpa6130a2@60 { - compatible = "ti,tpa6130a2"; - reg = <0x60>; - - Vdd-supply = <&vmmc2>; - - power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ - }; - - si4713: si4713@63 { - compatible = "silabs,si4713"; - reg = <0x63>; - - interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ - vio-supply = <&vio>; - vdd-supply = <&vaux1>; - }; - - bq24150a: bq24150a@6b { - compatible = "ti,bq24150a"; - reg = <0x6b>; - - ti,current-limit = <100>; - ti,weak-battery-voltage = <3400>; - ti,battery-regulation-voltage = <4200>; - ti,charge-current = <650>; - ti,termination-current = <100>; - ti,resistor-sense = <68>; - - ti,usb-charger-detection = <&isp1707>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - lis302dl: lis3lv02d@1d { - compatible = "st,lis3lv02d"; - reg = <0x1d>; - - Vdd-supply = <&vaux1>; - Vdd_IO-supply = <&vio>; - - interrupt-parent = <&gpio6>; - interrupts = <21 20>; /* 181 and 180 */ - - /* click flags */ - st,click-single-x; - st,click-single-y; - st,click-single-z; - - /* Limits are 0.5g * value */ - st,click-threshold-x = <8>; - st,click-threshold-y = <8>; - st,click-threshold-z = <10>; - - /* Click must be longer than time limit */ - st,click-time-limit = <9>; - - /* Kind of debounce filter */ - st,click-latency = <50>; - - /* Interrupt line 2 for click detection */ - st,irq2-click; - - st,wakeup-x-hi; - st,wakeup-y-hi; - st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ - - st,wakeup2-z-hi; - st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */ - - st,hipass1-disable; - st,hipass2-disable; - - st,axis-x = <1>; /* LIS3_DEV_X */ - st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-32)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - - st,max-limit-x = <(-3)>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */ -}; - -/* most boards use vaux3, only some old versions use vmmc2 instead */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vaux3>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; - non-removable; - no-sdio; - no-sd; -}; - -&mmc3 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ - <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; - gpmc,sync-clk-ps = <15000>; - - /* - * MTD partition table corresponding to Nokia's - * Maemo 5 (Fremantle) release. - */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@1 { - label = "config"; - reg = <0x00020000 0x00060000>; - }; - partition@2 { - label = "log"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "kernel"; - reg = <0x000c0000 0x00200000>; - }; - partition@4 { - label = "initfs"; - reg = <0x002c0000 0x00200000>; - }; - partition@5 { - label = "rootfs"; - reg = <0x004c0000 0x0fb40000>; - }; - }; - - /* Ethernet is on some early development boards and qemu */ - ethernet@gpmc { - compatible = "smsc,lan91c94"; - interrupt-parent = <&gpio2>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ - reg = <1 0 0xf>; /* 16 byte IO range */ - bank-width = <2>; - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; - power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */ - reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */ - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <48>; - gpmc,cs-wr-off-ns = <24>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <0>; - gpmc,adv-wr-off-ns = <0>; - gpmc,we-on-ns = <12>; - gpmc,we-off-ns = <18>; - gpmc,oe-on-ns = <12>; - gpmc,oe-off-ns = <48>; - gpmc,page-burst-access-ns = <0>; - gpmc,access-ns = <42>; - gpmc,rd-cycle-ns = <180>; - gpmc,wr-cycle-ns = <180>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <0>; - gpmc,wr-data-mux-bus-ns = <12>; - }; -}; - -&mcspi1 { - /* - * For some reason, touchscreen is necessary for screen to work at - * all on real hw. It works well without it on emulator. - * - * Also... order in the device tree actually matters here. - */ - tsc2005@0 { - compatible = "ti,tsc2005"; - spi-max-frequency = <6000000>; - reg = <0>; - - vio-supply = <&vio>; - - reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ - interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; - - acx565akm@2 { - compatible = "sony,acx565akm"; - spi-max-frequency = <6000000>; - reg = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&acx565akm_pins>; - - label = "lcd"; - reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&sdi_out>; - }; - }; - }; -}; - -&mcspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi4_pins>; - - wl1251@0 { - pinctrl-names = "default"; - pinctrl-0 = <&wl1251_pins>; - - vio-supply = <&vio>; - - compatible = "ti,wl1251"; - reg = <0>; - spi-max-frequency = <48000000>; - - spi-cpol; - spi-cpha; - - ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ - - interrupt-parent = <&gpio2>; - interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ - }; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <2>; - power = <50>; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_sdi_pins>; - - vdds_sdi-supply = <&vaux1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - sdi_out: endpoint { - remote-endpoint = <&lcd_in>; - datapairs = <2>; - }; - }; - }; -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <1>; - }; - }; -}; - -&mcbsp2 { - status = "ok"; -}; - -&ssi_port1 { - pinctrl-names = "default"; - pinctrl-0 = <&ssi_pins>; - - ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ - - modem: hsi-client { - compatible = "nokia,n900-modem"; - - pinctrl-names = "default"; - pinctrl-0 = <&modem_pins>; - - hsi-channel-ids = <0>, <1>, <2>, <3>; - hsi-channel-names = "mcsaab-control", - "speech-control", - "speech-data", - "mcsaab-data"; - hsi-speed-kbps = <55000>; - hsi-mode = "frame"; - hsi-flow = "synchronized"; - hsi-arb-mode = "round-robin"; - - interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ - - gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ - <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ - <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ - <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ - <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ - gpio-names = "cmt_apeslpx", - "cmt_rst_rq", - "cmt_en", - "cmt_rst", - "cmt_bsi"; - }; -}; - -&ssi_port2 { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-n950-n9.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-n950-n9.dtsi deleted file mode 100644 index 5d8c4b4a4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ /dev/null @@ -1,437 +0,0 @@ -/* - * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) - * - * Written by: Aaro Koskinen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap36xx.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - operating-points = < - /* kHz uV */ - 300000 1012500 - 600000 1200000 - 800000 1325000 - 1000000 1375000 - >; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - vemmc: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "VEMMC"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */ - startup-delay-us = <150>; - enable-active-high; - }; - - vwlan_fixed: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "VWLAN"; - gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ - enable-active-high; - regulator-boot-off; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "debug::sleep"; - gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */ - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&debug_leds>; - }; - }; -}; - -&omap3_pmx_core { - accelerator_pins: pinmux_accelerator_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ - >; - }; - - debug_leds: pinmux_debug_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ - OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ - >; - }; - - ssi_pins: pinmux_ssi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ - >; - }; - - ssi_pins_idle: pinmux_ssi_pins_idle { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ - OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */ - >; - }; - - modem_pins1: pinmux_modem_core1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ - >; - }; -}; - -&omap3_pmx_core2 { - modem_pins2: pinmux_modem_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2900000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -/include/ "twl4030.dtsi" - -&twl { - compatible = "ti,twl5031"; - - twl_power: power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,pullups = <0x000001>; /* BIT(0) */ - ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ -}; - -&vdac { - regulator-name = "vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vpll1 { - regulator-name = "vpll1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vpll2 { - regulator-name = "vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vaux1 { - regulator-name = "vaux1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* CSI-2 receiver */ -&vaux2 { - regulator-name = "vaux2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -/* Cameras */ -&vaux3 { - regulator-name = "vaux3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&vaux4 { - regulator-name = "vaux4"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&vmmc1 { - regulator-name = "vmmc1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; -}; - -&vmmc2 { - regulator-name = "vmmc2"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vintana1 { - regulator-name = "vintana1"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; -}; - -&vintana2 { - regulator-name = "vintana2"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; -}; - -&vintdig { - regulator-name = "vintdig"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; -}; - -&vsim { - regulator-name = "vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vio { - regulator-name = "vio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - lis302: lis302@1d { - compatible = "st,lis3lv02d"; - reg = <0x1d>; - - Vdd-supply = <&vaux1>; - Vdd_IO-supply = <&vio>; - - pinctrl-names = "default"; - pinctrl-0 = <&accelerator_pins>; - - interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ - - /* click flags */ - st,click-single-x; - st,click-single-y; - st,click-single-z; - - /* Limits are 0.5g * value */ - st,click-threshold-x = <8>; - st,click-threshold-y = <8>; - st,click-threshold-z = <10>; - - /* Click must be longer than time limit */ - st,click-time-limit = <9>; - - /* Kind of debounce filter */ - st,click-latency = <50>; - - st,wakeup-x-hi; - st,wakeup-y-hi; - st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ - - st,wakeup2-z-hi; - st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */ - - st,highpass-cutoff-hz = <2>; - - /* Interrupt line 1 for thresholds */ - st,irq1-ff-wu-1; - st,irq1-ff-wu-2; - /* Interrupt line 2 for click detection */ - st,irq2-click; - - st,wu-duration-1 = <8>; - st,wu-duration-2 = <8>; - }; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vemmc>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ - - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; - gpmc,sync-clk-ps = <15000>; - - /* - * MTD partition table corresponding to Nokia's MeeGo 1.2 - * Harmattan release. - */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "config"; - reg = <0x00100000 0x002c0000>; - }; - partition@2 { - label = "kernel"; - reg = <0x003c0000 0x01000000>; - }; - partition@3 { - label = "log"; - reg = <0x013c0000 0x00200000>; - }; - partition@4 { - label = "var"; - reg = <0x015c0000 0x1ca40000>; - }; - partition@5 { - label = "moslo"; - reg = <0x1e000000 0x02000000>; - }; - partition@6 { - label = "omap2-onenand"; - reg = <0x00000000 0x20000000>; - }; - }; -}; - -&ssi_port1 { - pinctrl-names = "default", "idle"; - pinctrl-0 = <&ssi_pins>; - pinctrl-1 = <&ssi_pins_idle>; - - ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ - - modem: hsi-client { - pinctrl-names = "default"; - pinctrl-0 = <&modem_pins1 &modem_pins2>; - - hsi-channel-ids = <0>, <1>, <2>, <3>; - hsi-channel-names = "mcsaab-control", - "speech-control", - "speech-data", - "mcsaab-data"; - hsi-speed-kbps = <96000>; - hsi-mode = "frame"; - hsi-flow = "synchronized"; - hsi-arb-mode = "round-robin"; - - interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */ - - gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */ - <&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */ - <&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */ - gpio-names = "cmt_apeslpx", - "cmt_rst_rq", - "cmt_en"; - }; -}; - -&ssi_port2 { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-n950.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-n950.dts deleted file mode 100644 index 646601a3e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-n950.dts +++ /dev/null @@ -1,187 +0,0 @@ -/* - * omap3-n950.dts - Device Tree file for Nokia N950 - * - * Written by: Aaro Koskinen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "omap3-n950-n9.dtsi" -#include - -/ { - model = "Nokia N950"; - compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3"; - - keys { - compatible = "gpio-keys"; - - keypad_slide { - label = "Keypad Slide"; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */ - linux,input-type = ; - linux,code = ; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_slide_pins>; - }; - }; -}; - -&omap3_pmx_core { - keypad_slide_pins: pinmux_debug_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ - >; - }; -}; - -&omap3_pmx_core { - spi4_pins: pinmux_spi4_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ - OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ - >; - }; -}; - -&i2c2 { - smia_1: camera@10 { - compatible = "nokia,smia"; - reg = <0x10>; - /* No reset gpio */ - vana-supply = <&vaux3>; - clocks = <&isp 0>; - clock-frequency = <9600000>; - nokia,nvm-size = <(16 * 64)>; - port { - smia_1_1: endpoint { - link-frequencies = /bits/ 64 <210000000 333600000 398400000>; - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi2a_ep>; - }; - }; - }; -}; - -&isp { - vdd-csiphy1-supply = <&vaux2>; - vdd-csiphy2-supply = <&vaux2>; - ports { - port@2 { - reg = <2>; - csi2a_ep: endpoint { - remote-endpoint = <&smia_1_1>; - clock-lanes = <2>; - data-lanes = <3 1>; - crc = <1>; - lane-polarities = <1 1 1>; - }; - }; - }; -}; - -&mcspi4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_pins>; - - wlcore: wlcore@0 { - compatible = "ti,wl1271"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - reg = <0>; - spi-max-frequency = <48000000>; - clock-xtal; - ref-clock-frequency = <38400000>; - interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_HIGH>; /* gpio 42 */ - vwlan-supply = <&vwlan_fixed>; - }; -}; - -&modem { - compatible = "nokia,n950-modem"; -}; - -&twl { - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - }; -}; - -&twl_keypad { - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH) - MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT) - MATRIX_KEY(0x02, 0x00, KEY_COMPOSE) - MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) - MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) - MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE) - MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN) - MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP) - - MATRIX_KEY(0x03, 0x01, KEY_Z) - MATRIX_KEY(0x04, 0x01, KEY_A) - MATRIX_KEY(0x05, 0x01, KEY_Q) - MATRIX_KEY(0x06, 0x01, KEY_W) - MATRIX_KEY(0x07, 0x01, KEY_E) - - MATRIX_KEY(0x03, 0x02, KEY_X) - MATRIX_KEY(0x04, 0x02, KEY_S) - MATRIX_KEY(0x05, 0x02, KEY_D) - MATRIX_KEY(0x06, 0x02, KEY_C) - MATRIX_KEY(0x07, 0x02, KEY_V) - - MATRIX_KEY(0x03, 0x03, KEY_O) - MATRIX_KEY(0x04, 0x03, KEY_I) - MATRIX_KEY(0x05, 0x03, KEY_U) - MATRIX_KEY(0x06, 0x03, KEY_L) - MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE) - - MATRIX_KEY(0x03, 0x04, KEY_Y) - MATRIX_KEY(0x04, 0x04, KEY_K) - MATRIX_KEY(0x05, 0x04, KEY_J) - MATRIX_KEY(0x06, 0x04, KEY_H) - MATRIX_KEY(0x07, 0x04, KEY_G) - - MATRIX_KEY(0x03, 0x05, KEY_B) - MATRIX_KEY(0x04, 0x05, KEY_COMMA) - MATRIX_KEY(0x05, 0x05, KEY_M) - MATRIX_KEY(0x06, 0x05, KEY_N) - MATRIX_KEY(0x07, 0x05, KEY_DOT) - - MATRIX_KEY(0x00, 0x06, KEY_SPACE) - MATRIX_KEY(0x03, 0x06, KEY_T) - MATRIX_KEY(0x04, 0x06, KEY_UP) - MATRIX_KEY(0x05, 0x06, KEY_LEFT) - MATRIX_KEY(0x06, 0x06, KEY_RIGHT) - MATRIX_KEY(0x07, 0x06, KEY_DOWN) - - MATRIX_KEY(0x03, 0x07, KEY_P) - MATRIX_KEY(0x04, 0x07, KEY_ENTER) - MATRIX_KEY(0x05, 0x07, KEY_SLASH) - MATRIX_KEY(0x06, 0x07, KEY_F) - MATRIX_KEY(0x07, 0x07, KEY_R) - >; -}; - -&lis302 { - st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-32)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; - - st,max-limit-x = <(-3)>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi deleted file mode 100644 index 99a7eee6e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd35.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - gpio148 { - label = "overo:red:gpio148"; - gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */ - }; - gpio150 { - label = "overo:yellow:gpio150"; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */ - }; - gpio151 { - label = "overo:blue:gpio151"; - gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */ - }; - gpio170 { - label = "overo:green:gpio170"; - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */ - wakeup-source; - }; - }; -}; - -&omap3_pmx_core { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ - OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4) /* uart1_rx.gpio_151 */ - OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; -}; - -&omap3_pmx_wkup { - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */ - >; - }; -}; - -&usbhshost { - status = "disabled"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-alto35.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-alto35.dts deleted file mode 100644 index a3249eb75..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-alto35.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-alto35-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Alto35"; - compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-base.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-base.dtsi deleted file mode 100644 index 401fae838..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-base.dtsi +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * The Gumstix Overo must be combined with an expansion board. - */ - -/ { - - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - pwmleds { - compatible = "pwm-leds"; - - overo { - label = "overo:blue:COM"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; - linux,default-trigger = "mmc0"; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "overo"; - - ti,mcbsp = <&mcbsp2>; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; /* gpio_168: vbus enable */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ - vcc-supply = <&hsusb2_power>; - }; - - /* Regulator to trigger the nPoweron signal of the Wifi module */ - w3cbw003c_npoweron: regulator-w3cbw003c-npoweron { - compatible = "regulator-fixed"; - regulator-name = "regulator-w3cbw003c-npoweron"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */ - enable-active-high; - }; - - /* Regulator to trigger the nReset signal of the Wifi module */ - w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset { - pinctrl-names = "default"; - pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>; - compatible = "regulator-fixed"; - regulator-name = "regulator-w3cbw003c-wifi-nreset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */ - startup-delay-us = <10000>; - }; - - /* Regulator to trigger the nReset signal of the Bluetooth module */ - w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset { - compatible = "regulator-fixed"; - regulator-name = "regulator-w3cbw003c-bt-nreset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164: BT nReset */ - startup-delay-us = <10000>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_pins - >; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - /* WiFi/BT combo */ - w3cbw003c_pins: pinmux_w3cbw003c_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ - >; - }; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -/* i2c2 pins are used for gpio */ -&i2c2 { - status = "disabled"; -}; - -/* on board microSD slot */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; -}; - -/* optional on board WiFi */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&w3cbw003c_npoweron>; - vqmmc-supply = <&w3cbw003c_bt_nreset>; - vmmc_aux-supply = <&w3cbw003c_wifi_nreset>; - bus-width = <4>; - cap-sdio-irq; - non-removable; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcbsp2 { - status = "okay"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0 */ - <4 0 0x2b000000 0x1000000>, /* CS4 */ - <5 0 0x2c000000 0x1000000>; /* CS5 */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29c4g96maz"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0 0x80000>; /* 512KiB */ - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1C0000>; /* 1792KiB */ - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; /* 256KiB */ - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x800000>; /* 8192KiB */ - }; - partition@780000 { - label = "Filesystem"; - reg = <0xA80000 0>; - /* HACK: MTDPART_SIZ_FULL=0 so fill to end */ - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi deleted file mode 100644 index 56dbd1134..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-chestnut43.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-chestnut43.dts deleted file mode 100644 index fe0824aca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-chestnut43.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-chestnut43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Chestnut43"; - compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi deleted file mode 100644 index ae5564abb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * DVI output for some Gumstix Overo boards (Tobi and Summit) - */ - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &dvi0; - }; - - tfp410: encoder { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi deleted file mode 100644 index 854117dc0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) - */ - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lb035_pins: pinmux_lb035_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT | MUX_MODE0) /* mcspi1_cs1.mcspi1_cs1 */ - >; - }; - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ - - default-on; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - lcd0: display@1 { - compatible = "lgphilips,lb035q02"; - label = "lcd35"; - - reg = <1>; /* CS1 */ - spi-max-frequency = <500000>; - spi-cpol; - spi-cpha; - - pinctrl-names = "default"; - pinctrl-0 = <&lb035_pins>; - enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio4>; - interrupts = <18 0>; /* gpio_114 */ - pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi deleted file mode 100644 index b0753ef8a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * 4.3'' LCD panel output for some Gumstix Overo boards (Gallop43, Chestnut43) - */ - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: pinmux_lte430_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "samsung,lte430wq-f0c", "panel-dpi"; - label = "lcd43"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ - - default-on; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio4>; - interrupts = <18 0>; /* gpio_114 */ - pendown-gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi deleted file mode 100644 index 520453d95..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...) - */ - -/ { - lis33_3v3: lis33-3v3-reg { - compatible = "regulator-fixed"; - regulator-name = "lis33-3v3-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lis33_1v8: lis33-1v8-reg { - compatible = "regulator-fixed"; - regulator-name = "lis33-1v8-reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&omap3_pmx_core { - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; - - /* optional 1K EEPROM with revision information */ - eeprom@51 { - compatible = "atmel,24c01"; - reg = <0x51>; - pagesize = <8>; - }; - - lis33de: lis33de@1d { - compatible = "st,lis33de", "st,lis3lv02d"; - reg = <0x1d>; - Vdd-supply = <&lis33_1v8>; - Vdd_IO-supply = <&lis33_3v3>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi deleted file mode 100644 index 286f5badd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - -&usbhshost { - status = "disabled"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-gallop43.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-gallop43.dts deleted file mode 100644 index 241f5c191..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-gallop43.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-gallop43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Gallop43"; - compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi deleted file mode 100644 index a8020fb42..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2015 Ash Charles, Gumstix Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd35.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo35.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo35.dts deleted file mode 100644 index e3e2bce6e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo35.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2015 Ash Charles, Gumstix Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-palo35-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Palo35"; - compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi deleted file mode 100644 index 11965737e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-lcd43.dtsi" - -#include - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - gpio22 { - label = "overo:blue:gpio22"; - gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ - wakeup-source; - }; - button1 { - label = "button1"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ - wakeup-source; - }; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo43.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo43.dts deleted file mode 100644 index cedb103b4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-palo43.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-palo43-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Palo43"; - compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-alto35.dts deleted file mode 100644 index e9cae52af..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-alto35.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Alto35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-alto35-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35"; - compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts deleted file mode 100644 index 7d82fdfd9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Chestnut43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-chestnut43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43"; - compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts deleted file mode 100644 index a1b57e0cf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Gallop43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-gallop43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43"; - compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-palo35.dts deleted file mode 100644 index 4e725d2d0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-palo35.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Palo35 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-palo35-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35"; - compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-palo43.dts deleted file mode 100644 index b585d8fbc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-palo43.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Palo43 expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-palo43-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43"; - compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-summit.dts deleted file mode 100644 index a0d7fd836..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-summit.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-summit-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit"; - compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-tobi.dts deleted file mode 100644 index 879383aca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-tobi.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-tobi-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi"; - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts deleted file mode 100644 index da6afafcc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo-storm.dtsi" -#include "omap3-overo-tobiduo-common.dtsi" - -/ { - model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo"; - compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm.dtsi deleted file mode 100644 index 6cb418b41..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-storm.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap36xx.dtsi" -#include "omap3-overo-base.dtsi" - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-summit-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-summit-common.dtsi deleted file mode 100644 index 0ac97ba98..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-summit-common.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-dvi.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-summit.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-summit.dts deleted file mode 100644 index 697656094..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-summit.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Summit expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-summit-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Summit"; - compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ - >; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi deleted file mode 100644 index 1b304e2f1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" -#include "omap3-overo-common-dvi.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - heartbeat { - label = "overo:red:gpio21"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; -}; - -&lis33de { - status = "disabled"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobi.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobi.dts deleted file mode 100644 index fd6400efc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobi.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Tobi expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-tobi-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on Tobi"; - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi deleted file mode 100644 index 82e98ee30..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -#include "omap3-overo-common-peripherals.dtsi" - -#include "omap-gpmc-smsc9221.dtsi" - -&gpmc { - smsc1: ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ - }; - - smsc2: ethernet@4,0 { - compatible = "smsc,lan9221","smsc,lan9115"; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <42>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <12>; - gpmc,adv-wr-off-ns = <12>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <42>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <36>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <54>; - gpmc,access-ns = <36>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wr-data-mux-bus-ns = <18>; - gpmc,wr-access-ns = <42>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - - reg = <4 0 0xff>; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* GPIO 65 */ - }; -}; - -&lis33de { - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobiduo.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobiduo.dts deleted file mode 100644 index b9ce310f6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo-tobiduo.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2015 Ash Charles, Gumstix, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * TobiDuo expansion board is manufactured by Gumstix Inc. - */ - -/dts-v1/; - -#include "omap3-overo.dtsi" -#include "omap3-overo-tobiduo-common.dtsi" - -/ { - model = "OMAP35xx Gumstix Overo on TobiDuo"; - compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-overo.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-overo.dtsi deleted file mode 100644 index 932a02ff5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-overo.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap34xx.dtsi" -#include "omap3-overo-base.dtsi" - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-1ghz.dts deleted file mode 100644 index 25498f756..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-1ghz.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2015 - * Nikolaus Schaller - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * device tree for OpenPandora 1GHz with DM3730 - */ - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-pandora-common.dtsi" - -/ { - model = "Pandora Handheld Console 1GHz"; - - compatible = "openpandora,omap3-pandora-1ghz", "ti,omap36xx", "ti,omap3"; -}; - -&omap3_pmx_core2 { - - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - &control_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - >; - }; - - control_pins: pinmux_control_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ - OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT | MUX_MODE4) /* reserved.gpio_127 = MMC2_WP */ - OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 = MMC1_WP */ - OMAP3_WKUP_IOPAD(0x2a58, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_128 = LED_MMC1 */ - OMAP3_WKUP_IOPAD(0x2a5a, PIN_OUTPUT | MUX_MODE4) /* reserved.gpio_129 = LED_MMC2 */ - - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-600mhz.dts deleted file mode 100644 index 8775897a4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-600mhz.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2015 - * Nikolaus Schaller - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * device tree for OpenPandora with OMAP3530 - */ - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-pandora-common.dtsi" - -/ { - model = "Pandora Handheld Console"; - - compatible = "openpandora,omap3-pandora-600mhz", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - - pinctrl-names = "default"; - pinctrl-0 = < - &hsusb2_2_pins - &control_pins - >; - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - >; - }; - - control_pins: pinmux_control_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ - OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ - OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 = RESET_USB_HOST */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE4) /* etk_d7.gpio_21 = WIFI IRQ */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 = MSECURE */ - OMAP3430_CORE2_IOPAD(0x25ee, PIN_OUTPUT | MUX_MODE4) /* etk_d9.gpio_23 = WIFI_POWER */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-common.dtsi deleted file mode 100644 index 53e007abd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ /dev/null @@ -1,690 +0,0 @@ -/* - * Copyright (C) 2015 - * Nikolaus Schaller - * - * Common device tree include for OpenPandora devices. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - aliases { - display0 = &lcd; - }; - - tv: connector { - compatible = "connector-analog-tv"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; - }; - - gpio-leds { - - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - label = "pandora::sd1"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "pandora::sd2"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led3 { - label = "pandora::bluetooth"; - gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led4 { - label = "pandora::wifi"; - gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ - linux,default-trigger = "mmc2"; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&button_pins>; - - up-button { - label = "up"; - linux,code = ; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* GPIO_110 */ - wakeup-source; - }; - - down-button { - label = "down"; - linux,code = ; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* GPIO_103 */ - wakeup-source; - }; - - left-button { - label = "left"; - linux,code = ; - gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */ - wakeup-source; - }; - - right-button { - label = "right"; - linux,code = ; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; /* GPIO_98 */ - wakeup-source; - }; - - pageup-button { - label = "game 1"; - linux,code = ; - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* GPIO_109 */ - wakeup-source; - }; - - pagedown-button { - label = "game 3"; - linux,code = ; - gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* GPIO_106 */ - wakeup-source; - }; - - home-button { - label = "game 4"; - linux,code = ; - gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* GPIO_101 */ - wakeup-source; - }; - - end-button { - label = "game 2"; - linux,code = ; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* GPIO_111 */ - wakeup-source; - }; - - right-shift { - label = "l"; - linux,code = ; - gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* GPIO_102 */ - wakeup-source; - }; - - kp-plus { - label = "l2"; - linux,code = ; - gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; /* GPIO_97 */ - wakeup-source; - }; - - right-ctrl { - label = "r"; - linux,code = ; - gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* GPIO_105 */ - wakeup-source; - }; - - kp-minus { - label = "r2"; - linux,code = ; - gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* GPIO_107 */ - wakeup-source; - }; - - left-ctrl { - label = "ctrl"; - linux,code = ; - gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* GPIO_104 */ - wakeup-source; - }; - - menu { - label = "menu"; - linux,code = ; - gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; /* GPIO_99 */ - wakeup-source; - }; - - hold { - label = "hold"; - linux,code = ; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* GPIO_176 */ - wakeup-source; - }; - - left-alt { - label = "alt"; - linux,code = ; - gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* GPIO_100 */ - wakeup-source; - }; - - lid { - label = "lid"; - linux,code = <0x00>; /* SW_LID lid shut */ - linux,input-type = <0x05>; /* EV_SW */ - gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; /* GPIO_108 */ - }; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ - vcc-supply = <&vaux2>; - }; - - /* HS USB Host VBUS supply - * disabling this regulator causes current leakage, and LCD flicker - * on earlier (CC) board revisions, so keep it always on */ - usb_host_5v: fixed-regulator-usb_host_5v { - compatible = "regulator-fixed"; - regulator-name = "usb_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */ - }; - - /* wg7210 (wifi+bt module) 32k clock buffer */ - wg7210_32k: fixed-regulator-wg7210_32k { - compatible = "regulator-fixed"; - regulator-name = "wg7210_32k"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - enable-active-high; - gpio = <&twl_gpio 13 GPIO_ACTIVE_HIGH>; - }; -}; - -&omap3_pmx_core { - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dirdat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dirdat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dircmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* GPIO_157 = lcd reset */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - led_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ - OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE4) /* GPIO_158 */ - OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ - OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* GPIO_98 */ - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE4) /* GPIO_99 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE4) /* GPIO_100 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* GPIO_101 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* GPIO_102 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE4) /* GPIO_103 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE4) /* GPIO_104 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE4) /* GPIO_105 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE4) /* GPIO_106 */ - OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE4) /* GPIO_107 */ - OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE4) /* GPIO_108 */ - OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* GPIO_109 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT | MUX_MODE4) /* GPIO_110 */ - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* GPIO_111 */ - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ - >; - }; - - penirq_pins: pinmux_penirq_pins { - pinctrl-single,pins = < - /* here we could enable to wakeup the cpu from suspend by a pen touch */ - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ - >; - }; - -}; - -&omap3_pmx_core2 { - /* define in CPU specific file that includes this one - * use either OMAP3430_CORE2_IOPAD() or OMAP3630_CORE2_IOPAD() - */ -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_power: power { - compatible = "ti,twl4030-power-reset"; - ti,use_poweroff; - }; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - - codec { - ti,ramp_delay_value = <3>; - }; - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl_keypad { - keypad,num-rows = <8>; - keypad,num-columns = <6>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_9) - MATRIX_KEY(0, 1, KEY_8) - MATRIX_KEY(0, 2, KEY_I) - MATRIX_KEY(0, 3, KEY_J) - MATRIX_KEY(0, 4, KEY_N) - MATRIX_KEY(0, 5, KEY_M) - MATRIX_KEY(1, 0, KEY_0) - MATRIX_KEY(1, 1, KEY_7) - MATRIX_KEY(1, 2, KEY_U) - MATRIX_KEY(1, 3, KEY_H) - MATRIX_KEY(1, 4, KEY_B) - MATRIX_KEY(1, 5, KEY_SPACE) - MATRIX_KEY(2, 0, KEY_BACKSPACE) - MATRIX_KEY(2, 1, KEY_6) - MATRIX_KEY(2, 2, KEY_Y) - MATRIX_KEY(2, 3, KEY_G) - MATRIX_KEY(2, 4, KEY_V) - MATRIX_KEY(2, 5, KEY_FN) - MATRIX_KEY(3, 0, KEY_O) - MATRIX_KEY(3, 1, KEY_5) - MATRIX_KEY(3, 2, KEY_T) - MATRIX_KEY(3, 3, KEY_F) - MATRIX_KEY(3, 4, KEY_C) - MATRIX_KEY(4, 0, KEY_P) - MATRIX_KEY(4, 1, KEY_4) - MATRIX_KEY(4, 2, KEY_R) - MATRIX_KEY(4, 3, KEY_D) - MATRIX_KEY(4, 4, KEY_X) - MATRIX_KEY(5, 0, KEY_K) - MATRIX_KEY(5, 1, KEY_3) - MATRIX_KEY(5, 2, KEY_E) - MATRIX_KEY(5, 3, KEY_S) - MATRIX_KEY(5, 4, KEY_Z) - MATRIX_KEY(6, 0, KEY_L) - MATRIX_KEY(6, 1, KEY_2) - MATRIX_KEY(6, 2, KEY_W) - MATRIX_KEY(6, 3, KEY_A) - MATRIX_KEY(6, 4, KEY_RIGHTBRACE) - MATRIX_KEY(7, 0, KEY_ENTER) - MATRIX_KEY(7, 1, KEY_1) - MATRIX_KEY(7, 2, KEY_Q) - MATRIX_KEY(7, 3, KEY_LEFTSHIFT) - MATRIX_KEY(7, 4, KEY_LEFTBRACE ) - >; -}; - -/* backup battery charger */ -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -/* MMC2 */ -&vmmc2 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; -}; - -/* LCD */ -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -/* USB Host PHY */ -&vaux2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -/* available on expansion connector */ -&vaux3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* ADS7846 and nubs */ -&vaux4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -/* power audio DAC and LID sensor */ -&vsim { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; -}; - -&i2c2 { - clock-frequency = <100000>; - /* no clients so we should disable clock */ -}; - -&i2c3 { - clock-frequency = <100000>; - - bq27500@55 { - compatible = "ti,bq27500"; - reg = <0x55>; - }; - -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -/* - * Many pandora boards have been produced with defective write-protect switches - * on either slot, so it was decided not to use this feature. If you know - * your board has good switches, feel free to uncomment wp-gpios below. - */ -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; - /*wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;*/ /* GPIO_126 */ -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmc2>; - bus-width = <4>; - cd-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; - /*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */ -}; - -/* mmc3 is probed using pdata-quirks to pass wl1251 card data */ -&mmc3 { - status = "disabled"; -}; - -/* bluetooth*/ -&uart1 { -}; - -/* spare (expansion connector) */ -&uart2 { -}; - -/* console (expansion connector) */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "sw"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - - #address-cells = <1>; - #size-cells = <1>; - - /* u-boot uses mtdparts=nand:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs) */ - - x-loader@0 { - label = "xloader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "uboot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "uboot-env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "boot"; - reg = <0x280000 0xa00000>; - }; - - filesystem@c80000 { - label = "rootfs"; - reg = <0xc80000 0>; /* 0 = MTDPART_SIZ_FULL */ - }; - }; -}; - -&mcspi1 { - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - spi-max-frequency = <1000000>; - pinctrl-names = "default"; - pinctrl-0 = <&penirq_pins>; - interrupt-parent = <&gpio3>; - interrupts = <30 0>; /* GPIO_94 */ - pendown-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - vcc-supply = <&vaux4>; - - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <8000>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4800>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; - - lcd: lcd@1 { - reg = <1>; /* CS1 */ - compatible = "omapdss,tpo,td043mtea1"; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; /* GPIO_157 */ - vcc-supply = <&vaux1>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - -}; - -/* n/a - used as GPIOs */ -&mcbsp1 { -}; - -/* audio DAC */ -&mcbsp2 { -}; - -/* bluetooth */ -&mcbsp3 { -}; - -/* to twl4030*/ -&mcbsp4 { -}; - -&venc { - status = "ok"; - - vdda-supply = <&vdac>; - - port { - venc_out: endpoint { - remote-endpoint = <&tv_connector_in>; - ti,channels = <2>; - }; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < &dss_dpi_pins >; - - status = "ok"; - vdds_dsi-supply = <&vpll2>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi deleted file mode 100644 index 157345bb8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Common file for omap dpi panels with QVGA and reset pins - * - * Note that the board specifc DTS file needs to specify - * at minimum the GPIO enable-gpios for display, and - * gpios for gpio-backlight. - */ - -/ { - aliases { - display0 = &lcd0; - }; - - backlight0: backlight { - compatible = "gpio-backlight"; - default-on; - }; - - /* 3.3V GPIO controlled regulator for LCD_ENVDD */ - lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - lcd0: display { - compatible = "sharp,ls037v7dw01"; - label = "lcd"; - power-supply = <&lcd_3v3>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <18>; - }; - }; -}; - -&mcspi1 { - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - spi-max-frequency = <1000000>; - vcc-supply = <&lcd_3v3>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <8000>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4800>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy; - wakeup-source; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-sb-t35.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-sb-t35.dtsi deleted file mode 100644 index 73643fabd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 - */ - -/ { - tfp410: encoder { - compatible = "ti,tfp410"; - - powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ - - pinctrl-names = "default"; - pinctrl-0 = <&tfp410_pins>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector { - compatible = "dvi-connector"; - label = "dvi"; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - audio_amp: audio_amp { - compatible = "regulator-fixed"; - regulator-name = "audio_amp"; - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_audio_amp>; - gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */ - enable-active-low; - regulator-always-on; - }; -}; - -&omap3_pmx_core { - smsc2_pins: pinmux_smsc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ - OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ - >; - }; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - sb_t35_audio_amp: pinmux_sb_t35_audio_amp { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */ - >; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "at24,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -&gpmc { - ranges = <4 0 0x2d000000 0x01000000>; - - smsc2: ethernet@4,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - pinctrl-names = "default"; - pinctrl-0 = <&smsc2_pins>; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - reg = <4 0 0xff>; - bank-width = <2>; - gpmc,device-width = <1>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <5>; - gpmc,cs-rd-off-ns = <150>; - gpmc,cs-wr-off-ns = <150>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <15>; - gpmc,adv-wr-off-ns = <40>; - gpmc,oe-on-ns = <45>; - gpmc,oe-off-ns = <140>; - gpmc,we-on-ns = <45>; - gpmc,we-off-ns = <140>; - gpmc,rd-cycle-ns = <155>; - gpmc,wr-cycle-ns = <155>; - gpmc,access-ns = <120>; - gpmc,page-burst-access-ns = <20>; - gpmc,bus-turnaround-ns = <75>; - gpmc,cycle2cycle-delay-ns = <75>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wr-access-ns = <0>; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3517.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3517.dts deleted file mode 100644 index c2d5c28a1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3517.dts +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Suppport for CompuLab SBC-T3517 with CM-T3517 - */ - -#include "omap3-cm-t3517.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3517 with CM-T3517"; - compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; - - /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ - vddvario: regulator-vddvario-sb-t35 { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a-sb-t35 { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &sb_t35_usb_hub_pins - &usb_hub_pins - >; - - mmc1_aux_pins: pinmux_mmc1_aux_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ - >; - }; - - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc1_pins - &mmc1_aux_pins - >; - - wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ - cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&gpmc { - ranges = <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3530.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3530.dts deleted file mode 100644 index 834bc786c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3530.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Suppport for CompuLab SBC-T3530 with CM-T3530 - */ - -#include "omap3-cm-t3530.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3530 with CM-T3530"; - compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_usb_hub_pins>; - - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ - >; - }; -}; - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; - -&mmc1 { - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3730.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3730.dts deleted file mode 100644 index 73c7bf4a4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-sbc-t3730.dts +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Suppport for CompuLab SBC-T3730 with CM-T3730 - */ - -#include "omap3-cm-t3730.dts" -#include "omap3-sb-t35.dtsi" - -/ { - model = "CompuLab SBC-T3730 with CM-T3730"; - compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; - - aliases { - display0 = &dvi0; - display1 = &tv0; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&sb_t35_usb_hub_pins>; - - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ - >; - }; -}; - -&gpmc { - ranges = <5 0 0x2c000000 0x01000000>, /* CM-T3x30 SMSC9x Eth */ - <4 0 0x2d000000 0x01000000>, /* SB-T35 SMSC9x Eth */ - <0 0 0x00000000 0x01000000>; /* CM-T3x NAND */ -}; - -&dss { - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-sniper.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-sniper.dts deleted file mode 100644 index bc4498e77..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-sniper.dts +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2015-2016 Paul Kocialkowski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include - -/ { - model = "LG Optimus Black"; - compatible = "lg,omap3-sniper", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ - >; - }; - - dp3t_sel_pins: pinmux_dp3t_sel_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - lp8720_en_pin: pinmux_lp8720_en_pin { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7 */ - >; - }; - - usb_otg_hs_pins: pinmux_usb_otg_hs_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7 */ - >; - }; -}; - -&omap3_pmx_wkup { - pinctrl-names = "default"; - - mmc1_cd_pin: pinmux_mmc1_cd_pin { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */ - >; - }; -}; - -&gpio2 { - ti,no-reset-on-init; -}; - -&gpio5 { - ti,no-reset-on-init; -}; - -&gpio6 { - ti,no-reset-on-init; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &dp3t_sel_pins>; - - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - lp8720@7d { - pinctrl-names = "default"; - pinctrl-0 = <&lp8720_en_pin>; - - compatible = "ti,lp8720"; - reg = <0x7d>; - - enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio_37 */ - - lp8720_ldo1: ldo1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1_cd_pin>; - - vmmc-supply = <&lp8720_ldo1>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio 10 */ - bus-width = <4>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - vmmc-supply = <&vmmc2>; - ti,non-removable; - bus-width = <8>; -}; - -&mmc3 { - status = "disabled"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_hs_pins>; - - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(0x00, 0x00, KEY_VOLUMEUP) - MATRIX_KEY(0x01, 0x00, KEY_VOLUMEDOWN) - MATRIX_KEY(0x02, 0x00, KEY_SELECT) - >; -}; - -/* - * The TWL4030 VAUX2 and VDAC regulators power sensors that are slaves on I2C3. - * When not powered, these sensors cause the I2C3 clock to stay low at all times, - * making it impossible to reach other devices on I2C3. - */ - -&vaux2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; -}; - -&vdac { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-tao3530.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3-tao3530.dtsi deleted file mode 100644 index dc80886b5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-tao3530.dtsi +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/* Secure omaps have some devices inaccessible depending on the firmware */ -&aes { - status = "disabled"; -}; - -&sham { - status = "disabled"; -}; - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ - vcc-supply = <&hsusb2_power>; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - /* McBSP2 is used for onboard sound, same as on beagle */ - ti,mcbsp = <&mcbsp2>; - }; - - /* Regulator to enable/switch the vcc of the Wifi module */ - mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { - compatible = "regulator-fixed"; - regulator-name = "regulator-mmc2-sdio-poweron"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ - enable-active-low; - startup-delay-us = <10000>; - }; -}; - -&omap3_pmx_core { - hsusbb2_pins: pinmux_hsusbb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - /* wlan GPIO output for WLAN_EN */ - wlan_gpio: pinmux_wlan_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */ - OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */ - >; - }; - - mcbsp3_pins: pinmux_mcbsp3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ - OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ - OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */ - OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */ - >; - }; -}; - -/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */ -&mcbsp1 { - status = "disabled"; -}; - -&mcbsp2 { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; - - spidev@0 { - compatible = "spidev"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-cpha; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; - bus-width = <8>; -}; - -// WiFi (Marvell 88W8686) on MMC2/SDIO -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&mmc2_sdio_poweron>; - non-removable; - bus-width = <4>; - cap-power-off-card; -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&mcbsp3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp3_pins>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <16>; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - ti,nand-ecc-opt = "sw"; - - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&vaux2 { - regulator-name = "vdd_ehci"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-thunder.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-thunder.dts deleted file mode 100644 index 9736ba79b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-thunder.dts +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2014 Stefan Roese - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap3-tao3530.dtsi" - -/ { - model = "TI OMAP3 Thunder baseboard with TAO3530 SOM"; - compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; -}; - -&omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - lte430_pins: pinmux_lte430_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - compatible = "samsung,lte430wq-f0c", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <<e430_pins>; - enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <2>; - vfront-porch = <3>; - vsync-len = <11>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - - backlight { - compatible = "gpio-backlight"; - - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ - - default-on; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3-zoom3.dts b/software/linux/kernel/arch/arm/boot/dts/omap3-zoom3.dts deleted file mode 100644 index 45e2ce080..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3-zoom3.dts +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap-zoom-common.dtsi" - -/ { - model = "TI Zoom3"; - compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&omap3_pmx_core { - /* REVISIT: twl gpio0 is mmc0_cd */ - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ - OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ - >; - }; -}; - -&omap3_pmx_core2 { - mmc3_2_pins: pinmux_mmc3_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - >; - }; -}; - -&omap3_pmx_wkup { - wlan_host_wkup: pinmux_wlan_host_wkup_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; -/* -&mmc2 { - vmmc-supply = <&vmmc2>; - ti,non-removable; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; -*/ -&mmc3 { - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */ - ref-clock-frequency = <26000000>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - mode = <3>; - power = <50>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3.dtsi deleted file mode 100644 index 2008648b8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3.dtsi +++ /dev/null @@ -1,853 +0,0 @@ -/* - * Device Tree Source for OMAP3 SoC - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include - -/ { - compatible = "ti,omap3430", "ti,omap3"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0x0>; - - clocks = <&dpll1_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - }; - - pmu@54000000 { - compatible = "arm,cortex-a8-pmu"; - reg = <0x54000000 0x800000>; - interrupts = <3>; - ti,hwmods = "debugss"; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - - iva: iva { - compatible = "ti,iva2.2"; - ti,hwmods = "iva"; - - dsp { - compatible = "ti,omap3-c64"; - }; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP3 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp@68000000 { - compatible = "ti,omap3-l3-smx", "simple-bus"; - reg = <0x68000000 0x10000>; - interrupts = <9 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main"; - - l4_core: l4@48000000 { - compatible = "ti,omap3-l4-core", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x1000000>; - - scm: scm@2000 { - compatible = "ti,omap3-scm", "simple-bus"; - reg = <0x2000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x2000>; - - omap3_pmx_core: pinmux@30 { - compatible = "ti,omap3-padconf", - "pinctrl-single"; - reg = <0x30 0x238>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon", "simple-bus"; - reg = <0x270 0x330>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x270 0x330>; - - pbias_regulator: pbias_regulator@2b0 { - compatible = "ti,pbias-omap3", "ti,pbias-omap"; - reg = <0x2b0 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - scm_clockdomains: clockdomains { - }; - - omap3_pmx_wkup: pinmux@a00 { - compatible = "ti,omap3-padconf", - "pinctrl-single"; - reg = <0xa00 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - }; - }; - - aes: aes@480c5000 { - compatible = "ti,omap3-aes"; - ti,hwmods = "aes"; - reg = <0x480c5000 0x50>; - interrupts = <0>; - dmas = <&sdma 65 &sdma 66>; - dma-names = "tx", "rx"; - }; - - prm: prm@48306000 { - compatible = "ti,omap3-prm"; - reg = <0x48306000 0x4000>; - interrupts = <11>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - cm: cm@48004000 { - compatible = "ti,omap3-cm"; - reg = <0x48004000 0x4000>; - - cm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@48320000 { - compatible = "ti,omap-counter32k"; - reg = <0x48320000 0x20>; - ti,hwmods = "counter_32k"; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,omap3-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - sdma: dma-controller@48056000 { - compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <96>; - }; - - gpio1: gpio@48310000 { - compatible = "ti,omap3-gpio"; - reg = <0x48310000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@49050000 { - compatible = "ti,omap3-gpio"; - reg = <0x49050000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@49052000 { - compatible = "ti,omap3-gpio"; - reg = <0x49052000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@49054000 { - compatible = "ti,omap3-gpio"; - reg = <0x49054000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@49056000 { - compatible = "ti,omap3-gpio"; - reg = <0x49056000 0x200>; - interrupts = <33>; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@49058000 { - compatible = "ti,omap3-gpio"; - reg = <0x49058000 0x200>; - interrupts = <34>; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap3-uart"; - reg = <0x4806a000 0x2000>; - interrupts-extended = <&intc 72>; - dmas = <&sdma 49 &sdma 50>; - dma-names = "tx", "rx"; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap3-uart"; - reg = <0x4806c000 0x400>; - interrupts-extended = <&intc 73>; - dmas = <&sdma 51 &sdma 52>; - dma-names = "tx", "rx"; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - }; - - uart3: serial@49020000 { - compatible = "ti,omap3-uart"; - reg = <0x49020000 0x400>; - interrupts-extended = <&intc 74>; - dmas = <&sdma 53 &sdma 54>; - dma-names = "tx", "rx"; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap3-i2c"; - reg = <0x48070000 0x80>; - interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap3-i2c"; - reg = <0x48072000 0x80>; - interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap3-i2c"; - reg = <0x48060000 0x80>; - interrupts = <61>; - dmas = <&sdma 25 &sdma 26>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap3-mailbox"; - ti,hwmods = "mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>; - #mbox-cells = <1>; - ti,mbox-num-users = <2>; - ti,mbox-num-fifos = <2>; - mbox_dsp: dsp { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap2-mcspi"; - reg = <0x48098000 0x100>; - interrupts = <65>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap2-mcspi"; - reg = <0x4809a000 0x100>; - interrupts = <66>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap2-mcspi"; - reg = <0x480b8000 0x100>; - interrupts = <91>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, - <&sdma 16>, - <&sdma 23>, - <&sdma 24>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap2-mcspi"; - reg = <0x480ba000 0x100>; - interrupts = <48>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - ti,hwmods = "hdq1w"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x4809c000 0x200>; - interrupts = <83>; - ti,hwmods = "mmc1"; - ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x480b4000 0x200>; - interrupts = <86>; - ti,hwmods = "mmc2"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap3-hsmmc"; - reg = <0x480ad000 0x200>; - interrupts = <94>; - ti,hwmods = "mmc3"; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - - mmu_isp: mmu@480bd400 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x480bd400 0x80>; - interrupts = <24>; - ti,hwmods = "mmu_isp"; - ti,#tlb-entries = <8>; - }; - - mmu_iva: mmu@5d000000 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x5d000000 0x80>; - interrupts = <28>; - ti,hwmods = "mmu_iva"; - status = "disabled"; - }; - - wdt2: wdt@48314000 { - compatible = "ti,omap3-wdt"; - reg = <0x48314000 0x80>; - ti,hwmods = "wd_timer2"; - }; - - mcbsp1: mcbsp@48074000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x48074000 0xff>; - reg-names = "mpu"; - interrupts = <16>, /* OCP compliant interrupt */ - <59>, /* TX interrupt */ - <60>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - clocks = <&mcbsp1_fck>; - clock-names = "fck"; - status = "disabled"; - }; - - mcbsp2: mcbsp@49022000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49022000 0xff>, - <0x49028000 0xff>; - reg-names = "mpu", "sidetone"; - interrupts = <17>, /* OCP compliant interrupt */ - <62>, /* TX interrupt */ - <63>, /* RX interrupt */ - <4>; /* Sidetone */ - interrupt-names = "common", "tx", "rx", "sidetone"; - ti,buffer-size = <1280>; - ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; - clock-names = "fck", "ick"; - status = "disabled"; - }; - - mcbsp3: mcbsp@49024000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49024000 0xff>, - <0x4902a000 0xff>; - reg-names = "mpu", "sidetone"; - interrupts = <22>, /* OCP compliant interrupt */ - <89>, /* TX interrupt */ - <90>, /* RX interrupt */ - <5>; /* Sidetone */ - interrupt-names = "common", "tx", "rx", "sidetone"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; - clock-names = "fck", "ick"; - status = "disabled"; - }; - - mcbsp4: mcbsp@49026000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49026000 0xff>; - reg-names = "mpu"; - interrupts = <23>, /* OCP compliant interrupt */ - <54>, /* TX interrupt */ - <55>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - clocks = <&mcbsp4_fck>; - clock-names = "fck"; - status = "disabled"; - }; - - mcbsp5: mcbsp@48096000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x48096000 0xff>; - reg-names = "mpu"; - interrupts = <27>, /* OCP compliant interrupt */ - <81>, /* TX interrupt */ - <82>; /* RX interrupt */ - interrupt-names = "common", "tx", "rx"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp5"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; - clocks = <&mcbsp5_fck>; - clock-names = "fck"; - status = "disabled"; - }; - - sham: sham@480c3000 { - compatible = "ti,omap3-sham"; - ti,hwmods = "sham"; - reg = <0x480c3000 0x64>; - interrupts = <49>; - dmas = <&sdma 69>; - dma-names = "rx"; - }; - - smartreflex_core: smartreflex@480cb000 { - compatible = "ti,omap3-smartreflex-core"; - ti,hwmods = "smartreflex_core"; - reg = <0x480cb000 0x400>; - interrupts = <19>; - }; - - smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-iva"; - ti,hwmods = "smartreflex_mpu_iva"; - reg = <0x480c9000 0x400>; - interrupts = <18>; - }; - - timer1: timer@48318000 { - compatible = "ti,omap3430-timer"; - reg = <0x48318000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@49032000 { - compatible = "ti,omap3430-timer"; - reg = <0x49032000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; - }; - - timer3: timer@49034000 { - compatible = "ti,omap3430-timer"; - reg = <0x49034000 0x400>; - interrupts = <39>; - ti,hwmods = "timer3"; - }; - - timer4: timer@49036000 { - compatible = "ti,omap3430-timer"; - reg = <0x49036000 0x400>; - interrupts = <40>; - ti,hwmods = "timer4"; - }; - - timer5: timer@49038000 { - compatible = "ti,omap3430-timer"; - reg = <0x49038000 0x400>; - interrupts = <41>; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@4903a000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903a000 0x400>; - interrupts = <42>; - ti,hwmods = "timer6"; - ti,timer-dsp; - }; - - timer7: timer@4903c000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903c000 0x400>; - interrupts = <43>; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@4903e000 { - compatible = "ti,omap3430-timer"; - reg = <0x4903e000 0x400>; - interrupts = <44>; - ti,hwmods = "timer8"; - ti,timer-pwm; - ti,timer-dsp; - }; - - timer9: timer@49040000 { - compatible = "ti,omap3430-timer"; - reg = <0x49040000 0x400>; - interrupts = <45>; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap3430-timer"; - reg = <0x48086000 0x400>; - interrupts = <46>; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap3430-timer"; - reg = <0x48088000 0x400>; - interrupts = <47>; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - timer12: timer@48304000 { - compatible = "ti,omap3430-timer"; - reg = <0x48304000 0x400>; - interrupts = <95>; - ti,hwmods = "timer12"; - ti,timer-alwon; - ti,timer-secure; - }; - - usbhstll: usbhstll@48062000 { - compatible = "ti,usbhs-tll"; - reg = <0x48062000 0x1000>; - interrupts = <78>; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@48064000 { - compatible = "ti,usbhs-host"; - reg = <0x48064000 0x400>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbhsohci: ohci@48064400 { - compatible = "ti,ohci-omap3"; - reg = <0x48064400 0x400>; - interrupt-parent = <&intc>; - interrupts = <76>; - }; - - usbhsehci: ehci@48064800 { - compatible = "ti,ehci-omap"; - reg = <0x48064800 0x400>; - interrupt-parent = <&intc>; - interrupts = <77>; - }; - }; - - gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x02d0>; - interrupts = <20>; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - usb_otg_hs: usb_otg_hs@480ab000 { - compatible = "ti,omap3-musb"; - reg = <0x480ab000 0x1000>; - interrupts = <92>, <93>; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - }; - - dss: dss@48050000 { - compatible = "ti,omap3-dss"; - reg = <0x48050000 0x200>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&dss1_alwon_fck>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@48050400 { - compatible = "ti,omap3-dispc"; - reg = <0x48050400 0x400>; - interrupts = <25>; - ti,hwmods = "dss_dispc"; - clocks = <&dss1_alwon_fck>; - clock-names = "fck"; - }; - - dsi: encoder@4804fc00 { - compatible = "ti,omap3-dsi"; - reg = <0x4804fc00 0x200>, - <0x4804fe00 0x40>, - <0x4804ff00 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = <25>; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; - clock-names = "fck", "sys_clk"; - }; - - rfbi: encoder@48050800 { - compatible = "ti,omap3-rfbi"; - reg = <0x48050800 0x100>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&dss1_alwon_fck>, <&dss_ick>; - clock-names = "fck", "ick"; - }; - - venc: encoder@48050c00 { - compatible = "ti,omap3-venc"; - reg = <0x48050c00 0x100>; - status = "disabled"; - ti,hwmods = "dss_venc"; - clocks = <&dss_tv_fck>; - clock-names = "fck"; - }; - }; - - ssi: ssi-controller@48058000 { - compatible = "ti,omap3-ssi"; - ti,hwmods = "ssi"; - - status = "disabled"; - - reg = <0x48058000 0x1000>, - <0x48059000 0x1000>; - reg-names = "sys", - "gdd"; - - interrupts = <71>; - interrupt-names = "gdd_mpu"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ssi_port1: ssi-port@4805a000 { - compatible = "ti,omap3-ssi-port"; - - reg = <0x4805a000 0x800>, - <0x4805a800 0x800>; - reg-names = "tx", - "rx"; - - interrupt-parent = <&intc>; - interrupts = <67>, - <68>; - }; - - ssi_port2: ssi-port@4805b000 { - compatible = "ti,omap3-ssi-port"; - - reg = <0x4805b000 0x800>, - <0x4805b800 0x800>; - reg-names = "tx", - "rx"; - - interrupt-parent = <&intc>; - interrupts = <69>, - <70>; - }; - }; - }; -}; - -/include/ "omap3xxx-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3430-sdp.dts b/software/linux/kernel/arch/arm/boot/dts/omap3430-sdp.dts deleted file mode 100644 index abd692114..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3430-sdp.dts +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "TI OMAP3430 SDP"; - compatible = "ti,omap3430-sdp", "ti,omap3"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - /* - * S6-3 must be in ON position for 8 bit mode to function - * Else, use 4 bit mode - */ - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x10000000 0x08000000>, - <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ - <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,pf48f6000m0y1be"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x08000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - partition@0 { - label = "bootloader-nor"; - reg = <0 0x40000>; - }; - partition@40000 { - label = "params-nor"; - reg = <0x40000 0x40000>; - }; - partition@80000 { - label = "kernel-nor"; - reg = <0x80000 0x200000>; - }; - partition@280000 { - label = "filesystem-nor"; - reg = <0x240000 0x7d80000>; - }; - }; - - nand@1,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f1g08abb"; - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "sw"; - nand-bus-width = <8>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - partition@0 { - label = "xloader-nand"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "bootloader-nand"; - reg = <0x80000 0x140000>; - }; - partition@1c0000 { - label = "params-nand"; - reg = <0x1c0000 0xc0000>; - }; - partition@280000 { - label = "kernel-nand"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "filesystem-nand"; - reg = <0x780000 0x7880000>; - }; - }; - - onenand@2,0 { - linux,mtd-name= "samsung,kfm2g16q2m-deb8"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ - - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <84>; - gpmc,cs-wr-off-ns = <72>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <18>; - gpmc,oe-on-ns = <30>; - gpmc,oe-off-ns = <84>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <42>; - gpmc,rd-cycle-ns = <108>; - gpmc,wr-cycle-ns = <96>; - gpmc,access-ns = <78>; - gpmc,wr-data-mux-bus-ns = <30>; - - partition@0 { - label = "xloader-onenand"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "bootloader-onenand"; - reg = <0x80000 0x40000>; - }; - partition@c0000 { - label = "params-onenand"; - reg = <0xc0000 0x20000>; - }; - partition@e0000 { - label = "kernel-onenand"; - reg = <0xe0000 0x200000>; - }; - partition@2e0000 { - label = "filesystem-onenand"; - reg = <0x2e0000 0xfd20000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3430es1-clocks.dtsi deleted file mode 100644 index 86de819a0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Device Tree Source for OMAP3430 ES1 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&cm_clocks { - gfx_l3_ck: gfx_l3_ck@b10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&l3_ick>; - reg = <0x0b10>; - ti,bit-shift = <0>; - }; - - gfx_l3_fck: gfx_l3_fck@b40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,max-div = <7>; - reg = <0x0b40>; - ti,index-starts-at-one; - }; - - gfx_l3_ick: gfx_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&gfx_l3_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gfx_cg1_ck: gfx_cg1_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <1>; - }; - - gfx_cg2_ck: gfx_cg2_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <2>; - }; - - d2d_26m_fck: d2d_26m_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <3>; - }; - - fshostusb_fck: fshostusb_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <5>; - }; - - ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; - }; - - ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; - }; - - ssi_ssr_fck: ssi_ssr_fck_3430es1 { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; - }; - - ssi_sst_fck: ssi_sst_fck_3430es1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - fac_ick: fac_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <8>; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - ssi_ick: ssi_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@a10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <5>; - reg = <0x0a10>; - }; - - usb_l4_div_ick: usb_l4_div_ick@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <4>; - ti,max-div = <1>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; - }; - - dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; - }; - - dss_ick: dss_ick_3430es1@e10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0e10>; - ti,bit-shift = <0>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; - }; - - gfx_3430es1_clkdm: gfx_3430es1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck>, <&dss_ick>; - }; - - d2d_clkdm: d2d_clkdm { - compatible = "ti,clockdomain"; - clocks = <&d2d_26m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi deleted file mode 100644 index 858aa0796..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Device Tree Source for OMAP34XX/OMAP36XX clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&cm_clocks { - security_l4_ick2: security_l4_ick2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes1_ick: aes1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; - reg = <0x0a14>; - }; - - rng_ick: rng_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <2>; - }; - - sha11_ick: sha11_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <1>; - }; - - des1_ick: des1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <0>; - }; - - cam_mclk: cam_mclk@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; - reg = <0x0f00>; - ti,set-rate-parent; - }; - - cam_ick: cam_ick@f10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0f10>; - ti,bit-shift = <0>; - }; - - csi2_96m_fck: csi2_96m_fck@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0f00>; - ti,bit-shift = <1>; - }; - - security_l3_ick: security_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - pka_ick: pka_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l3_ick>; - reg = <0x0a14>; - ti,bit-shift = <4>; - }; - - icr_ick: icr_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <29>; - }; - - des2_ick: des2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <26>; - }; - - mspro_ick: mspro_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; - - mailboxes_ick: mailboxes_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <7>; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - sr1_fck: sr1_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <6>; - }; - - sr2_fck: sr2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <7>; - }; - - sr_l4_ick: sr_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll2_fck: dpll2_fck@40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <19>; - ti,max-div = <7>; - reg = <0x0040>; - ti,index-starts-at-one; - }; - - dpll2_ck: dpll2_ck@4 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&dpll2_fck>; - reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; - ti,low-power-stop; - ti,lock; - ti,low-power-bypass; - }; - - dpll2_m2_ck: dpll2_m2_ck@44 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll2_ck>; - ti,max-div = <31>; - reg = <0x0044>; - ti,index-starts-at-one; - }; - - iva2_ck: iva2_ck@0 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&dpll2_m2_ck>; - reg = <0x0000>; - ti,bit-shift = <0>; - }; - - modem_fck: modem_fck@a00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <31>; - }; - - sad2d_ick: sad2d_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <3>; - }; - - mad2d_ick: mad2d_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a18>; - ti,bit-shift = <3>; - }; - - mspro_fck: mspro_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; - }; -}; - -&cm_clockdomains { - cam_clkdm: cam_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cam_ick>, <&csi2_96m_fck>; - }; - - iva2_clkdm: iva2_clkdm { - compatible = "ti,clockdomain"; - clocks = <&iva2_ck>; - }; - - dpll2_clkdm: dpll2_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll2_ck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; - }; - - d2d_clkdm: d2d_clkdm { - compatible = "ti,clockdomain"; - clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, - <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, - <&mspro_fck>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap34xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap34xx.dtsi deleted file mode 100644 index e41c52d3b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap34xx.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Device Tree Source for OMAP34xx/OMAP35xx SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -#include "omap3.dtsi" - -/ { - cpus { - cpu@0 { - /* OMAP343x/OMAP35xx variants OPP1-5 */ - operating-points = < - /* kHz uV */ - 125000 975000 - 250000 1075000 - 500000 1200000 - 550000 1270000 - 600000 1350000 - >; - clock-latency = <300000>; /* From legacy driver */ - }; - }; - - ocp@68000000 { - omap3_pmx_core2: pinmux@480025d8 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025d8 0x24>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - isp: isp@480bc000 { - compatible = "ti,omap3-isp"; - reg = <0x480bc000 0x12fc - 0x480bd800 0x017c>; - interrupts = <24>; - iommus = <&mmu_isp>; - syscon = <&scm_conf 0x6c>; - ti,phy-type = ; - #clock-cells = <1>; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - bandgap@48002524 { - reg = <0x48002524 0x4>; - compatible = "ti,omap34xx-bandgap"; - #thermal-sensor-cells = <0>; - }; - }; -}; - -&ssi { - status = "ok"; - - clocks = <&ssi_ssr_fck>, - <&ssi_sst_fck>, - <&ssi_ick>; - clock-names = "ssi_ssr_fck", - "ssi_sst_fck", - "ssi_ick"; -}; - -/include/ "omap34xx-omap36xx-clocks.dtsi" -/include/ "omap36xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi deleted file mode 100644 index 15d186690..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&prm_clocks { - corex2_d3_fck: corex2_d3_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&corex2_fck>; - clock-mult = <1>; - clock-div = <3>; - }; - - corex2_d5_fck: corex2_d5_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&corex2_fck>; - clock-mult = <1>; - clock-div = <5>; - }; -}; -&cm_clocks { - dpll5_ck: dpll5_ck@d04 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; - ti,low-power-stop; - ti,lock; - }; - - dpll5_m2_ck: dpll5_m2_ck@d50 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll5_ck>; - ti,max-div = <31>; - reg = <0x0d50>; - ti,index-starts-at-one; - }; - - sgx_gate_fck: sgx_gate_fck@b00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <1>; - reg = <0x0b00>; - }; - - core_d3_ck: core_d3_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - core_d4_ck: core_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - core_d6_ck: core_d6_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <6>; - }; - - omap_192m_alwon_fck: omap_192m_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_d2_ck: core_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - sgx_mux_fck: sgx_mux_fck@b40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; - reg = <0x0b40>; - }; - - sgx_fck: sgx_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; - }; - - sgx_ick: sgx_ick@b10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&l3_ick>; - reg = <0x0b10>; - ti,bit-shift = <0>; - }; - - cpefuse_fck: cpefuse_fck@a08 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a08>; - ti,bit-shift = <0>; - }; - - ts_fck: ts_fck@a08 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_32k_fck>; - reg = <0x0a08>; - ti,bit-shift = <1>; - }; - - usbtll_fck: usbtll_fck@a08 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&dpll5_m2_ck>; - reg = <0x0a08>; - ti,bit-shift = <2>; - }; - - usbtll_ick: usbtll_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a18>; - ti,bit-shift = <2>; - }; - - mmchs3_ick: mmchs3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <30>; - }; - - mmchs3_fck: mmchs3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <30>; - }; - - dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; - }; - - dss_ick: dss_ick_3430es2@e10 { - #clock-cells = <0>; - compatible = "ti,omap3-dss-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0e10>; - ti,bit-shift = <0>; - }; - - usbhost_120m_fck: usbhost_120m_fck@1400 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll5_m2_ck>; - reg = <0x1400>; - ti,bit-shift = <1>; - }; - - usbhost_48m_fck: usbhost_48m_fck@1400 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&omap_48m_fck>; - reg = <0x1400>; - ti,bit-shift = <0>; - }; - - usbhost_ick: usbhost_ick@1410 { - #clock-cells = <0>; - compatible = "ti,omap3-dss-interface-clock"; - clocks = <&l4_ick>; - reg = <0x1410>; - ti,bit-shift = <0>; - }; -}; - -&cm_clockdomains { - dpll5_clkdm: dpll5_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll5_ck>; - }; - - sgx_clkdm: sgx_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sgx_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck>, <&dss_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; - }; - - usbhost_clkdm: usbhost_clkdm { - compatible = "ti,clockdomain"; - clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, - <&usbhost_ick>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap36xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap36xx-clocks.dtsi deleted file mode 100644 index a21d1f021..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Device Tree Source for OMAP36xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&cm_clocks { - dpll4_ck: dpll4_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-per-j-type-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; - }; - - dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m5x2_mul_ck>; - ti,bit-shift = <0x1e>; - reg = <0x0d00>; - ti,set-rate-parent; - ti,set-bit-to-disable; - }; - - dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m2x2_mul_ck>; - ti,bit-shift = <0x1b>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll3_m3x2_mul_ck>; - ti,bit-shift = <0xc>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m3x2_mul_ck>; - ti,bit-shift = <0x1c>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m6x2_mul_ck>; - ti,bit-shift = <0x1f>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - uart4_fck: uart4_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; - reg = <0x1000>; - ti,bit-shift = <18>; - }; -}; - -&dpll4_m2x2_mul_ck { - clock-mult = <1>; -}; - -&dpll4_m3x2_mul_ck { - clock-mult = <1>; -}; - -&dpll4_m4x2_mul_ck { - ti,clock-mult = <1>; -}; - -&dpll4_m5x2_mul_ck { - ti,clock-mult = <1>; -}; - -&dpll4_m6x2_mul_ck { - clock-mult = <1>; -}; - -&cm_clockdomains { - dpll4_clkdm: dpll4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll4_ck>; - }; - - per_clkdm: per_clkdm { - compatible = "ti,clockdomain"; - clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, - <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, - <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, - <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, - <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, - <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, - <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>, <&uart4_fck>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi deleted file mode 100644 index 1a4fbdf0d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Device Tree Source for OMAP34xx/OMAP36xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&cm_clocks { - ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; - }; - - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; - }; - - ssi_ssr_fck: ssi_ssr_fck_3430es2 { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; - }; - - ssi_sst_fck: ssi_sst_fck_3430es2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-hsotgusb-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - ssi_ick: ssi_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - - usim_gate_fck: usim_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; - reg = <0x0c00>; - }; - - sys_d2_ck: sys_d2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_96m_d2_fck: omap_96m_d2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_96m_d4_fck: omap_96m_d4_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <4>; - }; - - omap_96m_d8_fck: omap_96m_d8_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <8>; - }; - - omap_96m_d10_fck: omap_96m_d10_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <10>; - }; - - dpll5_m2_d4_ck: dpll5_m2_d4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll5_m2_d8_ck: dpll5_m2_d8_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - dpll5_m2_d16_ck: dpll5_m2_d16_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dpll5_m2_d20_ck: dpll5_m2_d20_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll5_m2_ck>; - clock-mult = <1>; - clock-div = <20>; - }; - - usim_mux_fck: usim_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; - }; - - usim_fck: usim_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usim_gate_fck>, <&usim_mux_fck>; - }; - - usim_ick: usim_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <9>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>, <&usim_ick>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, - <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&ssi_ick>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap36xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap36xx.dtsi deleted file mode 100644 index 718fa8840..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap36xx.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Device Tree Source for OMAP3 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -#include "omap3.dtsi" - -/ { - aliases { - serial3 = &uart4; - }; - - cpus { - /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ - cpu@0 { - operating-points = < - /* kHz uV */ - 300000 1012500 - 600000 1200000 - 800000 1325000 - >; - clock-latency = <300000>; /* From legacy driver */ - }; - }; - - ocp@68000000 { - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - - abb_mpu_iva: regulator-abb-mpu { - compatible = "ti,abb-v1"; - regulator-name = "abb_mpu_iva"; - #address-cells = <0>; - #size-cells = <0>; - reg = <0x483072f0 0x8>, <0x48306818 0x4>; - reg-names = "base-address", "int-address"; - ti,tranxdone-status-mask = <0x4000000>; - clocks = <&sys_ck>; - ti,settling-time = <30>; - ti,clock-cycles = <8>; - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1012500 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1325000 0 0 0 0 0 - 1375000 1 0 0 0 0 - >; - }; - - omap3_pmx_core2: pinmux@480025a0 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025a0 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - isp: isp@480bc000 { - compatible = "ti,omap3-isp"; - reg = <0x480bc000 0x12fc - 0x480bd800 0x0600>; - interrupts = <24>; - iommus = <&mmu_isp>; - syscon = <&scm_conf 0x2f0>; - ti,phy-type = ; - #clock-cells = <1>; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - bandgap@48002524 { - reg = <0x48002524 0x4>; - compatible = "ti,omap36xx-bandgap"; - #thermal-sensor-cells = <0>; - }; - }; -}; - -/* OMAP3630 needs dss_96m_fck for VENC */ -&venc { - clocks = <&dss_tv_fck>, <&dss_96m_fck>; - clock-names = "fck", "tv_dac_clk"; -}; - -&ssi { - status = "ok"; - - clocks = <&ssi_ssr_fck>, - <&ssi_sst_fck>, - <&ssi_ick>; - clock-names = "ssi_ssr_fck", - "ssi_sst_fck", - "ssi_ick"; -}; - -/include/ "omap34xx-omap36xx-clocks.dtsi" -/include/ "omap36xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" -/include/ "omap36xx-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap3xxx-clocks.dtsi deleted file mode 100644 index 9bd91641a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ /dev/null @@ -1,1665 +0,0 @@ -/* - * Device Tree Source for OMAP3 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&prm_clocks { - virt_16_8m_ck: virt_16_8m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - osc_sys_ck: osc_sys_ck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; - reg = <0x0d40>; - }; - - sys_ck: sys_ck@1270 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&osc_sys_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1270>; - ti,index-starts-at-one; - }; - - sys_clkout1: sys_clkout1@d70 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&osc_sys_ck>; - reg = <0x0d70>; - ti,bit-shift = <7>; - }; - - dpll3_x2_ck: dpll3_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll3_m2x2_ck: dpll3_m2x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_x2_ck: dpll4_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - corex2_fck: corex2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - wkup_l4_ick: wkup_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_ck>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&scm_clocks { - mcbsp5_mux_fck: mcbsp5_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x68>; - }; - - mcbsp5_fck: mcbsp5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; - }; - - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x04>; - }; - - mcbsp1_fck: mcbsp1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; - }; - - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x04>; - }; - - mcbsp2_fck: mcbsp2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; - }; - - mcbsp3_mux_fck: mcbsp3_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x68>; - }; - - mcbsp3_fck: mcbsp3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; - }; - - mcbsp4_mux_fck: mcbsp4_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x68>; - }; - - mcbsp4_fck: mcbsp4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; - }; -}; -&cm_clocks { - dummy_apb_pclk: dummy_apb_pclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - omap_32k_fck: omap_32k_fck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12m_ck: virt_12m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13m_ck: virt_13m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_38_4m_ck: virt_38_4m_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - dpll4_ck: dpll4_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-per-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; - }; - - dpll4_m2_ck: dpll4_m2_ck@d48 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <63>; - reg = <0x0d48>; - ti,index-starts-at-one; - }; - - dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m2x2_mul_ck>; - ti,bit-shift = <0x1b>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - omap_96m_alwon_fck: omap_96m_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m2x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll3_ck: dpll3_ck@d00 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-core-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; - }; - - dpll3_m3_ck: dpll3_m3_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <16>; - ti,max-div = <31>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll3_m3x2_mul_ck>; - ti,bit-shift = <0xc>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - emu_core_alwon_ck: emu_core_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m3x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sys_altclk: sys_altclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - mcbsp_clks: mcbsp_clks { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0x0>; - }; - - dpll3_m2_ck: dpll3_m2_ck@d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <27>; - ti,max-div = <31>; - reg = <0x0d40>; - ti,index-starts-at-one; - }; - - core_ck: core_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll3_m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll1_fck: dpll1_fck@940 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,bit-shift = <19>; - ti,max-div = <7>; - reg = <0x0940>; - ti,index-starts-at-one; - }; - - dpll1_ck: dpll1_ck@904 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&dpll1_fck>; - reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; - }; - - dpll1_x2_ck: dpll1_x2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll1_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll1_x2m2_ck: dpll1_x2m2_ck@944 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll1_x2_ck>; - ti,max-div = <31>; - reg = <0x0944>; - ti,index-starts-at-one; - }; - - cm_96m_fck: cm_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_alwon_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - omap_96m_fck: omap_96m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0d40>; - }; - - dpll4_m3_ck: dpll4_m3_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - reg = <0x0e40>; - ti,index-starts-at-one; - }; - - dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m3_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m3x2_mul_ck>; - ti,bit-shift = <0x1c>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - omap_54m_fck: omap_54m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; - reg = <0x0d40>; - }; - - cm_96m_d2_fck: cm_96m_d2_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cm_96m_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - omap_48m_fck: omap_48m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; - reg = <0x0d40>; - }; - - omap_12m_fck: omap_12m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll4_m4_ck: dpll4_m4_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <32>; - reg = <0x0e40>; - ti,index-starts-at-one; - }; - - dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll4_m4_ck>; - ti,clock-mult = <2>; - ti,clock-div = <1>; - ti,set-rate-parent; - }; - - dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_mul_ck>; - ti,bit-shift = <0x1d>; - reg = <0x0d00>; - ti,set-bit-to-disable; - ti,set-rate-parent; - }; - - dpll4_m5_ck: dpll4_m5_ck@f40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <63>; - reg = <0x0f40>; - ti,index-starts-at-one; - }; - - dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll4_m5_ck>; - ti,clock-mult = <2>; - ti,clock-div = <1>; - ti,set-rate-parent; - }; - - dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_mul_ck>; - ti,bit-shift = <0x1e>; - reg = <0x0d00>; - ti,set-bit-to-disable; - ti,set-rate-parent; - }; - - dpll4_m6_ck: dpll4_m6_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <24>; - ti,max-div = <63>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m6_ck>; - clock-mult = <2>; - clock-div = <1>; - }; - - dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m6x2_mul_ck>; - ti,bit-shift = <0x1f>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - emu_per_alwon_ck: emu_per_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll4_m6x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0d70>; - }; - - clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; - reg = <0x0d70>; - }; - - clkout2_src_ck: clkout2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; - }; - - sys_clkout2: sys_clkout2@d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0d70>; - ti,index-power-of-two; - }; - - mpu_ck: mpu_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll1_x2m2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - arm_fck: arm_fck@924 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mpu_ck>; - reg = <0x0924>; - ti,max-div = <2>; - }; - - emu_mpu_alwon_ck: emu_mpu_alwon_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mpu_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3_ick: l3_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - l4_ick: l4_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,bit-shift = <2>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - rm_ick: rm_ick@c40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <1>; - ti,max-div = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; - }; - - gpt10_gate_fck: gpt10_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <11>; - reg = <0x0a00>; - }; - - gpt10_mux_fck: gpt10_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0a40>; - }; - - gpt10_fck: gpt10_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; - }; - - gpt11_gate_fck: gpt11_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <12>; - reg = <0x0a00>; - }; - - gpt11_mux_fck: gpt11_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x0a40>; - }; - - gpt11_fck: gpt11_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; - }; - - core_96m_fck: core_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mmchs2_fck: mmchs2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <25>; - }; - - mmchs1_fck: mmchs1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <24>; - }; - - i2c3_fck: i2c3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <17>; - }; - - i2c2_fck: i2c2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <16>; - }; - - i2c1_fck: i2c1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <15>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; - reg = <0x0a00>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; - reg = <0x0a00>; - }; - - core_48m_fck: core_48m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcspi4_fck: mcspi4_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <21>; - }; - - mcspi3_fck: mcspi3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <20>; - }; - - mcspi2_fck: mcspi2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <19>; - }; - - mcspi1_fck: mcspi1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <18>; - }; - - uart2_fck: uart2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <14>; - }; - - uart1_fck: uart1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <13>; - }; - - core_12m_fck: core_12m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_12m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - hdq_fck: hdq_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_12m_fck>; - reg = <0x0a00>; - ti,bit-shift = <22>; - }; - - core_l3_ick: core_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - sdrc_ick: sdrc_ick@a10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <1>; - }; - - gpmc_fck: gpmc_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&core_l3_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - core_l4_ick: core_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - mmchs2_ick: mmchs2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <25>; - }; - - mmchs1_ick: mmchs1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <24>; - }; - - hdq_ick: hdq_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <22>; - }; - - mcspi4_ick: mcspi4_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <21>; - }; - - mcspi3_ick: mcspi3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <20>; - }; - - mcspi2_ick: mcspi2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <19>; - }; - - mcspi1_ick: mcspi1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <18>; - }; - - i2c3_ick: i2c3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <17>; - }; - - i2c2_ick: i2c2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <16>; - }; - - i2c1_ick: i2c1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <15>; - }; - - uart2_ick: uart2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <14>; - }; - - uart1_ick: uart1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <13>; - }; - - gpt11_ick: gpt11_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <12>; - }; - - gpt10_ick: gpt10_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <11>; - }; - - mcbsp5_ick: mcbsp5_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <10>; - }; - - mcbsp1_ick: mcbsp1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <9>; - }; - - omapctrl_ick: omapctrl_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <6>; - }; - - dss_tv_fck: dss_tv_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_54m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; - - dss_96m_fck: dss_96m_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_96m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; - - dss2_alwon_fck: dss2_alwon_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0e00>; - ti,bit-shift = <1>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - gpt1_gate_fck: gpt1_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0c00>; - }; - - gpt1_mux_fck: gpt1_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - reg = <0x0c40>; - }; - - gpt1_fck: gpt1_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; - }; - - aes2_ick: aes2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - ti,bit-shift = <28>; - reg = <0x0a10>; - }; - - wkup_32k_fck: wkup_32k_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gpio1_dbck: gpio1_dbck@c00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <3>; - }; - - sha12_ick: sha12_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <27>; - }; - - wdt2_fck: wdt2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <5>; - }; - - wdt2_ick: wdt2_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <5>; - }; - - wdt1_ick: wdt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <4>; - }; - - gpio1_ick: gpio1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <3>; - }; - - omap_32ksync_ick: omap_32ksync_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <2>; - }; - - gpt12_ick: gpt12_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <1>; - }; - - gpt1_ick: gpt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <0>; - }; - - per_96m_fck: per_96m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_96m_alwon_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - per_48m_fck: per_48m_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_48m_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - uart3_fck: uart3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; - reg = <0x1000>; - ti,bit-shift = <11>; - }; - - gpt2_gate_fck: gpt2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1000>; - }; - - gpt2_mux_fck: gpt2_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - reg = <0x1040>; - }; - - gpt2_fck: gpt2_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; - }; - - gpt3_gate_fck: gpt3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1000>; - }; - - gpt3_mux_fck: gpt3_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x1040>; - }; - - gpt3_fck: gpt3_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; - }; - - gpt4_gate_fck: gpt4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1000>; - }; - - gpt4_mux_fck: gpt4_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x1040>; - }; - - gpt4_fck: gpt4_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; - }; - - gpt5_gate_fck: gpt5_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1000>; - }; - - gpt5_mux_fck: gpt5_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1040>; - }; - - gpt5_fck: gpt5_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; - }; - - gpt6_gate_fck: gpt6_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1000>; - }; - - gpt6_mux_fck: gpt6_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1040>; - }; - - gpt6_fck: gpt6_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; - }; - - gpt7_gate_fck: gpt7_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <8>; - reg = <0x1000>; - }; - - gpt7_mux_fck: gpt7_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1040>; - }; - - gpt7_fck: gpt7_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; - }; - - gpt8_gate_fck: gpt8_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <9>; - reg = <0x1000>; - }; - - gpt8_mux_fck: gpt8_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1040>; - }; - - gpt8_fck: gpt8_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; - }; - - gpt9_gate_fck: gpt9_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <10>; - reg = <0x1000>; - }; - - gpt9_mux_fck: gpt9_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1040>; - }; - - gpt9_fck: gpt9_fck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; - }; - - per_32k_alwon_fck: per_32k_alwon_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&omap_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gpio6_dbck: gpio6_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <17>; - }; - - gpio5_dbck: gpio5_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <16>; - }; - - gpio4_dbck: gpio4_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <15>; - }; - - gpio3_dbck: gpio3_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <14>; - }; - - gpio2_dbck: gpio2_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <13>; - }; - - wdt3_fck: wdt3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <12>; - }; - - per_l4_ick: per_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - gpio6_ick: gpio6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <17>; - }; - - gpio5_ick: gpio5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <16>; - }; - - gpio4_ick: gpio4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <15>; - }; - - gpio3_ick: gpio3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <14>; - }; - - gpio2_ick: gpio2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <13>; - }; - - wdt3_ick: wdt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <12>; - }; - - uart3_ick: uart3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <11>; - }; - - uart4_ick: uart4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <18>; - }; - - gpt9_ick: gpt9_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <10>; - }; - - gpt8_ick: gpt8_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <9>; - }; - - gpt7_ick: gpt7_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <8>; - }; - - gpt6_ick: gpt6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <7>; - }; - - gpt5_ick: gpt5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <6>; - }; - - gpt4_ick: gpt4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <5>; - }; - - gpt3_ick: gpt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <4>; - }; - - gpt2_ick: gpt2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <3>; - }; - - mcbsp2_ick: mcbsp2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <0>; - }; - - mcbsp3_ick: mcbsp3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <1>; - }; - - mcbsp4_ick: mcbsp4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <2>; - }; - - mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; - reg = <0x1000>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; - reg = <0x1000>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x1000>; - }; - - emu_src_mux_ck: emu_src_mux_ck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - reg = <0x1140>; - }; - - emu_src_ck: emu_src_ck { - #clock-cells = <0>; - compatible = "ti,clkdm-gate-clock"; - clocks = <&emu_src_mux_ck>; - }; - - pclk_fck: pclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <8>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - pclkx2_fck: pclkx2_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - atclk_fck: atclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <4>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - traceclk_src_fck: traceclk_src_fck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; - reg = <0x1140>; - }; - - traceclk_fck: traceclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - secure_32k_fck: secure_32k_fck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - gpt12_fck: gpt12_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&secure_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; - - wdt1_fck: wdt1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&secure_32k_fck>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>; - }; - - dpll3_clkdm: dpll3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll3_ck>; - }; - - dpll1_clkdm: dpll1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll1_ck>; - }; - - per_clkdm: per_clkdm { - compatible = "ti,clockdomain"; - clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, - <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, - <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, - <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, - <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, - <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, - <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, - <&mcbsp4_ick>; - }; - - emu_clkdm: emu_clkdm { - compatible = "ti,clockdomain"; - clocks = <&emu_src_ck>; - }; - - dpll4_clkdm: dpll4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll4_ck>; - }; - - wkup_clkdm: wkup_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, - <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, - <&gpt1_ick>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap4-cpu-thermal.dtsi deleted file mode 100644 index ab7f87ae9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-cpu-thermal.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Device Tree Source for OMAP4/5 SoC CPU thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Contact: Eduardo Valentin - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -cpu_thermal: cpu_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 0>; - - cpu_trips: trips { - cpu_alert0: cpu_alert { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <125000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-duovero-parlor.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-duovero-parlor.dts deleted file mode 100644 index 1b825128a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap4-duovero.dtsi" - -#include - -/ { - model = "OMAP4430 Gumstix Duovero on Parlor"; - compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - - aliases { - display0 = &hdmi0; - }; - - leds { - compatible = "gpio-leds"; - led0 { - label = "duovero:blue:led0"; - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio_122 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button0 { - label = "button0"; - linux,code = ; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ - wakeup-source; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "d"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-0 = < - &led_pins - &button_pins - &smsc_pins - >; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ - >; - }; - - button_pins: pinmux_button_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - smsc_pins: pinmux_smsc_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ - OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ - OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ - >; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <100000>; - - /* optional 1K EEPROM with revision information */ - eeprom@51 { - compatible = "atmel,24c01"; - reg = <0x51>; - pagesize = <8>; - }; -}; - -&mmc3 { - status = "disabled"; -}; - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ - - ethernet@gpmc { - reg = <5 0 0xff>; - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ - - phy-mode = "mii"; - - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <50>; - gpmc,cs-wr-off-ns = <50>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <50>; - gpmc,we-on-ns = <15>; - gpmc,we-off-ns = <50>; - gpmc,rd-cycle-ns = <50>; - gpmc,wr-cycle-ns = <50>; - gpmc,access-ns = <50>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <35>; - gpmc,cycle2cycle-delay-ns = <35>; - gpmc,wr-data-mux-bus-ns = <35>; - gpmc,wr-access-ns = <50>; - - gpmc,mux-add-data = <2>; - gpmc,sync-read; - gpmc,sync-write; - gpmc,clk-activation-ns = <5>; - gpmc,sync-clk-ps = <20000>; - }; -}; - -&dss { - status = "ok"; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&vdac>; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-duovero.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap4-duovero.dtsi deleted file mode 100644 index ec0bd9779..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-duovero.dtsi +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap443x.dtsi" - -/ { - model = "Gumstix Duovero"; - compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - sound { - compatible = "ti,abe-twl6040"; - ti,model = "DuoVero"; - - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias"; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ - - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1phy_pins>; - - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - /* regulator for w2cbw0015 on sdio5 */ - w2cbw0015_vmmc: w2cbw0015_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&w2cbw0015_pins>; - compatible = "regulator-fixed"; - regulator-name = "w2cbw0015"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; /* gpio_43 */ - startup-delay-us = <70000>; - enable-active-high; - regulator-boot-on; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &twl6040_pins - &hsusbb1_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - hsusb1phy_pins: pinmux_hsusb1phy_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ - >; - }; - - w2cbw0015_pins: pinmux_w2cbw0015_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ - OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ - OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ - OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ - OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ - OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc5_pins: pinmux_mmc5_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ - >; - }; -}; - -/* PMIC */ -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -/* on-board bluetooth / WiFi module */ -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - vmmc-supply = <&vmmc>; - ti,bus-width = <4>; - ti,non-removable; /* FIXME: use PMIC_MMC detect */ -}; - -&mmc2 { - status = "disabled"; -}; - -/* mmc3 is available to the expansion board */ - -&mmc4 { - status = "disabled"; -}; - -/* on-board WiFi module */ -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc5_pins>; - - vmmc-supply = <&w2cbw0015_vmmc>; - ti,bus-width = <4>; - ti,non-removable; - cap-power-off-card; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-kc1.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-kc1.dts deleted file mode 100644 index e3763ac75..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-kc1.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (C) 2016 Paul Kocialkowski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap443x.dtsi" - -/ { - model = "Amazon Kindle Fire (first generation)"; - compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - pwmleds { - compatible = "pwm-leds"; - - green { - label = "green"; - pwms = <&twl_pwm 0 7812500>; - max-brightness = <127>; - }; - - orange { - label = "orange"; - pwms = <&twl_pwm 1 7812500>; - max-brightness = <127>; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */ - OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */ - OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat2 */ - OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat3 */ - OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4 */ - OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5 */ - OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6 */ - OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7 */ - OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_clk */ - OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_cmd */ - >; - }; - - usb_otg_hs_pins: pinmux_usb_otg_hs_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ - OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ - OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ - >; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* IRQ# = 7 */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - - twl_power: power { - compatible = "ti,twl6030-power"; - ti,system-power-controller; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - vmmc-supply = <&vaux1>; - ti,non-removable; - bus-width = <8>; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_hs_pins>; - - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-panda-a4.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-panda-a4.dts deleted file mode 100644 index 78d363177..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-panda-a4.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "omap4-panda-common.dtsi" - -/* Pandaboard Rev A4+ have external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-panda-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap4-panda-common.dtsi deleted file mode 100644 index 1673689e6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-panda-common.dtsi +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include "elpida_ecb240abacn.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - aliases { - display0 = &dvi0; - display1 = &hdmi0; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = < - &led_wkgpio_pins - >; - - heartbeat { - label = "pandaboard::status1"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "pandaboard::status2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "PandaBoard"; - - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; - - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */ - startup-delay-us = <70000>; - enable-active-high; - /* - * boot-on is required along with always-on as the - * regulator framework doesn't enable the regulator - * if boot-on is not there. - */ - regulator-always-on; - regulator-boot-on; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ - vcc-supply = <&hsusb1_power>; - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - /* regulator for wl12xx on sdio5 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tpd12s015: encoder1 { - compatible = "ti,tpd12s015"; - - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ - <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ - <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector1 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins - &tfp410_pins - &dss_hdmi_pins - &tpd12s015_pins - &hsusbb1_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ - OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ - OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ - OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ - OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ - OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ - OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ - OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ - OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ - OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ - - OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ - OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ - OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ - OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ - OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ - OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ - OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ - OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ - OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ - OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ - OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ - OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ - OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ - - OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ - OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ - OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ - >; - }; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - /* - * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP - * REVISIT: Are the pull-ups needed for GPIO 48 and 49? - */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */ - OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ - OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */ - >; - }; - - /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: pinmux_wl12xx_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; -}; - -&omap4_pmx_wkup { - led_wkgpio_pins: pinmux_leds_wkpins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ - OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* IRQ# = 7 */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* IRQ# = 119 */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in their EEPROM as EDID data. - * The EEPROM is connected as I2C slave device. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_pins>; - vmmc-supply = <&wl12xx_vmmc>; - interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core 0x10e>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ - ref-clock-frequency = <38400000>; - }; -}; - -&emif1 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&emif2 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&uart2 { - interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; -}; - -&uart4 { - interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART4_RX>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&dss { - status = "ok"; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "ok"; - vdd-supply = <&vcxio>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-panda-es.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-panda-es.dts deleted file mode 100644 index 119f8e657..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-panda-es.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap4460.dtsi" -#include "omap4-panda-common.dtsi" - -/ { - model = "TI OMAP4 PandaBoard-ES"; - compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4"; -}; - -/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ -&sound { - ti,model = "PandaBoardES"; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "AFML", "Line In", - "AFMR", "Line In"; -}; - -/* PandaboardES has external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; - -&omap4_pmx_core { - led_gpio_pins: gpio_led_pmx { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ - >; - }; -}; - -&led_wkgpio_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ - >; -}; - -&leds { - pinctrl-0 = < - &led_gpio_pins - &led_wkgpio_pins - >; - - heartbeat { - gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - }; - mmc { - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio1 { - ti,no-reset-on-init; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-panda.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-panda.dts deleted file mode 100644 index a0e28b2e2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-panda.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "omap4-panda-common.dtsi" - -/ { - model = "TI OMAP4 PandaBoard"; - compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-sdp-es23plus.dts deleted file mode 100644 index b4d19a7ae..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-sdp-es23plus.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include "omap4-sdp.dts" - -/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ -&dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-sdp.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-sdp.dts deleted file mode 100644 index d728ec963..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-sdp.dts +++ /dev/null @@ -1,704 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap443x.dtsi" -#include "elpida_ecb240abacn.dtsi" - -/ { - model = "TI OMAP4 SDP board"; - compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - aliases { - display0 = &lcd0; - display1 = &lcd1; - display2 = &hdmi0; - }; - - vdd_eth: fixedregulator-vdd-eth { - compatible = "regulator-fixed"; - regulator-name = "VDD_ETH"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */ - enable-active-high; - regulator-boot-on; - }; - - vbat: fixedregulator-vbat { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - regulator-min-microvolt = <3750000>; - regulator-max-microvolt = <3750000>; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - debug0 { - label = "omap4:green:debug0"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ - }; - - debug1 { - label = "omap4:green:debug1"; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ - }; - - debug2 { - label = "omap4:green:debug2"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ - }; - - debug3 { - label = "omap4:green:debug3"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ - }; - - debug4 { - label = "omap4:green:debug4"; - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ - }; - - user1 { - label = "omap4:blue:user"; - gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ - }; - - user2 { - label = "omap4:red:user"; - gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ - }; - - user3 { - label = "omap4:green:user"; - gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ - }; - }; - - pwmleds { - compatible = "pwm-leds"; - kpad { - label = "omap4::keypad"; - pwms = <&twl_pwm 0 7812500>; - max-brightness = <127>; - }; - - charging { - label = "omap4:green:chrg"; - pwms = <&twl_pwmled 0 7812500>; - max-brightness = <255>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&twl_pwm 1 7812500>; - brightness-levels = < - 0 10 20 30 40 - 50 60 70 80 90 - 100 110 120 127 - >; - default-brightness-level = <13>; - }; - - sound { - compatible = "ti,abe-twl6040"; - ti,model = "SDP4430"; - - ti,jack-detection = <1>; - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - ti,dmic = <&dmic>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Earphone Spk", "EP", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "Vibrator", "VIBRAL", - "Vibrator", "VIBRAR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "MAINMIC", "Main Handset Mic", - "Main Handset Mic", "Main Mic Bias", - "SUBMIC", "Sub Handset Mic", - "Sub Handset Mic", "Main Mic Bias", - "AFML", "Line In", - "AFMR", "Line In", - "DMic", "Digital Mic", - "Digital Mic", "Digital Mic1 Bias"; - }; - - /* regulator for wl12xx on sdio5 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ - <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ - <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "c"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &dss_hdmi_pins - &tpd12s015_pins - >; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ - OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ - >; - }; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - >; - }; - - dmic_pins: pinmux_dmic_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ - OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ - OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */ - OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ - OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ - OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */ - OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ - OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */ - >; - }; - - /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: pinmux_wl12xx_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - - /* regulators for vibra motor */ - vddvibl-supply = <&vbat>; - vddvibr-supply = <&vbat>; - - vibra { - /* Vibra driver, motor resistance parameters */ - ti,vibldrv-res = <8>; - ti,vibrdrv-res = <3>; - ti,viblmotor-res = <10>; - ti,vibrmotor-res = <10>; - }; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; - - /* - * Temperature Sensor - * http://www.ti.com/lit/ds/symlink/tmp105.pdf - */ - tmp105@48 { - compatible = "ti,tmp105"; - reg = <0x48>; - }; - - /* - * Ambient Light Sensor - * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf - */ - bh1780@29 { - compatible = "rohm,bh1780"; - reg = <0x29>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; - - /* - * 3-Axis Digital Compass - * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf - */ - hmc5843@1e { - compatible = "honeywell,hmc5843"; - reg = <0x1e>; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - eth@0 { - compatible = "ks8851"; - spi-max-frequency = <24000000>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ - vdd-supply = <&vdd_eth>; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - bus-width = <8>; -}; - -&mmc2 { - vmmc-supply = <&vaux1>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_pins>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1281"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&emif1 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&emif2 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = <0x00000012 /* KEY_E */ - 0x00010013 /* KEY_R */ - 0x00020014 /* KEY_T */ - 0x00030066 /* KEY_HOME */ - 0x0004003f /* KEY_F5 */ - 0x000500f0 /* KEY_UNKNOWN */ - 0x00060017 /* KEY_I */ - 0x0007002a /* KEY_LEFTSHIFT */ - 0x01000020 /* KEY_D*/ - 0x01010021 /* KEY_F */ - 0x01020022 /* KEY_G */ - 0x010300e7 /* KEY_SEND */ - 0x01040040 /* KEY_F6 */ - 0x010500f0 /* KEY_UNKNOWN */ - 0x01060025 /* KEY_K */ - 0x0107001c /* KEY_ENTER */ - 0x0200002d /* KEY_X */ - 0x0201002e /* KEY_C */ - 0x0202002f /* KEY_V */ - 0x0203006b /* KEY_END */ - 0x02040041 /* KEY_F7 */ - 0x020500f0 /* KEY_UNKNOWN */ - 0x02060034 /* KEY_DOT */ - 0x0207003a /* KEY_CAPSLOCK */ - 0x0300002c /* KEY_Z */ - 0x0301004e /* KEY_KPLUS */ - 0x03020030 /* KEY_B */ - 0x0303003b /* KEY_F1 */ - 0x03040042 /* KEY_F8 */ - 0x030500f0 /* KEY_UNKNOWN */ - 0x03060018 /* KEY_O */ - 0x03070039 /* KEY_SPACE */ - 0x04000011 /* KEY_W */ - 0x04010015 /* KEY_Y */ - 0x04020016 /* KEY_U */ - 0x0403003c /* KEY_F2 */ - 0x04040073 /* KEY_VOLUMEUP */ - 0x040500f0 /* KEY_UNKNOWN */ - 0x04060026 /* KEY_L */ - 0x04070069 /* KEY_LEFT */ - 0x0500001f /* KEY_S */ - 0x05010023 /* KEY_H */ - 0x05020024 /* KEY_J */ - 0x0503003d /* KEY_F3 */ - 0x05040043 /* KEY_F9 */ - 0x05050072 /* KEY_VOLUMEDOWN */ - 0x05060032 /* KEY_M */ - 0x0507006a /* KEY_RIGHT */ - 0x06000010 /* KEY_Q */ - 0x0601001e /* KEY_A */ - 0x06020031 /* KEY_N */ - 0x0603009e /* KEY_BACK */ - 0x0604000e /* KEY_BACKSPACE */ - 0x060500f0 /* KEY_UNKNOWN */ - 0x06060019 /* KEY_P */ - 0x06070067 /* KEY_UP */ - 0x07000094 /* KEY_PROG1 */ - 0x07010095 /* KEY_PROG2 */ - 0x070200ca /* KEY_PROG3 */ - 0x070300cb /* KEY_PROG4 */ - 0x0704003e /* KEY_F4 */ - 0x070500f0 /* KEY_UNKNOWN */ - 0x07060160 /* KEY_OK */ - 0x0707006c>; /* KEY_DOWN */ - linux,input-no-autorepeat; -}; - -&uart2 { - interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH - &omap4_pmx_core OMAP4_UART4_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&dmic { - pinctrl-names = "default"; - pinctrl-0 = <&dmic_pins>; - status = "okay"; -}; - -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&dss { - status = "ok"; -}; - -&dsi1 { - status = "ok"; - vdd-supply = <&vcxio>; - - port { - dsi1_out_ep: endpoint { - remote-endpoint = <&lcd0_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd0: display { - compatible = "tpo,taal", "panel-dsi-cm"; - label = "lcd0"; - - reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi1_out_ep>; - }; - }; - }; -}; - -&dsi2 { - status = "ok"; - vdd-supply = <&vcxio>; - - port { - dsi2_out_ep: endpoint { - remote-endpoint = <&lcd1_in>; - lanes = <0 1 2 3 4 5>; - }; - }; - - lcd1: display { - compatible = "tpo,taal", "panel-dsi-cm"; - label = "lcd1"; - - reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ - - port { - lcd1_in: endpoint { - remote-endpoint = <&dsi2_out_ep>; - }; - }; - }; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-var-dvk-om44.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-var-dvk-om44.dts deleted file mode 100644 index 458d79fa3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-var-dvk-om44.dts +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2014 Joachim Eastwood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap4-var-som-om44.dtsi" -#include "omap4-var-som-om44-wlan.dtsi" -#include "omap4-var-om44customboard.dtsi" - -/ { - model = "Variscite VAR-DVK-OM44"; - compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - - aliases { - display0 = &lcd0; - display1 = &hdmi0; - }; - - lcd0: display { - compatible = "innolux,at070tn83", "panel-dpi"; - label = "lcd"; - panel-timing { - clock-frequency = <33333333>; - - hback-porch = <40>; - hactive = <800>; - hfront-porch = <40>; - hsync-len = <48>; - - vback-porch = <29>; - vactive = <480>; - vfront-porch = <13>; - vsync-len = <3>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - backlight { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio 122 */ - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "okay"; - vdd-supply = <&vcxio>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap4-var-om44customboard.dtsi deleted file mode 100644 index 74940b6d7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-var-om44customboard.dtsi +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (C) 2014 Joachim Eastwood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - aliases { - display0 = &hdmi0; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_led_pins>; - - led0 { - label = "var:green:led0"; - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio 173 */ - linux,default-trigger = "heartbeat"; - }; - - led1 { - label = "var:green:led1"; - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; /* gpio 172 */ - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - #address-cells = <1>; - #size-cells = <0>; - - user-key@184 { - label = "user"; - gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; /* gpio 184 */ - linux,code = ; - wakeup-source; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins>; - label = "hdmi"; - type = "a"; - - hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; -}; - -&omap4_pmx_core { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ - OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ - OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */ - OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - mcasp_pins: pinmux_mcsasp_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ - OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ - OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ - OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ - OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ - OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ - OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ - OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ - OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ - OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ - OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ - OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ - OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ - OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ - OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ - OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ - OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ - OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ - OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ - OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ - OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ - OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ - OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ - OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ - OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ - OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ - OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ - OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc5_pins: pinmux_mmc5_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ - OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ - >; - }; - - gpio_led_pins: pinmux_gpio_led_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ - OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ - >; - }; - - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ - >; - }; - - ks8851_irq_pins: pinmux_ks8851_irq_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ - >; - }; - - hdmi_hpd_pins: pinmux_hdmi_hpd_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ - >; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - status = "okay"; - - eth@0 { - compatible = "ks8851"; - pinctrl-names = "default"; - pinctrl-0 = <&ks8851_irq_pins>; - spi-max-frequency = <24000000>; - reg = <0>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio 171 */ - }; -}; - -&mmc5 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc5_pins>; - vmmc-supply = <&vbat>; - bus-width = <4>; - cd-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio 110 */ - status = "okay"; -}; - -&dss { - status = "okay"; -}; - -&hdmi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - vdda-supply = <&vdac>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi deleted file mode 100644 index 1c5f6f35e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2014 Joachim Eastwood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - /* regulator for wl12xx on sdio4 */ - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_ctrl_pins>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* gpio 43 */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&omap4_pmx_core { - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ - OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ - >; - }; - - mmc4_pins: pinmux_mmc4_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ - OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ - OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_somi.sdmmc4_dat0 */ - OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_tx.sdmmc4_dat1 */ - OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_rx.sdmmc4_dat2 */ - OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_cs0.sdmmc4_dat3 */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&mmc4 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc4_pins>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ - ref-clock-frequency = <38400000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap4-var-som-om44.dtsi deleted file mode 100644 index 758b6eb7a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (C) 2014 Joachim Eastwood - * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include "omap4460.dtsi" - -/ { - model = "Variscite VAR-SOM-OM44"; - compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "VAR-SOM-OM44"; - - ti,mclk-freq = <38400000>; - ti,mcpdm = <&mcpdm>; - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "AFML", "Line In", - "AFMR", "Line In"; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_phy_clk_pins - &hsusbb1_phy_rst_pins - >; - - reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ - vcc-supply = <&vbat>; - - clocks = <&auxclk3_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - vbat: fixedregulator-vbat { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ - OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ - OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ - >; - }; - - hsusbb1_phy_rst_pins: pinmux_hsusbb1_phy_rst_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; -}; - -&omap4_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_hub_rst_pins - &lan7500_rst_pins - >; - - hsusbb1_phy_clk_pins: pinmux_hsusbb1_phy_clk_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ - >; - }; - - hsusbb1_hub_rst_pins: pinmux_hsusbb1_hub_rst_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ - >; - }; - - lan7500_rst_pins: pinmux_lan7500_rst_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - ti,audpwron-gpio = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio 182 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -#include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" - -&vusim { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; - - clock-frequency = <400000>; - - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* gpio 101 */ - status = "disabled"; - }; - - tmp105@49 { - compatible = "ti,tmp105"; - reg = <0x49>; - }; - - eeprom@50 { - compatible = "microchip,24c32"; - reg = <0x50>; - }; -}; - -&i2c4 { - status = "disabled"; -}; - -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - -&gpmc { - status = "disabled"; -}; - -&mcspi1 { - status = "disabled"; -}; - -&mcspi2 { - status = "disabled"; -}; - -&mcspi3 { - status = "disabled"; -}; - -&mcspi4 { - status = "disabled"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc>; - bus-width = <4>; - ti,non-removable; - status = "okay"; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&keypad { - status = "disabled"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4-var-stk-om44.dts b/software/linux/kernel/arch/arm/boot/dts/omap4-var-stk-om44.dts deleted file mode 100644 index 56b64e618..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4-var-stk-om44.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2014 Joachim Eastwood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap4-var-som-om44.dtsi" -#include "omap4-var-som-om44-wlan.dtsi" -#include "omap4-var-om44customboard.dtsi" - -/ { - model = "Variscite VAR-STK-OM44"; - compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap4.dtsi deleted file mode 100644 index 4d6584f15..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4.dtsi +++ /dev/null @@ -1,1026 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -/ { - compatible = "ti,omap4430", "ti,omap4"; - interrupt-parent = <&wakeupgen>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&L2>; - reg = <0x0>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - }; - - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; - interrupt-parent = <&gic>; - }; - - L2: l2-cache-controller@48242000 { - compatible = "arm,pl310-cache"; - reg = <0x48242000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - local-timer@48240600 { - compatible = "arm,cortex-a9-twd-timer"; - clocks = <&mpu_periphclk>; - reg = <0x48240600 0x20>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - sram = <&ocmcram>; - }; - - dsp { - compatible = "ti,omap3-c64"; - ti,hwmods = "dsp"; - }; - - iva { - compatible = "ti,ivahd"; - ti,hwmods = "iva"; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP4 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,omap4-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0x44000000 0x1000>, - <0x44800000 0x2000>, - <0x45000000 0x1000>; - interrupts = , - ; - - l4_cfg: l4@4a000000 { - compatible = "ti,omap4-l4-cfg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x1000000>; - - cm1: cm1@4000 { - compatible = "ti,omap4-cm1"; - reg = <0x4000 0x2000>; - - cm1_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm1_clockdomains: clockdomains { - }; - }; - - cm2: cm2@8000 { - compatible = "ti,omap4-cm2"; - reg = <0x8000 0x3000>; - - cm2_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm2_clockdomains: clockdomains { - }; - }; - - omap4_scm_core: scm@2000 { - compatible = "ti,omap4-scm-core", "simple-bus"; - reg = <0x2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x1000>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - omap4_padconf_core: scm@100000 { - compatible = "ti,omap4-scm-padconf-core", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x100000 0x1000>; - - omap4_pmx_core: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap4_padconf_global: omap4_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0x170>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0x170>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap4", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap4_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap4 { - regulator-name = "pbias_mmc_omap4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - }; - - l4_wkup: l4@300000 { - compatible = "ti,omap4-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300000 0x40000>; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x20>; - ti,hwmods = "counter_32k"; - }; - - prm: prm@6000 { - compatible = "ti,omap4-prm"; - reg = <0x6000 0x3000>; - interrupts = ; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@a000 { - compatible = "ti,omap4-scrm"; - reg = <0xa000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - omap4_pmx_wkup: pinmux@1e040 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x1e040 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - }; - }; - - ocmcram: ocmcram@40304000 { - compatible = "mmio-sram"; - reg = <0x40304000 0xa000>; /* 40k */ - }; - - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - - gpio1: gpio@4a310000 { - compatible = "ti,omap4-gpio"; - reg = <0x4a310000 0x200>; - interrupts = ; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - reg = <0x48055000 0x200>; - interrupts = ; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - reg = <0x48057000 0x200>; - interrupts = ; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - reg = <0x48059000 0x200>; - interrupts = ; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805b000 0x200>; - interrupts = ; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805d000 0x200>; - interrupts = ; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - elm: elm@48078000 { - compatible = "ti,am3352-elm"; - reg = <0x48078000 0x2000>; - interrupts = ; - ti,hwmods = "elm"; - status = "disabled"; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = ; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - ti,no-idle-on-init; - clocks = <&l3_div_ck>; - clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts = ; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap4-uart"; - reg = <0x4806c000 0x100>; - interrupts = ; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - }; - - uart3: serial@48020000 { - compatible = "ti,omap4-uart"; - reg = <0x48020000 0x100>; - interrupts = ; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - }; - - uart4: serial@4806e000 { - compatible = "ti,omap4-uart"; - reg = <0x4806e000 0x100>; - interrupts = ; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - reg = <0x48070000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - reg = <0x48072000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - reg = <0x48060000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - i2c4: i2c@48350000 { - compatible = "ti,omap4-i2c"; - reg = <0x48350000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - interrupts = ; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480b4000 0x400>; - interrupts = ; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480ad000 0x400>; - interrupts = ; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d1000 0x400>; - interrupts = ; - ti,hwmods = "mmc4"; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - - mmc5: mmc@480d5000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d5000 0x400>; - interrupts = ; - ti,hwmods = "mmc5"; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - - mmu_dsp: mmu@4a066000 { - compatible = "ti,omap4-iommu"; - reg = <0x4a066000 0x100>; - interrupts = ; - ti,hwmods = "mmu_dsp"; - #iommu-cells = <0>; - }; - - mmu_ipu: mmu@55082000 { - compatible = "ti,omap4-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - - wdt2: wdt@4a314000 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x4a314000 0x80>; - interrupts = ; - ti,hwmods = "wd_timer2"; - }; - - mcpdm: mcpdm@40132000 { - compatible = "ti,omap4-mcpdm"; - reg = <0x40132000 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "mcpdm"; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - status = "disabled"; - }; - - dmic: dmic@4012e000 { - compatible = "ti,omap4-dmic"; - reg = <0x4012e000 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "dmic"; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - - mcbsp1: mcbsp@40122000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40122000 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@40124000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40124000 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp3: mcbsp@40126000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40126000 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp4: mcbsp@48096000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x48096000 0xff>; /* L4 Interconnect */ - reg-names = "mpu"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - keypad: keypad@4a31c000 { - compatible = "ti,omap4-keypad"; - reg = <0x4a31c000 0x80>; - interrupts = ; - reg-names = "mpu"; - ti,hwmods = "kbd"; - }; - - dmm@4e000000 { - compatible = "ti,omap4-dmm"; - reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; - ti,hwmods = "dmm"; - }; - - emif1: emif@4c000000 { - compatible = "ti,emif-4d"; - reg = <0x4c000000 0x100>; - interrupts = ; - ti,hwmods = "emif1"; - ti,no-idle-on-init; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - emif2: emif@4d000000 { - compatible = "ti,emif-4d"; - reg = <0x4d000000 0x100>; - interrupts = ; - ti,hwmods = "emif2"; - ti,no-idle-on-init; - phy-type = <1>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - ocp2scp@4a0ad000 { - compatible = "ti,omap-ocp2scp"; - reg = <0x4a0ad000 0x1f>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp_usb_phy"; - usb2_phy: usb2phy@4a0ad080 { - compatible = "ti,omap-usb2"; - reg = <0x4a0ad080 0x58>; - ctrl-module = <&omap_control_usb2phy>; - clocks = <&usb_phy_cm_clk32k>; - clock-names = "wkupclk"; - #phy-cells = <0>; - }; - }; - - mailbox: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = ; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - - timer1: timer@4a318000 { - compatible = "ti,omap3430-timer"; - reg = <0x4a318000 0x80>; - interrupts = ; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@48032000 { - compatible = "ti,omap3430-timer"; - reg = <0x48032000 0x80>; - interrupts = ; - ti,hwmods = "timer2"; - }; - - timer3: timer@48034000 { - compatible = "ti,omap4430-timer"; - reg = <0x48034000 0x80>; - interrupts = ; - ti,hwmods = "timer3"; - }; - - timer4: timer@48036000 { - compatible = "ti,omap4430-timer"; - reg = <0x48036000 0x80>; - interrupts = ; - ti,hwmods = "timer4"; - }; - - timer5: timer@40138000 { - compatible = "ti,omap4430-timer"; - reg = <0x40138000 0x80>, - <0x49038000 0x80>; - interrupts = ; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@4013a000 { - compatible = "ti,omap4430-timer"; - reg = <0x4013a000 0x80>, - <0x4903a000 0x80>; - interrupts = ; - ti,hwmods = "timer6"; - ti,timer-dsp; - }; - - timer7: timer@4013c000 { - compatible = "ti,omap4430-timer"; - reg = <0x4013c000 0x80>, - <0x4903c000 0x80>; - interrupts = ; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@4013e000 { - compatible = "ti,omap4430-timer"; - reg = <0x4013e000 0x80>, - <0x4903e000 0x80>; - interrupts = ; - ti,hwmods = "timer8"; - ti,timer-pwm; - ti,timer-dsp; - }; - - timer9: timer@4803e000 { - compatible = "ti,omap4430-timer"; - reg = <0x4803e000 0x80>; - interrupts = ; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap3430-timer"; - reg = <0x48086000 0x80>; - interrupts = ; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap4430-timer"; - reg = <0x48088000 0x80>; - interrupts = ; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = ; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3"; - reg = <0x4a064800 0x400>; - interrupts = ; - }; - - usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap"; - reg = <0x4a064c00 0x400>; - interrupts = ; - }; - }; - - omap_control_usb2phy: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usbotg: control-phy@4a00233c { - compatible = "ti,control-phy-otghs"; - reg = <0x4a00233c 0x4>; - reg-names = "otghs_control"; - }; - - usb_otg_hs: usb_otg_hs@4a0ab000 { - compatible = "ti,omap4-musb"; - reg = <0x4a0ab000 0x7ff>; - interrupts = , ; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - ctrl-module = <&omap_control_usbotg>; - }; - - aes: aes@4b501000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x4b501000 0xa0>; - interrupts = ; - dmas = <&sdma 111>, <&sdma 110>; - dma-names = "tx", "rx"; - }; - - des: des@480a5000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x480a5000 0xa0>; - interrupts = ; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v2"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - ti,tranxdone-status-mask = <0x80>; - clocks = <&sys_clkin_ck>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - status = "disabled"; - }; - - abb_iva: regulator-abb-iva { - compatible = "ti,abb-v2"; - regulator-name = "abb_iva"; - #address-cells = <0>; - #size-cells = <0>; - ti,tranxdone-status-mask = <0x80000000>; - clocks = <&sys_clkin_ck>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - status = "disabled"; - }; - - dss: dss@58000000 { - compatible = "ti,omap4-dss"; - reg = <0x58000000 0x80>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&dss_dss_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,omap4-dispc"; - reg = <0x58001000 0x1000>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&dss_dss_clk>; - clock-names = "fck"; - }; - - rfbi: encoder@58002000 { - compatible = "ti,omap4-rfbi"; - reg = <0x58002000 0x1000>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&dss_dss_clk>, <&l3_div_ck>; - clock-names = "fck", "ick"; - }; - - venc: encoder@58003000 { - compatible = "ti,omap4-venc"; - reg = <0x58003000 0x1000>; - status = "disabled"; - ti,hwmods = "dss_venc"; - clocks = <&dss_tv_clk>; - clock-names = "fck"; - }; - - dsi1: encoder@58004000 { - compatible = "ti,omap4-dsi"; - reg = <0x58004000 0x200>, - <0x58004200 0x40>, - <0x58004300 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&dss_dss_clk>, <&dss_sys_clk>; - clock-names = "fck", "sys_clk"; - }; - - dsi2: encoder@58005000 { - compatible = "ti,omap4-dsi"; - reg = <0x58005000 0x200>, - <0x58005200 0x40>, - <0x58005300 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_dsi2"; - clocks = <&dss_dss_clk>, <&dss_sys_clk>; - clock-names = "fck", "sys_clk"; - }; - - hdmi: encoder@58006000 { - compatible = "ti,omap4-hdmi"; - reg = <0x58006000 0x200>, - <0x58006200 0x100>, - <0x58006300 0x100>, - <0x58006400 0x1000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; - }; - }; - }; -}; - -/include/ "omap44xx-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap443x-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap443x-clocks.dtsi deleted file mode 100644 index f370d96a8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap443x-clocks.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&prm_clocks { - bandgap_fclk: bandgap_fclk@1888 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1888>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap443x.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap443x.dtsi deleted file mode 100644 index fc6a8610c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap443x.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Device Tree Source for OMAP443x SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include "omap4.dtsi" - -/ { - cpus { - cpu0: cpu@0 { - /* OMAP443x variants OPP50-OPPNT */ - operating-points = < - /* kHz uV */ - 300000 1025000 - 600000 1200000 - 800000 1313000 - 1008000 1375000 - >; - clock-latency = <300000>; /* From legacy driver */ - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <3>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - }; - - ocp { - bandgap: bandgap@4a002260 { - reg = <0x4a002260 0x4 - 0x4a00232C 0x4>; - compatible = "ti,omap4430-bandgap"; - - #thermal-sensor-cells = <0>; - }; - }; - - ocp { - abb_mpu: regulator-abb-mpu { - status = "okay"; - - reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>; - reg-names = "base-address", "int-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1313000 0 0 0 0 0 - 1375000 1 0 0 0 0 - 1389000 1 0 0 0 0 - >; - }; - - /* Default unused, just provide register info for record */ - abb_iva: regulator-abb-iva { - reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>; - reg-names = "base-address", "int-address"; - }; - - }; - -}; - -/include/ "omap443x-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap4460.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap4460.dtsi deleted file mode 100644 index ef66e12e0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap4460.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Device Tree Source for OMAP4460 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ -#include "omap4.dtsi" - -/ { - cpus { - /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */ - cpu0: cpu@0 { - operating-points = < - /* kHz uV */ - 350000 1025000 - 700000 1200000 - 920000 1313000 - >; - clock-latency = <300000>; /* From legacy driver */ - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - ti,hwmods = "debugss"; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - }; - - ocp { - bandgap: bandgap@4a002260 { - reg = <0x4a002260 0x4 - 0x4a00232C 0x4 - 0x4a002378 0x18>; - compatible = "ti,omap4460-bandgap"; - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ - gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */ - - #thermal-sensor-cells = <0>; - }; - - abb_mpu: regulator-abb-mpu { - status = "okay"; - - reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, - <0x4A002268 0x4>; - reg-names = "base-address", "int-address", - "efuse-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0 0 0 0 - 1200000 0 0 0 0 0 - 1313000 0 0 0x100000 0x40000 0 - 1375000 1 0 0 0 0 - 1389000 1 0 0 0 0 - >; - }; - - abb_iva: regulator-abb-iva { - status = "okay"; - - reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>, - <0x4A002268 0x4>; - reg-names = "base-address", "int-address", - "efuse-address"; - - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 950000 0 0 0 0 0 - 1140000 0 0 0 0 0 - 1291000 0 0 0x200000 0 0 - 1375000 1 0 0 0 0 - 1376000 1 0 0 0 0 - >; - }; - }; - -}; - -/include/ "omap446x-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap446x-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap446x-clocks.dtsi deleted file mode 100644 index fb5929b74..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap446x-clocks.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&prm_clocks { - div_ts_ck: div_ts_ck@1888 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <24>; - reg = <0x1888>; - ti,dividers = <8>, <16>, <32>; - }; - - bandgap_ts_fclk: bandgap_ts_fclk@1888 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&div_ts_ck>; - ti,bit-shift = <8>; - reg = <0x1888>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap44xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap44xx-clocks.dtsi deleted file mode 100644 index 9573b37fb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ /dev/null @@ -1,1643 +0,0 @@ -/* - * Device Tree Source for OMAP4 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&cm1_clocks { - extalt_clkin_ck: extalt_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <59000000>; - }; - - pad_clks_src_ck: pad_clks_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - pad_clks_ck: pad_clks_ck@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_src_ck>; - ti,bit-shift = <8>; - reg = <0x0108>; - }; - - pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - slimbus_src_clk: slimbus_src_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - slimbus_clk: slimbus_clk@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_src_clk>; - ti,bit-shift = <10>; - reg = <0x0108>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - tie_low_clock_ck: tie_low_clock_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - utmi_phy_clkout_ck: utmi_phy_clkout_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60mhsp1_ck: xclk60mhsp1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60mhsp2_ck: xclk60mhsp2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60motg_ck: xclk60motg_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_abe_ck>; - reg = <0x01f0>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - abe_24m_fclk: abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - aess_fclk: aess_fclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x0528>; - }; - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01f4>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0140>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0130>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - ddrphy_ck: ddrphy_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x013c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - div_core_ck: div_core_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5x2_ck>; - reg = <0x0100>; - ti,max-div = <2>; - }; - - div_iva_hs_clk: div_iva_hs_clk@1dc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5x2_ck>; - ti,max-div = <4>; - reg = <0x01dc>; - ti,index-power-of-two; - }; - - div_mpu_hs_clk: div_mpu_hs_clk@19c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5x2_ck>; - ti,max-div = <4>; - reg = <0x019c>; - ti,index-power-of-two; - }; - - dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0138>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dll_clk_div_ck: dll_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_ck>; - ti,max-div = <31>; - reg = <0x01f0>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_x2_ck>; - ti,bit-shift = <8>; - reg = <0x0134>; - }; - - dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_ck: dpll_core_m3x2_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; - }; - - dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0144>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - }; - - dpll_iva_x2_ck: dpll_iva_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_iva_ck>; - }; - - dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01b8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x01bc>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0170>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - per_hs_clk_div_ck: per_hs_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_hs_clk_div_ck: usb_hs_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - l3_div_ck: l3_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&div_core_ck>; - ti,bit-shift = <4>; - ti,max-div = <2>; - reg = <0x0100>; - }; - - l4_div_ck: l4_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <2>; - reg = <0x0100>; - }; - - lp_clk_div_ck: lp_clk_div_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - mpu_periphclk: mpu_periphclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_mpu_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - ocp_abe_iclk: ocp_abe_iclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&aess_fclk>; - ti,bit-shift = <24>; - reg = <0x0528>; - ti,dividers = <2>, <1>; - }; - - per_abe_24m_fclk: per_abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dmic_sync_mux_ck: dmic_sync_mux_ck@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0538>; - }; - - func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0538>; - }; - - mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0540>; - }; - - func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0540>; - }; - - mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0548>; - }; - - func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0548>; - }; - - mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0550>; - }; - - func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0550>; - }; - - mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; - ti,bit-shift = <25>; - reg = <0x0558>; - }; - - func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0558>; - }; - - slimbus1_fclk_1: slimbus1_fclk_1@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_24m_clk>; - ti,bit-shift = <9>; - reg = <0x0560>; - }; - - slimbus1_fclk_0: slimbus1_fclk_0@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&abe_24m_fclk>; - ti,bit-shift = <8>; - reg = <0x0560>; - }; - - slimbus1_fclk_2: slimbus1_fclk_2@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_ck>; - ti,bit-shift = <10>; - reg = <0x0560>; - }; - - slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_clk>; - ti,bit-shift = <11>; - reg = <0x0560>; - }; - - timer5_sync_mux: timer5_sync_mux@568 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0568>; - }; - - timer6_sync_mux: timer6_sync_mux@570 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0570>; - }; - - timer7_sync_mux: timer7_sync_mux@578 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0578>; - }; - - timer8_sync_mux: timer8_sync_mux@580 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0580>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin_ck: sys_clkin_ck@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0108>; - }; - - abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - dbgclk_mux_ck: dbgclk_mux_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; - reg = <0x0108>; - }; - - syc_clk_div_ck: syc_clk_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - reg = <0x0100>; - ti,max-div = <2>; - }; - - gpio1_dbclk: gpio1_dbclk@1838 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1838>; - }; - - dmt1_clk_mux: dmt1_clk_mux@1840 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1840>; - }; - - usim_ck: usim_ck@1858 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m4x2_ck>; - ti,bit-shift = <24>; - reg = <0x1858>; - ti,dividers = <14>, <18>; - }; - - usim_fclk: usim_fclk@1858 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&usim_ck>; - ti,bit-shift = <8>; - reg = <0x1858>; - }; - - pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; - ti,bit-shift = <20>; - reg = <0x1a20>; - }; - - pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; - ti,bit-shift = <22>; - reg = <0x1a20>; - }; - - stm_clk_div_ck: stm_clk_div_ck@1a20 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&pmd_stm_clock_mux_ck>; - ti,bit-shift = <27>; - ti,max-div = <64>; - reg = <0x1a20>; - ti,index-power-of-two; - }; - - trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&pmd_trace_clk_mux_ck>; - ti,bit-shift = <24>; - reg = <0x1a20>; - ti,dividers = <0>, <1>, <2>, <0>, <4>; - }; - - trace_clk_div_ck: trace_clk_div_ck { - #clock-cells = <0>; - compatible = "ti,clkdm-gate-clock"; - clocks = <&trace_clk_div_div_ck>; - }; -}; - -&prm_clockdomains { - emu_sys_clkdm: emu_sys_clkdm { - compatible = "ti,clockdomain"; - clocks = <&trace_clk_div_ck>; - }; -}; - -&cm2_clocks { - per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_x2_ck: dpll_per_x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_per_ck>; - reg = <0x0150>; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0150>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_per_x2_ck>; - ti,bit-shift = <8>; - reg = <0x0154>; - }; - - dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_per_m3x2_ck: dpll_per_m3x2_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; - }; - - dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0158>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x015c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0160>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x0164>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x01b4>; - ti,clock-mult = <1>; - ti,invert-autoidle-bit; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0190>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - ducati_clk_mux_ck: ducati_clk_mux_ck@100 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; - reg = <0x0100>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_24mc_fclk: func_24mc_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - func_48m_fclk: func_48m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - reg = <0x0108>; - ti,dividers = <4>, <8>; - }; - - func_48mc_fclk: func_48mc_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_64m_fclk: func_64m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m4x2_ck>; - reg = <0x0108>; - ti,dividers = <2>, <4>; - }; - - func_96m_fclk: func_96m_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - reg = <0x0108>; - ti,dividers = <2>, <4>; - }; - - init_60m_fclk: init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - per_abe_nc_fclk: per_abe_nc_fclk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2_ck>; - reg = <0x0108>; - ti,max-div = <2>; - }; - - aes1_fck: aes1_fck@15a0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15a0>; - }; - - aes2_fck: aes2_fck@15a8 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15a8>; - }; - - dss_sys_clk: dss_sys_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&syc_clk_div_ck>; - ti,bit-shift = <10>; - reg = <0x1120>; - }; - - dss_tv_clk: dss_tv_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&extalt_clkin_ck>; - ti,bit-shift = <11>; - reg = <0x1120>; - }; - - dss_dss_clk: dss_dss_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_m5x2_ck>; - ti,bit-shift = <8>; - reg = <0x1120>; - ti,set-rate-parent; - }; - - dss_48mhz_clk: dss_48mhz_clk@1120 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48mc_fclk>; - ti,bit-shift = <9>; - reg = <0x1120>; - }; - - fdif_fck: fdif_fck@1028 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m4x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <4>; - reg = <0x1028>; - ti,index-power-of-two; - }; - - gpio2_dbclk: gpio2_dbclk@1460 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1460>; - }; - - gpio3_dbclk: gpio3_dbclk@1468 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1468>; - }; - - gpio4_dbclk: gpio4_dbclk@1470 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1470>; - }; - - gpio5_dbclk: gpio5_dbclk@1478 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1478>; - }; - - gpio6_dbclk: gpio6_dbclk@1480 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1480>; - }; - - sgx_clk_mux: sgx_clk_mux@1220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>; - ti,bit-shift = <24>; - reg = <0x1220>; - }; - - hsi_fck: hsi_fck@1338 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <4>; - reg = <0x1338>; - ti,index-power-of-two; - }; - - iss_ctrlclk: iss_ctrlclk@1020 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_fclk>; - ti,bit-shift = <8>; - reg = <0x1020>; - }; - - mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>; - ti,bit-shift = <25>; - reg = <0x14e0>; - }; - - per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>; - ti,bit-shift = <24>; - reg = <0x14e0>; - }; - - hsmmc1_fclk: hsmmc1_fclk@1328 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_64m_fclk>, <&func_96m_fclk>; - ti,bit-shift = <24>; - reg = <0x1328>; - }; - - hsmmc2_fclk: hsmmc2_fclk@1330 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_64m_fclk>, <&func_96m_fclk>; - ti,bit-shift = <24>; - reg = <0x1330>; - }; - - ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48m_fclk>; - ti,bit-shift = <8>; - reg = <0x13e0>; - }; - - sha2md5_fck: sha2md5_fck@15c8 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15c8>; - }; - - slimbus2_fclk_1: slimbus2_fclk_1@1538 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_abe_24m_fclk>; - ti,bit-shift = <9>; - reg = <0x1538>; - }; - - slimbus2_fclk_0: slimbus2_fclk_0@1538 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_24mc_fclk>; - ti,bit-shift = <8>; - reg = <0x1538>; - }; - - slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_slimbus_core_clks_ck>; - ti,bit-shift = <10>; - reg = <0x1538>; - }; - - smartreflex_core_fck: smartreflex_core_fck@638 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0638>; - }; - - smartreflex_iva_fck: smartreflex_iva_fck@630 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0630>; - }; - - smartreflex_mpu_fck: smartreflex_mpu_fck@628 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_wkup_clk_mux_ck>; - ti,bit-shift = <1>; - reg = <0x0628>; - }; - - cm2_dm10_mux: cm2_dm10_mux@1428 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1428>; - }; - - cm2_dm11_mux: cm2_dm11_mux@1430 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1430>; - }; - - cm2_dm2_mux: cm2_dm2_mux@1438 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1438>; - }; - - cm2_dm3_mux: cm2_dm3_mux@1440 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1440>; - }; - - cm2_dm4_mux: cm2_dm4_mux@1448 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1448>; - }; - - cm2_dm9_mux: cm2_dm9_mux@1450 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1450>; - }; - - usb_host_fs_fck: usb_host_fs_fck@13d0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48mc_fclk>; - ti,bit-shift = <1>; - reg = <0x13d0>; - }; - - utmi_p1_gfclk: utmi_p1_gfclk@1358 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>; - ti,bit-shift = <24>; - reg = <0x1358>; - }; - - usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&utmi_p1_gfclk>; - ti,bit-shift = <8>; - reg = <0x1358>; - }; - - utmi_p2_gfclk: utmi_p2_gfclk@1358 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>; - ti,bit-shift = <25>; - reg = <0x1358>; - }; - - usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&utmi_p2_gfclk>; - ti,bit-shift = <9>; - reg = <0x1358>; - }; - - usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <10>; - reg = <0x1358>; - }; - - usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <13>; - reg = <0x1358>; - }; - - usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <11>; - reg = <0x1358>; - }; - - usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <12>; - reg = <0x1358>; - }; - - usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <14>; - reg = <0x1358>; - }; - - usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48mc_fclk>; - ti,bit-shift = <15>; - reg = <0x1358>; - }; - - usb_host_hs_fck: usb_host_hs_fck@1358 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <1>; - reg = <0x1358>; - }; - - otg_60m_gfclk: otg_60m_gfclk@1360 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>; - ti,bit-shift = <24>; - reg = <0x1360>; - }; - - usb_otg_hs_xclk: usb_otg_hs_xclk@1360 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&otg_60m_gfclk>; - ti,bit-shift = <8>; - reg = <0x1360>; - }; - - usb_otg_hs_ick: usb_otg_hs_ick@1360 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <0>; - reg = <0x1360>; - }; - - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <10>; - reg = <0x1368>; - }; - - usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <8>; - reg = <0x1368>; - }; - - usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&init_60m_fclk>; - ti,bit-shift = <9>; - reg = <0x1368>; - }; - - usb_tll_hs_ick: usb_tll_hs_ick@1368 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4_div_ck>; - ti,bit-shift = <0>; - reg = <0x1368>; - }; -}; - -&cm2_clockdomains { - l3_init_clkdm: l3_init_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>; - }; -}; - -&scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0310>; - }; - - auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0310>; - }; - - auxclk0_src_ck: auxclk0_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; - }; - - auxclk0_ck: auxclk0_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk0_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0310>; - }; - - auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0314>; - }; - - auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0314>; - }; - - auxclk1_src_ck: auxclk1_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; - }; - - auxclk1_ck: auxclk1_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk1_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0314>; - }; - - auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0318>; - }; - - auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0318>; - }; - - auxclk2_src_ck: auxclk2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; - }; - - auxclk2_ck: auxclk2_ck@318 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk2_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0318>; - }; - - auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x031c>; - }; - - auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x031c>; - }; - - auxclk3_src_ck: auxclk3_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; - }; - - auxclk3_ck: auxclk3_ck@31c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk3_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x031c>; - }; - - auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0320>; - }; - - auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0320>; - }; - - auxclk4_src_ck: auxclk4_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; - }; - - auxclk4_ck: auxclk4_ck@320 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk4_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0320>; - }; - - auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0324>; - }; - - auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0324>; - }; - - auxclk5_src_ck: auxclk5_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; - }; - - auxclk5_ck: auxclk5_ck@324 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk5_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0324>; - }; - - auxclkreq0_ck: auxclkreq0_ck@210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0210>; - }; - - auxclkreq1_ck: auxclkreq1_ck@214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - auxclkreq2_ck: auxclkreq2_ck@218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0218>; - }; - - auxclkreq3_ck: auxclkreq3_ck@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; - - auxclkreq4_ck: auxclkreq4_ck@220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0220>; - }; - - auxclkreq5_ck: auxclkreq5_ck@224 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; - ti,bit-shift = <2>; - reg = <0x0224>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap5-board-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap5-board-common.dtsi deleted file mode 100644 index 4caadb253..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap5-board-common.dtsi +++ /dev/null @@ -1,749 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include "omap5.dtsi" -#include -#include - -/ { - aliases { - display0 = &hdmi0; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vsys_cobra: fixedregulator-vsys_cobra { - compatible = "regulator-fixed"; - regulator-name = "vsys_cobra"; - vin-supply = <&vmain>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdds_1v8_main: fixedregulator-vdds_1v8_main { - compatible = "regulator-fixed"; - regulator-name = "vdds_1v8_main"; - vin-supply = <&smps7_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vmmcsd_fixed: fixedregulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - mmc3_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clk32kgaudio>; - clock-names = "ext_clock"; - }; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */ - enable-active-high; - startup-delay-us = <70000>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ - clocks = <&auxclk1_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - }; - - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - /* gpios defined in the board specific dts */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "b"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "omap5-uevm"; - - ti,jack-detection; - ti,mclk-freq = <19200000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; -}; - -&gpio8 { - /* TI trees use GPIO instead of msecure, see also muxing */ - p234 { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "gpio8_234/msecure"; - }; -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_pins - &led_gpio_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ - OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ - OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ - OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ - OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ - OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ - OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ - OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ - OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ - OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ - OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ - OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ - OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ - OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ - OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ - OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ - OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ - OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ - OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ - >; - }; - - /* TI trees use GPIO mode; msecure mode does not work reliably? */ - palmas_msecure_pins: palmas_msecure_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ - >; - }; - - usbhost_pins: pinmux_usbhost_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ - OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ - - OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ - OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ - - OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ - OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ - >; - }; - - led_gpio_pins: pinmux_led_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ - OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ - OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ - >; - }; - - uart5_pins: pinmux_uart5_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ - OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ - OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ - OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ - OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ - >; - }; -}; - -&omap5_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_wkup_pins - >; - - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */ - >; - }; - - usbhost_wkup_pins: pinmux_usbhost_wkup_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ - >; - }; - - wlcore_irq_pin: pinmux_wlcore_irq_pin { - pinctrl-single,pins = < - OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap5_pmx_core 0x16a>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wlcore_irq_pin>; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ - ref-clock-frequency = <26000000>; - }; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - palmas: palmas@48 { - compatible = "ti,palmas"; - interrupts = ; /* IRQ_SYS_1N */ - reg = <0x48>; - interrupt-controller; - #interrupt-cells = <2>; - ti,system-power-controller; - ti,mux-pad1 = <0xa1>; - ti,mux-pad2 = <0x1b>; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; - }; - - clk32kgaudio: palmas_clk32k@1 { - compatible = "ti,palmas-clk32kgaudio"; - #clock-cells = <0>; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 IRQ_TYPE_NONE>; - ti,backup-battery-chargeable; - ti,backup-battery-charge-high-current; - }; - - gpadc: gpadc { - compatible = "ti,palmas-gpadc"; - interrupts = <18 0 - 16 0 - 17 0>; - #io-channel-cells = <1>; - ti,channel0-current-microamp = <5>; - ti,channel3-current-microamp = <10>; - }; - - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupt-names = "short-irq"; - - ti,ldo6-vibrator; - - smps123-in-supply = <&vsys_cobra>; - smps45-in-supply = <&vsys_cobra>; - smps6-in-supply = <&vsys_cobra>; - smps7-in-supply = <&vsys_cobra>; - smps8-in-supply = <&vsys_cobra>; - smps9-in-supply = <&vsys_cobra>; - smps10_out2-in-supply = <&vsys_cobra>; - smps10_out1-in-supply = <&vsys_cobra>; - ldo1-in-supply = <&vsys_cobra>; - ldo2-in-supply = <&vsys_cobra>; - ldo3-in-supply = <&vdds_1v8_main>; - ldo4-in-supply = <&vdds_1v8_main>; - ldo5-in-supply = <&vsys_cobra>; - ldo6-in-supply = <&vdds_1v8_main>; - ldo7-in-supply = <&vsys_cobra>; - ldo8-in-supply = <&vsys_cobra>; - ldo9-in-supply = <&vmmcsd_fixed>; - ldoln-in-supply = <&vsys_cobra>; - ldousb-in-supply = <&vsys_cobra>; - - regulators { - smps123_reg: smps123 { - /* VDD_OPP_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_OPP_MM */ - regulator-name = "smps45"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_DDR3 - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ - regulator-name = "smps7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_OPP_CORE */ - regulator-name = "smps8"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDA_2v1_AUD over VDD_2v1 */ - regulator-name = "smps9"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - ti,smps-range = <0x80>; - }; - - smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: ldo2 { - /* VCC_2V8_DISP: Does not go anywhere */ - regulator-name = "ldo2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - /* Unused */ - status = "disabled"; - }; - - ldo3_reg: ldo3 { - /* VDDAPHY_MDM: vdda_lli */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - /* Only if Modem is used */ - status = "disabled"; - }; - - ldo4_reg: ldo4 { - /* VDDAPHY_DISP: vdda_dsiport/hdmi */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PHY: usb/sata/hdmi.. */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: ldo6 { - /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7_reg: ldo7 { - /* VDD_VPP: vpp1 */ - regulator-name = "ldo7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - /* Only for efuse reprograming! */ - status = "disabled"; - }; - - ldo8_reg: ldo8 { - /* VDD_3v0: Does not go anywhere */ - regulator-name = "ldo8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - /* Unused */ - status = "disabled"; - }; - - ldo9_reg: ldo9 { - /* VCC_DV_SDIO: vdds_sdcard */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3250000>; - regulator-always-on; - regulator-boot-on; - }; - - regen3_reg: regen3 { - /* REGEN3 controls LDO9 supply to card */ - regulator-name = "regen3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - palmas_power_button: palmas_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&palmas>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - - /* audpwron gpio defined in the board specific dts */ - - vio-supply = <&smps7_reg>; - v2v1-supply = <&smps9_reg>; - enable-active-high; - - clocks = <&clk32kgaudio>; - clock-names = "clk32k"; - }; -}; - -&mcpdm { - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - - clocks = <&twl6040>; - clock-names = "pdmclk"; - - status = "okay"; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&usbhshost { - port2-mode = "ehci-hsic"; - port3-mode = "ehci-hsic"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy &hsusb3_phy>; -}; - -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - -&mcspi1 { - -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&omap5_pmx_core 0x19c>; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&dss { - status = "ok"; -}; - -&hdmi { - status = "ok"; - - /* vdda-supply populated in board specific dts file */ - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap5-cm-t54.dts b/software/linux/kernel/arch/arm/boot/dts/omap5-cm-t54.dts deleted file mode 100644 index b153f6049..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap5-cm-t54.dts +++ /dev/null @@ -1,684 +0,0 @@ -/* - * Support for CompuLab CM-T54 - */ -/dts-v1/; - -#include "omap5.dtsi" -#include -#include - -/ { - model = "CompuLab CM-T54"; - compatible = "compulab,omap5-cm-t54", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */ - }; - - aliases { - display0 = &hdmi0; - display1 = &dvi0; - display2 = &lcd0; - }; - - vmmcsd_fixed: fixed-regulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vwlan_pdn_fixed: fixed-regulator-vwlan-pdn { - compatible = "regulator-fixed"; - regulator-name = "vwlan_pdn_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ldo2_reg>; - gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* gpio4_109 */ - startup-delay-us = <1000>; - enable-active-high; - }; - - vwlan_fixed: fixed-regulator-vwlan { - compatible = "regulator-fixed"; - regulator-name = "vwlan_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vwlan_pdn_fixed>; - gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio4_110 */ - startup-delay-us = <1000>; - enable-active-high; - }; - - ads7846reg: ads7846-reg { - compatible = "regulator-fixed"; - regulator-name = "ads7846-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ - }; - - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "Heartbeat"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - lcd0: display { - compatible = "startek,startek-kd050c", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <43>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - }; - }; - }; - - hdmi0: connector0 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_conn_pins>; - - hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - tfp410: encoder0 { - compatible = "ti,tfp410"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_dvi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector1 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c2>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; -}; - -&omap5_pmx_wkup { - - ads7846_pins: pinmux_ads7846_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ - >; - }; -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &led_gpio_pins - &usbhost_pins - >; - - led_gpio_pins: pinmux_led_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ - OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ - OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ - OMAP5_IOPAD(0x01e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */ - OMAP5_IOPAD(0x01e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */ - OMAP5_IOPAD(0x01ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */ - OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ - OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ - OMAP5_IOPAD(0x0044, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */ - OMAP5_IOPAD(0x0046, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */ - OMAP5_IOPAD(0x0048, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */ - OMAP5_IOPAD(0x004a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */ - OMAP5_IOPAD(0x004c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */ - OMAP5_IOPAD(0x004e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */ - OMAP5_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */ - OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ - OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ - OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ - OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ - OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ - OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ - >; - }; - - wlan_gpios_pins: pinmux_wlan_gpios_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ - OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ - >; - }; - - usbhost_pins: pinmux_usbhost_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ - OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ - - OMAP5_IOPAD(0x01dc, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ - OMAP5_IOPAD(0x01de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ - - OMAP5_IOPAD(0x00a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */ - OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */ - OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ - OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ - >; - }; - - lcd_pins: pinmux_lcd_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ - >; - }; - - hdmi_conn_pins: pinmux_hdmi_conn_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ - OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ - OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */ - OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */ - OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */ - OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */ - OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */ - OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */ - OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */ - OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */ - OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */ - OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */ - OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */ - OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */ - OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */ - OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */ - OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */ - OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */ - OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */ - OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */ - OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */ - OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */ - OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */ - OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */ - OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */ - OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */ - OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */ - OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ - >; - }; - - mcspi2_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */ - OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; - - /* touch controller */ - ads7846@0 { - pinctrl-names = "default"; - pinctrl-0 = <&ads7846_pins>; - - compatible = "ti,ads7846"; - vcc-supply = <&ads7846reg>; - - reg = <0>; /* CS0 */ - spi-max-frequency = <1500000>; - - interrupt-parent = <&gpio1>; - interrupts = <15 0>; /* gpio1_wk15 */ - pendown-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - - - ti,x-min = /bits/ 16 <0x0>; - ti,x-max = /bits/ 16 <0x0fff>; - ti,y-min = /bits/ 16 <0x0>; - ti,y-max = /bits/ 16 <0x0fff>; - - ti,x-plate-ohms = /bits/ 16 <180>; - ti,pressure-max = /bits/ 16 <255>; - - ti,debounce-max = /bits/ 16 <30>; - ti,debounce-tol = /bits/ 16 <10>; - ti,debounce-rep = /bits/ 16 <1>; - - wakeup-source; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc3_pins - &wlan_gpios_pins - >; - vmmc-supply = <&vwlan_fixed>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "at24,24c02"; - pagesize = <16>; - reg = <0x50>; - }; - - palmas: palmas@48 { - compatible = "ti,palmas"; - interrupts = ; /* IRQ_SYS_1N */ - reg = <0x48>; - interrupt-controller; - #interrupt-cells = <2>; - ti,system-power-controller; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 IRQ_TYPE_NONE>; - }; - - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupt-names = "short-irq"; - - ti,ldo6-vibrator; - - regulators { - smps123_reg: smps123 { - /* VDD_OPP_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_OPP_MM */ - regulator-name = "smps45"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_DDR3 - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ - regulator-name = "smps7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_OPP_CORE */ - regulator-name = "smps8"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDA_2v1_AUD over VDD_2v1 */ - regulator-name = "smps9"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - ti,smps-range = <0x80>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: ldo2 { - /* VDD_3V3_WLAN */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <1000>; - }; - - ldo3_reg: ldo3 { - /* VCC_1V5_AUD */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDAPHY_DISP: vdda_dsiport/hdmi */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PHY: usb/sata/hdmi.. */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: ldo6 { - /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7_reg: ldo7 { - /* VDD_VPP: vpp1 */ - regulator-name = "ldo7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - /* Only for efuse reprograming! */ - status = "disabled"; - }; - - ldo8_reg: ldo8 { - /* VDD_3V_GP: act led/serial console */ - regulator-name = "ldo8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VCC_DV_SDIO: vdds_sdcard */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3250000>; - regulator-always-on; - regulator-boot-on; - }; - - regen3_reg: regen3 { - /* REGEN3 controls LDO9 supply to card */ - regulator-name = "regen3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <100000>; -}; - -&usbhshost { - port2-mode = "ehci-hsic"; - port3-mode = "ehci-hsic"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy &hsusb3_phy>; -}; - -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - dpi_dvi_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - - dpi_lcd_out: endpoint@1 { - reg = <1>; - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; - -&dsi2 { - status = "ok"; - vdd-supply = <&ldo4_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - lanes = <1 0 3 2 5 4 7 6>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap5-core-thermal.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap5-core-thermal.dtsi deleted file mode 100644 index de8a3d456..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap5-core-thermal.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Device Tree Source for OMAP543x SoC CORE thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Contact: Eduardo Valentin - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -core_thermal: core_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 2>; - - trips { - core_crit: core_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap5-gpu-thermal.dtsi deleted file mode 100644 index bc3090f2e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap5-gpu-thermal.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Device Tree Source for OMAP543x SoC GPU thermal - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * Contact: Eduardo Valentin - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include - -gpu_thermal: gpu_thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap 1>; - - trips { - gpu_crit: gpu_crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap5-igep0050.dts b/software/linux/kernel/arch/arm/boot/dts/omap5-igep0050.dts deleted file mode 100644 index 8fc192180..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap5-igep0050.dts +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include -#include "omap5-board-common.dtsi" - -/ { - model = "IGEPv5"; - compatible = "isee,omap5-igep0050", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */ - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&power_button_pin>; - pinctrl-names = "default"; - - power-button { - label = "Power Button"; - linux,code = ; - gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led@1 { - label = "board:green:usr0"; - gpios = <&tca6416 1 0>; - default-state = "off"; - }; - led@2 { - label = "board:red:usr1"; - gpios = <&tca6416 2 0>; - default-state = "off"; - }; - led@3 { - label = "board:blue:usr1"; - gpios = <&tca6416 3 0>; - default-state = "off"; - }; - }; -}; - -&hdmi { - vdda-supply = <&ldo7_reg>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - tca6416: tca6416@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -/* LDO4 is VPP1 - ball AD9 */ -&ldo4_reg { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; -}; - -/* - * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33, - * VDDA_HDMI - ball AN25 - */ -&ldo7_reg { - status = "okay"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&omap5_pmx_core { - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ - OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ - >; - }; - - power_button_pin: pinctrl_power_button_pin { - pinctrl-single,pins = < - OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ - >; - }; -}; - -&tpd12s015 { - gpios = <&tca6416 11 0>, /* TCA6416 P01, CT_CP_HDP */ - <&tca6416 12 0>, /* TCA6416 P00, LS_OE*/ - <&gpio7 1 0>, /* 193, HPD */ - <&gpio7 2 0>, /* 194, SCL */ - <&gpio7 3 0>; /* 195, SDA */ -}; - -&twl6040 { - ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio line 144 */ -}; - -&twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_144 */ - OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ - >; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap5-sbc-t54.dts b/software/linux/kernel/arch/arm/boot/dts/omap5-sbc-t54.dts deleted file mode 100644 index 337bbbc01..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap5-sbc-t54.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Suppport for CompuLab CM-T54 on SB-T54 baseboard - */ - -#include "omap5-cm-t54.dts" - -/ { - model = "CompuLab CM-T54 on SB-T54"; - compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; -}; - -&omap5_pmx_core { - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ - >; - }; - - mmc1_aux_pins: pinmux_mmc1_aux_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ - OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = < - &mmc1_pins - &mmc1_aux_pins - >; - cd-inverted; - wp-inverted; - cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */ - wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */ -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; - - at24@50 { - compatible = "at24,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap5-uevm.dts b/software/linux/kernel/arch/arm/boot/dts/omap5-uevm.dts deleted file mode 100644 index f3a3e6be7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap5-uevm.dts +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap5-board-common.dtsi" - -/ { - model = "TI OMAP5 uEVM board"; - compatible = "ti,omap5-uevm", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ - }; - - aliases { - ethernet = ðernet; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "omap5:blue:usr1"; - gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; -}; - -&hdmi { - vdda-supply = <&ldo4_reg>; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - - clock-frequency = <400000>; - - gpio9: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&omap5_pmx_core { - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ - OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ - >; - }; -}; - -&tpd12s015 { - gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */ - <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ - <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ -}; - -&twl6040 { - ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ -}; - -&twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; -}; - -&usbhsehci { - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,3503"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ethernet: usbether@3 { - compatible = "usb424,9730"; - reg = <3>; - }; -}; - -&wlcore { - compatible = "ti,wl1837"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/omap5.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap5.dtsi deleted file mode 100644 index 1d1d8e90c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap5.dtsi +++ /dev/null @@ -1,1130 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * Based on "omap4.dtsi" - */ - -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "ti,omap5"; - interrupt-parent = <&wakeupgen>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - #include "omap5-gpu-thermal.dtsi" - #include "omap5-core-thermal.dtsi" - }; - - timer { - compatible = "arm,armv7-timer"; - /* PPI secure/nonsecure IRQ */ - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - ; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48211000 0 0x1000>, - <0 0x48212000 0 0x1000>, - <0 0x48214000 0 0x2000>, - <0 0x48216000 0 0x2000>; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48281000 0 0x1000>; - interrupt-parent = <&gic>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - sram = <&ocmcram>; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP3 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,omap5-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xc0000000>; - ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0 0x44000000 0 0x2000>, - <0 0x44800000 0 0x3000>, - <0 0x45000000 0 0x4000>; - interrupts = , - ; - - l4_cfg: l4@4a000000 { - compatible = "ti,omap5-l4-cfg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x22a000>; - - scm_core: scm@2000 { - compatible = "ti,omap5-scm-core", "simple-bus"; - reg = <0x2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x800>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - scm_padconf_core: scm@2800 { - compatible = "ti,omap5-scm-padconf-core", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2800 0x800>; - - omap5_pmx_core: pinmux@40 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x40 0x01b6>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_padconf_global: omap5_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0xec>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0xec>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap5", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - }; - - cm_core_aon: cm_core_aon@4000 { - compatible = "ti,omap5-cm-core-aon"; - reg = <0x4000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core@8000 { - compatible = "ti,omap5-cm-core"; - reg = <0x8000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - }; - - l4_wkup: l4@4ae00000 { - compatible = "ti,omap5-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4ae00000 0x2b000>; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x40>; - ti,hwmods = "counter_32k"; - }; - - prm: prm@6000 { - compatible = "ti,omap5-prm"; - reg = <0x6000 0x3000>; - interrupts = ; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@a000 { - compatible = "ti,omap5-scrm"; - reg = <0xa000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - omap5_pmx_wkup: pinmux@c840 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0xc840 0x003c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - }; - - ocmcram: ocmcram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x20000>; /* 128k */ - }; - - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - - gpio1: gpio@4ae10000 { - compatible = "ti,omap4-gpio"; - reg = <0x4ae10000 0x200>; - interrupts = ; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - reg = <0x48055000 0x200>; - interrupts = ; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - reg = <0x48057000 0x200>; - interrupts = ; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - reg = <0x48059000 0x200>; - interrupts = ; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805b000 0x200>; - interrupts = ; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805d000 0x200>; - interrupts = ; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@48051000 { - compatible = "ti,omap4-gpio"; - reg = <0x48051000 0x200>; - interrupts = ; - ti,hwmods = "gpio7"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@48053000 { - compatible = "ti,omap4-gpio"; - reg = <0x48053000 0x200>; - interrupts = ; - ti,hwmods = "gpio8"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = ; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - reg = <0x48070000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - reg = <0x48072000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - reg = <0x48060000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - i2c4: i2c@4807a000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807a000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - }; - - i2c5: i2c@4807c000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c5"; - }; - - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts = ; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap4-uart"; - reg = <0x4806c000 0x100>; - interrupts = ; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - }; - - uart3: serial@48020000 { - compatible = "ti,omap4-uart"; - reg = <0x48020000 0x100>; - interrupts = ; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - }; - - uart4: serial@4806e000 { - compatible = "ti,omap4-uart"; - reg = <0x4806e000 0x100>; - interrupts = ; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - - uart5: serial@48066000 { - compatible = "ti,omap4-uart"; - reg = <0x48066000 0x100>; - interrupts = ; - ti,hwmods = "uart5"; - clock-frequency = <48000000>; - }; - - uart6: serial@48068000 { - compatible = "ti,omap4-uart"; - reg = <0x48068000 0x100>; - interrupts = ; - ti,hwmods = "uart6"; - clock-frequency = <48000000>; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - interrupts = ; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480b4000 0x400>; - interrupts = ; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480ad000 0x400>; - interrupts = ; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d1000 0x400>; - interrupts = ; - ti,hwmods = "mmc4"; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - - mmc5: mmc@480d5000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d5000 0x400>; - interrupts = ; - ti,hwmods = "mmc5"; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - - mmu_dsp: mmu@4a066000 { - compatible = "ti,omap4-iommu"; - reg = <0x4a066000 0x100>; - interrupts = ; - ti,hwmods = "mmu_dsp"; - #iommu-cells = <0>; - }; - - mmu_ipu: mmu@55082000 { - compatible = "ti,omap4-iommu"; - reg = <0x55082000 0x100>; - interrupts = ; - ti,hwmods = "mmu_ipu"; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - - keypad: keypad@4ae1c000 { - compatible = "ti,omap4-keypad"; - reg = <0x4ae1c000 0x400>; - ti,hwmods = "kbd"; - }; - - mcpdm: mcpdm@40132000 { - compatible = "ti,omap4-mcpdm"; - reg = <0x40132000 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "mcpdm"; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - status = "disabled"; - }; - - dmic: dmic@4012e000 { - compatible = "ti,omap4-dmic"; - reg = <0x4012e000 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - ti,hwmods = "dmic"; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - - mcbsp1: mcbsp@40122000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40122000 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp1"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp2: mcbsp@40124000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40124000 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp2"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcbsp3: mcbsp@40126000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x40126000 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = ; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp3"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mailbox: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = ; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - - timer1: timer@4ae18000 { - compatible = "ti,omap5430-timer"; - reg = <0x4ae18000 0x80>; - interrupts = ; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@48032000 { - compatible = "ti,omap5430-timer"; - reg = <0x48032000 0x80>; - interrupts = ; - ti,hwmods = "timer2"; - }; - - timer3: timer@48034000 { - compatible = "ti,omap5430-timer"; - reg = <0x48034000 0x80>; - interrupts = ; - ti,hwmods = "timer3"; - }; - - timer4: timer@48036000 { - compatible = "ti,omap5430-timer"; - reg = <0x48036000 0x80>; - interrupts = ; - ti,hwmods = "timer4"; - }; - - timer5: timer@40138000 { - compatible = "ti,omap5430-timer"; - reg = <0x40138000 0x80>, - <0x49038000 0x80>; - interrupts = ; - ti,hwmods = "timer5"; - ti,timer-dsp; - ti,timer-pwm; - }; - - timer6: timer@4013a000 { - compatible = "ti,omap5430-timer"; - reg = <0x4013a000 0x80>, - <0x4903a000 0x80>; - interrupts = ; - ti,hwmods = "timer6"; - ti,timer-dsp; - ti,timer-pwm; - }; - - timer7: timer@4013c000 { - compatible = "ti,omap5430-timer"; - reg = <0x4013c000 0x80>, - <0x4903c000 0x80>; - interrupts = ; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@4013e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4013e000 0x80>, - <0x4903e000 0x80>; - interrupts = ; - ti,hwmods = "timer8"; - ti,timer-dsp; - ti,timer-pwm; - }; - - timer9: timer@4803e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4803e000 0x80>; - interrupts = ; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap5430-timer"; - reg = <0x48086000 0x80>; - interrupts = ; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap5430-timer"; - reg = <0x48088000 0x80>; - interrupts = ; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - wdt2: wdt@4ae14000 { - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; - reg = <0x4ae14000 0x80>; - interrupts = ; - ti,hwmods = "wd_timer2"; - }; - - dmm@4e000000 { - compatible = "ti,omap5-dmm"; - reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; - ti,hwmods = "dmm"; - }; - - emif1: emif@4c000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif1"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4c000000 0x400>; - interrupts = ; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - emif2: emif@4d000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif2"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4d000000 0x400>; - interrupts = ; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - usb3: omap_dwc3@4a020000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss"; - reg = <0x4a020000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - dwc3: dwc3@4a030000 { - compatible = "snps,dwc3"; - reg = <0x4a030000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "peripheral"; - }; - }; - - ocp2scp@4a080000 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4a080000 0x20>; - ranges; - ti,hwmods = "ocp2scp1"; - usb2_phy: usb2phy@4a084000 { - compatible = "ti,omap-usb2"; - reg = <0x4a084000 0x7c>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - usb3_phy: usb3phy@4a084400 { - compatible = "ti,omap-usb3"; - reg = <0x4a084400 0x80>, - <0x4a084800 0x64>, - <0x4a084c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy_cm_clk32k>, - <&sys_clkin>, - <&usb_otg_ss_refclk960m>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = ; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&l3init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3"; - reg = <0x4a064800 0x400>; - interrupts = ; - }; - - usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap"; - reg = <0x4a064c00 0x400>; - interrupts = ; - }; - }; - - bandgap: bandgap@4a0021e0 { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c>; - interrupts = ; - compatible = "ti,omap5430-bandgap"; - - #thermal-sensor-cells = <1>; - }; - - /* OCP2SCP3 */ - ocp2scp@4a090000 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4a090000 0x20>; - ranges; - ti,hwmods = "ocp2scp3"; - sata_phy: phy@4a096000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x4A096000 0x80>, /* phy_rx */ - <0x4A096400 0x64>, /* phy_tx */ - <0x4A096800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, <&sata_ref_clk>; - clock-names = "sysclk", "refclk"; - #phy-cells = <0>; - }; - }; - - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&sata_ref_clk>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; - }; - - dss: dss@58000000 { - compatible = "ti,omap5-dss"; - reg = <0x58000000 0x80>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&dss_dss_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,omap5-dispc"; - reg = <0x58001000 0x1000>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&dss_dss_clk>; - clock-names = "fck"; - }; - - rfbi: encoder@58002000 { - compatible = "ti,omap5-rfbi"; - reg = <0x58002000 0x100>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&dss_dss_clk>, <&l3_iclk_div>; - clock-names = "fck", "ick"; - }; - - dsi1: encoder@58004000 { - compatible = "ti,omap5-dsi"; - reg = <0x58004000 0x200>, - <0x58004200 0x40>, - <0x58004300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&dss_dss_clk>, <&dss_sys_clk>; - clock-names = "fck", "sys_clk"; - }; - - dsi2: encoder@58005000 { - compatible = "ti,omap5-dsi"; - reg = <0x58009000 0x200>, - <0x58009200 0x40>, - <0x58009300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_dsi2"; - clocks = <&dss_dss_clk>, <&dss_sys_clk>; - clock-names = "fck", "sys_clk"; - }; - - hdmi: encoder@58060000 { - compatible = "ti,omap5-hdmi"; - reg = <0x58040000 0x200>, - <0x58040200 0x80>, - <0x58040300 0x80>, - <0x58060000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; - }; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v2"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, - <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80>; - /* LDOVBBMPU_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMPU_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1250000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - - abb_mm: regulator-abb-mm { - compatible = "ti,abb-v2"; - regulator-name = "abb_mm"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, - <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80000000>; - /* LDOVBBMM_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMM_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0x0 0 0x02000000 0x01F00000 - 1120000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - }; -}; - -&cpu_thermal { - polling-delay = <500>; /* milliseconds */ -}; - -/include/ "omap54xx-clocks.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/omap54xx-clocks.dtsi b/software/linux/kernel/arch/arm/boot/dts/omap54xx-clocks.dtsi deleted file mode 100644 index 4899c2359..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ /dev/null @@ -1,1390 +0,0 @@ -/* - * Device Tree Source for OMAP5 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -&cm_core_aon_clocks { - pad_clks_src_ck: pad_clks_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - pad_clks_ck: pad_clks_ck@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_src_ck>; - ti,bit-shift = <8>; - reg = <0x0108>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - slimbus_src_clk: slimbus_src_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - slimbus_clk: slimbus_clk@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_src_clk>; - ti,bit-shift = <10>; - reg = <0x0108>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - xclk60mhsp1_ck: xclk60mhsp1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60mhsp2_ck: xclk60mhsp2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_abe_ck>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f0>; - ti,index-starts-at-one; - }; - - abe_24m_fclk: abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - abe_iclk: abe_iclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&aess_fclk>; - ti,bit-shift = <24>; - reg = <0x0528>; - ti,dividers = <2>, <1>; - }; - - abe_lp_clk_div: abe_lp_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f4>; - ti,index-starts-at-one; - }; - - dpll_core_byp_mux: dpll_core_byp_mux@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin>, <&dpll_core_byp_mux>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - c2c_fclk: c2c_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h21x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - c2c_iclk: c2c_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&c2c_fclk>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0138>; - ti,index-starts-at-one; - }; - - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x013c>; - ti,index-starts-at-one; - }; - - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0140>; - ti,index-starts-at-one; - }; - - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0144>; - ti,index-starts-at-one; - }; - - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - reg = <0x0130>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; - }; - - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - }; - - dpll_iva_x2_ck: dpll_iva_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_iva_ck>; - }; - - dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01b8>; - ti,index-starts-at-one; - }; - - dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01bc>; - ti,index-starts-at-one; - }; - - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap5-mpu-dpll-clock"; - clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - reg = <0x0170>; - ti,index-starts-at-one; - }; - - per_dpll_hs_clk_div: per_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - l3_iclk_div: l3_iclk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; - }; - - gpu_l3_iclk: gpu_l3_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_iclk_div>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4_root_clk_div: l4_root_clk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <8>; - reg = <0x100>; - clocks = <&l3_iclk_div>; - ti,index-power-of-two; - }; - - slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_clk>; - ti,bit-shift = <11>; - reg = <0x0560>; - }; - - aess_fclk: aess_fclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x0528>; - }; - - dmic_sync_mux_ck: dmic_sync_mux_ck@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0538>; - }; - - dmic_gfclk: dmic_gfclk@538 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0538>; - }; - - mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0540>; - }; - - mcasp_gfclk: mcasp_gfclk@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0540>; - }; - - mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0548>; - }; - - mcbsp1_gfclk: mcbsp1_gfclk@548 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0548>; - }; - - mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0550>; - }; - - mcbsp2_gfclk: mcbsp2_gfclk@550 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0550>; - }; - - mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0558>; - }; - - mcbsp3_gfclk: mcbsp3_gfclk@558 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0558>; - }; - - timer5_gfclk_mux: timer5_gfclk_mux@568 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0568>; - }; - - timer6_gfclk_mux: timer6_gfclk_mux@570 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0570>; - }; - - timer7_gfclk_mux: timer7_gfclk_mux@578 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0578>; - }; - - timer8_gfclk_mux: timer8_gfclk_mux@580 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0580>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin: sys_clkin@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x0108>; - }; - - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <2>; - }; - - dss_syc_gfclk_div: dss_syc_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <1>; - }; - - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&abe_lp_clk_div>; - reg = <0x0108>; - }; - - l3instr_ts_gclk_div: l3instr_ts_gclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&wkupaon_iclk_mux>; - clock-mult = <1>; - clock-div = <1>; - }; - - gpio1_dbclk: gpio1_dbclk@1938 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1938>; - }; - - timer1_gfclk_mux: timer1_gfclk_mux@1940 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1940>; - }; -}; -&cm_core_clocks { - - dpll_per_byp_mux: dpll_per_byp_mux@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&dpll_per_byp_mux>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_x2_ck: dpll_per_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_per_ck>; - }; - - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0164>; - ti,index-starts-at-one; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_unipro1_ck: dpll_unipro1_ck@200 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; - }; - - dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_unipro1_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_unipro1_ck>; - ti,max-div = <127>; - reg = <0x0210>; - ti,index-starts-at-one; - }; - - dpll_unipro2_ck: dpll_unipro2_ck@1c0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; - }; - - dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_unipro2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_unipro2_ck>; - ti,max-div = <127>; - reg = <0x01d0>; - ti,index-starts-at-one; - }; - - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - reg = <0x0190>; - ti,index-starts-at-one; - }; - - func_128m_clk: func_128m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_48m_fclk: func_48m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_96m_fclk: func_96m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_60m_fclk: l3init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - dss_32khz_clk: dss_32khz_clk@1420 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <11>; - reg = <0x1420>; - }; - - dss_48mhz_clk: dss_48mhz_clk@1420 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_48m_fclk>; - ti,bit-shift = <9>; - reg = <0x1420>; - }; - - dss_dss_clk: dss_dss_clk@1420 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_per_h12x2_ck>; - ti,bit-shift = <8>; - reg = <0x1420>; - ti,set-rate-parent; - }; - - dss_sys_clk: dss_sys_clk@1420 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dss_syc_gfclk_div>; - ti,bit-shift = <10>; - reg = <0x1420>; - }; - - gpio2_dbclk: gpio2_dbclk@1060 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1060>; - }; - - gpio3_dbclk: gpio3_dbclk@1068 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1068>; - }; - - gpio4_dbclk: gpio4_dbclk@1070 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1070>; - }; - - gpio5_dbclk: gpio5_dbclk@1078 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1078>; - }; - - gpio6_dbclk: gpio6_dbclk@1080 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1080>; - }; - - gpio7_dbclk: gpio7_dbclk@1110 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1110>; - }; - - gpio8_dbclk: gpio8_dbclk@1118 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1118>; - }; - - iss_ctrlclk: iss_ctrlclk@1320 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_fclk>; - ti,bit-shift = <8>; - reg = <0x1320>; - }; - - lli_txphy_clk: lli_txphy_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_unipro1_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x0f20>; - }; - - lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_unipro1_m2_ck>; - ti,bit-shift = <9>; - reg = <0x0f20>; - }; - - mmc1_32khz_clk: mmc1_32khz_clk@1628 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x1628>; - }; - - sata_ref_clk: sata_ref_clk@1688 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin>; - ti,bit-shift = <8>; - reg = <0x1688>; - }; - - usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <13>; - reg = <0x1658>; - }; - - usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <14>; - reg = <0x1658>; - }; - - usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_m2_ck>; - ti,bit-shift = <7>; - reg = <0x1658>; - }; - - usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <11>; - reg = <0x1658>; - }; - - usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <12>; - reg = <0x1658>; - }; - - usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <6>; - reg = <0x1658>; - }; - - utmi_p1_gfclk: utmi_p1_gfclk@1658 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; - ti,bit-shift = <24>; - reg = <0x1658>; - }; - - usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&utmi_p1_gfclk>; - ti,bit-shift = <8>; - reg = <0x1658>; - }; - - utmi_p2_gfclk: utmi_p2_gfclk@1658 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; - ti,bit-shift = <25>; - reg = <0x1658>; - }; - - usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&utmi_p2_gfclk>; - ti,bit-shift = <9>; - reg = <0x1658>; - }; - - usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <10>; - reg = <0x1658>; - }; - - usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_usb_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x16f0>; - }; - - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <8>; - reg = <0x1668>; - }; - - usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <9>; - reg = <0x1668>; - }; - - usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3init_60m_fclk>; - ti,bit-shift = <10>; - reg = <0x1668>; - }; - - fdif_fclk: fdif_fclk@1328 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_h11x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1328>; - }; - - gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <24>; - reg = <0x1520>; - }; - - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <25>; - reg = <0x1520>; - }; - - hsi_fclk: hsi_fclk@1638 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1638>; - }; - - mmc1_fclk_mux: mmc1_fclk_mux@1628 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1628>; - }; - - mmc1_fclk: mmc1_fclk@1628 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc1_fclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <2>; - reg = <0x1628>; - }; - - mmc2_fclk_mux: mmc2_fclk_mux@1630 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - reg = <0x1630>; - }; - - mmc2_fclk: mmc2_fclk@1630 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&mmc2_fclk_mux>; - ti,bit-shift = <25>; - ti,max-div = <2>; - reg = <0x1630>; - }; - - timer10_gfclk_mux: timer10_gfclk_mux@1028 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1028>; - }; - - timer11_gfclk_mux: timer11_gfclk_mux@1030 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1030>; - }; - - timer2_gfclk_mux: timer2_gfclk_mux@1038 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1038>; - }; - - timer3_gfclk_mux: timer3_gfclk_mux@1040 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1040>; - }; - - timer4_gfclk_mux: timer4_gfclk_mux@1048 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1048>; - }; - - timer9_gfclk_mux: timer9_gfclk_mux@1050 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x1050>; - }; -}; - -&cm_core_clockdomains { - l3init_clkdm: l3init_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0310>; - }; - - auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0310>; - }; - - auxclk0_src_ck: auxclk0_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; - }; - - auxclk0_ck: auxclk0_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk0_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0310>; - }; - - auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0314>; - }; - - auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0314>; - }; - - auxclk1_src_ck: auxclk1_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; - }; - - auxclk1_ck: auxclk1_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk1_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0314>; - }; - - auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0318>; - }; - - auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0318>; - }; - - auxclk2_src_ck: auxclk2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; - }; - - auxclk2_ck: auxclk2_ck@318 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk2_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0318>; - }; - - auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x031c>; - }; - - auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x031c>; - }; - - auxclk3_src_ck: auxclk3_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; - }; - - auxclk3_ck: auxclk3_ck@31c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk3_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x031c>; - }; - - auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0320>; - }; - - auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0320>; - }; - - auxclk4_src_ck: auxclk4_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; - }; - - auxclk4_ck: auxclk4_ck@320 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk4_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0320>; - }; - - auxclkreq0_ck: auxclkreq0_ck@210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0210>; - }; - - auxclkreq1_ck: auxclkreq1_ck@214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - auxclkreq2_ck: auxclkreq2_ck@218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0218>; - }; - - auxclkreq3_ck: auxclkreq3_ck@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/original.infinity2m-spinand-ssc011a-s01a-rgb565-rmii-doublenet.dts b/software/linux/kernel/arch/arm/boot/dts/original.infinity2m-spinand-ssc011a-s01a-rgb565-rmii-doublenet.dts new file mode 100644 index 000000000..e69de29bb diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-kuroboxpro.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-kuroboxpro.dts deleted file mode 100644 index 1a672b098..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-kuroboxpro.dts +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Device Tree file for Buffalo/Revogear Kurobox Pro - * - * Copyright (C) 2016 - * Roger Shimizu - * - * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c - * Copyright (C) Ronen Shitrit - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include - -/ { - model = "Buffalo/Revogear Kurobox Pro"; - compatible = "buffalo,kurobox-pro", "marvell,orion5x-88f5182", "marvell,orion5x"; - - soc { - ranges = , - , - , - ; - }; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; -}; - -&devbus_cs0 { - status = "okay"; - compatible = "marvell,orion-nand"; - reg = ; - cle = <0>; - ale = <1>; - bank-width = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - uImage@0 { /* 4 MB */ - reg = <0 0x400000>; - read-only; - }; - - rootfs@400000 { /* 64 MB */ - reg = <0x400000 0x4000000>; - read-only; - }; - - extra@4400000 { /* 188 MB */ - reg = <0x4400000 0xBC00000>; - read-only; - }; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; - -&ehci1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-lacie-d2-network.dts deleted file mode 100644 index c701e8d16..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-lacie-d2-network.dts +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni - * Copyright (C) 2009 Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "LaCie d2 Network"; - compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - front_button { - label = "Front Push Button"; - linux,code = ; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - }; - - power_rocker_sw_on { - label = "Power rocker switch (on|auto)"; - linux,input-type = <5>; /* EV_SW */ - linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - power_rocker_sw_off { - label = "Power rocker switch (auto|off)"; - linux,input-type = <5>; /* EV_SW */ - linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; - pinctrl-names = "default"; - - sata0_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full512Kb"; - reg = <0 0x80000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372b"; - reg = <0x32>; - }; - - fan@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - - /* Not enough HW info */ - status = "disabled"; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>; - pinctrl-names = "default"; - - pmx_board_id: pmx-board-id { - marvell,pins = "mpp0", "mpp1", "mpp2"; - marvell,function = "gpio"; - }; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp8", "mpp9", "mpp18"; - marvell,function = "gpio"; - }; - - pmx_fan_fail: pmx-fan-fail { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - /* - * MPP6: Red front LED - * MPP16: Blue front LED blink control - */ - pmx_leds: pmx-leds { - marvell,pins = "mpp6", "mpp16"; - marvell,function = "gpio"; - }; - - pmx_sata0_led_active: pmx-sata0-led-active { - marvell,pins = "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata0_power: pmx-sata0-power { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_sata1_led_active: pmx-sata1-led-active { - marvell,pins = "mpp15"; - marvell,function = "sata1"; - }; - - pmx_sata1_power: pmx-sata1-power { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - /* - * Non MPP GPIOs: - * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) - * GPIO 23: Blue front LED off - * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) - */ -}; - -&sata { - pinctrl-0 = <&pmx_sata0_led_active - &pmx_sata1_led_active>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts deleted file mode 100644 index 89ff404a5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright (C) 2012 Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * TODO: add Orion USB device port init when kernel.org support is added. - * TODO: add flash write support: see below. - * TODO: add power-off support. - * TODO: add I2C EEPROM support. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "LaCie Ethernet Disk mini V2"; - compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_power_button>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - button@1 { - label = "Power-on Switch"; - linux,code = ; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_power_led>; - pinctrl-names = "default"; - - led@1 { - label = "power:blue"; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full512Kb"; - reg = <0 0x80000>; - read-only; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>; - pinctrl-names = "default"; - - pmx_power_button: pmx-power-button { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_power_led: pmx-power-led { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_power_led_ctrl: pmx-power-led-ctrl { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; -}; - -&sata { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation-lsgl.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation-lsgl.dts deleted file mode 100644 index 51dc734cd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation-lsgl.dts +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-GL - * (also known as Buffalo Linkstation Pro/Live) - * - * Copyright (C) 2016 - * Roger Shimizu - * - * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c - * Copyright (C) Ronen Shitrit - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include - -/ { - model = "Buffalo Linkstation Pro/Live"; - compatible = "buffalo,lsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; - -&ehci1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts deleted file mode 100644 index 0eead400f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Device Tree file for Buffalo Linkstation LS-WTGL - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "orion5x-linkstation.dtsi" -#include "mvebu-linkstation-gpio-simple.dtsi" -#include "mvebu-linkstation-fan.dtsi" -#include - -/ { - model = "Buffalo Linkstation LS-WTGL"; - compatible = "buffalo,lswtgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { /* 64 MB */ - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - gpio_keys { - power-on-switch { - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - }; - - power-auto-switch { - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - blue-power-led { - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - red-alarm-led { - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - amber-info-led { - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW - &gpio0 17 GPIO_ACTIVE_LOW>; - - alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&pinctrl { - pmx_led_power: pmx-leds { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp8", "mpp10"; - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; -}; - -&hdd_power { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -&usb_power { - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; -}; - -&sata { - nr-ports = <2>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation.dtsi b/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation.dtsi deleted file mode 100644 index ed456ab35..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-linkstation.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Device Tree common file for orion5x based Buffalo Linkstation - * - * Copyright (C) 2015, 2016 - * Roger Shimizu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "orion5x-mv88f5182.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - hdd_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&pinctrl { - pmx_power_hdd: pmx-power-hdd { - marvell,function = "gpio"; - }; - - pmx_power_usb: pmx-power-usb { - marvell,function = "gpio"; - }; -}; - -&devbus_bootcs { - status = "okay"; - devbus,keep-config; - - flash@0 { - compatible = "jedec-flash"; - reg = <0 0x40000>; - bank-width = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - header@0 { - reg = <0 0x30000>; - read-only; - }; - - uboot@30000 { - reg = <0x30000 0xF000>; - read-only; - }; - - uboot_env@3F000 { - reg = <0x3F000 0x1000>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c { - status = "okay"; - - rtc { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; -}; - -&wdt { - status = "disabled"; -}; - -&sata { - status = "okay"; - nr-ports = <1>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-lswsgl.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-lswsgl.dts deleted file mode 100644 index 6b47a52ce..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-lswsgl.dts +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (C) 2015 Benjamin Cama - * Copyright (C) 2014 Thomas Petazzoni - * Based on the board file arch/arm/mach-orion5x/lsmini-setup.c, - * Copyright (C) 2008 Alexey Kopytko - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Buffalo Linkstation Mini (LS-WSGL)"; - compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - reg = <0x00000000 0x8000000>; /* 128 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - linux,stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - func { - label = "Function Button"; - linux,code = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - - power { - label = "Power-on Switch"; - linux,input-type = <5>; /* EV_SW */ - linux,code = ; /* LSMINI_SW_POWER */ - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - - autopower { - label = "Power-auto Switch"; - linux,input-type = <5>; /* EV_SW */ - linux,code = ; /* LSMINI_SW_AUTOPOWER */ - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_alarm &pmx_led_info &pmx_led_func - &pmx_led_power>; - pinctrl-names = "default"; - - alarm { - label = "lswsgl:alarm:red"; - gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - info { - label = "lswsgl:info:amber"; - gpio = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - - func { - label = "lswsgl:func:blue:top"; - gpio = <&gpio0 9 GPIO_ACTIVE_LOW>; - }; - - power { - label = "lswsgl:power:blue:bottom"; - gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power &pmx_usb_power>; - pinctrl-names = "default"; - - sata0_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 1 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; - }; - - usb_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x40000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Full256Kb"; - reg = <0 0x40000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@32 { - compatible = "ricoh,rs5c372a"; - reg = <0x32>; - }; -}; - -&pinctrl { - pmx_buttons: pmx-buttons { - marvell,pins = "mpp15", "mpp17", "mpp18"; - marvell,function = "gpio"; - }; - - pmx_led_alarm: pmx-leds { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_led_info: pmx-leds { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_led_func: pmx-leds { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_led_power: pmx-leds { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_sata0_power: pmx-sata0-power { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_sata1_power: pmx-sata1-power { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts deleted file mode 100644 index ff3484904..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni - * Copyright (C) Sylver Bruneau - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Maxtor Shared Storage II"; - compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_buttons>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - power { - label = "Power"; - linux,code = ; - gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - }; - - reset { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - /* - * Currently the MTD code does not recognize the MX29LV400CBCT - * as a bottom-type device. This could cause risks of - * accidentally erasing critical flash sectors. We thus define - * a single, write-protected partition covering the whole - * flash. TODO: once the flash part TOP/BOTTOM detection - * issue is sorted out in the MTD code, break this into at - * least three partitions: 'u-boot code', 'u-boot environment' - * and 'whatever is left'. - */ - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x40000>; - bank-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@68 { - compatible = "st,m41t81"; - reg = <0x68>; - pinctrl-0 = <&pmx_rtc>; - pinctrl-names = "default"; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_leds &pmx_misc>; - pinctrl-names = "default"; - - pmx_buttons: pmx-buttons { - marvell,pins = "mpp11", "mpp12"; - marvell,function = "gpio"; - }; - - /* - * MPP0: Power LED - * MPP1: Error LED - */ - pmx_leds: pmx-leds { - marvell,pins = "mpp0", "mpp1"; - marvell,function = "gpio"; - }; - - /* - * MPP4: HDD ind. (Single/Dual) - * MPP5: HD0 5V control - * MPP6: HD0 12V control - * MPP7: HD1 5V control - * MPP8: HD1 12V control - */ - pmx_misc: pmx-misc { - marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_sata0_led_active: pmx-sata0-led-active { - marvell,pins = "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata1_led_active: pmx-sata1-led-active { - marvell,pins = "mpp15"; - marvell,function = "sata1"; - }; - - /* - * Non MPP GPIOs: - * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) - * GPIO 23: Blue front LED off - * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) - */ -}; - -&sata { - pinctrl-0 = <&pmx_sata0_led_active - &pmx_sata1_led_active>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/software/linux/kernel/arch/arm/boot/dts/orion5x-mv88f5181.dtsi deleted file mode 100644 index f667012b2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-mv88f5181.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2016 Jamie Lentin - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include "orion5x.dtsi" - -/ { - compatible = "marvell,orion5x-88f5181", "marvell,orion5x"; - - soc { - compatible = "marvell,orion5x-88f5181-mbus", "simple-bus"; - - internal-regs { - pinctrl: pinctrl@10000 { - compatible = "marvell,88f5181-pinctrl"; - reg = <0x10000 0x8>, <0x10050 0x4>; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,mv88f5181-core-clock"; - reg = <0x10010 0x4>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x1500 0x20>; - }; - }; - }; -}; - -&pinctrl { - pmx_ge: pmx-ge { - marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11", - "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19"; - marvell,function = "ge"; - }; -}; - -ð { - pinctrl-0 = <&pmx_ge>; - pinctrl-names = "default"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/software/linux/kernel/arch/arm/boot/dts/orion5x-mv88f5182.dtsi deleted file mode 100644 index d1ed71c60..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-mv88f5182.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include "orion5x.dtsi" - -/ { - compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; - - soc { - compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; - - internal-regs { - pinctrl: pinctrl@10000 { - compatible = "marvell,88f5182-pinctrl"; - reg = <0x10000 0x8>, <0x10050 0x4>; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp12", "mpp14"; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp13", "mpp15"; - marvell,function = "sata1"; - }; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,mv88f5182-core-clock"; - reg = <0x10010 0x4>; - #clock-cells = <1>; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x1500 0x20>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts deleted file mode 100644 index 9f6ae4e1d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (C) 2016 Jamie Lentin - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include -#include "orion5x-mv88f5181.dtsi" - -/ { - model = "Netgear WNR854-t"; - compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", - "marvell,orion5x"; - aliases { - serial0 = &uart0; - }; - - memory { - reg = <0x00000000 0x2000000>; /* 32 MB */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - ranges = , - , - ; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_reset_button>; - pinctrl-names = "default"; - - reset { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; - pinctrl-names = "default"; - - led@0 { - label = "wnr854t:green:power"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - - led@1 { - label = "wnr854t:blink:power"; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - }; - - led@2 { - label = "wnr854t:green:wan"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - devbus,keep-config; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x800000>; - bank-width = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "rootfs"; - reg = <0x100000 0x660000>; - }; - - partition@760000 { - label = "uboot_env"; - reg = <0x760000 0x20000>; - }; - - partition@780000 { - label = "uboot"; - reg = <0x780000 0x80000>; - read-only; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan3"; - phy-handle = <&lan3phy>; - }; - - port@1 { - reg = <1>; - label = "lan4"; - phy-handle = <&lan4phy>; - }; - - port@2 { - reg = <2>; - label = "wan"; - phy-handle = <&wanphy>; - }; - - port@3 { - reg = <3>; - label = "cpu"; - ethernet = <ðport>; - }; - - port@5 { - reg = <5>; - label = "lan1"; - phy-handle = <&lan1phy>; - }; - - port@7 { - reg = <7>; - label = "lan2"; - phy-handle = <&lan2phy>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - lan3phy: ethernet-phy@0 { - /* Marvell 88E1121R (port 1) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan4phy: ethernet-phy@1 { - /* Marvell 88E1121R (port 2) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - wanphy: ethernet-phy@2 { - /* Marvell 88E1121R (port 1) */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <2>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan1phy: ethernet-phy@5 { - /* Marvell 88E1112 */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <5>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - - lan2phy: ethernet-phy@7 { - /* Marvell 88E1112 */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <7>; - marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; - }; - }; - }; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - /* Hardwired to DSA switch */ - speed = <1000>; - duplex = <1>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_pci_gpios>; - pinctrl-names = "default"; - - pmx_power_led: pmx-power-led { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_reset_button: pmx-reset-button { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_power_led_blink: pmx-power-led-blink { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_wan_led: pmx-wan-led { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_pci_gpios: pmx-pci-gpios { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/software/linux/kernel/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts deleted file mode 100644 index 6fb052507..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include -#include "orion5x-mv88f5182.dtsi" - -/ { - model = "Marvell Reference Design 88F5182 NAS"; - compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; - - memory { - reg = <0x00000000 0x4000000>; /* 64 MB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - linux,stdout-path = &uart0; - }; - - soc { - ranges = , - , - , - ; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_debug_led>; - pinctrl-names = "default"; - - led@0 { - label = "rd88f5182:cpu"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&devbus_bootcs { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x80000>; - bank-width = <1>; - }; -}; - -&devbus_cs1 { - status = "okay"; - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <90000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <186000>; - devbus,acc-next-ps = <186000>; - - /* Write parameters */ - devbus,wr-high-ps = <90000>; - devbus,wr-low-ps = <90000>; - devbus,ale-wr-ps = <90000>; - - flash@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <1>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -ð { - status = "okay"; - - ethernet-port@0 { - phy-handle = <ðphy>; - }; -}; - -&i2c { - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - - rtc@68 { - pinctrl-0 = <&pmx_rtc>; - pinctrl-names = "default"; - compatible = "dallas,ds1338"; - reg = <0x68>; - }; -}; - -&mdio { - status = "okay"; - - ethphy: ethernet-phy { - reg = <8>; - }; -}; - -&pinctrl { - pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios - &pmx_pci_gpios>; - pinctrl-names = "default"; - - /* - * MPP[20] PCI Clock to MV88F5182 - * MPP[21] PCI Clock to mini PCI CON11 - * MPP[22] USB 0 over current indication - * MPP[23] USB 1 over current indication - * MPP[24] USB 1 over current enable - * MPP[25] USB 0 over current enable - */ - - pmx_debug_led: pmx-debug_led { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_reset_switch: pmx-reset-switch { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_rtc: pmx-rtc { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_misc_gpios: pmx-misc-gpios { - marvell,pins = "mpp4", "mpp5"; - marvell,function = "gpio"; - }; - - pmx_pci_gpios: pmx-pci-gpios { - marvell,pins = "mpp6", "mpp7"; - marvell,function = "gpio"; - }; -}; - -&sata { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/orion5x.dtsi b/software/linux/kernel/arch/arm/boot/dts/orion5x.dtsi deleted file mode 100644 index fbccfbbab..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/orion5x.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (C) 2012 Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include "skeleton.dtsi" - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - model = "Marvell Orion5x SoC"; - compatible = "marvell,orion5x"; - interrupt-parent = <&intc>; - - aliases { - gpio0 = &gpio0; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - - devbus_bootcs: devbus-bootcs { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs0: devbus-cs0 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs1: devbus-cs1 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - devbus_cs2: devbus-cs2 { - compatible = "marvell,orion-devbus"; - reg = ; - ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <6>, <7>, <8>, <9>; - }; - - spi: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = <0x10600 0x28>; - status = "disabled"; - }; - - i2c: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <5>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <3>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <4>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <4>; - }; - - intc: interrupt-controller@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x08>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - wdt: wdt@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&core_clk 0>; - status = "okay"; - }; - - ehci0: ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <17>; - status = "disabled"; - }; - - xor: dma-controller@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - status = "okay"; - - xor00 { - interrupts = <30>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <31>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - eth: ethernet-controller@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethport: ethernet-port@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <21>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <22>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <29>; - status = "disabled"; - }; - - cesa: crypto@90000 { - compatible = "marvell,orion-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <28>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - ehci1: ehci@a0000 { - compatible = "marvell,orion-ehci"; - reg = <0xa0000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - }; - - crypto_sram: sa-sram { - compatible = "mmio-sram"; - reg = ; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ox810se.dtsi b/software/linux/kernel/arch/arm/boot/dts/ox810se.dtsi deleted file mode 100644 index ce13705c3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ox810se.dtsi +++ /dev/null @@ -1,336 +0,0 @@ -/* - * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC - * - * Copyright (C) 2016 Neil Armstrong - * - * Licensed under GPLv2 or later - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "oxsemi,ox810se"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - clocks = <&armclk>; - }; - }; - - memory { - /* Max 256MB @ 0x48000000 */ - reg = <0x48000000 0x10000000>; - }; - - clocks { - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - gmacclk: gmacclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - rpsclk: rpsclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc>; - }; - - pll400: pll400 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <733333333>; - }; - - sysclk: sysclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll400>; - }; - - armclk: armclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - clocks = <&pll400>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc>; - - apb-bridge@44000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x44000000 0x1000000>; - - pinctrl: pinctrl { - compatible = "oxsemi,ox810se-pinctrl"; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - pinctrl_uart0: uart0 { - uart0a { - pins = "gpio31"; - function = "fct3"; - }; - uart0b { - pins = "gpio32"; - function = "fct3"; - }; - }; - - pinctrl_uart0_modem: uart0_modem { - uart0c { - pins = "gpio27"; - function = "fct3"; - }; - uart0d { - pins = "gpio28"; - function = "fct3"; - }; - uart0e { - pins = "gpio29"; - function = "fct3"; - }; - uart0f { - pins = "gpio30"; - function = "fct3"; - }; - uart0g { - pins = "gpio33"; - function = "fct3"; - }; - uart0h { - pins = "gpio34"; - function = "fct3"; - }; - }; - - pinctrl_uart1: uart1 { - uart1a { - pins = "gpio20"; - function = "fct3"; - }; - uart1b { - pins = "gpio22"; - function = "fct3"; - }; - }; - - pinctrl_uart1_modem: uart1_modem { - uart1c { - pins = "gpio8"; - function = "fct3"; - }; - uart1d { - pins = "gpio9"; - function = "fct3"; - }; - uart1e { - pins = "gpio23"; - function = "fct3"; - }; - uart1f { - pins = "gpio24"; - function = "fct3"; - }; - uart1g { - pins = "gpio25"; - function = "fct3"; - }; - uart1h { - pins = "gpio26"; - function = "fct3"; - }; - }; - - pinctrl_uart2: uart2 { - uart2a { - pins = "gpio6"; - function = "fct3"; - }; - uart2b { - pins = "gpio7"; - function = "fct3"; - }; - }; - - pinctrl_uart2_modem: uart2_modem { - uart2c { - pins = "gpio0"; - function = "fct3"; - }; - uart2d { - pins = "gpio1"; - function = "fct3"; - }; - uart2e { - pins = "gpio2"; - function = "fct3"; - }; - uart2f { - pins = "gpio3"; - function = "fct3"; - }; - uart2g { - pins = "gpio4"; - function = "fct3"; - }; - uart2h { - pins = "gpio5"; - function = "fct3"; - }; - }; - }; - - gpio0: gpio@000000 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x000000 0x100000>; - interrupts = <21>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <32>; - oxsemi,gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - }; - - gpio1: gpio@100000 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x100000 0x100000>; - interrupts = <22>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <3>; - oxsemi,gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 3>; - }; - - uart0: serial@200000 { - compatible = "ns16550a"; - reg = <0x200000 0x100000>; - clocks = <&sysclk>; - interrupts = <23>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset 17>; - }; - - uart1: serial@300000 { - compatible = "ns16550a"; - reg = <0x300000 0x100000>; - clocks = <&sysclk>; - interrupts = <24>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset 18>; - }; - - uart2: serial@900000 { - compatible = "ns16550a"; - reg = <0x900000 0x100000>; - clocks = <&sysclk>; - interrupts = <29>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset 22>; - }; - - uart3: serial@a00000 { - compatible = "ns16550a"; - reg = <0xa00000 0x100000>; - clocks = <&sysclk>; - interrupts = <30>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset 23>; - }; - }; - - apb-bridge@45000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x45000000 0x1000000>; - - sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; - - stdclk: stdclk { - compatible = "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; - }; - - rps@300000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x300000 0x100000>; - - intc: interrupt-controller@0 { - compatible = "oxsemi,ox810se-rps-irq"; - interrupt-controller; - reg = <0 0x200>; - #interrupt-cells = <1>; - valid-mask = <0xFFFFFFFF>; - clear-mask = <0>; - }; - - timer0: timer@200 { - compatible = "oxsemi,ox810se-rps-timer"; - reg = <0x200 0x40>; - clocks = <&rpsclk>; - interrupts = <4 5>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc3x2.dtsi deleted file mode 100644 index 533919e96..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Copyright (C) 2011 Picochip, Jamie Iles - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/include/ "skeleton.dtsi" -/ { - model = "Picochip picoXcell PC3X2"; - compatible = "picochip,pc3x2"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1176jz-s"; - device_type = "cpu"; - clock-frequency = <400000000>; - d-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-line-size = <32>; - i-cache-size = <32768>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pclk: clock@0 { - compatible = "fixed-clock"; - clock-outputs = "bus", "pclk"; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - }; - - paxi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80000000 0x400000>; - - emac: gem@30000 { - compatible = "cadence,gem"; - reg = <0x30000 0x10000>; - interrupts = <31>; - }; - - dmac1: dmac@40000 { - compatible = "snps,dw-dmac"; - reg = <0x40000 0x10000>; - interrupts = <25>; - }; - - dmac2: dmac@50000 { - compatible = "snps,dw-dmac"; - reg = <0x50000 0x10000>; - interrupts = <26>; - }; - - vic0: interrupt-controller@60000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x60000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@64000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x64000 0x1000>; - #interrupt-cells = <1>; - }; - - fuse: picoxcell-fuse@80000 { - compatible = "picoxcell,fuse-pc3x2"; - reg = <0x80000 0x10000>; - }; - - ssi: picoxcell-spi@90000 { - compatible = "picoxcell,spi"; - reg = <0x90000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <10>; - }; - - ipsec: spacc@100000 { - compatible = "picochip,spacc-ipsec"; - reg = <0x100000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - ref-clock = <&pclk>, "ref"; - }; - - srtp: spacc@140000 { - compatible = "picochip,spacc-srtp"; - reg = <0x140000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <23>; - }; - - l2_engine: spacc@180000 { - compatible = "picochip,spacc-l2"; - reg = <0x180000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <22>; - ref-clock = <&pclk>, "ref"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x200000 0x80000>; - - rtc0: rtc@00000 { - compatible = "picochip,pc3x2-rtc"; - clock-freq = <200000000>; - reg = <0x00000 0xf>; - interrupt-parent = <&vic1>; - interrupts = <8>; - }; - - timer0: timer@10000 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <4>; - clock-freq = <200000000>; - reg = <0x10000 0x14>; - }; - - timer1: timer@10014 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-freq = <200000000>; - reg = <0x10014 0x14>; - }; - - timer2: timer@10028 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <6>; - clock-freq = <200000000>; - reg = <0x10028 0x14>; - }; - - timer3: timer@1003c { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <7>; - clock-freq = <200000000>; - reg = <0x1003c 0x14>; - }; - - gpio: gpio@20000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x20000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - reg-io-width = <4>; - - banka: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <8>; - - regoffset-dat = <0x50>; - regoffset-set = <0x00>; - regoffset-dirout = <0x04>; - }; - - bankb: gpio-controller@1 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <8>; - - regoffset-dat = <0x54>; - regoffset-set = <0x0c>; - regoffset-dirout = <0x10>; - }; - }; - - uart0: uart@30000 { - compatible = "snps,dw-apb-uart"; - reg = <0x30000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-frequency = <3686400>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart1: uart@40000 { - compatible = "snps,dw-apb-uart"; - reg = <0x40000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <9>; - clock-frequency = <3686400>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - wdog: watchdog@50000 { - compatible = "snps,dw-apb-wdg"; - reg = <0x50000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <11>; - bus-clock = <&pclk>, "bus"; - }; - }; - }; - - rwid-axi { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - ebi@50000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x08000000 - 1 0 0x48000000 0x08000000 - 2 0 0x50000000 0x08000000 - 3 0 0x58000000 0x08000000>; - }; - - axi2pico@c0000000 { - compatible = "picochip,axi2pico-pc3x2"; - reg = <0xc0000000 0x10000>; - interrupts = <13 14 15 16 17 18 19 20 21>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc3x3.dtsi deleted file mode 100644 index ab3e80085..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ /dev/null @@ -1,365 +0,0 @@ -/* - * Copyright (C) 2011 Picochip, Jamie Iles - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/include/ "skeleton.dtsi" -/ { - model = "Picochip picoXcell PC3X3"; - compatible = "picochip,pc3x3"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm1176jz-s"; - device_type = "cpu"; - cpu-clock = <&arm_clk>, "cpu"; - d-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-line-size = <32>; - i-cache-size = <32768>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clkgate: clkgate@800a0048 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x800a0048 4>; - compatible = "picochip,pc3x3-clk-gate"; - - tzprot_clk: clock@0 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <0>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - spi_clk: clock@1 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <1>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - dmac0_clk: clock@2 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <2>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - dmac1_clk: clock@3 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <3>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - ebi_clk: clock@4 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <4>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - ipsec_clk: clock@5 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <5>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - l2_clk: clock@6 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <6>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - trng_clk: clock@7 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <7>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - fuse_clk: clock@8 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <8>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - - otp_clk: clock@9 { - compatible = "picochip,pc3x3-gated-clk"; - clock-outputs = "bus"; - picochip,clk-disable-bit = <9>; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - }; - - arm_clk: clock@11 { - compatible = "picochip,pc3x3-pll"; - reg = <0x800a0050 0x8>; - picochip,min-freq = <140000000>; - picochip,max-freq = <700000000>; - ref-clock = <&ref_clk>, "ref"; - clock-outputs = "cpu"; - }; - - pclk: clock@12 { - compatible = "fixed-clock"; - clock-outputs = "bus", "pclk"; - clock-frequency = <200000000>; - ref-clock = <&ref_clk>, "ref"; - }; - }; - - paxi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80000000 0x400000>; - - emac: gem@30000 { - compatible = "cadence,gem"; - reg = <0x30000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <31>; - }; - - dmac1: dmac@40000 { - compatible = "snps,dw-dmac"; - reg = <0x40000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <25>; - }; - - dmac2: dmac@50000 { - compatible = "snps,dw-dmac"; - reg = <0x50000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - }; - - vic0: interrupt-controller@60000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x60000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@64000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x64000 0x1000>; - #interrupt-cells = <1>; - }; - - fuse: picoxcell-fuse@80000 { - compatible = "picoxcell,fuse-pc3x3"; - reg = <0x80000 0x10000>; - }; - - ssi: picoxcell-spi@90000 { - compatible = "picoxcell,spi"; - reg = <0x90000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <10>; - }; - - ipsec: spacc@100000 { - compatible = "picochip,spacc-ipsec"; - reg = <0x100000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - ref-clock = <&ipsec_clk>, "ref"; - }; - - srtp: spacc@140000 { - compatible = "picochip,spacc-srtp"; - reg = <0x140000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <23>; - }; - - l2_engine: spacc@180000 { - compatible = "picochip,spacc-l2"; - reg = <0x180000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <22>; - ref-clock = <&l2_clk>, "ref"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x200000 0x80000>; - - rtc0: rtc@00000 { - compatible = "picochip,pc3x2-rtc"; - clock-freq = <200000000>; - reg = <0x00000 0xf>; - interrupt-parent = <&vic0>; - interrupts = <8>; - }; - - timer0: timer@10000 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <4>; - clock-freq = <200000000>; - reg = <0x10000 0x14>; - }; - - timer1: timer@10014 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-freq = <200000000>; - reg = <0x10014 0x14>; - }; - - gpio: gpio@20000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x20000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - reg-io-width = <4>; - - banka: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <8>; - - regoffset-dat = <0x50>; - regoffset-set = <0x00>; - regoffset-dirout = <0x04>; - }; - - bankb: gpio-controller@1 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <16>; - - regoffset-dat = <0x54>; - regoffset-set = <0x0c>; - regoffset-dirout = <0x10>; - }; - - bankd: gpio-controller@2 { - compatible = "snps,dw-apb-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - gpio-generic,nr-gpio = <30>; - - regoffset-dat = <0x5c>; - regoffset-set = <0x24>; - regoffset-dirout = <0x28>; - }; - }; - - uart0: uart@30000 { - compatible = "snps,dw-apb-uart"; - reg = <0x30000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-frequency = <3686400>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart1: uart@40000 { - compatible = "snps,dw-apb-uart"; - reg = <0x40000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <9>; - clock-frequency = <3686400>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - wdog: watchdog@50000 { - compatible = "snps,dw-apb-wdg"; - reg = <0x50000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <11>; - bus-clock = <&pclk>, "bus"; - }; - - timer2: timer@60000 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <6>; - clock-freq = <200000000>; - reg = <0x60000 0x14>; - }; - - timer3: timer@60014 { - compatible = "picochip,pc3x2-timer"; - interrupt-parent = <&vic0>; - interrupts = <7>; - clock-freq = <200000000>; - reg = <0x60014 0x14>; - }; - }; - }; - - rwid-axi { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - ebi@50000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x08000000 - 1 0 0x48000000 0x08000000 - 2 0 0x50000000 0x08000000 - 3 0 0x58000000 0x08000000>; - }; - - axi2pico@c0000000 { - compatible = "picochip,axi2pico-pc3x3"; - reg = <0xc0000000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <13 14 15 16 17 18 19 20 21>; - }; - - otp@ffff8000 { - compatible = "picochip,otp-pc3x3"; - reg = <0xffff8000 0x8000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts b/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts deleted file mode 100644 index 1297414dd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2011 Picochip, Jamie Iles - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -/include/ "picoxcell-pc3x2.dtsi" -/ { - model = "Picochip PC7302 (PC3X2)"; - compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2"; - - memory { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; - - chosen { - linux,stdout-path = &uart0; - }; - - clocks { - ref_clk: clock@1 { - compatible = "fixed-clock"; - clock-outputs = "ref"; - clock-frequency = <20000000>; - }; - }; - - rwid-axi { - ebi@50000000 { - nand: gpio-nand@2,0 { - compatible = "gpio-control-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2 0x0000 0x1000>; - bus-clock = <&pclk>, "bus"; - gpio-control-nand,io-sync-reg = - <0x00000000 0x80220000>; - - gpios = <&banka 1 0 /* rdy */ - &banka 2 0 /* nce */ - &banka 3 0 /* ale */ - &banka 4 0 /* cle */ - 0 /* nwp */>; - - boot@100000 { - label = "Boot"; - reg = <0x100000 0x80000>; - }; - - redundant-boot@200000 { - label = "Redundant Boot"; - reg = <0x200000 0x80000>; - }; - - boot-env@300000 { - label = "Boot Evironment"; - reg = <0x300000 0x20000>; - }; - - redundant-boot-env@320000 { - label = "Redundant Boot Environment"; - reg = <0x300000 0x20000>; - }; - - kernel@380000 { - label = "Kernel"; - reg = <0x380000 0x800000>; - }; - - fs@b80000 { - label = "File System"; - reg = <0xb80000 0xf480000>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts b/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts deleted file mode 100644 index 9e317a4f4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2011 Picochip, Jamie Iles - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -/include/ "picoxcell-pc3x3.dtsi" -/ { - model = "Picochip PC7302 (PC3X3)"; - compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3"; - - memory { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; - - chosen { - linux,stdout-path = &uart0; - }; - - clocks { - ref_clk: clock@10 { - compatible = "fixed-clock"; - clock-outputs = "ref"; - clock-frequency = <20000000>; - }; - - clkgate: clkgate@800a0048 { - clock@4 { - picochip,clk-no-disable; - }; - }; - }; - - rwid-axi { - ebi@50000000 { - nand: gpio-nand@2,0 { - compatible = "gpio-control-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2 0x0000 0x1000>; - bus-clock = <&ebi_clk>, "bus"; - gpio-control-nand,io-sync-reg = - <0x00000000 0x80220000>; - - gpios = <&banka 1 0 /* rdy */ - &banka 2 0 /* nce */ - &banka 3 0 /* ale */ - &banka 4 0 /* cle */ - 0 /* nwp */>; - - boot@100000 { - label = "Boot"; - reg = <0x100000 0x80000>; - }; - - redundant-boot@200000 { - label = "Redundant Boot"; - reg = <0x200000 0x80000>; - }; - - boot-env@300000 { - label = "Boot Evironment"; - reg = <0x300000 0x20000>; - }; - - redundant-boot-env@320000 { - label = "Redundant Boot Environment"; - reg = <0x300000 0x20000>; - }; - - kernel@380000 { - label = "Kernel"; - reg = <0x380000 0x800000>; - }; - - fs@b80000 { - label = "File System"; - reg = <0xb80000 0xf480000>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/pm9g45.dts b/software/linux/kernel/arch/arm/boot/dts/pm9g45.dts deleted file mode 100644 index 0abd7bf17..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/pm9g45.dts +++ /dev/null @@ -1,164 +0,0 @@ -/* - * pm9g45.dts - Device Tree file for Ronetix pm9g45 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9g45.dtsi" - -/ { - model = "Ronetix pm9g45"; - compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - reg = <0x70000000 0x8000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - pinctrl@fffff200 { - - board { - pinctrl_board_nand: nand0-board { - atmel,pins = - ; /* PC14 gpio enable pin pull_up */ - }; - }; - - mmc { - pinctrl_board_mmc: mmc0-board { - atmel,pins = - ; /* PD6 gpio CD pin pull_up and deglitch */ - }; - }; - }; - - mmc0: mmc@fff80000 { - pinctrl-0 = < - &pinctrl_board_mmc - &pinctrl_mmc0_slot0_clk_cmd_dat0 - &pinctrl_mmc0_slot0_dat1_3>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>; - }; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - pinctrl-0 = <&pinctrl_board_nand>; - - gpios = <&pioD 3 GPIO_ACTIVE_HIGH - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x1A0000>; - }; - - kernel@200000 { - label = "bareboxenv2"; - reg = <0x200000 0x300000>; - }; - - kernel@500000 { - label = "root"; - reg = <0x500000 0x400000>; - }; - - data@900000 { - label = "data"; - reg = <0x900000 0x8340000>; - }; - }; - - usb0: ohci@00700000 { - status = "okay"; - num-ports = <2>; - }; - - usb1: ehci@00800000 { - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "led0"; - gpios = <&pioD 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "nand-disk"; - }; - - led1 { - label = "led1"; - gpios = <&pioD 31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - right { - label = "SW4"; - gpios = <&pioE 7 GPIO_ACTIVE_LOW>; - linux,code = <106>; - }; - - up { - label = "SW3"; - gpios = <&pioE 8 GPIO_ACTIVE_LOW>; - linux,code = <103>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/prima2-evb.dts b/software/linux/kernel/arch/arm/boot/dts/prima2-evb.dts deleted file mode 100644 index 57286b4e7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/prima2-evb.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * DTS file for CSR SiRFprimaII Evaluation Board - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; - -/include/ "prima2.dtsi" - -/ { - model = "CSR SiRFprimaII Evaluation Board"; - compatible = "sirf,prima2", "sirf,prima2-cb"; - - memory { - reg = <0x00000000 0x20000000>; - }; - - axi { - peri-iobg { - uart@b0060000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - }; - spi@b00d0000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - }; - spi@b0170000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/prima2.dtsi b/software/linux/kernel/arch/arm/boot/dts/prima2.dtsi deleted file mode 100644 index 1ca1a9aa9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/prima2.dtsi +++ /dev/null @@ -1,840 +0,0 @@ -/* - * DTS file for CSR SiRFprimaII SoC - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -/include/ "skeleton.dtsi" -/ { - compatible = "sirf,prima2"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - clocks = <&clks 12>; - operating-points = < - /* kHz uV */ - 200000 1025000 - 400000 1025000 - 664000 1050000 - 800000 1100000 - >; - clock-latency = <150000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <29>; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - l2-cache-controller@80040000 { - compatible = "arm,pl310-cache"; - reg = <0x80040000 0x1000>; - interrupts = <59>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - arm,filter-ranges = <0 0x40000000>; - }; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clks: clock-controller@88000000 { - compatible = "sirf,prima2-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - #clock-cells = <1>; - }; - - rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - - cphifbg@88030000 { - compatible = "sirf,prima2-cphifbg"; - reg = <0x88030000 0x1000>; - clocks = <&clks 42>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x2000>; - interrupts = <27>; - clocks = <&clks 5>; - }; - - memc-monitor { - compatible = "sirf,prima2-memcmon"; - reg = <0x90002000 0x200>; - interrupts = <4>; - clocks = <&clks 32>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - display@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx531"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - clocks = <&clks 32>; - }; - }; - - multimedia-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - multimedia@a0000000 { - compatible = "sirf,prima2-video-codec"; - reg = <0xa0000000 0x8000000>; - interrupts = <5>; - clocks = <&clks 33>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - resets = <&rstc 1>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - clocks = <&clks 9>; - resets = <&rstc 2>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - clocks = <&clks 8>; - resets = <&rstc 0>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>, - <0x56000000 0x56000000 0x1b00000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - clocks = <&clks 11>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - clocks = <&clks 26>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - clocks = <&clks 27>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x1000>; - interrupts = <17>; - fifosize = <128>; - clocks = <&clks 13>; - dmas = <&dmac1 5>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x1000>; - interrupts = <18>; - fifosize = <32>; - clocks = <&clks 14>; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x1000>; - interrupts = <19>; - fifosize = <128>; - clocks = <&clks 15>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - fifosize = <128>; - clocks = <&clks 28>; - dmas = <&dmac1 1>, <&dmac1 2>; - dma-names = "rx", "tx"; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - fifosize = <128>; - clocks = <&clks 29>; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "rx", "tx"; - }; - - usp2: usp@b00a0000 { - cell-index = <2>; - compatible = "sirf,prima2-usp"; - reg = <0xb00a0000 0x10000>; - interrupts = <22>; - fifosize = <128>; - clocks = <&clks 30>; - dmas = <&dmac0 10>, <&dmac0 11>; - dma-names = "rx", "tx"; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - clocks = <&clks 24>; - #dma-cells = <1>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - clocks = <&clks 25>; - #dma-cells = <1>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - clocks = <&clks 31>; - interrupts = <14>; - sirf,vip-dma-rx-channel = <16>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 19>; - status = "disabled"; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac0 12>, - <&dmac0 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 20>; - status = "disabled"; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - clocks = <&clks 17>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - clocks = <&clks 18>; - #address-cells = <1>; - #size-cells = <0>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - clocks = <&clks 16>; - }; - - gpio: pinctrl@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,prima2-pinctrl"; - reg = <0xb0120000 0x10000>; - interrupts = <43 44 45 46 47>; - gpio-controller; - interrupt-controller; - - lcd_16pins_a: lcd0@0 { - lcd { - sirf,pins = "lcd_16bitsgrp"; - sirf,function = "lcd_16bits"; - }; - }; - lcd_18pins_a: lcd0@1 { - lcd { - sirf,pins = "lcd_18bitsgrp"; - sirf,function = "lcd_18bits"; - }; - }; - lcd_24pins_a: lcd0@2 { - lcd { - sirf,pins = "lcd_24bitsgrp"; - sirf,function = "lcd_24bits"; - }; - }; - lcdrom_pins_a: lcdrom0@0 { - lcd { - sirf,pins = "lcdromgrp"; - sirf,function = "lcdrom"; - }; - }; - uart0_pins_a: uart0@0 { - uart { - sirf,pins = "uart0grp"; - sirf,function = "uart0"; - }; - }; - uart0_noflow_pins_a: uart0@1 { - uart { - sirf,pins = "uart0_nostreamctrlgrp"; - sirf,function = "uart0_nostreamctrl"; - }; - }; - uart1_pins_a: uart1@0 { - uart { - sirf,pins = "uart1grp"; - sirf,function = "uart1"; - }; - }; - uart2_pins_a: uart2@0 { - uart { - sirf,pins = "uart2grp"; - sirf,function = "uart2"; - }; - }; - uart2_noflow_pins_a: uart2@1 { - uart { - sirf,pins = "uart2_nostreamctrlgrp"; - sirf,function = "uart2_nostreamctrl"; - }; - }; - spi0_pins_a: spi0@0 { - spi { - sirf,pins = "spi0grp"; - sirf,function = "spi0"; - }; - }; - spi1_pins_a: spi1@0 { - spi { - sirf,pins = "spi1grp"; - sirf,function = "spi1"; - }; - }; - i2c0_pins_a: i2c0@0 { - i2c { - sirf,pins = "i2c0grp"; - sirf,function = "i2c0"; - }; - }; - i2c1_pins_a: i2c1@0 { - i2c { - sirf,pins = "i2c1grp"; - sirf,function = "i2c1"; - }; - }; - pwm0_pins_a: pwm0@0 { - pwm { - sirf,pins = "pwm0grp"; - sirf,function = "pwm0"; - }; - }; - pwm1_pins_a: pwm1@0 { - pwm { - sirf,pins = "pwm1grp"; - sirf,function = "pwm1"; - }; - }; - pwm2_pins_a: pwm2@0 { - pwm { - sirf,pins = "pwm2grp"; - sirf,function = "pwm2"; - }; - }; - pwm3_pins_a: pwm3@0 { - pwm { - sirf,pins = "pwm3grp"; - sirf,function = "pwm3"; - }; - }; - gps_pins_a: gps@0 { - gps { - sirf,pins = "gpsgrp"; - sirf,function = "gps"; - }; - }; - vip_pins_a: vip@0 { - vip { - sirf,pins = "vipgrp"; - sirf,function = "vip"; - }; - }; - sdmmc0_pins_a: sdmmc0@0 { - sdmmc0 { - sirf,pins = "sdmmc0grp"; - sirf,function = "sdmmc0"; - }; - }; - sdmmc1_pins_a: sdmmc1@0 { - sdmmc1 { - sirf,pins = "sdmmc1grp"; - sirf,function = "sdmmc1"; - }; - }; - sdmmc2_pins_a: sdmmc2@0 { - sdmmc2 { - sirf,pins = "sdmmc2grp"; - sirf,function = "sdmmc2"; - }; - }; - sdmmc3_pins_a: sdmmc3@0 { - sdmmc3 { - sirf,pins = "sdmmc3grp"; - sirf,function = "sdmmc3"; - }; - }; - sdmmc4_pins_a: sdmmc4@0 { - sdmmc4 { - sirf,pins = "sdmmc4grp"; - sirf,function = "sdmmc4"; - }; - }; - sdmmc5_pins_a: sdmmc5@0 { - sdmmc5 { - sirf,pins = "sdmmc5grp"; - sirf,function = "sdmmc5"; - }; - }; - i2s_mclk_pins_a: i2s_mclk@0 { - i2s_mclk { - sirf,pins = "i2smclkgrp"; - sirf,function = "i2s_mclk"; - }; - }; - i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { - i2s_ext_clk_input { - sirf,pins = "i2s_ext_clk_inputgrp"; - sirf,function = "i2s_ext_clk_input"; - }; - }; - i2s_pins_a: i2s@0 { - i2s { - sirf,pins = "i2sgrp"; - sirf,function = "i2s"; - }; - }; - i2s_no_din_pins_a: i2s_no_din@0 { - i2s_no_din { - sirf,pins = "i2s_no_dingrp"; - sirf,function = "i2s_no_din"; - }; - }; - i2s_6chn_pins_a: i2s_6chn@0 { - i2s_6chn { - sirf,pins = "i2s_6chngrp"; - sirf,function = "i2s_6chn"; - }; - }; - ac97_pins_a: ac97@0 { - ac97 { - sirf,pins = "ac97grp"; - sirf,function = "ac97"; - }; - }; - nand_pins_a: nand@0 { - nand { - sirf,pins = "nandgrp"; - sirf,function = "nand"; - }; - }; - usp0_pins_a: usp0@0 { - usp0 { - sirf,pins = "usp0grp"; - sirf,function = "usp0"; - }; - }; - usp0_uart_nostreamctrl_pins_a: usp0@1 { - usp0 { - sirf,pins = - "usp0_uart_nostreamctrl_grp"; - sirf,function = - "usp0_uart_nostreamctrl"; - }; - }; - usp0_only_utfs_pins_a: usp0@2 { - usp0 { - sirf,pins = "usp0_only_utfs_grp"; - sirf,function = "usp0_only_utfs"; - }; - }; - usp0_only_urfs_pins_a: usp0@3 { - usp0 { - sirf,pins = "usp0_only_urfs_grp"; - sirf,function = "usp0_only_urfs"; - }; - }; - usp1_pins_a: usp1@0 { - usp1 { - sirf,pins = "usp1grp"; - sirf,function = "usp1"; - }; - }; - usp1_uart_nostreamctrl_pins_a: usp1@1 { - usp1 { - sirf,pins = - "usp1_uart_nostreamctrl_grp"; - sirf,function = - "usp1_uart_nostreamctrl"; - }; - }; - usp2_pins_a: usp2@0 { - usp2 { - sirf,pins = "usp2grp"; - sirf,function = "usp2"; - }; - }; - usp2_uart_nostreamctrl_pins_a: usp2@1 { - usp2 { - sirf,pins = - "usp2_uart_nostreamctrl_grp"; - sirf,function = - "usp2_uart_nostreamctrl"; - }; - }; - usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { - usb0_utmi_drvbus { - sirf,pins = "usb0_utmi_drvbusgrp"; - sirf,function = "usb0_utmi_drvbus"; - }; - }; - usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { - usb1_utmi_drvbus { - sirf,pins = "usb1_utmi_drvbusgrp"; - sirf,function = "usb1_utmi_drvbus"; - }; - }; - usb1_dp_dn_pins_a: usb1_dp_dn@0 { - usb1_dp_dn { - sirf,pins = "usb1_dp_dngrp"; - sirf,function = "usb1_dp_dn"; - }; - }; - uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { - uart1_route_io_usb1 { - sirf,pins = "uart1_route_io_usb1grp"; - sirf,function = "uart1_route_io_usb1"; - }; - }; - warm_rst_pins_a: warm_rst@0 { - warm_rst { - sirf,pins = "warm_rstgrp"; - sirf,function = "warm_rst"; - }; - }; - pulse_count_pins_a: pulse_count@0 { - pulse_count { - sirf,pins = "pulse_countgrp"; - sirf,function = "pulse_count"; - }; - }; - cko0_pins_a: cko0@0 { - cko0 { - sirf,pins = "cko0grp"; - sirf,function = "cko0"; - }; - }; - cko1_pins_a: cko1@0 { - cko1 { - sirf,pins = "cko1grp"; - sirf,function = "cko1"; - }; - }; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - clocks = <&clks 21>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - clocks = <&clks 22>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - clocks = <&clks 23>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <8>; - clocks = <&clks 36>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 36>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - status = "disabled"; - clocks = <&clks 37>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - status = "disabled"; - clocks = <&clks 37>; - }; - - sd4: sdhci@56400000 { - cell-index = <4>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56400000 0x100000>; - interrupts = <39>; - status = "disabled"; - clocks = <&clks 38>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - clocks = <&clks 38>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - minigpsrtc@2000 { - compatible = "sirf,prima2-minigpsrtc"; - reg = <0x2000 0x1000>; - interrupts = <54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - clocks = <&clks 40>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - clocks = <&clks 41>; - }; - - sata@b00f0000 { - compatible = "synopsys,dwc-ahsata"; - reg = <0xb8020000 0x10000>; - interrupts = <37>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - clocks = <&clks 7>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/pxa168-aspenite.dts b/software/linux/kernel/arch/arm/boot/dts/pxa168-aspenite.dts deleted file mode 100644 index 0a988b3fb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/pxa168-aspenite.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; -#include "pxa168.dtsi" - -/ { - model = "Marvell PXA168 Aspenite Development Board"; - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x04000000>; - }; - - soc { - apb@d4000000 { - uart1: uart@d4017000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/pxa168.dtsi b/software/linux/kernel/arch/arm/boot/dts/pxa168.dtsi deleted file mode 100644 index b899e25cb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/pxa168.dtsi +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks PXA168_CLK_UART0>; - resets = <&soc_clocks PXA168_CLK_UART0>; - status = "disabled"; - }; - - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks PXA168_CLK_UART1>; - resets = <&soc_clocks PXA168_CLK_UART1>; - status = "disabled"; - }; - - uart3: uart@d4026000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4026000 0x1000>; - interrupts = <29>; - clocks = <&soc_clocks PXA168_CLK_UART2>; - resets = <&soc_clocks PXA168_CLK_UART2>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - clocks = <&soc_clocks PXA168_CLK_GPIO>; - resets = <&soc_clocks PXA168_CLK_GPIO>; - interrupt-names = "gpio_mux"; - interrupt-controller; - #interrupt-cells = <1>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks PXA168_CLK_TWSI0>; - resets = <&soc_clocks PXA168_CLK_TWSI0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4025000 0x1000>; - interrupts = <58>; - clocks = <&soc_clocks PXA168_CLK_TWSI1>; - resets = <&soc_clocks PXA168_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5 6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - clocks = <&soc_clocks PXA168_CLK_RTC>; - resets = <&soc_clocks PXA168_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,pxa168-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/pxa27x.dtsi b/software/linux/kernel/arch/arm/boot/dts/pxa27x.dtsi deleted file mode 100644 index 9e73dc6b3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/pxa27x.dtsi +++ /dev/null @@ -1,140 +0,0 @@ -/* The pxa3xx skeleton simply augments the 2xx version */ -#include "pxa2xx.dtsi" -#include "dt-bindings/clock/pxa-clock.h" - -/ { - model = "Marvell PXA27x familiy SoC"; - compatible = "marvell,pxa27x"; - - pxabus { - pdma: dma-controller@40000000 { - compatible = "marvell,pdma-1.0"; - reg = <0x40000000 0x10000>; - interrupts = <25>; - #dma-channels = <32>; - #dma-cells = <2>; - #dma-requests = <75>; - status = "okay"; - }; - - pxairq: interrupt-controller@40d00000 { - marvell,intc-priority; - marvell,intc-nr-irqs = <34>; - }; - - pinctrl: pinctrl@40e00000 { - reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 - 0x40f00020 0x10>; - compatible = "marvell,pxa27x-pinctrl"; - }; - - gpio: gpio@40e00000 { - compatible = "intel,pxa27x-gpio"; - gpio-ranges = <&pinctrl 0 0 128>; - clocks = <&clks CLK_NONE>; - }; - - pxa27x_ohci: usb@4c000000 { - compatible = "marvell,pxa-ohci"; - reg = <0x4c000000 0x10000>; - interrupts = <3>; - clocks = <&clks CLK_USBHOST>; - status = "disabled"; - }; - - pwm0: pwm@40b00000 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - }; - - pwm1: pwm@40b00010 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40b00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - }; - - pwm2: pwm@40c00000 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40c00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - }; - - pwm3: pwm@40c00010 { - compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; - reg = <0x40c00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - }; - - pwri2c: i2c@40f000180 { - compatible = "mrvl,pxa-i2c"; - reg = <0x40f00180 0x24>; - interrupts = <6>; - clocks = <&clks CLK_PWRI2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - pxa27x_udc: udc@40600000 { - compatible = "marvell,pxa270-udc"; - reg = <0x40600000 0x10000>; - interrupts = <11>; - clocks = <&clks CLK_USB>; - status = "disabled"; - }; - - keypad: keypad@41500000 { - compatible = "marvell,pxa27x-keypad"; - reg = <0x41500000 0x4c>; - interrupts = <4>; - clocks = <&clks CLK_KEYPAD>; - status = "disabled"; - }; - - pxa_camera: imaging@50000000 { - compatible = "marvell,pxa270-qci"; - reg = <0x50000000 0x1000>; - interrupts = <33>; - dmas = <&pdma 68 0 /* Y channel */ - &pdma 69 0 /* U channel */ - &pdma 70 0>; /* V channel */ - dma-names = "CI_Y", "CI_U", "CI_V"; - - clocks = <&clks CLK_CAMERA>; - clock-names = "ciclk"; - clock-frequency = <5000000>; - clock-output-names = "qci_mclk"; - - status = "disabled"; - }; - }; - - clocks { - /* - * The muxing of external clocks/internal dividers for osc* clock - * sources has been hidden under the carpet by now. - */ - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clks: pxa2xx_clks@41300004 { - compatible = "marvell,pxa270-clocks"; - #clock-cells = <1>; - status = "okay"; - }; - }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clks CLK_OSTIMER>; - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/pxa2xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/pxa2xx.dtsi deleted file mode 100644 index 3ff077ca4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/pxa2xx.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -/* - * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC - * - * Copyright (C) 2011 Marek Vasut - * - * Licensed under GPLv2 or later. - */ - -#include "skeleton.dtsi" -#include "dt-bindings/clock/pxa-clock.h" - -/ { - model = "Marvell PXA2xx family SoC"; - compatible = "marvell,pxa2xx"; - interrupt-parent = <&pxairq>; - - aliases { - serial0 = &ffuart; - serial1 = &btuart; - serial2 = &stuart; - serial3 = &hwuart; - i2c0 = &pwri2c; - i2c1 = &pxai2c1; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - cpu { - compatible = "marvell,xscale"; - device_type = "cpu"; - }; - }; - - pxabus { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pxairq: interrupt-controller@40d00000 { - #interrupt-cells = <1>; - compatible = "marvell,pxa-intc"; - interrupt-controller; - interrupt-parent; - marvell,intc-nr-irqs = <32>; - reg = <0x40d00000 0xd0>; - }; - - gpio: gpio@40e00000 { - compatible = "mrvl,pxa-gpio"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x40e00000 0x10000>; - gpio-controller; - #gpio-cells = <0x2>; - interrupts = <10>; - interrupt-names = "gpio_mux"; - interrupt-controller; - #interrupt-cells = <0x2>; - ranges; - - gcb0: gpio@40e00000 { - reg = <0x40e00000 0x4>; - }; - - gcb1: gpio@40e00004 { - reg = <0x40e00004 0x4>; - }; - - gcb2: gpio@40e00008 { - reg = <0x40e00008 0x4>; - }; - gcb3: gpio@40e0000c { - reg = <0x40e0000c 0x4>; - }; - }; - - ffuart: uart@40100000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40100000 0x30>; - interrupts = <22>; - clocks = <&clks CLK_FFUART>; - status = "disabled"; - }; - - btuart: uart@40200000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40200000 0x30>; - interrupts = <21>; - clocks = <&clks CLK_BTUART>; - status = "disabled"; - }; - - stuart: uart@40700000 { - compatible = "mrvl,pxa-uart"; - reg = <0x40700000 0x30>; - interrupts = <20>; - clocks = <&clks CLK_STUART>; - status = "disabled"; - }; - - hwuart: uart@41100000 { - compatible = "mrvl,pxa-uart"; - reg = <0x41100000 0x30>; - interrupts = <7>; - status = "disabled"; - }; - - pxai2c1: i2c@40301680 { - compatible = "mrvl,pxa-i2c"; - reg = <0x40301680 0x30>; - interrupts = <18>; - clocks = <&clks CLK_I2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb0: ohci@4c000000 { - compatible = "marvell,pxa-ohci"; - reg = <0x4c000000 0x10000>; - interrupts = <3>; - status = "disabled"; - }; - - mmc0: mmc@41100000 { - compatible = "marvell,pxa-mmc"; - reg = <0x41100000 0x1000>; - interrupts = <23>; - clocks = <&clks CLK_MMC>; - dmas = <&pdma 21 3 - &pdma 22 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@40900000 { - compatible = "marvell,pxa-rtc"; - reg = <0x40900000 0x3c>; - interrupts = <30 31>; - }; - - lcd-controller@40500000 { - compatible = "marvell,pxa2xx-lcdc"; - reg = <0x44000000 0x10000>; - interrupts = <17>; - clocks = <&clks CLK_LCD>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/pxa3xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/pxa3xx.dtsi deleted file mode 100644 index 9d6f3aace..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/pxa3xx.dtsi +++ /dev/null @@ -1,254 +0,0 @@ -/* The pxa3xx skeleton simply augments the 2xx version */ -#include "pxa2xx.dtsi" - -#define MFP_PIN_PXA300(gpio) \ - ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ - (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ - (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - 0) - -#define MFP_PIN_PXA310(gpio) \ - ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ - (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ - (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - (gpio <= 262) ? 0 : \ - (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ - 0) - -#define MFP_PIN_PXA320(gpio) \ - ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ - (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ - (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ - (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ - (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ - (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ - (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ - (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ - (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ - 0) - -/* - * MFP Alternate functions for pins having a gpio. - * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > - */ -#define MFP_AF0 (0 << 0) -#define MFP_AF1 (1 << 0) -#define MFP_AF2 (2 << 0) -#define MFP_AF3 (3 << 0) -#define MFP_AF4 (4 << 0) -#define MFP_AF5 (5 << 0) -#define MFP_AF6 (6 << 0) - -/* - * MFP drive strength functions for pins. - * Example of use: pinctrl-single,drive-strength = MFP_DS03X; - */ -#define MFP_DSMSK (0x7 << 10) -#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > -#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > -#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > -#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > -#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > -#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > -#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > -#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > - -/* - * MFP low power mode for pins. - * Example of use: - * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); - * - * Table that determines the low power modes outputs, with actual settings - * used in parentheses for don't-care values. Except for the float output, - * the configured driven and pulled levels match, so if there is a need for - * non-LPM pulled output, the same configuration could probably be used. - * - * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel - * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) - * - * Input 0 X(0) X(0) X(0) 0 - * Drive 0 0 0 0 X(1) 0 - * Drive 1 0 1 X(1) 0 0 - * Pull hi (1) 1 X(1) 1 0 0 - * Pull lo (0) 1 X(0) 0 1 0 - * Z (float) 1 X(0) 0 0 0 - */ -#define MFP_LPM(x) < (x) MFP_LPM_MSK > - -#define MFP_LPM_MSK 0xe1f0 -#define MFP_LPM_INPUT 0x0000 -#define MFP_LPM_DRIVE_LOW 0x2000 -#define MFP_LPM_DRIVE_HIGH 0x4100 -#define MFP_LPM_PULL_LOW 0x2080 -#define MFP_LPM_PULL_HIGH 0x4180 -#define MFP_LPM_FLOAT 0x0080 - -#define MFP_LPM_EDGE_NONE 0x0000 -#define MFP_LPM_EDGE_RISE 0x0010 -#define MFP_LPM_EDGE_FALL 0x0020 -#define MFP_LPM_EDGE_BOTH 0x0030 - -/ { - model = "Marvell PXA3xx familiy SoC"; - compatible = "marvell,pxa3xx"; - - pxabus { - pdma: dma-controller@40000000 { - compatible = "marvell,pdma-1.0"; - reg = <0x40000000 0x10000>; - interrupts = <25>; - #dma-channels = <32>; - #dma-cells = <2>; - #dma-requests = <100>; - status = "okay"; - }; - - pwri2c: i2c@40f500c0 { - compatible = "mrvl,pwri2c"; - reg = <0x40f500c0 0x30>; - interrupts = <6>; - clocks = <&clks CLK_PWRI2C>; - #address-cells = <0x1>; - #size-cells = <0>; - status = "disabled"; - }; - - nand0: nand@43100000 { - compatible = "marvell,pxa3xx-nand"; - reg = <0x43100000 90>; - interrupts = <45>; - clocks = <&clks CLK_NAND>; - dmas = <&pdma 97 3>; - dma-names = "data"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - pxairq: interrupt-controller@40d00000 { - marvell,intc-priority; - marvell,intc-nr-irqs = <56>; - }; - - pinctrl: pinctrl@40e10000 { - compatible = "pinconf-single"; - reg = <0x40e10000 0xffff>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7>; - }; - - gpio: gpio@40e00000 { - compatible = "intel,pxa3xx-gpio"; - reg = <0x40e00000 0x10000>; - clocks = <&clks CLK_GPIO>; - interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupts = <8 9 10>; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - mmc0: mmc@41100000 { - compatible = "marvell,pxa-mmc"; - reg = <0x41100000 0x1000>; - interrupts = <23>; - clocks = <&clks CLK_MMC>; - dmas = <&pdma 21 3 - &pdma 22 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mmc1: mmc@42000000 { - compatible = "marvell,pxa-mmc"; - reg = <0x42000000 0x1000>; - interrupts = <41>; - clocks = <&clks CLK_MMC1>; - dmas = <&pdma 93 3 - &pdma 94 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mmc2: mmc@42500000 { - compatible = "marvell,pxa-mmc"; - reg = <0x42500000 0x1000>; - interrupts = <55>; - clocks = <&clks CLK_MMC2>; - dmas = <&pdma 46 3 - &pdma 47 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pxa3xx_ohci: usb@4c000000 { - compatible = "marvell,pxa-ohci"; - reg = <0x4c000000 0x10000>; - interrupts = <3>; - clocks = <&clks CLK_USBH>; - status = "disabled"; - }; - - pwm0: pwm@40b00000 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - status = "disabled"; - }; - - pwm1: pwm@40b00010 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40b00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - status = "disabled"; - }; - - pwm2: pwm@40c00000 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40c00000 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM0>; - status = "disabled"; - }; - - pwm3: pwm@40c00010 { - compatible = "marvell,pxa270-pwm"; - reg = <0x40c00010 0x10>; - #pwm-cells = <1>; - clocks = <&clks CLK_PWM1>; - status = "disabled"; - }; - }; - - clocks { - /* - * The muxing of external clocks/internal dividers for osc* clock - * sources has been hidden under the carpet by now. - */ - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clks: pxa3xx_clks@41300004 { - compatible = "marvell,pxa300-clocks"; - #clock-cells = <1>; - status = "okay"; - }; - }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clks CLK_OSTIMER>; - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/pxa910-dkb.dts b/software/linux/kernel/arch/arm/boot/dts/pxa910-dkb.dts deleted file mode 100644 index c82f2810e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/pxa910-dkb.dts +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; -#include "pxa910.dtsi" - -/ { - model = "Marvell PXA910 DKB Development Board"; - compatible = "mrvl,pxa910-dkb", "mrvl,pxa910"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x10000000>; - }; - - soc { - apb@d4000000 { - uart1: uart@d4017000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - - pmic: 88pm860x@34 { - compatible = "marvell,88pm860x"; - reg = <0x34>; - interrupts = <4>; - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <1>; - - marvell,88pm860x-irq-read-clr; - marvell,88pm860x-slave-addr = <0x11>; - - regulators { - BUCK1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - rtc { - marvell,88pm860x-vrtc = <1>; - }; - touch { - marvell,88pm860x-gpadc-prebias = <1>; - marvell,88pm860x-gpadc-slot-cycle = <1>; - marvell,88pm860x-tsi-prebias = <6>; - marvell,88pm860x-pen-prebias = <16>; - marvell,88pm860x-pen-prechg = <2>; - marvell,88pm860x-resistor-X = <300>; - }; - backlights { - backlight-0 { - marvell,88pm860x-iset = <4>; - marvell,88pm860x-pwm = <3>; - }; - backlight-2 { - }; - }; - leds { - led0-red { - marvell,88pm860x-iset = <12>; - }; - led0-green { - marvell,88pm860x-iset = <12>; - }; - led0-blue { - marvell,88pm860x-iset = <12>; - }; - }; - }; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/pxa910.dtsi b/software/linux/kernel/arch/arm/boot/dts/pxa910.dtsi deleted file mode 100644 index 0868f6729..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/pxa910.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - timer1: timer@d4016000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4016000 0x100>; - interrupts = <29>; - status = "disabled"; - }; - - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks PXA910_CLK_UART0>; - resets = <&soc_clocks PXA910_CLK_UART0>; - status = "disabled"; - }; - - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks PXA910_CLK_UART1>; - resets = <&soc_clocks PXA910_CLK_UART1>; - status = "disabled"; - }; - - uart3: uart@d4036000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4036000 0x1000>; - interrupts = <59>; - clocks = <&soc_clocks PXA910_CLK_UART2>; - resets = <&soc_clocks PXA910_CLK_UART2>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks PXA910_CLK_GPIO>; - resets = <&soc_clocks PXA910_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <1>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks PXA910_CLK_TWSI0>; - resets = <&soc_clocks PXA910_CLK_TWSI0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4037000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4037000 0x1000>; - interrupts = <54>; - clocks = <&soc_clocks PXA910_CLK_TWSI1>; - resets = <&soc_clocks PXA910_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5 6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - clocks = <&soc_clocks PXA910_CLK_RTC>; - resets = <&soc_clocks PXA910_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,pxa910-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>, - <0xd403b000 0x1000>; - reg-names = "mpmu", "apmu", "apbc", "apbcp"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts deleted file mode 100644 index 6c0038398..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ /dev/null @@ -1,665 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include -#include "qcom-msm8660.dtsi" - -/ { - model = "Qualcomm APQ8060 Dragonboard"; - compatible = "qcom,apq8060-dragonboard", "qcom,msm8660"; - - aliases { - serial0 = &gsbi12_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - regulators { - compatible = "simple-bus"; - - /* Main power of the board: 3.7V */ - vph: regulator-fixed { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-always-on; - regulator-boot-on; - }; - - /* This is a levelshifter for SDCC5 */ - dragon_vio_txb: txb0104rgyr { - compatible = "regulator-fixed"; - regulator-name = "Dragon SDCC levelshifter"; - vin-supply = <&pm8058_l14>; - regulator-always-on; - }; - }; - - soc { - pinctrl@800000 { - /* eMMMC pins, all 8 data lines connected */ - dragon_sdcc1_pins: sdcc1 { - mux { - pins = "gpio159", "gpio160", "gpio161", - "gpio162", "gpio163", "gpio164", - "gpio165", "gpio166", "gpio167", - "gpio168"; - function = "sdc1"; - }; - clk { - pins = "gpio167"; /* SDC5 CLK */ - drive-strength = <16>; - bias-disable; - }; - cmd { - pins = "gpio168"; /* SDC5 CMD */ - drive-strength = <10>; - bias-pull-up; - }; - data { - /* SDC5 D0 to D7 */ - pins = "gpio159", "gpio160", "gpio161", "gpio162", - "gpio163", "gpio164", "gpio165", "gpio166"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - /* - * The SDCC3 pins are hardcoded (non-muxable) but need some pin - * configuration. - */ - dragon_sdcc3_pins: sdcc3 { - clk { - pins = "sdc3_clk"; - drive-strength = <8>; - bias-disable; - }; - cmd { - pins = "sdc3_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - data { - pins = "sdc3_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - /* Second SD card slot pins */ - dragon_sdcc5_pins: sdcc5 { - mux { - pins = "gpio95", "gpio96", "gpio97", - "gpio98", "gpio99", "gpio100"; - function = "sdc5"; - }; - clk { - pins = "gpio97"; /* SDC5 CLK */ - drive-strength = <16>; - bias-disable; - }; - cmd { - pins = "gpio95"; /* SDC5 CMD */ - drive-strength = <10>; - bias-pull-up; - }; - data { - /* SDC5 D0 to D3 */ - pins = "gpio96", "gpio98", "gpio99", "gpio100"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - dragon_gsbi12_i2c_pins: gsbi12_i2c { - mux { - pins = "gpio115", "gpio116"; - function = "gsbi12"; - }; - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <16>; - /* These have external pull-up 4.7kOhm to 1.8V */ - bias-disable; - }; - }; - - /* Primary serial port uart 0 pins */ - dragon_gsbi12_serial_pins: gsbi12_serial { - mux { - pins = "gpio117", "gpio118"; - function = "gsbi12"; - }; - tx { - pins = "gpio117"; - drive-strength = <8>; - bias-disable; - }; - rx { - pins = "gpio118"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qcom,ssbi@500000 { - pmic@0 { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_MENU) - MATRIX_KEY(0, 2, KEY_1) - MATRIX_KEY(0, 3, KEY_4) - MATRIX_KEY(0, 4, KEY_7) - MATRIX_KEY(1, 0, KEY_UP) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_DOWN) - MATRIX_KEY(1, 3, KEY_5) - MATRIX_KEY(1, 3, KEY_8) - MATRIX_KEY(2, 0, KEY_HOME) - MATRIX_KEY(2, 1, KEY_REPLY) - MATRIX_KEY(2, 2, KEY_2) - MATRIX_KEY(2, 3, KEY_6) - MATRIX_KEY(3, 0, KEY_VOLUMEUP) - MATRIX_KEY(3, 1, KEY_RIGHT) - MATRIX_KEY(3, 2, KEY_3) - MATRIX_KEY(3, 3, KEY_9) - MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE) - MATRIX_KEY(4, 0, KEY_VOLUMEDOWN) - MATRIX_KEY(4, 1, KEY_BACK) - MATRIX_KEY(4, 2, KEY_CAMERA) - MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE) - >; - keypad,num-rows = <6>; - keypad,num-columns = <5>; - }; - - gpio@150 { - dragon_bmp085_gpios: bmp085-gpios { - pinconf { - pins = "gpio16"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_sdcc3_gpios: sdcc3-gpios { - pinconf { - pins = "gpio22"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - dragon_sdcc5_gpios: sdcc5-gpios { - pinconf { - pins = "gpio26"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,pull-up-strength = ; - power-source = ; - }; - }; - dragon_ak8975_gpios: ak8975-gpios { - pinconf { - pins = "gpio33"; - function = "normal"; - input-enable; - bias-disable; - power-source = ; - }; - }; - }; - - led@48 { - /* - * The keypad LED @0x48 is routed to - * the sensor board where it is - * connected to an infrared LED - * SFH4650 (60mW, @850nm) next to the - * ambient light and proximity sensor - * Capella Microsystems CM3605. - */ - compatible = "qcom,pm8058-keypad-led"; - reg = <0x48>; - label = "pm8058:infrared:proximitysensor"; - default-state = "off"; - }; - led@131 { - compatible = "qcom,pm8058-led"; - reg = <0x131>; - label = "pm8058:red"; - default-state = "off"; - }; - led@132 { - /* - * This is actually green too on my - * board, but documented as yellow. - */ - compatible = "qcom,pm8058-led"; - reg = <0x132>; - label = "pm8058:yellow"; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - led@133 { - compatible = "qcom,pm8058-led"; - reg = <0x133>; - label = "pm8058:green"; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - }; - - gsbi@19c00000 { - status = "ok"; - qcom,mode = ; - - serial@19c40000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi12_serial_pins>; - }; - - i2c@19c80000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_gsbi12_i2c_pins>; - - ak8975@0c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - /* GPIO33 has interrupt 224 on the PM8058 */ - interrupt-parent = <&pm8058_gpio>; - interrupts = <224 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_ak8975_gpios>; - vid-supply = <&pm8058_lvs0>; // 1.8V - vdd-supply = <&pm8058_l14>; // 2.85V - }; - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - /* GPIO16 has interrupt 207 on the PM8058 */ - interrupt-parent = <&pm8058_gpio>; - interrupts = <207 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_bmp085_gpios>; - vddd-supply = <&pm8058_lvs0>; // 1.8V - vdda-supply = <&pm8058_l14>; // 2.85V - }; - }; - }; - - rpm@104000 { - /* - * Set up of the PMIC RPM regulators for this board - * PM8901 supplies "preliminary regulators" whatever - * that means - */ - pm8901-regulators { - vdd_l0-supply = <&pm8901_s4>; - vdd_l1-supply = <&vph>; - vdd_l2-supply = <&vph>; - vdd_l3-supply = <&vph>; - vdd_l4-supply = <&vph>; - vdd_l5-supply = <&vph>; - vdd_l6-supply = <&vph>; - /* vdd_s0-supply, vdd_s1-supply: SAW regulators */ - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - lvs0_in-supply = <&pm8058_s3>; - lvs1_in-supply = <&pm8901_s4>; - lvs2_in-supply = <&pm8058_l0>; - lvs3_in-supply = <&pm8058_s2>; - mvs_in-supply = <&pm8058_s3>; - - l0 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l2 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - l4 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l5 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l6 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - bias-pull-down; - }; - - /* s0 and s1 are SAW regulators controlled over SPM */ - s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* LVS0 thru 3 and mvs0 are just switches */ - lvs0 { - regulator-always-on; - }; - lvs1 { }; - lvs2 { }; - lvs3 { }; - mvs0 {}; - - }; - - pm8058-regulators { - vdd_l0_l1_lvs-supply = <&pm8058_s3>; - vdd_l2_l11_l12-supply = <&vph>; - vdd_l3_l4_l5-supply = <&vph>; - vdd_l6_l7-supply = <&vph>; - vdd_l8-supply = <&vph>; - vdd_l9-supply = <&vph>; - vdd_l10-supply = <&vph>; - vdd_l13_l16-supply = <&pm8058_s4>; - vdd_l14_l15-supply = <&vph>; - vdd_l17_l18-supply = <&vph>; - vdd_l19_l20-supply = <&vph>; - vdd_l21-supply = <&pm8058_s3>; - vdd_l22-supply = <&pm8058_s3>; - vdd_l23_l24_l25-supply = <&pm8058_s3>; - vdd_s0-supply = <&vph>; - vdd_s1-supply = <&vph>; - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - vdd_ncp-supply = <&vph>; - - l0 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l4 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l5 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l6 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - bias-pull-down; - }; - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3050000>; - bias-pull-down; - }; - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l10 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l11 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - bias-pull-down; - }; - l12 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - bias-pull-down; - }; - l13 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - bias-pull-down; - }; - l14 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - l15 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - regulator-always-on; - }; - l17 { - // 1.5V according to schematic - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - l18 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - bias-pull-down; - }; - l19 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - bias-pull-down; - }; - l20 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - l21 { - // 1.1 V according to schematic - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - regulator-always-on; - }; - l22 { - // 1.2 V according to schematic - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - l23 { - // Unused - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l24 { - // Unused - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - l25 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - s0 { - // regulator-min-microvolt = <500000>; - // regulator-max-microvolt = <1325000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s1 { - // regulator-min-microvolt = <500000>; - // regulator-max-microvolt = <1250000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s2 { - // 1.3 V according to schematic - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - regulator-always-on; - bias-pull-down; - }; - s4 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - qcom,switch-mode-frequency = <1600000>; - regulator-always-on; - bias-pull-down; - }; - - /* LVS0 and LVS1 are just switches */ - lvs0 { - bias-pull-down; - }; - lvs1 { - bias-pull-down; - }; - - ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; - }; - amba { - /* Internal 3.69 GiB eMMC */ - sdcc@12400000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc1_pins>; - vmmc-supply = <&pm8901_l5>; - vqmmc-supply = <&pm8901_lvs0>; - }; - - /* External micro SD card, directly connected, pulled up to 2.85 V */ - sdcc@12180000 { - status = "okay"; - /* Enable SSBI GPIO 22 as input, use for card detect */ - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>; - cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&pm8058_l14>; - }; - - /* - * Second external micro SD card, using two TXB104RGYR levelshifters - * to lift from 1.8 V to 2.85 V - */ - sdcc@12200000 { - status = "okay"; - /* Enable SSBI GPIO 26 as input, use for card detect */ - pinctrl-names = "default"; - pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>; - cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>; - wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&pm8058_l14>; - vqmmc-supply = <&dragon_vio_txb>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi deleted file mode 100644 index a3efb9704..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -&tlmm_pinmux { - card_detect: card-detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie-pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - - user_leds: user-leds { - mux { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - }; - - conf { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - output-low; - }; - }; - - magneto_pins: magneto-pins { - mux { - pins = "gpio31", "gpio48"; - function = "gpio"; - bias-disable; - }; - }; -}; - -&pm8921_mpps { - mpp_leds: mpp-leds { - pinconf { - pins = "mpp7", "mpp8"; - function = "digital"; - output-low; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts deleted file mode 100644 index 39ae2bc8c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts +++ /dev/null @@ -1,351 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include "qcom-apq8064-arrow-sd-600eval-pins.dtsi" -#include -#include - -/ { - model = "Arrow Electronics, APQ8064 SD_600eval"; - compatible = "arrow,sd_600eval", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi1_serial; - i2c0 = &gsbi2_i2c; - i2c1 = &gsbi3_i2c; - i2c2 = &gsbi4_i2c; - i2c3 = &gsbi7_i2c; - spi0 = &gsbi5_spi; - }; - - regulators { - compatible = "simple-bus"; - vph: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <4500000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-boot-on; - }; - - /* on board fixed 3.3v supply */ - vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - }; - - soc { - rpm@108000 { - regulators { - vdd_s1-supply = <&vph>; - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - vdd_s5-supply = <&vph>; - vdd_s6-supply = <&vph>; - vdd_s7-supply = <&vph>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l3_l15_l17-supply = <&vph>; - vdd_l4_l14-supply = <&vph>; - vdd_l5_l8_l16-supply = <&vph>; - vdd_l6_l7-supply = <&vph>; - vdd_l9_l11-supply = <&vph>; - vdd_l10_l22-supply = <&vph>; - vdd_l21_l23_l29-supply = <&vph>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - qcom,force-mode = ; - bias-pull-down; - regulator-always-on; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - regulator-boot-on; - regulator-always-on; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - lvs7 { - bias-pull-down; - }; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - serial@12450000 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi1_uart_4pins>; - }; - }; - - gsbi@12480000 { - status = "okay"; - qcom,mode = ; - i2c@124a0000 { - /* On Low speed expansion and Sensors */ - label = "LS-I2C0"; - status = "okay"; - lis3mdl_mag@1e { - compatible = "st,lis3mdl-magn"; - reg = <0x1e>; - vdd-supply = <&vcc3v3>; - vddio-supply = <&pm8921_s4>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_pins>; - interrupt-parent = <&tlmm_pinmux>; - - st,drdy-int-pin = <2>; - interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ - <31 IRQ_TYPE_EDGE_RISING>; /* INT */ - }; - }; - }; - - gsbi@16200000 { - status = "okay"; - qcom,mode = ; - i2c@16280000 { - /* On Low speed expansion */ - status = "okay"; - label = "LS-I2C1"; - clock-frequency = <200000>; - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <64>; - }; - }; - }; - - gsbi@16300000 { - status = "okay"; - qcom,mode = ; - i2c@16380000 { - /* On High speed expansion */ - label = "HS-CAM-I2C3"; - status = "okay"; - }; - }; - - gsbi@1a200000 { - status = "okay"; - spi@1a280000 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; - }; - }; - - /* DEBUG UART */ - gsbi@16600000 { - status = "okay"; - qcom,mode = ; - serial@16640000 { - label = "LS-UART0"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - - i2c@16680000 { - /* On High speed expansion */ - status = "okay"; - label = "HS-CAM-I2C2"; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>, <&mpp_leds>; - - compatible = "gpio-leds"; - - user-led0 { - label = "user0-led"; - gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user-led1 { - label = "user1-led"; - gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - user-led2 { - label = "user2-led"; - gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led3 { - label = "user3-led"; - gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - wifi-led { - label = "WiFi-led"; - gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - bt-led { - label = "BT-led"; - gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pci@1b500000 { - status = "okay"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&vcc3v3>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - target-supply = <&pm8921_lvs7>; - }; - - /* OTG */ - phy@12500000 { - status = "okay"; - dr_mode = "peripheral"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget@12500000 { - status = "okay"; - }; - - /* OTG */ - usb@12500000 { - status = "okay"; - }; - - usb@12520000 { - status = "okay"; - }; - - usb@12530000 { - status = "okay"; - }; - - amba { - /* eMMC */ - sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc@12180000 { - status = "okay"; - vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts deleted file mode 100644 index b72e09506..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ /dev/null @@ -1,291 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include -#include -#include -/ { - model = "Asus Nexus7(flo)"; - compatible = "asus,nexus7-flo", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi6_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - ext_3p3v: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ext_3p3v"; - regulator-type = "voltage"; - startup-delay-us = <0>; - gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - volume_up { - label = "Volume Up"; - gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - volume_down { - label = "Volume Down"; - gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - soc { - rpm@108000 { - regulators { - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vin_lvs2-supply = <&pm8921_s1>; - - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - vdd_ncp-supply = <&pm8921_l6>; - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - /* msm otg HSUSB_VDDCX */ - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - }; - - /* - * msm_sdcc.1-sdc-vdd_io - * tabla2x-slim-CDC_VDDA_RX - * tabla2x-slim-CDC_VDDA_TX - * tabla2x-slim-CDC_VDD_CP - * tabla2x-slim-VDDIO_CDC - */ - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - regulator-always-on; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - /* mipi_dsi.1-dsi1_pll_vdda */ - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - /* msm_otg-HSUSB_3p3 */ - l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - /* msm_otg-HSUSB_1p8 */ - l4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - /* msm_sdcc.1-sdc_vdd */ - l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - /* mipi_dsi.1-dsi1_avdd */ - l11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - /* pwm_power for backlight */ - l17 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - bias-pull-down; - }; - - /* camera, qdsp6 */ - l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - /* - * tabla2x-slim-CDC_VDDA_A_1P2V - * tabla2x-slim-VDDD_CDC_D - */ - l25 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - lvs1 { - bias-pull-down; - }; - - lvs4 { - bias-pull-down; - }; - - lvs5 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - /* - * mipi_dsi.1-dsi1_vddio - * pil_riva-pll_vdd - */ - lvs7 { - bias-pull-down; - }; - }; - }; - - gsbi@16200000 { - status = "okay"; - qcom,mode = ; - i2c@16280000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - - trackpad@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - }; - }; - }; - - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - - i2c@12460000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - }; - - bq27541@55 { - compatible = "ti,bq27541"; - reg = <0x55>; - }; - - }; - }; - - gsbi@16500000 { - status = "ok"; - qcom,mode = ; - - serial@16540000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&gsbi6_uart_4pins>; - }; - }; - - gsbi@16600000 { - status = "ok"; - qcom,mode = ; - serial@16640000 { - status = "ok"; - }; - }; - - /* OTG */ - phy@12500000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - dr_mode = "otg"; - }; - - gadget@12500000 { - status = "okay"; - }; - - /* OTG */ - usb@12500000 { - status = "okay"; - }; - - amba { - /* eMMC */ - sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - }; - - imem@2a03f000 { - compatible = "syscon", "simple-mfd"; - reg = <0x2a03f000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; - - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts deleted file mode 100644 index 35f1d46ed..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ /dev/null @@ -1,250 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include -#include - -/ { - model = "CompuLab CM-QS600"; - compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pwrseq { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - sdcc4_pwrseq: sdcc4_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_gpios>; - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; - }; - }; - - soc { - pinctrl@800000 { - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie_pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - }; - - rpm@108000 { - regulators { - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8921_lvs6: lvs6 { - bias-pull-down; - }; - - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - - i2c@12460000 { - status = "okay"; - clock-frequency = <200000>; - - eeprom@50 { - compatible = "24c02"; - reg = <0x50>; - pagesize = <32>; - }; - }; - }; - - gsbi@16600000 { - status = "ok"; - qcom,mode = ; - serial@16640000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - }; - - /* OTG */ - usb1_phy: phy@12500000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - usb3_phy: phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - usb4_phy: phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget1: gadget@12500000 { - status = "ok"; - }; - - /* OTG */ - usb1: usb@12500000 { - status = "ok"; - }; - - usb3: usb@12520000 { - status = "okay"; - }; - - usb4: usb@12530000 { - status = "okay"; - }; - - /* on board fixed 3.3v supply */ - v3p3_fixed: v3p3 { - compatible = "regulator-fixed"; - regulator-name = "PCIE V3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - qcom,ssbi@500000 { - pmic@0 { - gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { - pins = "gpio43"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; - }; - }; - }; - - pci@1b500000 { - status = "ok"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&v3p3_fixed>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - vmmc-supply = <&v3p3_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - }; - /* WLAN */ - sdcc4: sdcc@121c0000 { - status = "okay"; - vmmc-supply = <&v3p3_fixed>; - vqmmc-supply = <&v3p3_fixed>; - mmc-pwrseq = <&sdcc4_pwrseq>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts deleted file mode 100644 index 2eeb0904e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ /dev/null @@ -1,333 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include -#include - -/ { - model = "Qualcomm APQ8064/IFC6410"; - compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi6_serial; - i2c0 = &gsbi1_i2c; - i2c1 = &gsbi2_i2c; - i2c2 = &gsbi3_i2c; - i2c3 = &gsbi4_i2c; - spi0 = &gsbi5_spi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pwrseq { - compatible = "simple-bus"; - - sdcc4_pwrseq: sdcc4_pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_default_gpios>; - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <¬ify_led>; - - led@1 { - label = "apq8064:green:user1"; - gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - soc { - pinctrl@800000 { - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie_pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - }; - - rpm@108000 { - regulators { - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs1 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - }; - }; - - ext_3p3v: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ext_3p3v"; - regulator-type = "voltage"; - startup-delay-us = <0>; - gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - }; - - gsbi3: gsbi@16200000 { - status = "okay"; - qcom,mode = ; - i2c@16280000 { - status = "okay"; - }; - }; - - gsbi@16300000 { - status = "okay"; - qcom,mode = ; - /* CAM I2C MIPI-CSI connector */ - i2c@16380000 { - status = "okay"; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - - i2c@12460000 { - status = "okay"; - clock-frequency = <200000>; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - }; - }; - }; - - gsbi@1a200000 { - qcom,mode = ; - status = "okay"; - spi4: spi@1a280000 { - status = "okay"; - num-cs = <1>; - cs-gpios = <&tlmm_pinmux 53 0>; - }; - }; - - gsbi@16500000 { - status = "ok"; - qcom,mode = ; - - serial@16540000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi6_uart_4pins>; - }; - }; - - gsbi@16600000 { - status = "ok"; - qcom,mode = ; - serial@16640000 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - }; - - sata_phy0: phy@1b400000 { - status = "okay"; - }; - - sata0: sata@29000000 { - status = "okay"; - target-supply = <&pm8921_s4>; - }; - - /* OTG */ - usb1_phy: phy@12500000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - usb3_phy: phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - usb4_phy: phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget1: gadget@12500000 { - status = "okay"; - }; - - /* OTG */ - usb1: usb@12500000 { - status = "okay"; - }; - - usb3: usb@12520000 { - status = "okay"; - }; - - usb4: usb@12530000 { - status = "okay"; - }; - - pci@1b500000 { - status = "ok"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&ext_3p3v>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - qcom,ssbi@500000 { - pmic@0 { - gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { - pins = "gpio43"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; - - notify_led: nled { - pios { - pins = "gpio18"; - function = "normal"; - bias-disable; - power-source = ; - }; - }; - }; - }; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - }; - /* WLAN */ - sdcc4: sdcc@121c0000 { - status = "okay"; - vmmc-supply = <&ext_3p3v>; - vqmmc-supply = <&pm8921_lvs1>; - mmc-pwrseq = <&sdcc4_pwrseq>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-pins.dtsi deleted file mode 100644 index 6b801e7e5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ /dev/null @@ -1,287 +0,0 @@ - -&tlmm_pinmux { - sdc4_gpios: sdc4-gpios { - pios { - pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; - function = "sdc4"; - }; - }; - - sdcc1_pins: sdcc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strengh = <16>; - bias-disable; - }; - - cmd { - pins = "sdc1_cmd"; - drive-strengh = <10>; - bias-pull-up; - }; - - data { - pins = "sdc1_data"; - drive-strengh = <10>; - bias-pull-up; - }; - }; - - sdcc3_pins: sdcc3-pin-active { - clk { - pins = "sdc3_clk"; - drive-strengh = <8>; - bias-disable; - }; - - cmd { - pins = "sdc3_cmd"; - drive-strengh = <8>; - bias-pull-up; - }; - - data { - pins = "sdc3_data"; - drive-strengh = <8>; - bias-pull-up; - }; - }; - - ps_hold: ps_hold { - mux { - pins = "gpio78"; - function = "ps_hold"; - }; - }; - - i2c1_pins: i2c1 { - mux { - pins = "gpio20", "gpio21"; - function = "gsbi1"; - }; - - pinconf { - pins = "gpio20", "gpio21"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c1_pins_sleep: i2c1_pins_sleep { - mux { - pins = "gpio20", "gpio21"; - function = "gpio"; - }; - pinconf { - pins = "gpio20", "gpio21"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - gsbi1_uart_2pins: gsbi1_uart_2pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi1"; - }; - }; - - gsbi1_uart_4pins: gsbi1_uart_4pins { - mux { - pins = "gpio18", "gpio19", "gpio20", "gpio21"; - function = "gsbi1"; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio24", "gpio25"; - function = "gsbi2"; - }; - - pinconf { - pins = "gpio24", "gpio25"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c2_pins_sleep: i2c2_pins_sleep { - mux { - pins = "gpio24", "gpio25"; - function = "gpio"; - }; - - pinconf { - pins = "gpio24", "gpio25"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - i2c3_pins: i2c3 { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi3"; - }; - - pinconf { - pins = "gpio8", "gpio9"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c3_pins_sleep: i2c3_pins_sleep { - mux { - pins = "gpio8", "gpio9"; - function = "gpio"; - }; - pinconf { - pins = "gpio8", "gpio9"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - i2c4_pins: i2c4 { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - }; - - pinconf { - pins = "gpio12", "gpio13"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c4_pins_sleep: i2c4_pins_sleep { - mux { - pins = "gpio12", "gpio13"; - function = "gpio"; - }; - pinconf { - pins = "gpio12", "gpio13"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - spi5_default: spi5_default { - pinmux { - pins = "gpio51", "gpio52", "gpio54"; - function = "gsbi5"; - }; - - pinmux_cs { - function = "gpio"; - pins = "gpio53"; - }; - - pinconf { - pins = "gpio51", "gpio52", "gpio54"; - drive-strength = <16>; - bias-disable; - }; - - pinconf_cs { - pins = "gpio53"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi5_sleep: spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - }; - - pinconf { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - i2c6_pins: i2c6 { - mux { - pins = "gpio16", "gpio17"; - function = "gsbi6"; - }; - - pinconf { - pins = "gpio16", "gpio17"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c6_pins_sleep: i2c6_pins_sleep { - mux { - pins = "gpio16", "gpio17"; - function = "gpio"; - }; - pinconf { - pins = "gpio16", "gpio17"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - gsbi6_uart_2pins: gsbi6_uart_2pins { - mux { - pins = "gpio14", "gpio15"; - function = "gsbi6"; - }; - }; - - gsbi6_uart_4pins: gsbi6_uart_4pins { - mux { - pins = "gpio14", "gpio15", "gpio16", "gpio17"; - function = "gsbi6"; - }; - }; - - gsbi7_uart_2pins: gsbi7_uart_2pins { - mux { - pins = "gpio82", "gpio83"; - function = "gsbi7"; - }; - }; - - gsbi7_uart_4pins: gsbi7_uart_4pins { - mux { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "gsbi7"; - }; - }; - - i2c7_pins: i2c7 { - mux { - pins = "gpio84", "gpio85"; - function = "gsbi7"; - }; - - pinconf { - pins = "gpio84", "gpio85"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c7_pins_sleep: i2c7_pins_sleep { - mux { - pins = "gpio84", "gpio85"; - function = "gpio"; - }; - pinconf { - pins = "gpio84", "gpio85"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts deleted file mode 100644 index ebd675ca9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts +++ /dev/null @@ -1,394 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include -#include -#include -#include - -/ { - model = "Sony Xperia Z"; - compatible = "sony,xperia-yuga", "qcom,apq8064"; - - aliases { - serial0 = &gsbi5_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-down { - label = "volume_down"; - gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - soc { - pinctrl@800000 { - gsbi5_uart_pin_a: gsbi5-uart-pin-active { - rx { - pins = "gpio52"; - function = "gsbi5"; - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio51"; - function = "gsbi5"; - drive-strength = <4>; - bias-disable; - }; - }; - - - sdcc3_cd_pin_a: sdcc3-cd-pin-active { - pins = "gpio26"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - }; - - - rpm@108000 { - regulators { - vin_l1_l2_l12_l18-supply = <&pm8921_s4>; - vin_lvs_1_3_6-supply = <&pm8921_s4>; - vin_lvs_4_5_7-supply = <&pm8921_s4>; - vin_ncp-supply = <&pm8921_l6>; - vin_lvs2-supply = <&pm8921_s4>; - vin_l24-supply = <&pm8921_s1>; - vin_l25-supply = <&pm8921_s1>; - vin_l27-supply = <&pm8921_s7>; - vin_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = ; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - s8 { - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - qcom,switch-mode-frequency = <1600000>; - }; - - /* PMOS LDO */ - l1 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - bias-pull-down; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l8 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l10 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - bias-pull-down; - }; - - l11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - l17 { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - bias-pull-down; - }; - - l18 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - l21 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - l22 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2600000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - l25 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - l27 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - l28 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - l29 { - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - lvs1 { - bias-pull-down; - }; - - lvs2 { - bias-pull-down; - }; - - lvs3 { - bias-pull-down; - }; - - lvs4 { - bias-pull-down; - }; - - lvs5 { - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - lvs7 { - bias-pull-down; - }; - - usb-switch {}; - - hdmi-switch {}; - - ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; - }; - - qcom,ssbi@500000 { - pmic@0 { - gpio@150 { - gpio_keys_pin_a: gpio-keys-pin-active { - pins = "gpio3", "gpio4", "gpio29", "gpio35"; - function = "normal"; - - bias-pull-up; - drive-push-pull; - input-enable; - power-source = <2>; - qcom,drive-strength = ; - qcom,pull-up-strength = <0>; - }; - }; - }; - }; - - phy@12500000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - gadget@12500000 { - status = "okay"; - }; - - gsbi@1a200000 { - status = "ok"; - qcom,mode = ; - - serial@1a240000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&gsbi5_uart_pin_a>; - }; - }; - - amba { - sdcc1: sdcc@12400000 { - status = "okay"; - - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - sdcc3: sdcc@12180000 { - status = "okay"; - - vmmc-supply = <&pm8921_l6>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi deleted file mode 100644 index 935c3945f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "qcom-apq8064.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064.dtsi deleted file mode 100644 index 1dbe697b2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8064.dtsi +++ /dev/null @@ -1,1100 +0,0 @@ -/dts-v1/; - -#include "skeleton.dtsi" -#include -#include -#include -#include -#include -#include -/ { - model = "Qualcomm APQ8064"; - compatible = "qcom,apq8064"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_region: smem@80000000 { - reg = <0x80000000 0x200000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@2 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@3 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <400>; - exit-latency-us = <900>; - min-residency-us = <3000>; - }; - }; - }; - - thermal-zones { - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&gcc 7>; - coefficients = <1199 0>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&gcc 8>; - coefficients = <1132 0>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&gcc 9>; - coefficients = <1199 0>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&gcc 10>; - coefficients = <1132 0>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_wrapper_mutex 0x604 0x4>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - - hwlocks = <&sfpb_mutex 3>; - }; - - smd { - compatible = "qcom,smd"; - - modem@0 { - interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 3>; - qcom,smd-edge = <0>; - - status = "disabled"; - }; - - q6@1 { - interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 15>; - qcom,smd-edge = <1>; - - status = "disabled"; - }; - - dsps@3 { - interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&sps_sic_non_secure 0x4080 0>; - qcom,smd-edge = <3>; - - status = "disabled"; - }; - - riva@6 { - interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 25>; - qcom,smd-edge = <6>; - - status = "disabled"; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&l2cc 8 4>; - qcom,ipc-2 = <&l2cc 8 14>; - qcom,ipc-3 = <&l2cc 8 23>; - qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; - - apps_smsm: apps@0 { - reg = <0>; - #qcom,smem-state-cells = <1>; - }; - - modem_smsm: modem@1 { - reg = <1>; - interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - q6_smsm: q6@2 { - reg = <2>; - interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@3 { - reg = <3>; - interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - dsps_smsm: dsps@4 { - reg = <4>; - interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-apq8064"; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - tlmm_pinmux: pinctrl@800000 { - compatible = "qcom,apq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&ps_hold>; - }; - - sfpb_wrapper_mutex: syscon@1200000 { - compatible = "syscon"; - reg = <0x01200000 0x8000>; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - acc2: clock-controller@20a8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; - }; - - acc3: clock-controller@20b8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: power-controller@2089000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: power-controller@2099000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw2: power-controller@20a9000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw3: power-controller@20b9000 { - compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; - reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; - reg = <0x12100000 0x10000>; - }; - - gsbi1: gsbi@12440000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x12440000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi1_serial: serial@12450000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12450000 0x100>, - <0x12400000 0x03>; - interrupts = <0 193 0x0>; - clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi1_i2c: i2c@12460000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c1_pins>; - pinctrl-1 = <&i2c1_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x12460000 0x1000>; - interrupts = <0 194 IRQ_TYPE_NONE>; - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - }; - - gsbi2: gsbi@12480000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi2_i2c: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-1 = <&i2c2_pins_sleep>; - pinctrl-names = "default", "sleep"; - interrupts = <0 196 IRQ_TYPE_NONE>; - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi3: gsbi@16200000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <3>; - reg = <0x16200000 0x100>; - clocks = <&gcc GSBI3_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - gsbi3_i2c: i2c@16280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c3_pins>; - pinctrl-1 = <&i2c3_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16280000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI3_QUP_CLK>, - <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi4: gsbi@16300000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x03>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi4_i2c: i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c4_pins>; - pinctrl-1 = <&i2c4_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16380000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI4_QUP_CLK>, - <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - }; - }; - - gsbi5: gsbi@1a200000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x03>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi5_serial: serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x100>, - <0x1a200000 0x03>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi5_spi: spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; - pinctrl-names = "default", "sleep"; - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi6: gsbi@16500000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <6>; - reg = <0x16500000 0x03>; - clocks = <&gcc GSBI6_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gsbi6_serial: serial@16540000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16540000 0x100>, - <0x16500000 0x03>; - interrupts = <0 156 0x0>; - clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi6_i2c: i2c@16580000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c6_pins>; - pinctrl-1 = <&i2c6_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16580000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI6_QUP_CLK>, - <&gcc GSBI6_H_CLK>; - clock-names = "core", "iface"; - }; - }; - - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <7>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = <0 158 0x0>; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi7_i2c: i2c@16680000 { - compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c7_pins>; - pinctrl-1 = <&i2c7_pins_sleep>; - pinctrl-names = "default", "sleep"; - reg = <0x16680000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI7_QUP_CLK>, - <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic@0 { - compatible = "qcom,pm8921"; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <74 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pm8921_gpio: gpio@150 { - - compatible = "qcom,pm8921-gpio", - "qcom,ssbi-gpio"; - reg = <0x150>; - interrupts = <192 IRQ_TYPE_NONE>, - <193 IRQ_TYPE_NONE>, - <194 IRQ_TYPE_NONE>, - <195 IRQ_TYPE_NONE>, - <196 IRQ_TYPE_NONE>, - <197 IRQ_TYPE_NONE>, - <198 IRQ_TYPE_NONE>, - <199 IRQ_TYPE_NONE>, - <200 IRQ_TYPE_NONE>, - <201 IRQ_TYPE_NONE>, - <202 IRQ_TYPE_NONE>, - <203 IRQ_TYPE_NONE>, - <204 IRQ_TYPE_NONE>, - <205 IRQ_TYPE_NONE>, - <206 IRQ_TYPE_NONE>, - <207 IRQ_TYPE_NONE>, - <208 IRQ_TYPE_NONE>, - <209 IRQ_TYPE_NONE>, - <210 IRQ_TYPE_NONE>, - <211 IRQ_TYPE_NONE>, - <212 IRQ_TYPE_NONE>, - <213 IRQ_TYPE_NONE>, - <214 IRQ_TYPE_NONE>, - <215 IRQ_TYPE_NONE>, - <216 IRQ_TYPE_NONE>, - <217 IRQ_TYPE_NONE>, - <218 IRQ_TYPE_NONE>, - <219 IRQ_TYPE_NONE>, - <220 IRQ_TYPE_NONE>, - <221 IRQ_TYPE_NONE>, - <222 IRQ_TYPE_NONE>, - <223 IRQ_TYPE_NONE>, - <224 IRQ_TYPE_NONE>, - <225 IRQ_TYPE_NONE>, - <226 IRQ_TYPE_NONE>, - <227 IRQ_TYPE_NONE>, - <228 IRQ_TYPE_NONE>, - <229 IRQ_TYPE_NONE>, - <230 IRQ_TYPE_NONE>, - <231 IRQ_TYPE_NONE>, - <232 IRQ_TYPE_NONE>, - <233 IRQ_TYPE_NONE>, - <234 IRQ_TYPE_NONE>, - <235 IRQ_TYPE_NONE>; - gpio-controller; - #gpio-cells = <2>; - - }; - - pm8921_mpps: mpps@50 { - compatible = "qcom,pm8921-mpp", - "qcom,ssbi-mpp"; - reg = <0x50>; - gpio-controller; - #gpio-cells = <2>; - interrupts = - <128 IRQ_TYPE_NONE>, - <129 IRQ_TYPE_NONE>, - <130 IRQ_TYPE_NONE>, - <131 IRQ_TYPE_NONE>, - <132 IRQ_TYPE_NONE>, - <133 IRQ_TYPE_NONE>, - <134 IRQ_TYPE_NONE>, - <135 IRQ_TYPE_NONE>, - <136 IRQ_TYPE_NONE>, - <137 IRQ_TYPE_NONE>, - <138 IRQ_TYPE_NONE>, - <139 IRQ_TYPE_NONE>; - }; - - rtc@11d { - compatible = "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 1>; - reg = <0x11d>; - allow-set-time; - }; - - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - }; - }; - - qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - tsens_calib: calib { - reg = <0x404 0x10>; - }; - tsens_backup: backup_calib { - reg = <0x414 0x10>; - }; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; - reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #clock-cells = <1>; - #reset-cells = <1>; - #thermal-sensor-cells = <1>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-apq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mmcc: clock-controller@4000000 { - compatible = "qcom,mmcc-apq8064"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x2011000 0x1000>; - }; - - rpm@108000 { - compatible = "qcom,rpm-apq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - - pm8921_s1: s1 {}; - pm8921_s2: s2 {}; - pm8921_s3: s3 {}; - pm8921_s4: s4 {}; - pm8921_s7: s7 {}; - pm8921_s8: s8 {}; - - pm8921_l1: l1 {}; - pm8921_l2: l2 {}; - pm8921_l3: l3 {}; - pm8921_l4: l4 {}; - pm8921_l5: l5 {}; - pm8921_l6: l6 {}; - pm8921_l7: l7 {}; - pm8921_l8: l8 {}; - pm8921_l9: l9 {}; - pm8921_l10: l10 {}; - pm8921_l11: l11 {}; - pm8921_l12: l12 {}; - pm8921_l14: l14 {}; - pm8921_l15: l15 {}; - pm8921_l16: l16 {}; - pm8921_l17: l17 {}; - pm8921_l18: l18 {}; - pm8921_l21: l21 {}; - pm8921_l22: l22 {}; - pm8921_l23: l23 {}; - pm8921_l24: l24 {}; - pm8921_l25: l25 {}; - pm8921_l26: l26 {}; - pm8921_l27: l27 {}; - pm8921_l28: l28 {}; - pm8921_l29: l29 {}; - - pm8921_lvs1: lvs1 {}; - pm8921_lvs2: lvs2 {}; - pm8921_lvs3: lvs3 {}; - pm8921_lvs4: lvs4 {}; - pm8921_lvs5: lvs5 {}; - pm8921_lvs6: lvs6 {}; - pm8921_lvs7: lvs7 {}; - - pm8921_usb_switch: usb-switch {}; - - pm8921_hdmi_switch: hdmi-switch { - bias-pull-down; - }; - - pm8921_ncp: ncp {}; - }; - }; - - usb1_phy: phy@12500000 { - compatible = "qcom,usb-otg-ci"; - reg = <0x12500000 0x400>; - interrupts = ; - status = "disabled"; - - clocks = <&gcc USB_HS1_XCVR_CLK>, - <&gcc USB_HS1_H_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc USB_HS1_RESET>; - reset-names = "link"; - }; - - usb3_phy: phy@12520000 { - compatible = "qcom,usb-otg-ci"; - reg = <0x12520000 0x400>; - interrupts = ; - status = "disabled"; - dr_mode = "host"; - - clocks = <&gcc USB_HS3_XCVR_CLK>, - <&gcc USB_HS3_H_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc USB_HS3_RESET>; - reset-names = "link"; - }; - - usb4_phy: phy@12530000 { - compatible = "qcom,usb-otg-ci"; - reg = <0x12530000 0x400>; - interrupts = ; - status = "disabled"; - dr_mode = "host"; - - clocks = <&gcc USB_HS4_XCVR_CLK>, - <&gcc USB_HS4_H_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc USB_HS4_RESET>; - reset-names = "link"; - }; - - gadget1: gadget@12500000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12500000 0x400>; - status = "disabled"; - dr_mode = "peripheral"; - interrupts = ; - usb-phy = <&usb1_phy>; - }; - - usb1: usb@12500000 { - compatible = "qcom,ehci-host"; - reg = <0x12500000 0x400>; - interrupts = ; - status = "disabled"; - usb-phy = <&usb1_phy>; - }; - - usb3: usb@12520000 { - compatible = "qcom,ehci-host"; - reg = <0x12520000 0x400>; - interrupts = ; - status = "disabled"; - usb-phy = <&usb3_phy>; - }; - - usb4: usb@12530000 { - compatible = "qcom,ehci-host"; - reg = <0x12530000 0x400>; - interrupts = ; - status = "disabled"; - usb-phy = <&usb4_phy>; - }; - - sata_phy0: phy@1b400000 { - compatible = "qcom,apq8064-sata-phy"; - status = "disabled"; - reg = <0x1b400000 0x200>; - reg-names = "phy_mem"; - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - #phy-cells = <0>; - }; - - sata0: sata@29000000 { - compatible = "qcom,apq8064-ahci", "generic-ahci"; - status = "disabled"; - reg = <0x29000000 0x180>; - interrupts = ; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_iface", - "iface", - "bus", - "rxoob", - "core_pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy0>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - }; - - /* Temporary fixed regulator */ - sdcc1bam:dma@12402000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = <0 98 0>; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc3bam:dma@12182000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = <0 96 0>; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc4bam:dma@121c2000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x121c2000 0x8000>; - interrupts = <0 95 0>; - clocks = <&gcc SDC4_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pins>; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc4: sdcc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&sdc4_gpios>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-apq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - pcie: pci@1b500000 { - compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ - 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_REF_CLK>; - clock-names = "core", "iface", "phy"; - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; - status = "disabled"; - }; - }; -}; -#include "qcom-apq8064-pins.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts deleted file mode 100644 index ad51df27d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ /dev/null @@ -1,325 +0,0 @@ -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" - -/ { - model = "Qualcomm APQ8074 Dragonboard"; - compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; - - aliases { - serial0 = &blsp1_uart2; - usid0 = &pm8941_0; - usid4 = &pm8841_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f991e000 { - status = "ok"; - }; - - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "ok"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - cd-gpios = <&msmgpio 62 0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - bus-width = <4>; - status = "ok"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - }; - - - pinctrl@fd510000 { - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - }; - }; - - spi8_default: spi8_default { - mosi { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - }; - - i2c@f9967000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c11_pins>; - pinctrl-names = "default"; - - eeprom: eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - read-only; - }; - }; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vin_5vs-supply = <&pm8941_5v>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts deleted file mode 100644 index 2052b84a7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts +++ /dev/null @@ -1,33 +0,0 @@ -#include "qcom-apq8084.dtsi" -#include "qcom-pma8084.dtsi" - -/ { - model = "Qualcomm APQ8084/IFC6540"; - compatible = "qcom,apq8084-sbc", "qcom,apq8084"; - - aliases { - serial0 = &blsp2_uart2; - usid0 = &pma8084_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f995e000 { - status = "okay"; - }; - - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "okay"; - }; - - sdhci@f98a4900 { - cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; - bus-width = <4>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084-mtp.dts deleted file mode 100644 index d174d15bc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084-mtp.dts +++ /dev/null @@ -1,22 +0,0 @@ -#include "qcom-apq8084.dtsi" -#include "qcom-pma8084.dtsi" - -/ { - model = "Qualcomm APQ 8084-MTP"; - compatible = "qcom,apq8084-mtp", "qcom,apq8084"; - - aliases { - serial0 = &blsp2_uart2; - usid0 = &pma8084_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f995e000 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084.dtsi deleted file mode 100644 index 39eb7a4ed..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-apq8084.dtsi +++ /dev/null @@ -1,518 +0,0 @@ -/dts-v1/; - -#include "skeleton.dtsi" - -#include -#include - -/ { - model = "Qualcomm APQ 8084"; - compatible = "qcom,apq8084"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_mem: smem_region@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <0>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <1>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <2>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <3>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "qcom,arch-cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <150>; - exit-latency-us = <200>; - min-residency-us = <2000>; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - thermal-zones { - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 7 0xf04>; - }; - - clocks { - xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <19200000>; - }; - - smem { - compatible = "qcom,smem"; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - memory-region = <&smem_mem>; - - hwlocks = <&tcsr_mutex 3>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - qfprom: qfprom@fc4bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; - }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; - }; - }; - - tsens: thermal-sensor@fc4a8000 { - compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #thermal-sensor-cells = <1>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = <0 9 0x4>; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = <0 10 0x4>; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = <0 11 0x4>; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = <0 12 0x4>; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = <0 13 0x4>; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = <0 14 0x4>; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; - - saw1: power-controller@f9099000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; - }; - - saw2: power-controller@f90a9000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw3: power-controller@f90b9000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: clock-controller@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc1: clock-controller@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc2: clock-controller@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc3: clock-controller@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, - <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-apq8084"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; - }; - - tcsr_mutex_regs: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; - #hwlock-cells = <1>; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,apq8084-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 208 0>; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = <0 114 0x0>; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 0>, <0 138 0>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 125 0>, <0 221 0>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = <0 190 0>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-apq8084"; - qcom,smd-channels = "rpm_requests"; - - pma8084-regulators { - compatible = "qcom,rpm-pma8084-regulators"; - - pma8084_s1: s1 {}; - pma8084_s2: s2 {}; - pma8084_s3: s3 {}; - pma8084_s4: s4 {}; - pma8084_s5: s5 {}; - pma8084_s6: s6 {}; - pma8084_s7: s7 {}; - pma8084_s8: s8 {}; - pma8084_s9: s9 {}; - pma8084_s10: s10 {}; - pma8084_s11: s11 {}; - pma8084_s12: s12 {}; - - pma8084_l1: l1 {}; - pma8084_l2: l2 {}; - pma8084_l3: l3 {}; - pma8084_l4: l4 {}; - pma8084_l5: l5 {}; - pma8084_l6: l6 {}; - pma8084_l7: l7 {}; - pma8084_l8: l8 {}; - pma8084_l9: l9 {}; - pma8084_l10: l10 {}; - pma8084_l11: l11 {}; - pma8084_l12: l12 {}; - pma8084_l13: l13 {}; - pma8084_l14: l14 {}; - pma8084_l15: l15 {}; - pma8084_l16: l16 {}; - pma8084_l17: l17 {}; - pma8084_l18: l18 {}; - pma8084_l19: l19 {}; - pma8084_l20: l20 {}; - pma8084_l21: l21 {}; - pma8084_l22: l22 {}; - pma8084_l23: l23 {}; - pma8084_l24: l24 {}; - pma8084_l25: l25 {}; - pma8084_l26: l26 {}; - pma8084_l27: l27 {}; - - pma8084_lvs1: lvs1 {}; - pma8084_lvs2: lvs2 {}; - pma8084_lvs3: lvs3 {}; - pma8084_lvs4: lvs4 {}; - - pma8084_5vs1: 5vs1 {}; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts deleted file mode 100644 index 0d92f1bc3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "qcom-ipq4019-ap.dk01.1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; - -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi deleted file mode 100644 index b9457dd21..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ /dev/null @@ -1,112 +0,0 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "qcom-ipq4019.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; - compatible = "qcom,ipq4019"; - - clocks { - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - soc { - - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <48000000>; - }; - - pinctrl@0x01000000 { - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; - }; - - spi_0_pins: spi_0_pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio55", "gpio56", "gpio57"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio54"; - }; - pinconf { - pins = "gpio55", "gpio56", "gpio57"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio54"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - }; - - blsp_dma: dma@7884000 { - status = "ok"; - }; - - spi_0: spi@78b5000 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "ok"; - cs-gpios = <&tlmm 54 0>; - - mx25l25635e@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "mx25l25635e"; - spi-max-frequency = <24000000>; - }; - }; - - serial@78af000 { - pinctrl-0 = <&serial_pins>; - pinctrl-names = "default"; - status = "ok"; - }; - - cryptobam: dma@8e04000 { - status = "ok"; - }; - - crypto@8e3a000 { - status = "ok"; - }; - - watchdog@b017000 { - status = "ok"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019.dtsi deleted file mode 100644 index b7a24af8f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; - -#include "skeleton.dtsi" -#include -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ4019"; - compatible = "qcom,ipq4019"; - interrupt-parent = <&intc>; - - aliases { - spi0 = &spi_0; - i2c0 = &i2c_0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v1"; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - reg = <0x0>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - operating-points = < - /* kHz uV (fixed) */ - 48000 1100000 - 200000 1100000 - 500000 1100000 - 666000 1100000 - >; - clock-latency = <256000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v1"; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - reg = <0x1>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v1"; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - reg = <0x2>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - enable-method = "qcom,kpss-acc-v1"; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - reg = <0x3>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, - <0x0b002000 0x1000>; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-ipq4019"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x1800000 0x60000>; - }; - - tlmm: pinctrl@0x01000000 { - compatible = "qcom,ipq4019-pinctrl"; - reg = <0x01000000 0x300000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 208 0>; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x23000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - spi_0: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x78b5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_0: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b7000 0x6000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - - cryptobam: dma@8e04000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x08e04000 0x20000>; - interrupts = ; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,controlled-remotely; - status = "disabled"; - }; - - crypto@8e3a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0x08e3a000 0x6000>; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - acc0: clock-controller@b088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; - }; - - acc1: clock-controller@b098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; - }; - - acc2: clock-controller@b0a8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; - }; - - acc3: clock-controller@b0b8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; - }; - - saw0: regulator@b089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw1: regulator@b099000 { - compatible = "qcom,saw2"; - reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw2: regulator@b0a9000 { - compatible = "qcom,saw2"; - reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - saw3: regulator@b0b9000 { - compatible = "qcom,saw2"; - reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; - }; - - serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; - interrupts = <0 107 0>; - status = "disabled"; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; - }; - - serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b0000 0x200>; - interrupts = <0 108 0>; - status = "disabled"; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; - }; - - watchdog@b017000 { - compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; - reg = <0xb017000 0x40>; - clocks = <&sleep_clk>; - timeout-sec = <10>; - status = "disabled"; - }; - - restart@4ab000 { - compatible = "qcom,pshold"; - reg = <0x4ab000 0x4>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064-ap148.dts deleted file mode 100644 index 348503d1a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ /dev/null @@ -1,102 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/AP148"; - compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - soc { - pinmux@800000 { - i2c4_pins: i2c4_pinmux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - bias-disable; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "ok"; - serial@16340000 { - status = "ok"; - }; - - i2c4: i2c@16380000 { - status = "ok"; - - clock-frequency = <200000>; - - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - }; - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "ok"; - - spi4: spi@1a280000 { - status = "ok"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: m25p80@0 { - compatible = "s25fl256s1"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "rootfs"; - reg = <0x0 0x1000000>; - }; - - partition@1 { - label = "scratch"; - reg = <0x1000000 0x1000000>; - }; - }; - }; - }; - - sata-phy@1b400000 { - status = "ok"; - }; - - sata@29000000 { - ports-implemented = <0x1>; - status = "ok"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi deleted file mode 100644 index 7093b075e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "qcom-ipq8064.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064.dtsi deleted file mode 100644 index 76f4e8921..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -/dts-v1/; - -#include "skeleton.dtsi" -#include -#include -#include - -/ { - model = "Qualcomm IPQ8064"; - compatible = "qcom,ipq8064"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nss@40000000 { - reg = <0x40000000 0x1000000>; - no-map; - }; - - smem@41000000 { - reg = <0x41000000 0x200000>; - no-map; - }; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; - clocks = <&lcc AHBIX_CLK>, - <&lcc MI2S_OSR_CLK>, - <&lcc MI2S_BIT_CLK>; - clock-names = "ahbix-clk", - "mi2s-osr-clk", - "mi2s-bit-clk"; - interrupts = <0 85 1>; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x28100000 0x10000>; - reg-names = "lpass-lpaif"; - }; - - qcom_pinmux: pinmux@800000 { - compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 0x4>; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>, - <1 4 0x301>, - <1 5 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <25000000>, - <32768>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x80000>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - serial@12490000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12490000 0x1000>, - <0x12480000 0x1000>; - interrupts = <0 195 0x0>; - clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = <0 196 0>; - - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - }; - - gsbi4: gsbi@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi4_serial: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = <0 152 0x0>; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; - - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi5: gsbi@1a200000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x1000>, - <0x1a200000 0x1000>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@1a280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - status = "disabled"; - }; - - sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - - interrupts = <0 209 0x0>; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", - "rxoob", "pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-ipq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8660-surf.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-msm8660-surf.dts deleted file mode 100644 index 23de76455..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ /dev/null @@ -1,77 +0,0 @@ -#include - -#include "qcom-msm8660.dtsi" - -/ { - model = "Qualcomm MSM8660 SURF"; - compatible = "qcom,msm8660-surf", "qcom,msm8660"; - - aliases { - serial0 = &gsbi12_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - gsbi@19c00000 { - status = "ok"; - qcom,mode = ; - serial@19c40000 { - status = "ok"; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - vmmc-supply = <&vsdcc_fixed>; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - vmmc-supply = <&vsdcc_fixed>; - }; - }; - }; -}; - -&pmicintc { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_FN_F1) - MATRIX_KEY(0, 1, KEY_UP) - MATRIX_KEY(0, 2, KEY_LEFT) - MATRIX_KEY(0, 3, KEY_VOLUMEUP) - MATRIX_KEY(1, 0, KEY_FN_F2) - MATRIX_KEY(1, 1, KEY_RIGHT) - MATRIX_KEY(1, 2, KEY_DOWN) - MATRIX_KEY(1, 3, KEY_VOLUMEDOWN) - MATRIX_KEY(2, 3, KEY_ENTER) - MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS) - MATRIX_KEY(4, 1, KEY_UP) - MATRIX_KEY(4, 2, KEY_LEFT) - MATRIX_KEY(4, 3, KEY_HOME) - MATRIX_KEY(4, 4, KEY_FN_F3) - MATRIX_KEY(5, 0, KEY_CAMERA) - MATRIX_KEY(5, 1, KEY_RIGHT) - MATRIX_KEY(5, 2, KEY_DOWN) - MATRIX_KEY(5, 3, KEY_BACK) - MATRIX_KEY(5, 4, KEY_MENU) - >; - keypad,num-rows = <6>; - keypad,num-columns = <5>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8660.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-msm8660.dtsi deleted file mode 100644 index 8c65e0d82..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8660.dtsi +++ /dev/null @@ -1,416 +0,0 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" - -#include -#include -#include -#include - -/ { - model = "Qualcomm MSM8660"; - compatible = "qcom,msm8660"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu-pmu { - compatible = "qcom,scorpion-mp-pmu"; - interrupts = <1 9 0x304>; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2080000 { - compatible = "qcom,msm-8660-qgic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02080000 0x1000 >, - < 0x02081000 0x1000 >; - }; - - timer@2000000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; - reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x40000>; - }; - - tlmm: pinctrl@800000 { - compatible = "qcom,msm8660-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8660"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - gsbi12: gsbi@19c00000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <12>; - reg = <0x19c00000 0x100>; - clocks = <&gcc GSBI12_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi12_serial: serial@19c40000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x19c40000 0x1000>, - <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_NONE>; - clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - gsbi12_i2c: i2c@19c80000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_NONE>; - clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic@0 { - compatible = "qcom,pm8058"; - interrupt-parent = <&tlmm>; - interrupts = <88 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pm8058_gpio: gpio@150 { - compatible = "qcom,pm8058-gpio", - "qcom,ssbi-gpio"; - reg = <0x150>; - interrupt-parent = <&pmicintc>; - interrupts = <192 IRQ_TYPE_NONE>, - <193 IRQ_TYPE_NONE>, - <194 IRQ_TYPE_NONE>, - <195 IRQ_TYPE_NONE>, - <196 IRQ_TYPE_NONE>, - <197 IRQ_TYPE_NONE>, - <198 IRQ_TYPE_NONE>, - <199 IRQ_TYPE_NONE>, - <200 IRQ_TYPE_NONE>, - <201 IRQ_TYPE_NONE>, - <202 IRQ_TYPE_NONE>, - <203 IRQ_TYPE_NONE>, - <204 IRQ_TYPE_NONE>, - <205 IRQ_TYPE_NONE>, - <206 IRQ_TYPE_NONE>, - <207 IRQ_TYPE_NONE>, - <208 IRQ_TYPE_NONE>, - <209 IRQ_TYPE_NONE>, - <210 IRQ_TYPE_NONE>, - <211 IRQ_TYPE_NONE>, - <212 IRQ_TYPE_NONE>, - <213 IRQ_TYPE_NONE>, - <214 IRQ_TYPE_NONE>, - <215 IRQ_TYPE_NONE>, - <216 IRQ_TYPE_NONE>, - <217 IRQ_TYPE_NONE>, - <218 IRQ_TYPE_NONE>, - <219 IRQ_TYPE_NONE>, - <220 IRQ_TYPE_NONE>, - <221 IRQ_TYPE_NONE>, - <222 IRQ_TYPE_NONE>, - <223 IRQ_TYPE_NONE>, - <224 IRQ_TYPE_NONE>, - <225 IRQ_TYPE_NONE>, - <226 IRQ_TYPE_NONE>, - <227 IRQ_TYPE_NONE>, - <228 IRQ_TYPE_NONE>, - <229 IRQ_TYPE_NONE>, - <230 IRQ_TYPE_NONE>, - <231 IRQ_TYPE_NONE>, - <232 IRQ_TYPE_NONE>, - <233 IRQ_TYPE_NONE>, - <234 IRQ_TYPE_NONE>, - <235 IRQ_TYPE_NONE>; - gpio-controller; - #gpio-cells = <2>; - - }; - - pm8058_mpps: mpps@50 { - compatible = "qcom,pm8058-mpp", - "qcom,ssbi-mpp"; - reg = <0x50>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&pmicintc>; - interrupts = - <128 IRQ_TYPE_NONE>, - <129 IRQ_TYPE_NONE>, - <130 IRQ_TYPE_NONE>, - <131 IRQ_TYPE_NONE>, - <132 IRQ_TYPE_NONE>, - <133 IRQ_TYPE_NONE>, - <134 IRQ_TYPE_NONE>, - <135 IRQ_TYPE_NONE>, - <136 IRQ_TYPE_NONE>, - <137 IRQ_TYPE_NONE>, - <138 IRQ_TYPE_NONE>, - <139 IRQ_TYPE_NONE>; - }; - - pwrkey@1c { - compatible = "qcom,pm8058-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - keypad@148 { - compatible = "qcom,pm8058-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 1>, <75 1>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - - rtc@1e8 { - compatible = "qcom,pm8058-rtc"; - reg = <0x1e8>; - interrupt-parent = <&pmicintc>; - interrupts = <39 1>; - allow-set-time; - }; - - vibrator@4a { - compatible = "qcom,pm8058-vib"; - reg = <0x4a>; - }; - }; - }; - - l2cc: clock-controller@2082000 { - compatible = "syscon"; - reg = <0x02082000 0x1000>; - }; - - rpm: rpm@104000 { - compatible = "qcom,rpm-msm8660"; - reg = <0x00104000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - clocks = <&gcc RPM_MSG_RAM_H_CLK>; - clock-names = "ram"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - pm8901-regulators { - compatible = "qcom,rpm-pm8901-regulators"; - - pm8901_l0: l0 {}; - pm8901_l1: l1 {}; - pm8901_l2: l2 {}; - pm8901_l3: l3 {}; - pm8901_l4: l4 {}; - pm8901_l5: l5 {}; - pm8901_l6: l6 {}; - - /* S0 and S1 Handled as SAW regulators by SPM */ - pm8901_s2: s2 {}; - pm8901_s3: s3 {}; - pm8901_s4: s4 {}; - - pm8901_lvs0: lvs0 {}; - pm8901_lvs1: lvs1 {}; - pm8901_lvs2: lvs2 {}; - pm8901_lvs3: lvs3 {}; - - pm8901_mvs: mvs {}; - }; - - pm8058-regulators { - compatible = "qcom,rpm-pm8058-regulators"; - - pm8058_l0: l0 {}; - pm8058_l1: l1 {}; - pm8058_l2: l2 {}; - pm8058_l3: l3 {}; - pm8058_l4: l4 {}; - pm8058_l5: l5 {}; - pm8058_l6: l6 {}; - pm8058_l7: l7 {}; - pm8058_l8: l8 {}; - pm8058_l9: l9 {}; - pm8058_l10: l10 {}; - pm8058_l11: l11 {}; - pm8058_l12: l12 {}; - pm8058_l13: l13 {}; - pm8058_l14: l14 {}; - pm8058_l15: l15 {}; - pm8058_l16: l16 {}; - pm8058_l17: l17 {}; - pm8058_l18: l18 {}; - pm8058_l19: l19 {}; - pm8058_l20: l20 {}; - pm8058_l21: l21 {}; - pm8058_l22: l22 {}; - pm8058_l23: l23 {}; - pm8058_l24: l24 {}; - pm8058_l25: l25 {}; - - pm8058_s0: s0 {}; - pm8058_s1: s1 {}; - pm8058_s2: s2 {}; - pm8058_s3: s3 {}; - pm8058_s4: s4 {}; - - pm8058_lvs0: lvs0 {}; - pm8058_lvs1: lvs1 {}; - - pm8058_ncp: ncp {}; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - no-1-8-v; - }; - - sdcc5: sdcc@12200000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12200000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8660", "syscon"; - reg = <0x1a400000 0x100>; - }; - }; - -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-msm8960-cdp.dts deleted file mode 100644 index b72a55462..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ /dev/null @@ -1,353 +0,0 @@ -#include - -#include "qcom-msm8960.dtsi" - -/ { - model = "Qualcomm MSM8960 CDP"; - compatible = "qcom,msm8960-cdp", "qcom,msm8960"; - - aliases { - serial0 = &gsbi5_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - gsbi@16400000 { - status = "ok"; - qcom,mode = ; - serial@16440000 { - status = "ok"; - }; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - }; - }; - - rpm@108000 { - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - vdd_ncp-supply = <&pm8921_l6>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l21_l23_l29-supply = <&pm8921_s8>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - pm8921_s1: s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s2: s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8921_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - pm8921_s4: s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = ; - }; - - pm8921_s7: s7 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s8: s8 { - regulator-always-on; - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* PMOS LDO */ - pm8921_l1: l1 { - regulator-always-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8921_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l3: l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - pm8921_l4: l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l5: l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l6: l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l7: l7 { - regulator-always-on; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l8: l8 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l9: l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l10: l10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l11: l11 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8921_l12: l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l16: l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - pm8921_l17: l17 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l18: l18 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - bias-pull-down; - }; - - pm8921_l21: l21 { - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8921_l22: l22 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - bias-pull-down; - }; - - pm8921_l23: l23 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l24: l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - pm8921_l25: l25 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - pm8921_lvs1: lvs1 { - bias-pull-down; - }; - - pm8921_lvs2: lvs2 { - bias-pull-down; - }; - - pm8921_lvs3: lvs3 { - bias-pull-down; - }; - - pm8921_lvs4: lvs4 { - bias-pull-down; - }; - - pm8921_lvs5: lvs5 { - bias-pull-down; - }; - - pm8921_lvs6: lvs6 { - bias-pull-down; - }; - - pm8921_lvs7: lvs7 { - bias-pull-down; - }; - - pm8921_ncp: ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; - }; - - gsbi@16000000 { - status = "ok"; - qcom,mode = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_default>; - spi@16080000 { - status = "ok"; - eth@0 { - compatible = "micrel,ks8851"; - reg = <0>; - interrupt-parent = <&msmgpio>; - interrupts = <90 8>; - spi-max-frequency = <5400000>; - vdd-supply = <&ext_l2>; - vdd-io-supply = <&pm8921_lvs6>; - reset-gpios = <&msmgpio 89 0>; - }; - }; - }; - - pinctrl@800000 { - spi1_default: spi1_default { - mux { - pins = "gpio6", "gpio7", "gpio9"; - function = "gsbi1"; - }; - - mosi { - pins = "gpio6"; - drive-strength = <12>; - bias-disable; - }; - - miso { - pins = "gpio7"; - drive-strength = <12>; - bias-disable; - }; - - cs { - pins = "gpio8"; - drive-strength = <12>; - bias-disable; - output-low; - }; - - clk { - pins = "gpio9"; - drive-strength = <12>; - bias-disable; - }; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - - ext_l2: gpio-regulator@91 { - compatible = "regulator-fixed"; - regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; - startup-delay-us = <10000>; - enable-active-high; - }; - }; -}; - -&pmicintc { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_VOLUMEUP) - MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) - MATRIX_KEY(0, 3, KEY_CAMERA) - >; - keypad,num-rows = <1>; - keypad,num-columns = <5>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8960.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-msm8960.dtsi deleted file mode 100644 index 288f56e0c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8960.dtsi +++ /dev/null @@ -1,324 +0,0 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" - -#include -#include -#include -#include - -/ { - model = "Qualcomm MSM8960"; - compatible = "qcom,msm8960"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - interrupts = <1 14 0x304>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - qcom,no-pc-write; - }; - - clocks { - cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "cxo_board"; - }; - - pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "pxo_board"; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "sleep_clk"; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-msm8960", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - msmgpio: pinctrl@800000 { - compatible = "qcom,msm8960-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-msm8960"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x2011000 0x1000>; - }; - - rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = <0 19 0>, <0 21 0>, <0 22 0>; - interrupt-names = "ack", "err", "wakeup"; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - }; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - gsbi5_serial: serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic@0 { - compatible = "qcom,pm8921"; - interrupt-parent = <&msmgpio>; - interrupts = <104 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - keypad@148 { - compatible = "qcom,pm8921-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 1>, <75 1>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - - rtc@11d { - compatible = "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 1>; - reg = <0x11d>; - allow-set-time; - }; - }; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8960", "syscon"; - reg = <0x1a400000 0x100>; - }; - - gsbi@16000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x16000000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - spi@16080000 { - compatible = "qcom,spi-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16080000 0x1000>; - interrupts = <0 147 0>; - spi-max-frequency = <24000000>; - cs-gpios = <&msmgpio 8 0>; - - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts deleted file mode 100644 index c0fb4a698..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ /dev/null @@ -1,262 +0,0 @@ -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "LGE MSM 8974 HAMMERHEAD"; - compatible = "lge,hammerhead", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - serial@f991d000 { - status = "ok"; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts deleted file mode 100644 index e7c1577d5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ /dev/null @@ -1,460 +0,0 @@ -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include - -/ { - model = "Sony Xperia Z1"; - compatible = "sony,xperia-honami", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - memory@0 { - reg = <0 0x40000000>, <0x40000000 0x40000000>; - device_type = "memory"; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - vin_5vs-supply = <&pm8941_5v>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - sdhci@f9824900 { - status = "ok"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "ok"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - i2c@f9924000 { - status = "ok"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <10>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - syna,sensor-type = <1>; - }; - }; - }; - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - ts_int_pin: touch-int { - pin { - pins = "gpio61"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - }; - }; - - dma-controller@f9944000 { - qcom,controlled-remotely; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio4", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - }; - - coincell@2800 { - status = "ok"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; - - pm8941@1 { - wled@d800 { - status = "ok"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974.dtsi deleted file mode 100644 index d2109475b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-msm8974.dtsi +++ /dev/null @@ -1,757 +0,0 @@ -/dts-v1/; - -#include -#include -#include -#include "skeleton.dtsi" - -/ { - model = "Qualcomm MSM8974"; - compatible = "qcom,msm8974"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss@08000000 { - reg = <0x08000000 0x5100000>; - no-map; - }; - - mba@00d100000 { - reg = <0x0d100000 0x100000>; - no-map; - }; - - reserved@0d200000 { - reg = <0x0d200000 0xa00000>; - no-map; - }; - - adsp@0dc00000 { - reg = <0x0dc00000 0x1900000>; - no-map; - }; - - venus@0f500000 { - reg = <0x0f500000 0x500000>; - no-map; - }; - - smem_region: smem@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - - tz@0fc00000 { - reg = <0x0fc00000 0x160000>; - no-map; - }; - - rfsa@0fd60000 { - reg = <0x0fd60000 0x20000>; - no-map; - }; - - rmtfs@0fd80000 { - reg = <0x0fd80000 0x180000>; - no-map; - }; - - unused@0ff00000 { - reg = <0x0ff00000 0x10100000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - interrupts = <1 9 0xf04>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@2 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; - }; - - cpu@3 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <150>; - exit-latency-us = <200>; - min-residency-us = <2000>; - }; - }; - }; - - thermal-zones { - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 7 0xf04>; - }; - - clocks { - xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <19200000>; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupt-parent = <&intc>; - interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcnss { - compatible = "qcom,smp2p"; - qcom,smem = <451>, <431>; - - interrupt-parent = <&intc>; - interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-2 = <&apcs 8 9>; - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - modem_smsm: modem@1 { - reg = <1>; - interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - adsp_smsm: adsp@2 { - reg = <2>; - interrupts = <0 157 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@7 { - reg = <7>; - interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - qfprom: qfprom@fc4bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; - }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; - }; - }; - - tsens: thermal-sensor@fc4a8000 { - compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #thermal-sensor-cells = <1>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = <0 9 0x4>; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = <0 10 0x4>; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = <0 11 0x4>; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = <0 12 0x4>; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = <0 13 0x4>; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = <0 14 0x4>; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw0: power-controller@f9089000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; - - saw1: power-controller@f9099000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; - }; - - saw2: power-controller@f90a9000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw3: power-controller@f90b9000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: clock-controller@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; - }; - - acc1: clock-controller@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; - }; - - acc2: clock-controller@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; - }; - - acc3: clock-controller@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; - }; - - tcsr_mutex_block: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfd8c0000 0x6000>; - }; - - tcsr_mutex: tcsr-mutex { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - - #hwlock-cells = <1>; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - blsp1_uart1: serial@f991d000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991d000 0x1000>; - interrupts = <0 107 0x0>; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = <0 108 0x0>; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 0>, <0 138 0>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 125 0>, <0 221 0>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8974-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 208 0>; - }; - - i2c@f9924000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9924000 0x1000>; - interrupts = <0 96 IRQ_TYPE_NONE>; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c8: i2c@f9964000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9964000 0x1000>; - interrupts = <0 102 IRQ_TYPE_NONE>; - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c11: i2c@f9967000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9967000 0x1000>; - interrupts = <0 105 IRQ_TYPE_NONE>; - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; - dma-names = "tx", "rx"; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = <0 190 0>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - blsp2_dma: dma-controller@f9944000 { - compatible = "qcom,bam-v1.4.0"; - reg = <0xf9944000 0x19000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - }; - - smd { - compatible = "qcom,smd"; - - modem { - interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 12>; - qcom,smd-edge = <0>; - }; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - pm8841-regulators { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 {}; - pm8841_s2: s2 {}; - pm8841_s3: s3 {}; - pm8841_s4: s4 {}; - pm8841_s5: s5 {}; - pm8841_s6: s6 {}; - pm8841_s7: s7 {}; - pm8841_s8: s8 {}; - }; - - pm8941-regulators { - compatible = "qcom,rpm-pm8941-regulators"; - - pm8941_s1: s1 {}; - pm8941_s2: s2 {}; - pm8941_s3: s3 {}; - pm8941_5v: s4 {}; - - pm8941_l1: l1 {}; - pm8941_l2: l2 {}; - pm8941_l3: l3 {}; - pm8941_l4: l4 {}; - pm8941_l5: l5 {}; - pm8941_l6: l6 {}; - pm8941_l7: l7 {}; - pm8941_l8: l8 {}; - pm8941_l9: l9 {}; - pm8941_l10: l10 {}; - pm8941_l11: l11 {}; - pm8941_l12: l12 {}; - pm8941_l13: l13 {}; - pm8941_l14: l14 {}; - pm8941_l15: l15 {}; - pm8941_l16: l16 {}; - pm8941_l17: l17 {}; - pm8941_l18: l18 {}; - pm8941_l19: l19 {}; - pm8941_l20: l20 {}; - pm8941_l21: l21 {}; - pm8941_l22: l22 {}; - pm8941_l23: l23 {}; - pm8941_l24: l24 {}; - - pm8941_lvs1: lvs1 {}; - pm8941_lvs2: lvs2 {}; - pm8941_lvs3: lvs3 {}; - - pm8941_5vs1: 5vs1 {}; - pm8941_5vs2: 5vs2 {}; - }; - }; - }; - }; - - vreg_boost: vreg-boost { - compatible = "regulator-fixed"; - - regulator-name = "vreg-boost"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - regulator-always-on; - regulator-boot-on; - - gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&boost_bypass_n_pin>; - }; - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-pm8841.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-pm8841.dtsi deleted file mode 100644 index 0512f6459..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-pm8841.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -#include -#include - -&spmi_bus { - - pm8841_0: pm8841@4 { - compatible = "qcom,pm8841", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8841_mpps: mpps@a000 { - compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <4 0xa0 0 IRQ_TYPE_NONE>, - <4 0xa1 0 IRQ_TYPE_NONE>, - <4 0xa2 0 IRQ_TYPE_NONE>, - <4 0xa3 0 IRQ_TYPE_NONE>; - }; - - temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; - }; - }; - - pm8841_1: pm8841@5 { - compatible = "qcom,pm8841", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-pm8941.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-pm8941.dtsi deleted file mode 100644 index f8eb5e31c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-pm8941.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -#include -#include -#include - -&spmi_bus { - - pm8941_0: pm8941@0 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, - <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; - reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - }; - - charger@1000 { - compatible = "qcom,pm8941-charger"; - reg = <0x1000>; - interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "chg-done", - "chg-fast", - "chg-trkl", - "bat-temp-ok", - "bat-present", - "chg-gone", - "usb-valid", - "dc-valid"; - }; - - pm8941_gpios: gpios@c000 { - compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>, - <0 0xcc 0 IRQ_TYPE_NONE>, - <0 0xcd 0 IRQ_TYPE_NONE>, - <0 0xce 0 IRQ_TYPE_NONE>, - <0 0xcf 0 IRQ_TYPE_NONE>, - <0 0xd0 0 IRQ_TYPE_NONE>, - <0 0xd1 0 IRQ_TYPE_NONE>, - <0 0xd2 0 IRQ_TYPE_NONE>, - <0 0xd3 0 IRQ_TYPE_NONE>, - <0 0xd4 0 IRQ_TYPE_NONE>, - <0 0xd5 0 IRQ_TYPE_NONE>, - <0 0xd6 0 IRQ_TYPE_NONE>, - <0 0xd7 0 IRQ_TYPE_NONE>, - <0 0xd8 0 IRQ_TYPE_NONE>, - <0 0xd9 0 IRQ_TYPE_NONE>, - <0 0xda 0 IRQ_TYPE_NONE>, - <0 0xdb 0 IRQ_TYPE_NONE>, - <0 0xdc 0 IRQ_TYPE_NONE>, - <0 0xdd 0 IRQ_TYPE_NONE>, - <0 0xde 0 IRQ_TYPE_NONE>, - <0 0xdf 0 IRQ_TYPE_NONE>, - <0 0xe0 0 IRQ_TYPE_NONE>, - <0 0xe1 0 IRQ_TYPE_NONE>, - <0 0xe2 0 IRQ_TYPE_NONE>, - <0 0xe3 0 IRQ_TYPE_NONE>; - - boost_bypass_n_pin: boost-bypass { - pins = "gpio21"; - function = "normal"; - }; - }; - - pm8941_mpps: mpps@a000 { - compatible = "qcom,pm8941-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; - }; - - pm8941_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8941_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8941_vadc: vadc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - die_temp { - reg = ; - }; - ref_625mv { - reg = ; - }; - ref_1250v { - reg = ; - }; - ref_gnd { - reg = ; - }; - ref_vdd { - reg = ; - }; - }; - - pm8941_iadc: iadc@3600 { - compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc"; - reg = <0x3600>; - interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; - qcom,external-resistor-micro-ohms = <10000>; - }; - - coincell@2800 { - compatible = "qcom,pm8941-coincell"; - reg = <0x2800>; - status = "disabled"; - }; - }; - - pm8941_1: pm8941@1 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8941_wled: wled@d800 { - compatible = "qcom,pm8941-wled"; - reg = <0xd800>; - label = "backlight"; - - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/qcom-pma8084.dtsi b/software/linux/kernel/arch/arm/boot/dts/qcom-pma8084.dtsi deleted file mode 100644 index 82d258094..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/qcom-pma8084.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -#include -#include -#include - -&spmi_bus { - - pma8084_0: pma8084@0 { - compatible = "qcom,pma8084", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, - <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; - reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - }; - - pma8084_gpios: gpios@c000 { - compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>, - <0 0xcc 0 IRQ_TYPE_NONE>, - <0 0xcd 0 IRQ_TYPE_NONE>, - <0 0xce 0 IRQ_TYPE_NONE>, - <0 0xcf 0 IRQ_TYPE_NONE>, - <0 0xd0 0 IRQ_TYPE_NONE>, - <0 0xd1 0 IRQ_TYPE_NONE>, - <0 0xd2 0 IRQ_TYPE_NONE>, - <0 0xd3 0 IRQ_TYPE_NONE>, - <0 0xd4 0 IRQ_TYPE_NONE>, - <0 0xd5 0 IRQ_TYPE_NONE>; - }; - - pma8084_mpps: mpps@a000 { - compatible = "qcom,pma8084-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; - }; - - pma8084_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - #thermal-sensor-cells = <0>; - io-channels = <&pma8084_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - }; - - pma8084_vadc: vadc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - io-channel-ranges; - - die_temp { - reg = ; - }; - ref_625mv { - reg = ; - }; - ref_1250v { - reg = ; - }; - ref_buf_625mv { - reg = ; - }; - ref_gnd { - reg = ; - }; - ref_vdd { - reg = ; - }; - }; - }; - - pma8084_1: pma8084@1 { - compatible = "qcom,pma8084", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r7s72100-genmai.dts b/software/linux/kernel/arch/arm/boot/dts/r7s72100-genmai.dts deleted file mode 100644 index 118a8e2b8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r7s72100-genmai.dts +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Device Tree Source for the Genmai board - * - * Copyright (C) 2013-14 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r7s72100.dtsi" - -/ { - model = "Genmai"; - compatible = "renesas,genmai", "renesas,r7s72100"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x08000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&extal_clk { - clock-frequency = <13330000>; -}; - -&usb_x1_clk { - clock-frequency = <48000000>; -}; - -&mtu2 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "renesas,24c128"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&scif2 { - status = "okay"; -}; - -&spi4 { - status = "okay"; - - codec: codec@0 { - compatible = "wlf,wm8978"; - reg = <0>; - spi-max-frequency = <5000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r7s72100-rskrza1.dts b/software/linux/kernel/arch/arm/boot/dts/r7s72100-rskrza1.dts deleted file mode 100644 index e5dea5bb4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Device Tree Source for the RZ/A1H RSK board - * - * Copyright (C) 2016 Renesas Electronics - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r7s72100.dtsi" - -/ { - model = "RSKRZA1"; - compatible = "renesas,rskrza1", "renesas,r7s72100"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - - memory@8000000 { - device_type = "memory"; - reg = <0x08000000 0x02000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&extal_clk { - clock-frequency = <13330000>; -}; - -&usb_x1_clk { - clock-frequency = <48000000>; -}; - -&mtu2 { - status = "okay"; -}; - -ðer { - status = "okay"; - renesas,no-ether-link; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&scif2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r7s72100.dtsi b/software/linux/kernel/arch/arm/boot/dts/r7s72100.dtsi deleted file mode 100644 index fb9ef9ca1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r7s72100.dtsi +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Device Tree Source for the r7s72100 SoC - * - * Copyright (C) 2013-14 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r7s72100"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - }; - - clocks { - ranges; - #address-cells = <1>; - #size-cells = <1>; - - /* External clocks */ - extal_clk: extal { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; - - usb_x1_clk: usb_x1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - /* If clk present, value must be set by board */ - clock-frequency = <0>; - }; - - /* Fixed factor clocks */ - b_clk: b { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <3>; - }; - p1_clk: p1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <6>; - }; - p0_clk: p0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R7S72100_CLK_PLL>; - clock-mult = <1>; - clock-div = <12>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@fcfe0000 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-cpg-clocks", - "renesas,rz-cpg-clocks"; - reg = <0xfcfe0000 0x18>; - clocks = <&extal_clk>, <&usb_x1_clk>; - clock-output-names = "pll", "i", "g"; - #power-domain-cells = <0>; - }; - - /* MSTP clocks */ - mstp3_clks: mstp3_clks@fcfe0420 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0420 4>; - clocks = <&p0_clk>; - clock-indices = ; - clock-output-names = "mtu2"; - }; - - mstp4_clks: mstp4_clks@fcfe0424 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0424 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, - <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; - clock-indices = < - R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 - R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 - >; - clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; - }; - - mstp7_clks: mstp7_clks@fcfe0430 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0430 4>; - clocks = <&p0_clk>; - clock-indices = ; - clock-output-names = "ether"; - }; - - mstp9_clks: mstp9_clks@fcfe0438 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe0438 4>; - clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; - clock-indices = < - R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 - >; - clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; - }; - - mstp10_clks: mstp10_clks@fcfe043c { - #clock-cells = <1>; - compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xfcfe043c 4>; - clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, - <&p1_clk>; - clock-indices = < - R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 - R7S72100_CLK_SPI4 - >; - clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <400000000>; - }; - }; - - scif0: serial@e8007000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8007000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif1: serial@e8007800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8007800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif2: serial@e8008000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8008000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif3: serial@e8008800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8008800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif4: serial@e8009000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8009000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif5: serial@e8009800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe8009800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif6: serial@e800a000 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe800a000 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif7: serial@e800a800 { - compatible = "renesas,scif-r7s72100", "renesas,scif"; - reg = <0xe800a800 64>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - spi0: spi@e800c800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800c800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI0>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e800d000 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800d000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI1>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@e800d800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800d800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI2>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@e800e000 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800e000 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI3>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@e800e800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800e800 0x24>; - interrupts = , - , - ; - interrupt-names = "error", "rx", "tx"; - clocks = <&mstp10_clks R7S72100_CLK_SPI4>; - power-domains = <&cpg_clocks>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@e8201000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8201000 0x1000>, - <0xe8202000 0x1000>; - }; - - i2c0: i2c@fcfee000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C0>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c1: i2c@fcfee400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee400 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C1>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c2: i2c@fcfee800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee800 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C2>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c3: i2c@fcfeec00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfeec00 0x44>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp9_clks R7S72100_CLK_I2C3>; - clock-frequency = <100000>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = ; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - ether: ethernet@e8203000 { - compatible = "renesas,ether-r7s72100"; - reg = <0xe8203000 0x800>, - <0xe8204800 0x200>; - interrupts = ; - clocks = <&mstp7_clks R7S72100_CLK_ETHER>; - power-domains = <&cpg_clocks>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/software/linux/kernel/arch/arm/boot/dts/r8a73a4-ape6evm.dts deleted file mode 100644 index ec7c86e06..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Device Tree Source for the APE6EVM board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a73a4.dtsi" -#include -#include - -/ { - model = "APE6EVM"; - compatible = "renesas,ape6evm", "renesas,r8a73a4"; - - aliases { - serial0 = &scifa0; - }; - - chosen { - bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_mmc0: regulator-mmc0 { - compatible = "regulator-fixed"; - regulator-name = "MMC0 Vcc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vcc_sdhi0: regulator-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */ - ape6evm_fixed_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ape6evm_fixed_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 28 GPIO_ACTIVE_HIGH>; - label = "GNSS_EN"; - }; - led2 { - gpios = <&pfc 126 GPIO_ACTIVE_HIGH>; - label = "NFC_NRST"; - }; - led3 { - gpios = <&pfc 132 GPIO_ACTIVE_HIGH>; - label = "GNSS_NRST"; - }; - led4 { - gpios = <&pfc 232 GPIO_ACTIVE_HIGH>; - label = "BT_WAKEUP"; - }; - led5 { - gpios = <&pfc 250 GPIO_ACTIVE_HIGH>; - label = "STROBE"; - }; - led6 { - gpios = <&pfc 288 GPIO_ACTIVE_HIGH>; - label = "BBRESETOUT"; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&keyboard_pins>; - - zero-key { - gpios = <&pfc 324 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S16"; - wakeup-source; - }; - - menu-key { - gpios = <&pfc 325 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S17"; - }; - - home-key { - gpios = <&pfc 326 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S18"; - }; - - back-key { - gpios = <&pfc 327 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S19"; - }; - - volup-key { - gpios = <&pfc 328 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S20"; - }; - - voldown-key { - gpios = <&pfc 329 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "S21"; - }; - }; -}; - -&i2c5 { - status = "okay"; - vdd_dvfs: regulator@1b { - compatible = "maxim,max8973"; - reg = <0x1b>; - - regulator-min-microvolt = <935000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1950000 1115000 - 1462500 995000 - >; - voltage-tolerance = <1>; /* 1% */ -}; - -&bsc { - ethernet@8000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x08000000 0x1000>; - interrupt-parent = <&irqc1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&ape6evm_fixed_3v3>; - vddvario-supply = <&ape6evm_fixed_1v8>; - }; -}; - -&cmt1 { - status = "okay"; -}; - -&pfc { - scifa0_pins: scifa0 { - groups = "scifa0_data"; - function = "scifa0"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8", "mmc0_ctrl"; - function = "mmc0"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - function = "sdhi0"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; - - keyboard_pins: keyboard { - pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328", - "PORT329"; - bias-pull-up; - }; -}; - -&mmcif0 { - vmmc-supply = <&vcc_mmc0>; - bus-width = <8>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "okay"; -}; - -&scifa0 { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - vmmc-supply = <&vcc_sdhi0>; - bus-width = <4>; - toshiba,mmc-wrprotect-disable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi0_pins>; - status = "okay"; -}; - -&sdhi1 { - vmmc-supply = <&ape6evm_fixed_3v3>; - bus-width = <4>; - broken-cd; - toshiba,mmc-wrprotect-disable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a73a4.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a73a4.dtsi deleted file mode 100644 index ca8672778..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a73a4.dtsi +++ /dev/null @@ -1,895 +0,0 @@ -/* - * Device Tree Source for the r8a73a4 SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a73a4"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller@0 { - compatible = "cache"; - reg = <0>; - clocks = <&cpg_clocks R8A73A4_CLK_Z>; - power-domains = <&pd_a3sm>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller@100 { - compatible = "cache"; - reg = <0x100>; - clocks = <&cpg_clocks R8A73A4_CLK_Z2>; - power-domains = <&pd_a3km>; - cache-unified; - cache-level = <2>; - }; - }; - - ptm { - compatible = "arm,coresight-etm3x"; - power-domains = <&pd_d4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - dbsc1: memory-controller@e6790000 { - compatible = "renesas,dbsc-r8a73a4"; - reg = <0 0xe6790000 0 0x10000>; - power-domains = <&pd_a3bc>; - }; - - dbsc2: memory-controller@e67a0000 { - compatible = "renesas,dbsc-r8a73a4"; - reg = <0 0xe67a0000 0 0x10000>; - power-domains = <&pd_a3bc>; - }; - - dmac: dma-multiplexer { - compatible = "renesas,shdma-mux"; - #dma-cells = <1>; - dma-channels = <20>; - dma-requests = <256>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dma0: dma-controller@e6700020 { - compatible = "renesas,shdma-r8a73a4"; - reg = <0 0xe6700020 0 0x89e0>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19"; - clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; - power-domains = <&pd_a3sp>; - }; - }; - - i2c5: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; - power-domains = <&pd_a3sp>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; - power-domains = <&pd_c4>; - }; - - irqc1: interrupt-controller@e61c0200 { - compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0200 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; - power-domains = <&pd_c4>; - }; - - pfc: pfc@e6050000 { - compatible = "renesas,pfc-r8a73a4"; - reg = <0 0xe6050000 0 0x9000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = - <&pfc 0 0 31>, <&pfc 32 32 9>, - <&pfc 64 64 22>, <&pfc 96 96 31>, - <&pfc 128 128 7>, <&pfc 160 160 19>, - <&pfc 192 192 31>, <&pfc 224 224 27>, - <&pfc 256 256 28>, <&pfc 288 288 21>, - <&pfc 320 320 10>; - interrupts-extended = - <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, - <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, - <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, - <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, - <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, - <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, - <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, - <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, - <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, - <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, - <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, - <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, - <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, - <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, - <&irqc1 24 0>, <&irqc1 25 0>; - power-domains = <&pd_c5>; - }; - - thermal@e61f0000 { - compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, - <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; - interrupts = ; - clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; - power-domains = <&pd_c5>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c3: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6530000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c4: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6540000 0 0x428>; - interrupts = ; - clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c6: i2c@e6550000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6550000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c7: i2c@e6560000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6560000 0 0x428>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c8: i2c@e6570000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; - reg = <0 0xe6570000 0 0x428>; - interrupts = ; - clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; - reg = <0 0xe6c40000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; - reg = <0 0xe6c50000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb3: serial@e6cf0000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6cf0000 0 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; - clock-names = "fck"; - power-domains = <&pd_c4>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee100000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee120000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a73a4"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - }; - - bsc: bus@fec10000 { - compatible = "renesas,bsc-r8a73a4", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - reg = <0 0xfec10000 0 0x400>; - clocks = <&zb_clk>; - power-domains = <&pd_c4>; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clocks */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a73a4-cpg-clocks"; - reg = <0 0xe6150000 0 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll2s", "pll2h", "z", "z2", - "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; - }; - - /* Variable factor clocks (DIV6) */ - zb_clk: zb_clk@e6150010 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150010 0 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; - #clock-cells = <0>; - clock-output-names = "zb"; - }; - sdhi0_clk: sdhi0ck@e6150074 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150074 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - sdhi1_clk: sdhi1ck@e6150078 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - sdhi2_clk: sdhi2ck@e615007c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - mmc1_clk: mmc1@e6150244 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150244 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - }; - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150008 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615000c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk3_clk: vclk3@e615001c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615001c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk4_clk: vclk4@e6150014 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150014 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - vclk5_clk: vclk5@e6150034 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150034 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150018 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&fsiack_clk>, <0>; - #clock-cells = <0>; - }; - fsib_clk: fsib@e6150090 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150090 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&fsibck_clk>, <0>; - #clock-cells = <0>; - }; - mp_clk: mp@e6150080 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150080 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - m4_clk: m4@e6150098 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150098 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; - #clock-cells = <0>; - }; - hsi_clk: hsi@e615026c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, - <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; - #clock-cells = <0>; - }; - spuv_clk: spuv@e6150094 { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150094 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - main_div2_clk: main_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll0_div2_clk: pll0_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - extal1_div2_clk: extal1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&extal1_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 - R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 - R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 - R8A73A4_CLK_DMAC - >; - clock-output-names = - "scifa0", "scifa1", "scifb0", "scifb1", - "scifb2", "scifb3", "dmac"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, - <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, - <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, - <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks - R8A73A4_CLK_HP>, <&cpg_clocks - R8A73A4_CLK_HP>, <&extalr_clk>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 - R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 - R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 - R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 - R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 - R8A73A4_CLK_CMT1 - >; - clock-output-names = - "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "iic6", "iic7", "iic0", "iic1", - "cmt1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&main_div2_clk>, - <&cpg_clocks R8A73A4_CLK_HP>, - <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5 - R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3 - >; - clock-output-names = - "irqc", "iic5", "iic4", "iic3"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 - >; - clock-output-names = - "thermal", "iic8"; - }; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; - reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_c4: c4@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sg: a3sg@16 { - reg = <16>; - #power-domain-cells = <0>; - }; - - pd_a3ex: a3ex@17 { - reg = <17>; - #power-domain-cells = <0>; - }; - - pd_a3sp: a3sp@18 { - reg = <18>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2us: a2us@19 { - reg = <19>; - #power-domain-cells = <0>; - }; - }; - - pd_a3sm: a3sm@20 { - reg = <20>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2sl: a2sl@21 { - reg = <21>; - #power-domain-cells = <0>; - }; - }; - - pd_a3km: a3km@22 { - reg = <22>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2kl: a2kl@23 { - reg = <23>; - #power-domain-cells = <0>; - }; - }; - }; - - pd_c4ma: c4ma@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_c4cl: c4cl@2 { - reg = <2>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@3 { - reg = <3>; - #power-domain-cells = <0>; - }; - - pd_a4bc: a4bc@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3bc: a3bc@5 { - reg = <5>; - #power-domain-cells = <0>; - }; - }; - - pd_a4l: a4l@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - - pd_a4lc: a4lc@7 { - reg = <7>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3mp: a3mp@9 { - reg = <9>; - #power-domain-cells = <0>; - }; - - pd_a3vc: a3vc@10 { - reg = <10>; - #power-domain-cells = <0>; - }; - }; - - pd_a4sf: a4sf@11 { - reg = <11>; - #power-domain-cells = <0>; - }; - - pd_a3r: a3r@12 { - reg = <12>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2rv: a2rv@13 { - reg = <13>; - #power-domain-cells = <0>; - }; - - pd_a2is: a2is@14 { - reg = <14>; - #power-domain-cells = <0>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7740-armadillo800eva.dts deleted file mode 100644 index 788507542..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Device Tree Source for the armadillo 800 eva board - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7740.dtsi" -#include -#include -#include -#include - -/ { - model = "armadillo 800 eva"; - compatible = "renesas,armadillo800eva", "renesas,r8a7740"; - - aliases { - serial0 = &scifa1; - }; - - chosen { - bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=dhcp rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sdhi0>; - - enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; - gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; - states = <3300000 0 - 1800000 1>; - - enable-active-high; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5.0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - keyboard { - compatible = "gpio-keys"; - - power-key { - gpios = <&pfc 99 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - wakeup-source; - }; - - back-key { - gpios = <&pfc 100 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4"; - }; - - menu-key { - gpios = <&pfc 97 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW5"; - }; - - home-key { - gpios = <&pfc 98 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW6"; - }; - }; - - leds { - compatible = "gpio-leds"; - led3 { - gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; - label = "LED4"; - }; - led5 { - gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; - label = "LED5"; - }; - led6 { - gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - }; - - i2c2: i2c-2 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */ - &pfc 91 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,delay-us = <5>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; - brightness-levels = <0 1 2 4 8 16 32 64 128 255>; - default-brightness-level = <9>; - pinctrl-0 = <&backlight_pins>; - pinctrl-names = "default"; - power-supply = <®_5p0v>; - enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - bitclock-inversion; - }; - - simple-audio-card,codec { - sound-dai = <&wm8978>; - bitclock-master; - frame-master; - system-clock-frequency = <12288000>; - }; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy0>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&extal1_clk { - clock-frequency = <24000000>; -}; -&extal2_clk { - clock-frequency = <48000000>; -}; -&fsibck_clk { - clock-frequency = <12288000>; -}; -&cpg_clocks { - renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */ -}; - -&cmt1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupt-parent = <&irqpin1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&st1232_pins>; - pinctrl-names = "default"; - gpios = <&pfc 166 GPIO_ACTIVE_LOW>; - }; - - wm8978: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; -}; - -&i2c2 { - status = "okay"; - rtc@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; -}; - -&pfc { - pinctrl-0 = <&lcd0_pins>; - pinctrl-names = "default"; - - ether_pins: ether { - groups = "gether_mii", "gether_int"; - function = "gether"; - }; - - scifa1_pins: scifa1 { - groups = "scifa1_data"; - function = "scifa1"; - }; - - st1232_pins: touchscreen { - groups = "intc_irq10"; - function = "intc"; - }; - - backlight_pins: backlight { - groups = "tpu0_to2_1"; - function = "tpu0"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8_1", "mmc0_ctrl_1"; - function = "mmc0"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; - function = "sdhi0"; - }; - - fsia_pins: sounda { - groups = "fsia_sclk_in", "fsia_mclk_out", - "fsia_data_in_1", "fsia_data_out_0"; - function = "fsia"; - }; - - lcd0_pins: lcd0 { - groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; - function = "lcd0"; - - /* DBGMD/LCDC0/FSIA MUX */ - gpio-hog; - gpios = <176 0>; - output-high; - }; -}; - -&tpu { - status = "okay"; -}; - -&mmcif0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&scifa1 { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - bus-width = <4>; - cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&tmu0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7740.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a7740.dtsi deleted file mode 100644 index 159e04eb1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7740.dtsi +++ /dev/null @@ -1,724 +0,0 @@ -/* - * Device Tree Source for the r8a7740 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -#include -#include -#include - -/ { - compatible = "renesas,r8a7740"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - clock-frequency = <800000000>; - power-domains = <&pd_a3sm>; - next-level-cache = <&L2>; - }; - }; - - gic: interrupt-controller@c2800000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xc2800000 0x1000>, - <0xc2000000 0x1000>; - }; - - L2: cache-controller@f0100000 { - compatible = "arm,pl310-cache"; - reg = <0xf0100000 0x1000>; - interrupts = ; - power-domains = <&pd_a3sm>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,shared-override; - cache-unified; - cache-level = <2>; - }; - - dbsc3: memory-controller@fe400000 { - compatible = "renesas,dbsc3-r8a7740"; - reg = <0xfe400000 0x400>; - power-domains = <&pd_a4s>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - ptm { - compatible = "arm,coresight-etm3x"; - power-domains = <&pd_d4>; - }; - - cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; - reg = <0xe6138000 0x170>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - - renesas,channels-mask = <0x3f>; - - status = "disabled"; - }; - - /* irqpin0: IRQ0 - IRQ7 */ - irqpin0: interrupt-controller@e6900000 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900000 4>, - <0xe6900010 4>, - <0xe6900020 1>, - <0xe6900040 1>, - <0xe6900060 1>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin1: IRQ8 - IRQ15 */ - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin2: IRQ16 - IRQ23 */ - irqpin2: interrupt-controller@e6900008 { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900008 4>, - <0xe6900018 4>, - <0xe6900028 1>, - <0xe6900048 1>, - <0xe6900068 1>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - /* irqpin3: IRQ24 - IRQ31 */ - irqpin3: interrupt-controller@e690000c { - compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe690000c 4>, - <0xe690001c 4>, - <0xe690002c 1>, - <0xe690004c 1>, - <0xe690006c 1>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; - - ether: ethernet@e9a00000 { - compatible = "renesas,gether-r8a7740"; - reg = <0xe9a00000 0x800>, - <0xe9a01800 0x800>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_GETHER>; - power-domains = <&pd_a4s>; - phy-mode = "mii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@fff20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; - reg = <0xfff20000 0x425>; - interrupts = ; - clocks = <&mstp1_clks R8A7740_CLK_IIC0>; - power-domains = <&pd_a4r>; - status = "disabled"; - }; - - i2c1: i2c@e6c20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; - reg = <0xe6c20000 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c40000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c50000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c60000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c70000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa4: serial@e6c80000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6c80000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa5: serial@e6cb0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cb0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa6: serial@e6cc0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cc0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa7: serial@e6cd0000 { - compatible = "renesas,scifa-r8a7740", "renesas,scifa"; - reg = <0xe6cd0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb: serial@e6c30000 { - compatible = "renesas,scifb-r8a7740", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - pfc: pfc@e6050000 { - compatible = "renesas,pfc-r8a7740"; - reg = <0xe6050000 0x8000>, - <0xe605800c 0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 0 212>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - power-domains = <&pd_c5>; - }; - - tpu: pwm@e6600000 { - compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x100>; - clocks = <&mstp3_clks R8A7740_CLK_TPU0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - #pwm-cells = <3>; - }; - - mmcif0: mmc@e6bd0000 { - compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; - reg = <0xe6bd0000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_MMC>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - sdhi0: sd@e6850000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6850000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: sd@e6860000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6860000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi2: sd@e6870000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6870000 0x100>; - interrupts = ; - clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sh_fsi2: sound@fe1f0000 { - #sound-dai-cells = <1>; - compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; - reg = <0xfe1f0000 0x400>; - interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; - power-domains = <&pd_a4mp>; - status = "disabled"; - }; - - tmu0: timer@fff80000 { - compatible = "renesas,tmu-r8a7740", "renesas,tmu"; - reg = <0xfff80000 0x2c>; - interrupts = , - , - ; - clocks = <&mstp1_clks R8A7740_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&pd_a4r>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@fff90000 { - compatible = "renesas,tmu-r8a7740", "renesas,tmu"; - reg = <0xfff90000 0x2c>; - interrupts = , - , - ; - clocks = <&mstp1_clks R8A7740_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&pd_a4r>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clock */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - dv_clk: dv { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - fmsick_clk: fmsick { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fmsock_clk: fmsock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7740-cpg-clocks"; - reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extalr_clk>; - #clock-cells = <1>; - clock-output-names = "system", "pllc0", "pllc1", - "pllc2", "r", - "usb24s", - "i", "zg", "b", "m1", "hp", - "hpp", "usbp", "s", "zb", "m3", - "cp"; - }; - - /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150008 4>; - clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, - <&extal1_div2_clk>, <&extalr_clk>, <0>, - <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615000c 4>; - clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, - <&extal1_div2_clk>, <&extalr_clk>, <0>, - <0>; - #clock-cells = <0>; - }; - fmsi_clk: fmsi@e6150010 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150010 4>; - clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fmso_clk: fmso@e6150014 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150014 4>; - clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150018 4>; - clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; - #clock-cells = <0>; - }; - sub_clk: sub@e6150080 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150080 4>; - clocks = <&pllc1_div2_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; - #clock-cells = <0>; - }; - spu_clk: spu@e6150084 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150084 4>; - clocks = <&pllc1_div2_clk>, - <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; - #clock-cells = <0>; - }; - vou_clk: vou@e6150088 { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150088 4>; - clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, - <0>; - #clock-cells = <0>; - }; - stpro_clk: stpro@e615009c { - compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615009c 4>; - clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pllc1_div2_clk: pllc1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - extal1_div2_clk: extal1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&extal1_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - subck_clks: subck_clks@e6150080 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150080 4>; - clocks = <&sub_clk>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 - >; - clock-output-names = - "subck", "subck2"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150134 4>, <0xe6150038 4>; - clocks = <&cpg_clocks R8A7740_CLK_S>, - <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, - <&cpg_clocks R8A7740_CLK_B>, - <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, - <&cpg_clocks R8A7740_CLK_B>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 - R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 - R8A7740_CLK_LCDC0 - >; - clock-output-names = - "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", - "tmu1", "lcdc0"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150138 4>, <0xe6150040 4>; - clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA - R8A7740_CLK_SCIFA7 - R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 - R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC - R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB - R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 - R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 - R8A7740_CLK_SCIFA4 - >; - clock-output-names = - "scifa6", "intca", - "scifa7", "dmac1", "dmac2", "dmac3", - "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", - "scifa2", "scifa3", "scifa4"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe615013c 4>, <0xe6150048 4>; - clocks = <&cpg_clocks R8A7740_CLK_R>, - <&cpg_clocks R8A7740_CLK_HP>, - <&sub_clk>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 - R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 - R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 - >; - clock-output-names = - "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", - "mmc", "gether", "tpu0"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150140 4>, <0xe615004c 4>; - clocks = <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>, - <&cpg_clocks R8A7740_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - R8A7740_CLK_USBH R8A7740_CLK_SDHI2 - R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY - >; - clock-output-names = - "usbhost", "sdhi2", "usbfunc", "usphy"; - }; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; - reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a4lc: a4lc@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@2 { - reg = <2>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@3 { - reg = <3>; - #power-domain-cells = <0>; - }; - - pd_a4r: a4r@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3rv: a3rv@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - }; - - pd_a4s: a4s@10 { - reg = <10>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sp: a3sp@11 { - reg = <11>; - #power-domain-cells = <0>; - }; - - pd_a3sm: a3sm@12 { - reg = <12>; - #power-domain-cells = <0>; - }; - - pd_a3sg: a3sg@13 { - reg = <13>; - #power-domain-cells = <0>; - }; - }; - - pd_a4su: a4su@20 { - reg = <20>; - #power-domain-cells = <0>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7778-bockw.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7778-bockw.dts deleted file mode 100644 index 211d239d9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7778-bockw.dts +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Reference Device Tree Source for the Bock-W board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * based on r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7778.dtsi" -#include -#include - -/ { - model = "bockw"; - compatible = "renesas,bockw", "renesas,r8a7778"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel ip=dhcp root=/dev/nfs rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x10000000>; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - system-clock-frequency = <11289600>; - }; - }; -}; - -&bsc { - ethernet@18300000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x18300000 0x1000>; - - phy-mode = "mii"; - interrupt-parent = <&irqpin>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - reg-io-width = <4>; - vddvario-supply = <&fixedregulator3v3>; - vdd33a-supply = <&fixedregulator3v3>; - }; -}; - -&extal_clk { - clock-frequency = <33333333>; -}; - -&i2c0 { - status = "okay"; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - camera@41 { - compatible = "oki,ml86v7667"; - reg = <0x41>; - }; - - camera@43 { - compatible = "oki,ml86v7667"; - reg = <0x43>; - }; - - rx8581: rtc@51 { - compatible = "epson,rx8581"; - reg = <0x51>; - }; -}; - -&mmcif { - pinctrl-0 = <&mmc_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <8>; - broken-cd; - status = "okay"; -}; - -&irqpin { - status = "okay"; -}; - -&tmu0 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - scif0_pins: scif0 { - groups = "scif0_data_a", "scif0_ctrl"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - sdhi0_pup_pins: sd0_pup { - groups = "sdhi0_cd", "sdhi0_wp"; - function = "sdhi0"; - bias-pull-up; - }; - - hspi0_pins: hspi0 { - groups = "hspi0_a"; - function = "hspi0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; -}; - -&rcar_sound { - /* Single DAI */ - #sound-dai-cells = <0>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>, <&sdhi0_pup_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <4>; - status = "okay"; - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; -}; - -&hspi0 { - pinctrl-0 = <&hspi0_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl008k", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "data(spi)"; - reg = <0x00000000 0x00100000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7778.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a7778.dtsi deleted file mode 100644 index e571d66ea..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7778.dtsi +++ /dev/null @@ -1,629 +0,0 @@ -/* - * Device Tree Source for Renesas r8a7778 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * based on r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -#include -#include -#include - -/ { - compatible = "renesas,r8a7778"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <800000000>; - }; - }; - - aliases { - spi0 = &hspi0; - spi1 = &hspi1; - spi2 = &hspi2; - }; - - bsc: bus@1c000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1c000000>; - }; - - ether: ethernet@fde00000 { - compatible = "renesas,ether-r8a7778"; - reg = <0xfde00000 0x400>; - interrupts = ; - clocks = <&mstp1_clks R8A7778_CLK_ETHER>; - power-domains = <&cpg_clocks>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@fe438000 { - compatible = "arm,pl390"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfe438000 0x1000>, - <0xfe430000 0x100>; - }; - - /* irqpin: IRQ0 - IRQ3 */ - irqpin: interrupt-controller@fe78001c { - compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - status = "disabled"; /* default off */ - reg = <0xfe78001c 4>, - <0xfe780010 4>, - <0xfe780024 4>, - <0xfe780044 4>, - <0xfe780064 4>; - interrupts = ; - sense-bitfield-width = <2>; - }; - - gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; - reg = <0xffc40000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; - reg = <0xffc41000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; - reg = <0xffc42000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; - reg = <0xffc43000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; - reg = <0xffc44000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 27>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - pfc: pfc@fffc0000 { - compatible = "renesas,pfc-r8a7778"; - reg = <0xfffc0000 0x118>; - }; - - i2c0: i2c@ffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778"; - reg = <0xffc70000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c1: i2c@ffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778"; - reg = <0xffc71000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c2: i2c@ffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778"; - reg = <0xffc72000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C2>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - i2c3: i2c@ffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7778"; - reg = <0xffc73000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_I2C3>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@ffd81000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd81000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu2: timer@ffd82000 { - compatible = "renesas,tmu-r8a7778", "renesas,tmu"; - reg = <0xffd82000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7778_CLK_TMU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - rcar_sound: sound@ffd90000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; - reg = <0xffd90000 0x1000>, /* SRU */ - <0xffd91000 0x240>, /* SSI */ - <0xfffe0000 0x24>; /* ADG */ - clocks = <&mstp3_clks R8A7778_CLK_SSI8>, - <&mstp3_clks R8A7778_CLK_SSI7>, - <&mstp3_clks R8A7778_CLK_SSI6>, - <&mstp3_clks R8A7778_CLK_SSI5>, - <&mstp3_clks R8A7778_CLK_SSI4>, - <&mstp0_clks R8A7778_CLK_SSI3>, - <&mstp0_clks R8A7778_CLK_SSI2>, - <&mstp0_clks R8A7778_CLK_SSI1>, - <&mstp0_clks R8A7778_CLK_SSI0>, - <&mstp5_clks R8A7778_CLK_SRU_SRC8>, - <&mstp5_clks R8A7778_CLK_SRU_SRC7>, - <&mstp5_clks R8A7778_CLK_SRU_SRC6>, - <&mstp5_clks R8A7778_CLK_SRU_SRC5>, - <&mstp5_clks R8A7778_CLK_SRU_SRC4>, - <&mstp5_clks R8A7778_CLK_SRU_SRC3>, - <&mstp5_clks R8A7778_CLK_SRU_SRC2>, - <&mstp5_clks R8A7778_CLK_SRU_SRC1>, - <&mstp5_clks R8A7778_CLK_SRU_SRC0>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg_clocks R8A7778_CLK_S1>; - clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", - "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.8", "src.7", "src.6", "src.5", "src.4", - "src.3", "src.2", "src.1", "src.0", - "clk_a", "clk_b", "clk_c", "clk_i"; - - status = "disabled"; - - rcar_sound,src { - src3: src-3 { }; - src4: src-4 { }; - src5: src-5 { }; - src6: src-6 { }; - src7: src-7 { }; - src8: src-8 { }; - src9: src-9 { }; - }; - - rcar_sound,ssi { - ssi3: ssi-3 { interrupts = ; }; - ssi4: ssi-4 { interrupts = ; }; - ssi5: ssi-5 { interrupts = ; }; - ssi6: ssi-6 { interrupts = ; }; - ssi7: ssi-7 { interrupts = ; }; - ssi8: ssi-8 { interrupts = ; }; - ssi9: ssi-9 { interrupts = ; }; - }; - }; - - scif0: serial@ffe40000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe40000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF0>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif1: serial@ffe41000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe41000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF1>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif2: serial@ffe42000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe42000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF2>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif3: serial@ffe43000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe43000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF3>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif4: serial@ffe44000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe44000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF4>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - scif5: serial@ffe45000 { - compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe45000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF5>, - <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - mmcif: mmc@ffe4e000 { - compatible = "renesas,sh-mmcif"; - reg = <0xffe4e000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_MMC>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi0: sd@ffe4c000 { - compatible = "renesas,sdhi-r8a7778"; - reg = <0xffe4c000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi1: sd@ffe4d000 { - compatible = "renesas,sdhi-r8a7778"; - reg = <0xffe4d000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - sdhi2: sd@ffe4f000 { - compatible = "renesas,sdhi-r8a7778"; - reg = <0xffe4f000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; - power-domains = <&cpg_clocks>; - status = "disabled"; - }; - - hspi0: spi@fffc7000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc7000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hspi1: spi@fffc8000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc8000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hspi2: spi@fffc6000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc6000 0x18>; - interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_HSPI>; - power-domains = <&cpg_clocks>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External input clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@ffc80000 { - compatible = "renesas,r8a7778-cpg-clocks"; - reg = <0xffc80000 0x80>; - #clock-cells = <1>; - clocks = <&extal_clk>; - clock-output-names = "plla", "pllb", "b", - "out", "p", "s", "s1"; - #power-domain-cells = <0>; - }; - - /* Audio clocks; frequencies are set by boards if applicable. */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - /* Fixed ratio clocks */ - g_clk: g { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - s3_clk: s3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - s4_clk: s4 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - z_clk: z { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7778_CLK_PLLB>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@ffc80030 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80030 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_S>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 - R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 - R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 - R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 - R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 - R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 - R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 - R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 - R8A7778_CLK_SSI3 R8A7778_CLK_SRU - R8A7778_CLK_HSPI - >; - clock-output-names = - "i2c0", "i2c1", "i2c2", "i2c3", "scif0", - "scif1", "scif2", "scif3", "scif4", "scif5", - "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", - "ssi2", "ssi3", "sru", "hspi"; - }; - mstp1_clks: mstp1_clks@ffc80034 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80034 4>, <0xffc80044 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_S>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_ETHER R8A7778_CLK_VIN0 - R8A7778_CLK_VIN1 R8A7778_CLK_USB - >; - clock-output-names = - "ether", "vin0", "vin1", "usb"; - }; - mstp3_clks: mstp3_clks@ffc8003c { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc8003c 4>; - clocks = <&s4_clk>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_MMC R8A7778_CLK_SDHI0 - R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 - R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 - R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 - R8A7778_CLK_SSI8 - >; - clock-output-names = - "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", - "ssi5", "ssi6", "ssi7", "ssi8"; - }; - mstp5_clks: mstp5_clks@ffc80054 { - compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xffc80054 4>; - clocks = <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>, - <&cpg_clocks R8A7778_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 - R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 - R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 - R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 - R8A7778_CLK_SRU_SRC8 - >; - clock-output-names = - "sru-src0", "sru-src1", "sru-src2", - "sru-src3", "sru-src4", "sru-src5", - "sru-src6", "sru-src7", "sru-src8"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7779-marzen.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7779-marzen.dts deleted file mode 100644 index 541678df9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7779-marzen.dts +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Device Tree Source for the Marzen board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7779.dtsi" -#include -#include - -/ { - model = "marzen"; - compatible = "renesas,marzen", "renesas,r8a7779"; - - aliases { - serial0 = &scif2; - serial1 = &scif4; - }; - - chosen { - bootargs = "ignore_loglevel root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x18000000 0x100>; - pinctrl-0 = <ðernet_pins>; - pinctrl-names = "default"; - - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&fixedregulator3v3>; - vdd33a-supply = <&fixedregulator3v3>; - }; - - leds { - compatible = "gpio-leds"; - led2 { - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - }; - led3 { - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - }; - led4 { - gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - vga_enc_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - port@1 { - reg = <1>; - vga_enc_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&vga_enc_out>; - }; - }; - }; - - lvds-encoder { - compatible = "thine,thc63lvdm83d"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds_enc_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - lvds_connector: endpoint { - }; - }; - }; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <65000000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; - clock-names = "du", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&vga_enc_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&lvds_enc_in>; - }; - }; - }; -}; - -&irqpin0 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <31250000>; -}; - -&tmu0 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - du0 { - groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; - function = "du0"; - }; - du1 { - groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; - function = "du1"; - }; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; - - ethernet_pins: ethernet { - intc { - groups = "intc_irq1_b"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - scif2_pins: scif2 { - groups = "scif2_data_c"; - function = "scif2"; - }; - - scif4_pins: scif4 { - groups = "scif4_data"; - function = "scif4"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - function = "sdhi0"; - }; - - hspi0_pins: hspi0 { - groups = "hspi0"; - function = "hspi0"; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif4 { - pinctrl-0 = <&scif4_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <4>; - status = "okay"; -}; - -&hspi0 { - pinctrl-0 = <&hspi0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7779.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a7779.dtsi deleted file mode 100644 index b9bbcce69..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7779.dtsi +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Device Tree Source for Renesas r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7779"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <1000000000>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <1000000000>; - power-domains = <&sysc R8A7779_PD_ARM1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - clock-frequency = <1000000000>; - power-domains = <&sysc R8A7779_PD_ARM2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - clock-frequency = <1000000000>; - power-domains = <&sysc R8A7779_PD_ARM3>; - }; - }; - - aliases { - spi0 = &hspi0; - spi1 = &hspi1; - spi2 = &hspi2; - }; - - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; - - timer@f0000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf0000600 0x20>; - interrupts = ; - clocks = <&cpg_clocks R8A7779_CLK_ZS>; - }; - - gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; - reg = <0xffc40000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; - reg = <0xffc41000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; - reg = <0xffc42000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; - reg = <0xffc43000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; - reg = <0xffc44000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio5: gpio@ffc45000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; - reg = <0xffc45000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio6: gpio@ffc46000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; - reg = <0xffc46000 0x2c>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 9>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - irqpin0: interrupt-controller@fe78001c { - compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - status = "disabled"; - interrupt-controller; - reg = <0xfe78001c 4>, - <0xfe780010 4>, - <0xfe780024 4>, - <0xfe780044 4>, - <0xfe780064 4>, - <0xfe780000 4>; - interrupts = ; - sense-bitfield-width = <2>; - }; - - i2c0: i2c@ffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779"; - reg = <0xffc70000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C0>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c1: i2c@ffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779"; - reg = <0xffc71000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C1>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c2: i2c@ffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779"; - reg = <0xffc72000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C2>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c3: i2c@ffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7779"; - reg = <0xffc73000 0x1000>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_I2C3>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@ffe40000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe40000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif1: serial@ffe41000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe41000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif2: serial@ffe42000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe42000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif3: serial@ffe43000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe43000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif4: serial@ffe44000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe44000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif5: serial@ffe45000 { - compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", - "renesas,scif"; - reg = <0xffe45000 0x100>; - interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, - <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pfc: pfc@fffc0000 { - compatible = "renesas,pfc-r8a7779"; - reg = <0xfffc0000 0x23c>; - }; - - thermal@ffc48000 { - compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; - reg = <0xffc48000 0x38>; - }; - - tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu1: timer@ffd81000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd81000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU1>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - tmu2: timer@ffd82000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd82000 0x30>; - interrupts = , - , - ; - clocks = <&mstp0_clks R8A7779_CLK_TMU2>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - - #renesas,channels = <3>; - - status = "disabled"; - }; - - sata: sata@fc600000 { - compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; - reg = <0xfc600000 0x2000>; - interrupts = ; - clocks = <&mstp1_clks R8A7779_CLK_SATA>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - }; - - sdhi0: sd@ffe4c000 { - compatible = "renesas,sdhi-r8a7779"; - reg = <0xffe4c000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi1: sd@ffe4d000 { - compatible = "renesas,sdhi-r8a7779"; - reg = <0xffe4d000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi2: sd@ffe4e000 { - compatible = "renesas,sdhi-r8a7779"; - reg = <0xffe4e000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi3: sd@ffe4f000 { - compatible = "renesas,sdhi-r8a7779"; - reg = <0xffe4f000 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi0: spi@fffc7000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc7000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi1: spi@fffc8000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc8000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hspi2: spi@fffc6000 { - compatible = "renesas,hspi-r8a7779", "renesas,hspi"; - reg = <0xfffc6000 0x18>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp0_clks R8A7779_CLK_HSPI>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - }; - - du: display@fff80000 { - compatible = "renesas,du-r8a7779"; - reg = <0 0xfff80000 0 0x40000>; - interrupts = ; - clocks = <&mstp1_clks R8A7779_CLK_DU>; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: clocks@ffc80000 { - compatible = "renesas,r8a7779-cpg-clocks"; - reg = <0xffc80000 0x30>; - clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "plla", "z", "zs", "s", - "s1", "p", "b", "out"; - #power-domain-cells = <0>; - }; - - /* Fixed factor clocks */ - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - s3_clk: s3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - s4_clk: s4 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <16>; - clock-mult = <1>; - }; - g_clk: g { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7779_CLK_PLLA>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: clocks@ffc80030 { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc80030 4>; - clocks = <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_HSPI R8A7779_CLK_TMU2 - R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 - R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 - R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 - R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 - R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 - R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 - R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 - >; - clock-output-names = - "hspi", "tmu2", "tmu1", "tmu0", "hscif1", - "hscif0", "scif5", "scif4", "scif3", "scif2", - "scif1", "scif0", "i2c3", "i2c2", "i2c1", - "i2c0"; - }; - mstp1_clks: clocks@ffc80034 { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc80034 4>, <0xffc80044 4>; - clocks = <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_P>, - <&cpg_clocks R8A7779_CLK_S>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_USB01 R8A7779_CLK_USB2 - R8A7779_CLK_DU R8A7779_CLK_VIN2 - R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 - R8A7779_CLK_ETHER R8A7779_CLK_SATA - R8A7779_CLK_PCIE R8A7779_CLK_VIN3 - >; - clock-output-names = - "usb01", "usb2", - "du", "vin2", - "vin1", "vin0", - "ether", "sata", - "pcie", "vin3"; - }; - mstp3_clks: clocks@ffc8003c { - compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0xffc8003c 4>; - clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, - <&s4_clk>, <&s4_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 - R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 - R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 - >; - clock-output-names = - "sdhi3", "sdhi2", "sdhi1", "sdhi0", - "mmc1", "mmc0"; - }; - }; - - sysc: system-controller@ffd85000 { - compatible = "renesas,r8a7779-sysc"; - reg = <0xffd85000 0x0200>; - #power-domain-cells = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7790-lager.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7790-lager.dts deleted file mode 100644 index 52b56fcad..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7790-lager.dts +++ /dev/null @@ -1,762 +0,0 @@ -/* - * Device Tree Source for the Lager board - * - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded, Inc. - * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7790.dtsi" -#include -#include - -/ { - model = "Lager"; - compatible = "renesas,lager", "renesas,r8a7790"; - - aliases { - serial0 = &scif0; - serial1 = &scifa1; - i2c8 = "i2cexio"; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@140000000 { - device_type = "memory"; - reg = <1 0x40000000 0 0xc0000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - one { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - two { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; - three { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - four { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - }; - led7 { - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - led8 { - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - }; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - /* - * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only. - * We use the I2C demuxer, so the desired IP core can be selected at runtime - * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0). - * Note: For testing the I2C slave feature, it is convenient to connect this - * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and - * instantiate the slave device at runtime according to the documentation. - * You can then communicate with the slave via IIC3. - */ - i2cexio: i2c-8 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic0>, <&i2c0>; - i2c-bus-name = "i2c-exio"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", - "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@2 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - scifa1_pins: scifa1 { - groups = "scifa1_data"; - function = "scifa1"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - mmc1_pins: mmc1 { - groups = "mmc1_data8", "mmc1_ctrl"; - function = "mmc1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - msiof1_pins: msiof1 { - groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", - "msiof1_tx"; - function = "msiof1"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - iic0_pins: iic0 { - groups = "iic0"; - function = "iic0"; - }; - - iic1_pins: iic1 { - groups = "iic1"; - function = "iic1"; - }; - - iic2_pins: iic2 { - groups = "iic2"; - function = "iic2"; - }; - - iic3_pins: iic3 { - groups = "iic3"; - function = "iic3"; - }; - - hsusb_pins: hsusb { - groups = "usb0_ovc_vbus"; - function = "usb0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&mmcif1 { - pinctrl-0 = <&mmc1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scifa1 { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; - status = "okay"; -}; - -&msiof1 { - pinctrl-0 = <&msiof1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - pmic: pmic@0 { - compatible = "renesas,r2a11302ft"; - reg = <0>; - spi-max-frequency = <6000000>; - spi-cpol; - spi-cpha; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "i2c-exio"; -}; - -&iic0 { - pinctrl-0 = <&iic0_pins>; - pinctrl-names = "i2c-exio"; -}; - -&iic1 { - status = "okay"; - pinctrl-0 = <&iic1_pins>; - pinctrl-names = "default"; -}; - -&iic2 { - status = "okay"; - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "default"; - - clock-frequency = <100000>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&iic3 { - pinctrl-names = "default"; - pinctrl-0 = <&iic3_pins>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&xhci { - status = "okay"; - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; -}; - -&pci2 { - status = "okay"; - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&hsusb_pins>; - pinctrl-names = "default"; - renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; -}; - -&usbphy { - status = "okay"; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - vin1ep0: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7790.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a7790.dtsi deleted file mode 100644 index b6c6410ca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7790.dtsi +++ /dev/null @@ -1,1910 +0,0 @@ -/* - * Device Tree Source for the r8a7790 SoC - * - * Copyright (C) 2015 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7790"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &iic0; - i2c5 = &iic1; - i2c6 = &iic2; - i2c7 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - spi4 = &msiof3; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - vin3 = &vin3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1300000000>; - voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7790_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7790_PD_CA15_CPU0>; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1300000000>; - power-domains = <&sysc R8A7790_PD_CA15_CPU1>; - next-level-cache = <&L2_CA15>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - clock-frequency = <1300000000>; - power-domains = <&sysc R8A7790_PD_CA15_CPU2>; - next-level-cache = <&L2_CA15>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - clock-frequency = <1300000000>; - power-domains = <&sysc R8A7790_PD_CA15_CPU3>; - next-level-cache = <&L2_CA15>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clock-frequency = <780000000>; - power-domains = <&sysc R8A7790_PD_CA7_CPU0>; - next-level-cache = <&L2_CA7>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clock-frequency = <780000000>; - power-domains = <&sysc R8A7790_PD_CA7_CPU1>; - next-level-cache = <&L2_CA7>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clock-frequency = <780000000>; - power-domains = <&sysc R8A7790_PD_CA7_CPU2>; - next-level-cache = <&L2_CA7>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clock-frequency = <780000000>; - power-domains = <&sysc R8A7790_PD_CA7_CPU3>; - next-level-cache = <&L2_CA7>; - }; - - L2_CA15: cache-controller@0 { - compatible = "cache"; - reg = <0>; - power-domains = <&sysc R8A7790_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller@100 { - compatible = "cache"; - reg = <0x100>; - power-domains = <&sysc R8A7790_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #thermal-sensor-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&mstp1_clks R8A7790_CLK_CMT0>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,channels-mask = <0x60>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp3_clks R8A7790_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7790", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R8A7790_CLK_IRQC>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_I2C0>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_I2C1>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_I2C2>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_I2C3>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_IIC0>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_IIC1>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - iic2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_IIC2>; - dmas = <&dmac0 0x69>, <&dmac0 0x6a>, - <&dmac1 0x69>, <&dmac1 0x6a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; - dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, - <&dmac1 0xe1>, <&dmac1 0xe2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - pfc: pfc@e6060000 { - compatible = "renesas,pfc-r8a7790"; - reg = <0 0xe6060000 0 0x250>; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee120000 0 0x328>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7790"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif2: serial@e6e56000 { - compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e56000 0 64>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7790"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_ETHER>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7790", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7790"; - reg = <0 0xee300000 0 0x2000>; - interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_SATA0>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7790"; - reg = <0 0xee500000 0 0x2000>; - interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_SATA1>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7790"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7790"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_VIN0>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7790"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_VIN1>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7790"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_VIN2>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7790"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_VIN3>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vsp1@fe920000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - vsp1@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - vsp1@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - vsp1@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7790"; - reg = <0 0xfeb00000 0 0x70000>, - <0 0xfeb90000 0 0x1c>, - <0 0xfeb94000 0 0x1c>; - reg-names = "du", "lvds.0", "lvds.1"; - interrupts = , - , - ; - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - }; - }; - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - }; - }; - }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, - <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, - <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_JPU>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7790-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "sd1", - "z", "rcan", "adsp"; - #power-domain-cells = <0>; - }; - - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc1_clk: mmc1@e6150244 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150244 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssp_clk: ssp@e6150248 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150248 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssprs_clk: ssprs@e615024c { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615024c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z2_clk: z2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - imp_clk: imp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, - <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 - R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 - R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC - R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 - R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 - R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 - R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S - >; - clock-output-names = - "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", - "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", - "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", - "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 - R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 - R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 - R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "msiof3", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>, - <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 - R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 - >; - clock-output-names = - "iic2", "tpu0", "mmcif1", "scif2", "sdhi3", - "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "pciec", "iic1", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, - <&extal_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 - R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL - R8A7790_CLK_PWM - >; - clock-output-names = "audmac0", "audmac1", "adsp_mod", - "thermal", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, - <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 - R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 - R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 - R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif1", "hscif0", "scif1", - "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 - R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 - R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER - R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 - >; - clock-output-names = - "mlb", "vin3", "vin2", "vin1", "vin0", - "etheravb", "ether", "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 - R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 - R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS - R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 - >; - clock-output-names = - "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "iic3", - "i2c3", "i2c2", "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_SSI_ALL - R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 - R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 - R8A7790_CLK_SCU_ALL - R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 - R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 - R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 - R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7790-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7790", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6c90000 0 0x0064>; - interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; - dmas = <&dmac0 0x45>, <&dmac0 0x46>, - <&dmac1 0x45>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0b0000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0b0000 0 0xc00>, - <0 0xee0a0000 0 0x1100>; - interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - }; - - pci2: pci@ee0d0000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - device_type = "pci"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - status = "disabled"; - - bus-range = <2 2>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 - 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, - <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, - <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, - <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, - <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, - <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, - <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, - <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, - <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, - <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, - <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7791-koelsch.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7791-koelsch.dts deleted file mode 100644 index f8a7d090f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7791-koelsch.dts +++ /dev/null @@ -1,711 +0,0 @@ -/* - * Device Tree Source for the Koelsch board - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include -#include - -/ { - model = "Koelsch"; - compatible = "renesas,koelsch", "renesas,r8a7791"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW30"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW31"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW32"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW33"; - wakeup-source; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW34"; - wakeup-source; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW35"; - wakeup-source; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW36"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - label = "LED7"; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - label = "LED8"; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - msiof0_pins: msiof0 { - groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", - "msiof0_tx"; - function = "msiof0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00080000>; - read-only; - }; - partition@80000 { - label = "user"; - reg = <0x00080000 0x00580000>; - read-only; - }; - partition@600000 { - label = "flash"; - reg = <0x00600000 0x03a00000>; - }; - }; - }; -}; - -&msiof0 { - pinctrl-0 = <&msiof0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - pmic: pmic@0 { - compatible = "renesas,r2a11302ft"; - reg = <0>; - spi-max-frequency = <6000000>; - spi-cpol; - spi-cpha; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <100000>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c6 { - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; -}; - -&usbphy { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -/* composite video input */ -&vin1 { - status = "okay"; - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - vin1ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7791-porter.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7791-porter.dts deleted file mode 100644 index 6761d11d3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7791-porter.dts +++ /dev/null @@ -1,457 +0,0 @@ -/* - * Device Tree Source for the Porter board - * - * Copyright (C) 2015 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/* - * SSI-AK4642 - * - * JP3: 2-1: AK4642 - * 2-3: ADV7511 - * - * This command is required before playback/capture: - * - * amixer set "LINEOUT Mixer DACL" on - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include - -/ { - model = "Porter"; - compatible = "renesas,porter", "renesas,r8a7791"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x16_clk: x16-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x14_clk: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&soundcodec>; - simple-audio-card,frame-master = <&soundcodec>; - - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - soundcodec: simple-audio-card,codec { - sound-dai = <&ak4642>; - clocks = <&x14_clk>; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - ssi_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - audio_clk_pins: audio_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "ok"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader_prg"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user_prg"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash_fs"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - ak4642: codec@12 { - compatible = "asahi-kasei,ak4642"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&sata0 { - status = "okay"; -}; - -/* composite video input */ -&vin0 { - status = "ok"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pci1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&hsusb { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, - <&x3_clk>, <&x16_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&ssi_pins &audio_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>; - capture = <&ssi1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7791.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a7791.dtsi deleted file mode 100644 index 162b55c66..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7791.dtsi +++ /dev/null @@ -1,1891 +0,0 @@ -/* - * Device Tree Source for the r8a7791 SoC - * - * Copyright (C) 2013-2015 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7791"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7791_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7791_PD_CA15_CPU0>; - next-level-cache = <&L2_CA15>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - power-domains = <&sysc R8A7791_PD_CA15_CPU1>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller@0 { - compatible = "cache"; - reg = <0>; - power-domains = <&sysc R8A7791_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7791-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7791", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #thermal-sensor-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&mstp1_clks R8A7791_CLK_CMT0>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,channels-mask = <0x60>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp3_clks R8A7791_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7791", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A7791_CLK_IRQC>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C0>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C1>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C2>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C3>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C4>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C5>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_IIC0>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_IIC1>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pfc: pfc@e6060000 { - compatible = "renesas,pfc-r8a7791"; - reg = <0 0xe6060000 0 0x250>; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7791"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7791"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7791"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7791"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_ETHER>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7791", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791"; - reg = <0 0xee300000 0 0x2000>; - interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_SATA0>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7791"; - reg = <0 0xee500000 0 0x2000>; - interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_SATA1>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7791"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7791"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_VIN0>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7791"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_VIN1>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7791"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_VIN2>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vsp1@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - vsp1@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - vsp1@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7791"; - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; - reg-names = "du", "lvds.0"; - interrupts = , - ; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>; - clock-names = "du.0", "du.1", "lvds.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - }; - }; - }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&mstp1_clks R8A7791_CLK_JPU>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7791-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan", "adsp"; - #power-domain-cells = <0>; - }; - - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssp_clk: ssp@e6150248 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150248 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssprs_clk: ssprs@e615024c { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615024c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, - <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU - R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG - R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 - R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 - R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 - R8A7791_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", - "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", - "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 - R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 - R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 - R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 - R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 - R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 - R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 - >; - clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, - <&extal_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 - R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL - R8A7791_CLK_PWM - >; - clock-output-names = "audmac0", "audmac1", "adsp_mod", - "thermal", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>, <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 - R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 - R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 - R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 - R8A7791_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB - R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 - R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER - R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 - >; - clock-output-names = - "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", - "etheravb", "ether", "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, - <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 - R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 - R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 - R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 - R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", - "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SSI_ALL - R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 - R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 - R8A7791_CLK_SCU_ALL - R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 - R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 - R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 - R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7791-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 - 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - status = "disabled"; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, - <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, - <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, - <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, - <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, - <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, - <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, - <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, - <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, - <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, - <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7792-blanche.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7792-blanche.dts deleted file mode 100644 index f3ea43b7b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7792-blanche.dts +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Device Tree Source for the Blanche board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7792.dtsi" -#include -#include - -/ { - model = "Blanche"; - compatible = "renesas,blanche", "renesas,r8a7792"; - - aliases { - serial0 = &scif0; - serial1 = &scif3; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x1_clk: x1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x2_clk: x2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <65000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - key-1 { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - }; - key-2 { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - }; - key-3 { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - }; - key-4 { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - key-a { - linux,code = ; - label = "SW24"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - }; - key-b { - linux,code = ; - label = "SW25"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led17 { - gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>; - }; - led18 { - gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>; - }; - led19 { - gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>; - }; - led20 { - gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&can_clk { - clock-frequency = <48000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif3_pins: scif3 { - groups = "scif3_data"; - function = "scif3"; - }; - - lan89218_pins: lan89218 { - intc { - groups = "intc_irq0"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - can0_pins: can0 { - groups = "can0_data", "can_clk"; - function = "can0"; - }; - - sdhi0_pins: sdhi0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp"; - function = "du1"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif3 { - pinctrl-0 = <&scif3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&irqc>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du0_pins &du1_pins>; - pinctrl-names = "default"; - - clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, - <&x1_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7792-wheat.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7792-wheat.dts deleted file mode 100644 index 6dbb94114..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7792-wheat.dts +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Device Tree Source for the Wheat board - * - * Copyright (C) 2016 Renesas Electronics Corporation - * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7792.dtsi" -#include -#include - -/ { - model = "Wheat"; - compatible = "renesas,wheat", "renesas,r8a7792"; - - aliases { - serial0 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - smsc,save-mac-address; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - - keyboard { - compatible = "gpio-keys"; - - key-a { - linux,code = ; - label = "SW2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - }; - key-b { - linux,code = ; - label = "SW3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - lan89218_pins: lan89218 { - intc { - groups = "intc_irq0"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; - - sdhi0_pins: sdhi0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7792.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a7792.dtsi deleted file mode 100644 index 713141d38..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7792.dtsi +++ /dev/null @@ -1,929 +0,0 @@ -/* - * Device Tree Source for the r8a7792 SoC - * - * Copyright (C) 2016 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7792"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - spi0 = &qspi; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - vin3 = &vin3; - vin4 = &vin4; - vin5 = &vin5; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg_clocks R8A7792_CLK_Z>; - power-domains = <&sysc R8A7792_PD_CA15_CPU0>; - next-level-cache = <&L2_CA15>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1000000000>; - power-domains = <&sysc R8A7792_PD_CA15_CPU1>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller@0 { - compatible = "cache"; - reg = <0>; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7792_PD_CA15_SCU>; - }; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - apmu@e6152000 { - compatible = "renesas,r8a7792-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7792", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&mstp4_clks R8A7792_CLK_IRQC>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7792-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7792"; - reg = <0 0xe6060000 0 0x144>; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio6: gpio@e6055100 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6055100 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio7: gpio@e6055200 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6055200 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio8: gpio@e6055300 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6055300 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 256 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio9: gpio@e6055400 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 288 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio10: gpio@e6055500 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6055500 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 320 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - gpio11: gpio@e6055600 { - compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; - reg = <0 0xe6055600 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 352 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7792", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7792", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7792", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7792", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7792"; - reg = <0 0xee100000 0 0x328>; - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7792", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&mstp1_clks R8A7792_CLK_JPU>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7792", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* I2C doesn't need pinmux */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7792"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C0>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7792"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C1>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7792"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C2>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7792"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C3>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7792"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C4>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7792"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C5>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7792", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7792"; - reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; - interrupts = , - ; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, - <&mstp7_clks R8A7792_CLK_DU1>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7792", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_CAN0>, - <&rcan_clk>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7792", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_CAN1>, - <&rcan_clk>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN0>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN1>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN2>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN3>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN4>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN5>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vsp1@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - vsp1@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - vsp1@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7792-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "z"; - #power-domain-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - sd_clk: sd { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rcan_clk: rcan { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <49>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <5>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_JPU - R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0 - R8A7792_CLK_VSP1_SY - >; - clock-output-names = "jpu", "vsp1du1", "vsp1du0", - "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 - >; - clock-output-names = "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd_clk>; - #clock-cells = <1>; - renesas,clock-indices = ; - clock-output-names = "sdhi0"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 - R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 - R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 - R8A7792_CLK_DU1 R8A7792_CLK_DU0 - >; - clock-output-names = "hscif1", "hscif0", "scif3", - "scif2", "scif1", "scif0", - "du1", "du0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&zg_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 - R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 - R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 - R8A7792_CLK_ETHERAVB - >; - clock-output-names = "vin5", "vin4", "vin3", "vin2", - "vin1", "vin0", "etheravb"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, - <&cpg_clocks R8A7792_CLK_QSPI>, - <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 - R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 - R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 - R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 - R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 - R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 - R8A7792_CLK_QSPI_MOD - R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 - R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 - R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 - R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", - "gpio3", "gpio2", "gpio1", "gpio0", - "gpio11", "gpio10", "can1", "can0", - "qspi_mod", "gpio9", "gpio8", - "i2c5", "i2c4", "i2c3", "i2c2", - "i2c1", "i2c0"; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7793-gose.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7793-gose.dts deleted file mode 100644 index 90af18600..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7793-gose.dts +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Device Tree Source for the Gose board - * - * Copyright (C) 2014-2015 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7793.dtsi" -#include -#include - -/ { - model = "Gose"; - compatible = "renesas,gose", "renesas,r8a7793"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW30"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW31"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW32"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW33"; - wakeup-source; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW34"; - wakeup-source; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW35"; - wakeup-source; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW36"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - label = "LED7"; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - label = "LED8"; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp7_clks R8A7793_CLK_DU0>, - <&mstp7_clks R8A7793_CLK_DU1>, - <&mstp7_clks R8A7793_CLK_LVDS0>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "lvds.0", - "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; - }; - - sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; - }; - - sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <100000>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7793.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a7793.dtsi deleted file mode 100644 index 8d02aacf2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7793.dtsi +++ /dev/null @@ -1,1504 +0,0 @@ -/* - * Device Tree Source for the r8a7793 SoC - * - * Copyright (C) 2014-2015 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7793"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - spi0 = &qspi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "renesas,apmu"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7793_CLK_Z>; - clock-latency = <300000>; /* 300 us */ - power-domains = <&sysc R8A7793_PD_CA15_CPU0>; - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - next-level-cache = <&L2_CA15>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - power-domains = <&sysc R8A7793_PD_CA15_CPU1>; - }; - - L2_CA15: cache-controller@0 { - compatible = "cache"; - reg = <0>; - power-domains = <&sysc R8A7793_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7793-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO0>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO1>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO2>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO3>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO4>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO5>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO6>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO7>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7793", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&mstp5_clks R8A7793_CLK_THERMAL>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - #thermal-sensor-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&mstp1_clks R8A7793_CLK_CMT0>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - - renesas,channels-mask = <0x60>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp3_clks R8A7793_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7793", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A7793_CLK_IRQC>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C0>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C1>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C2>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C3>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C4>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C5>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_IIC0>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_IIC1>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pfc: pfc@e6060000 { - compatible = "renesas,pfc-r8a7793"; - reg = <0 0xe6060000 0 0x250>; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7793"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7793"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7793"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7793"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&mstp8_clks R8A7793_CLK_ETHER>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7793", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7793"; - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; - reg-names = "du", "lvds.0"; - interrupts = , - ; - clocks = <&mstp7_clks R8A7793_CLK_DU0>, - <&mstp7_clks R8A7793_CLK_DU1>, - <&mstp7_clks R8A7793_CLK_LVDS0>; - clock-names = "du.0", "du.1", "lvds.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - }; - }; - }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_RCAN0>, - <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_RCAN1>, - <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - status = "disabled"; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7793-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan", "adsp"; - #power-domain-cells = <0>; - }; - - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <5>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, - <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, - <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 - R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 - R8A7793_CLK_3DG R8A7793_CLK_2DDMAC - R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 - R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 - R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 - R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 - R8A7793_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "ssp_dev", "tmu1", - "pvrsrvkm", "tddmac", "fdp1", "fdp0", - "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", - "vsp1-du0", "vsps"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0 - R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2 - R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "scifb0", - "scifb1", "scifb2", "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, - <&rclk_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 - R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 - R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 - R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 - R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 - R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 - >; - clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "i2c7", "pciec", "i2c8", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "audmac0", "audmac1", "thermal"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, - <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_EHCI R8A7793_CLK_HSUSB - R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 - R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 - R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 - R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 - R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 - R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif2", "scif5", "scif4", - "hscif1", "hscif0", "scif3", "scif2", - "scif1", "scif0", "du1", "du0", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&p_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 - R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 - R8A7793_CLK_ETHER R8A7793_CLK_SATA1 - R8A7793_CLK_SATA0 - >; - clock-output-names = - "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", - "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, - <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, - <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6 - R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 - R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 - R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 - R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1 - R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5 - R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 - R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 - R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", - "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "i2c5", - "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", - "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SSI_ALL - R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5 - R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0 - R8A7793_CLK_SCU_ALL - R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0 - R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0 - R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5 - R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7793-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>, - <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>, - <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>, - <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>, - <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>, - <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>, - <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>, - <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>, - <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>, - <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>, - <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7794-alt.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7794-alt.dts deleted file mode 100644 index 8d1b35afa..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7794-alt.dts +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Device Tree Source for the Alt board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7794.dtsi" -#include - -/ { - model = "Alt"; - compatible = "renesas,alt", "renesas,r8a7794"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-d3-3v { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU0>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; - function = "du"; - }; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - mmcif0_pins: mmcif0 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&pfc { - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&d3_3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; -}; - -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "system"; - reg = <0x00040000 0x00040000>; - read-only; - }; - partition@80000 { - label = "user"; - reg = <0x00080000 0x03f80000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7794-silk.dts b/software/linux/kernel/arch/arm/boot/dts/r8a7794-silk.dts deleted file mode 100644 index cf880ac06..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7794-silk.dts +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Device Tree Source for the SILK board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2014-2015 Renesas Solutions Corp. - * Copyright (C) 2014-2015 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/* - * SSI-AK4643 - * - * SW1: 2-1: AK4643 - * 2-3: ADV7511 - * - * This command is required before playback/capture: - * - * amixer set "LINEOUT Mixer DACL" on - */ - -/dts-v1/; -#include "r8a7794.dtsi" -#include - -/ { - model = "SILK"; - compatible = "renesas,silk", "renesas,r8a7794"; - - aliases { - serial0 = &scif2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-d3-3v { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x9_clk: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&soundcodec>; - simple-audio-card,frame-master = <&soundcodec>; - - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - soundcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&x9_clk>; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmcif0_pins: mmcif0 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; - function = "du1"; - }; - - ssi_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - audio_clk_pins: audio_clk { - groups = "audio_clkc"; - function = "audio_clk"; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins &phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin0>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&d3_3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -/* composite video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du0_pins &du1_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU0>, - <&x2_clk>, <&x3_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&ssi_pins &audio_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>; - capture = <&ssi1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a7794.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a7794.dtsi deleted file mode 100644 index 7e860d373..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a7794.dtsi +++ /dev/null @@ -1,1615 +0,0 @@ -/* - * Device Tree Source for the r8a7794 SoC - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2014 Ulrich Hecht - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7794"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - spi0 = &qspi; - vin0 = &vin0; - vin1 = &vin1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - power-domains = <&sysc R8A7794_PD_CA7_CPU0>; - next-level-cache = <&L2_CA7>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - power-domains = <&sysc R8A7794_PD_CA7_CPU1>; - next-level-cache = <&L2_CA7>; - }; - - L2_CA7: cache-controller@0 { - compatible = "cache"; - reg = <0>; - power-domains = <&sysc R8A7794_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-gen2"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&mstp1_clks R8A7794_CLK_CMT0>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - - renesas,channels-mask = <0x60>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-gen2"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&mstp3_clks R8A7794_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - - renesas,channels-mask = <0xff>; - - status = "disabled"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7794", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&mstp4_clks R8A7794_CLK_IRQC>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7794"; - reg = <0 0xe6060000 0 0x11c>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", - "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 64>; - interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7794"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&mstp8_clks R8A7794_CLK_ETHER>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7794", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* The memory map in the User's Manual maps the cores to bus numbers */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7794"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C0>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7794"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C1>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7794"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C2>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7794"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C3>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7794"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C4>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7794"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C5>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e6500000 { - compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_IIC0>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@e6510000 { - compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_IIC1>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - reg-io-width = <4>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7794", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7794"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7794_CLK_VIN0>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7794"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&mstp8_clks R8A7794_CLK_VIN1>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_EHCI>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_EHCI>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@0,1 { - reg = <0x800 0 0 0 0>; - device_type = "pci"; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@0,2 { - reg = <0x1000 0 0 0 0>; - device_type = "pci"; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7794"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - vsp1@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - vsp1@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7794"; - reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; - interrupts = , - ; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU0>; - clock-names = "du.0", "du.1"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, - <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, - <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - status = "disabled"; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed - * frequency clocks by default. Boards that provide audio - * clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7794-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "rcan"; - #power-domain-cells = <0>; - }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - - acp_clk: acp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 - R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 - R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 - R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", - "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 - R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 - R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 - R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 - R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0 - R8A7794_CLK_IIC1 R8A7794_CLK_CMT1 - R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 - >; - clock-output-names = - "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c6", "i2c7", - "cmt1", "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "audmac0", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_EHCI R8A7794_CLK_HSUSB - R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 - R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 - R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 - R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 - >; - clock-output-names = - "ehci", "hsusb", - "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", "du0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 - R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER - >; - clock-output-names = - "vin1", "vin0", "etheravb", "ether"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, - <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = - "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", - "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", - "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7794-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", - "ssi6", "ssi5", "ssi4", "ssi3", - "ssi2", "ssi1", "ssi0", - "scu-all", "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src6", "scu-src5", "scu-src4", - "scu-src3", "scu-src2", "scu-src1"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7794-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - ipmmu_sy0: mmu@e6280000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: mmu@e6290000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec680000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: mmu@fe951000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: mmu@e62a0000 { - compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7794", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI9>, - <&mstp10_clks R8A7794_CLK_SSI8>, - <&mstp10_clks R8A7794_CLK_SSI7>, - <&mstp10_clks R8A7794_CLK_SSI6>, - <&mstp10_clks R8A7794_CLK_SSI5>, - <&mstp10_clks R8A7794_CLK_SSI4>, - <&mstp10_clks R8A7794_CLK_SSI3>, - <&mstp10_clks R8A7794_CLK_SSI2>, - <&mstp10_clks R8A7794_CLK_SSI1>, - <&mstp10_clks R8A7794_CLK_SSI0>, - <&mstp10_clks R8A7794_CLK_SCU_SRC6>, - <&mstp10_clks R8A7794_CLK_SCU_SRC5>, - <&mstp10_clks R8A7794_CLK_SCU_SRC4>, - <&mstp10_clks R8A7794_CLK_SCU_SRC3>, - <&mstp10_clks R8A7794_CLK_SCU_SRC2>, - <&mstp10_clks R8A7794_CLK_SCU_SRC1>, - <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, - <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, - <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7794_CLK_SCU_DVC0>, - <&mstp10_clks R8A7794_CLK_SCU_DVC1>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&m2_clk>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", "src.2", - "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc@0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc@1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix@0 { }; - mix1: mix@1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu@0 { }; - ctu01: ctu@1 { }; - ctu02: ctu@2 { }; - ctu03: ctu@3 { }; - ctu10: ctu@4 { }; - ctu11: ctu@5 { }; - ctu12: ctu@6 { }; - ctu13: ctu@7 { }; - }; - - rcar_sound,src { - src@0 { - status = "disabled"; - }; - src1: src@1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src@2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src@3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src@4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src@5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src@6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi@0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi@1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi@2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi@3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi@4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi@5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi@6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi@7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi@8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi@9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi deleted file mode 100644 index 65cb50f0c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Common file for the AA104XD12 panel connected to Renesas R-Car boards - * - * Copyright (C) 2014 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/ { - panel { - compatible = "mitsubishi,aa104xd12", "panel-dpi"; - - width-mm = <210>; - height-mm = <158>; - - panel-timing { - /* 1024x768 @65Hz */ - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hsync-len = <136>; - hfront-porch = <20>; - hback-porch = <160>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi b/software/linux/kernel/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi deleted file mode 100644 index a07ebf8f6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Common file for the AA121TD01 panel connected to Renesas R-Car boards - * - * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/ { - panel { - compatible = "mitsubishi,aa121td01", "panel-dpi"; - - width-mm = <261>; - height-mm = <163>; - - panel-timing { - /* 1280x800 @60Hz */ - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hsync-len = <70>; - hfront-porch = <20>; - hback-porch = <70>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <15>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3036-evb.dts b/software/linux/kernel/arch/arm/boot/dts/rk3036-evb.dts deleted file mode 100644 index 8db9e9b19..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3036-evb.dts +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "Rockchip RK3036 Evaluation board"; - compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; - phy = <&phy0>; - phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */ - phy-reset-duration = <10>; /* millisecond */ - - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&i2c1 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&uart2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3036-kylin.dts b/software/linux/kernel/arch/arm/boot/dts/rk3036-kylin.dts deleted file mode 100644 index 1df1557a4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3036-kylin.dts +++ /dev/null @@ -1,434 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "Rockchip RK3036 KylinBoard"; - compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; - - memory { - device_type = "memory"; - reg = <0x60000000 0x20000000>; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - label = "kylin:red:led"; - pinctrl-names = "default"; - pinctrl-0 = <&led_ctl>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_wake_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - SDIO_RESET_L_WL_RST - * - SDIO_RESET_L_BT_EN - */ - reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ - <&gpio0 27 GPIO_ACTIVE_LOW>, /* WL_RST */ - <&gpio2 9 GPIO_ACTIVE_LOW>; /* BT_EN */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rt5616-codec"; - simple-audio-card,mclk-fs = <512>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "MIC1", "Microphone Jack", - "MIC2", "Microphone Jack", - "Microphone Jack", "micbias1", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - - simple-audio-card,cpu { - sound-dai = <&i2s>; - }; - - simple-audio-card,codec { - sound-dai = <&rt5616>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&acodec { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; - phy = <&phy0>; - phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */ - phy-reset-duration = <10>; /* millisecond */ - - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&emmc { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vccio_pmu>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vout5: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vout5"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_codec: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - - rt5616: rt5616@1b { - compatible = "rt5616"; - reg = <0x1b>; - clocks = <&cru SCLK_I2S_OUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2s { - #sound-dai-cells = <0>; - status = "okay"; -}; - -&sdio { - status = "okay"; - - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - default-sample-phase = <90>; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; -}; - -&uart0 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&pinctrl { - leds { - led_ctl: led-ctl { - rockchip,pins = <2 30 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdio { - bt_wake_h: bt-wake-h { - rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sleep { - global_pwroff: global-pwroff { - rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3036.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3036.dtsi deleted file mode 100644 index a935523a1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3036.dtsi +++ /dev/null @@ -1,771 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "rockchip,rk3036"; - - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi = &spi; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3036-smp"; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x00 0x10>; - }; - }; - - vop: vop@10118000 { - compatible = "rockchip,rk3036-vop"; - reg = <0x10118000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@10118300 { - compatible = "rockchip,iommu"; - reg = <0x10118300 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - #iommu-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x10139000 0x1000>, - <0x1013a000 0x1000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = ; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - status = "disabled"; - }; - - emac: ethernet@10200000 { - compatible = "rockchip,rk3036-emac", "snps,arc-emac"; - reg = <0x10200000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - rockchip,grf = <&grf>; - clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref", "macclk"; - /* - * Fix the emac parent clock is DPLL instead of APLL. - * since that will cause some unstable things if the cpufreq - * is working. (e.g: the accurate 50MHz what mac_ref need) - */ - assigned-clocks = <&cru SCLK_MACPLL>; - assigned-clock-parents = <&cru PLL_DPLL>; - max-speed = <100>; - phy-mode = "rmii"; - status = "disabled"; - }; - - sdmmc: dwmmc@10214000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - status = "disabled"; - }; - - sdio: dwmmc@10218000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10218000 0x4000>; - clock-freq-min-max = <400000 37500000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - fifo-depth = <0x100>; - interrupts = ; - status = "disabled"; - }; - - emmc: dwmmc@1021c000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x1021c000 0x4000>; - interrupts = ; - bus-width = <8>; - cap-mmc-highspeed; - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - default-sample-phase = <158>; - disable-wp; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - fifo-depth = <0x100>; - mmc-ddr-1_8v; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "disabled"; - }; - - i2s: i2s@10220000 { - compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; - reg = <0x10220000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_bus>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; - reg = <0x20008000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x1d8>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - acodec: acodec-ana@20030000 { - compatible = "rk3036-codec"; - reg = <0x20030000 0x4000>; - rockchip,grf = <&grf>; - clock-names = "acodec_pclk"; - clocks = <&cru PCLK_ACODEC>; - status = "disabled"; - }; - - hdmi: hdmi@20034000 { - compatible = "rockchip,rk3036-inno-hdmi"; - reg = <0x20034000 0x4000>; - interrupts = ; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_ctl>; - status = "disabled"; - - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - - timer: timer@20044000 { - compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; - reg = <0x20044000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@2005a000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - i2c0: i2c@20072000 { - compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; - reg = <0x20072000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - spi: spi@20074000 { - compatible = "rockchip,rockchip-spi"; - reg = <0x20074000 0x1000>; - interrupts = ; - clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>; - clock-names = "apb-pclk","spi_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3036-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>; - }; - - sdmmc_cd: sdmcc-cd { - rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>, - <1 19 RK_FUNC_1 &pcfg_pull_default>, - <1 20 RK_FUNC_1 &pcfg_pull_default>, - <1 21 RK_FUNC_1 &pcfg_pull_default>; - }; - }; - - sdio { - sdio_bus1: sdio-bus1 { - rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>, - <0 12 RK_FUNC_1 &pcfg_pull_default>, - <0 13 RK_FUNC_1 &pcfg_pull_default>, - <0 14 RK_FUNC_1 &pcfg_pull_default>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>; - }; - - sdio_clk: sdio-clk { - rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>, - <1 25 RK_FUNC_2 &pcfg_pull_default>, - <1 26 RK_FUNC_2 &pcfg_pull_default>, - <1 27 RK_FUNC_2 &pcfg_pull_default>, - <1 28 RK_FUNC_2 &pcfg_pull_default>, - <1 29 RK_FUNC_2 &pcfg_pull_default>, - <1 30 RK_FUNC_2 &pcfg_pull_default>, - <1 31 RK_FUNC_2 &pcfg_pull_default>; - }; - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */ - <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */ - <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */ - <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */ - <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */ - <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */ - <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */ - <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */ - <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */ - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2s { - i2s_bus: i2s-bus { - rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>, - <1 1 RK_FUNC_1 &pcfg_pull_default>, - <1 2 RK_FUNC_1 &pcfg_pull_default>, - <1 3 RK_FUNC_1 &pcfg_pull_default>, - <1 4 RK_FUNC_1 &pcfg_pull_default>, - <1 5 RK_FUNC_1 &pcfg_pull_default>; - }; - }; - - hdmi { - hdmi_ctl: hdmi-ctl { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, - <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>, - <1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; - }; - /* no rts / cts for uart1 */ - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - spi { - spi_txd:spi-txd { - rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>; - }; - - spi_rxd:spi-rxd { - rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>; - }; - - spi_clk:spi-clk { - rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>; - }; - - spi_cs0:spi-cs0 { - rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>; - - }; - - spi_cs1:spi-cs1 { - rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>; - - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/software/linux/kernel/arch/arm/boot/dts/rk3066a-bqcurie2.dts deleted file mode 100644 index bc674ee20..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "rk3066a.dtsi" - -/ { - model = "bq Curie 2"; - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vcc_sd0: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - volume-down { - gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ - linux,code = ; - label = "GPIO Key Vol-"; - linux,input-type = <1>; - debounce-interval = <100>; - }; - /* VOL+ comes somehow thru the ADC */ - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - - interrupt-parent = <&gpio6>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc18_cif: regulator@5 { - regulator-name = "vcc18_cif"; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-always-on; - }; - - vcc_18: regulator@8 { - regulator-name = "vcc_18"; - regulator-always-on; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-always-on; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-always-on; - }; - - vcc_tp: regulator@11 { - regulator-name = "vcc_tp"; - regulator-always-on; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-always-on; - }; - }; - }; -}; - -/* must be included after &tps gets defined */ -#include "tps65910.dtsi" - -&mmc0 { /* sdmmc */ - num-slots = <1>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&mmc1 { /* wifi */ - num-slots = <1>; - status = "okay"; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - - bus-width = <4>; - disable-wp; -}; - -&pwm3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3066a-marsboard.dts b/software/linux/kernel/arch/arm/boot/dts/rk3066a-marsboard.dts deleted file mode 100644 index a2b763e94..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3066a-marsboard.dts +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) 2014 Romain Perier - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3066a.dtsi" - -/ { - model = "MarsBoard RK3066"; - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vcc_sd0: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - - interrupt-parent = <&gpio6>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - - vcc1-supply = <&vsys>; - vcc2-supply = <&vsys>; - vcc3-supply = <&vsys>; - vcc4-supply = <&vsys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - vcc7-supply = <&vsys>; - vccio-supply = <&vsys>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc18_cif: regulator@5 { - regulator-name = "vcc18_cif"; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-always-on; - }; - - vcc_18: regulator@8 { - regulator-name = "vcc_18"; - regulator-always-on; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-always-on; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-always-on; - }; - - vcc_rmii: regulator@11 { - regulator-name = "vcc_rmii"; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-always-on; - }; - }; - }; -}; - -/* must be included after &tps gets defined */ -#include "tps65910.dtsi" - -&emac { - status = "okay"; - - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&mmc0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; -}; - -&pinctrl { - lan8720a { - phy_int: phy-int { - rockchip,pins = ; - }; - }; -}; - -&pwm3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3066a-rayeager.dts b/software/linux/kernel/arch/arm/boot/dts/rk3066a-rayeager.dts deleted file mode 100644 index 6e7f2187a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3066a-rayeager.dts +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "rk3066a.dtsi" - -/ { - model = "Rayeager PX2"; - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - power { - wakeup-source; - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 1000>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - voltage-table = <1000000 100>, - <1200000 42>; - status = "okay"; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */ - vcc_stdby: 5v-stdby-regulator { - compatible = "regulator-fixed"; - regulator-name = "5v_stdby"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_emmc: emmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "emmc_vccq"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vsys>; - }; - - vcc_sata: sata-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sata_pwr>; - regulator-name = "usb_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_drv>; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_drv>; - regulator-name = "vcc_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_stdby>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm>; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; - vmmc-supply = <&vcc_emmc>; - vqmmc-supply = <&vcc_emmc>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - ak8963: ak8963@0d { - compatible = "asahi-kasei,ak8975"; - reg = <0x0d>; - interrupt-parent = <&gpio4>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&comp_int>; - }; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - tps: tps@2d { - reg = <0x2d>; - interrupt-parent = <&gpio6>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&pwr_hold>; - - vcc1-supply = <&vsys>; - vcc2-supply = <&vsys>; - vcc3-supply = <&vsys>; - vcc4-supply = <&vsys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - vcc7-supply = <&vsys>; - vccio-supply = <&vsys>; - - regulators { - vcc_rtc: regulator@0 { - regulator-name = "vcc_rtc"; - regulator-always-on; - }; - - vcc_io: regulator@1 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_arm: regulator@2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_ddr: regulator@3 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc18: regulator@5 { - regulator-name = "vcc18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_11: regulator@6 { - regulator-name = "vdd_11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_25: regulator@7 { - regulator-name = "vcc_25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vccio_wl: regulator@8 { - regulator-name = "vccio_wl"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc25_hdmi: regulator@9 { - regulator-name = "vcc25_hdmi"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vcca_33: regulator@10 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_rmii: regulator@11 { - regulator-name = "vcc_rmii"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc28_cif: regulator@12 { - regulator-name = "vcc28_cif"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - }; - }; -}; - -#include "tps65910.dtsi" - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&mmc0 { - bus-width = <4>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd>; - cap-mmc-highspeed; - cap-sd-highspeed; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; - vmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - ak8963 { - comp_int: comp-int { - rockchip,pins = <4 17 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - emac { - rmii_rst: rmii-rst { - rockchip,pins = <1 30 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <6 1 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <6 2 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - mma8452 { - gsensor_int: gsensor-int { - rockchip,pins = <4 16 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - mmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 7 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - usb_host { - host_drv: host-drv { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - hub_rst: hub-rst { - rockchip,pins = <1 31 RK_FUNC_GPIO &pcfg_output_high>; - }; - - sata_pwr: sata-pwr { - rockchip,pins = <4 22 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - sata_reset: sata-reset { - rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_drv: otg-drv { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - tps { - pmic_int: pmic-int { - rockchip,pins = <6 4 RK_FUNC_GPIO &pcfg_pull_default>; - }; - - pwr_hold: pwr-hold { - rockchip,pins = <6 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_25>; - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>, <&uart3_cts>, <&uart3_rts>; - status = "okay"; -}; - -&usb_host { - pinctrl-names = "default"; - pinctrl-0 = <&hub_rst>, <&sata_reset>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3066a.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3066a.dtsi deleted file mode 100644 index 0d0dae3a1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3066a.dtsi +++ /dev/null @@ -1,696 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3066a"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - operating-points = < - /* kHz uV */ - 1416000 1300000 - 1200000 1175000 - 1008000 1125000 - 816000 1125000 - 600000 1100000 - 504000 1100000 - 312000 1075000 - >; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x10000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - i2s0: i2s@10118000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x10118000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - dmas = <&dmac1_s 4>, <&dmac1_s 5>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - i2s1: i2s@1011a000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - i2s2: i2s@1011c000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011c000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - dmas = <&dmac1_s 9>, <&dmac1_s 10>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3066a-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - - timer@2000e000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2000e000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rockchip-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - timer@20038000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x20038000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; - - timer@2003a000 { - compatible = "snps,dw-apb-timer-osc"; - reg = <0x2003a000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; - }; - - tsadc: tsadc@20060000 { - compatible = "rockchip,rk3066-tsadc"; - reg = <0x20060000 0x100>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "saradc", "apb_pclk"; - interrupts = ; - #io-channel-cells = <1>; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - usbphy: phy { - compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@17c { - #phy-cells = <0>; - reg = <0x17c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@188 { - #phy-cells = <0>; - reg = <0x188>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio6@2000a000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg_pull_none { - bias-disable; - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = , /* mac_clk */ - , /* tx_en */ - , /* txd1 */ - , /* txd0 */ - , /* rx_err */ - , /* crs_dvalid */ - , /* rxd1 */ - ; /* rxd0 */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = , /* mac_md */ - ; /* mac_mdclk */ - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = ; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = ; - }; - - emmc_rst: emmc-rst { - rockchip,pins = ; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = , - ; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = , - ; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = , - ; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = , - ; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = , - ; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = ; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = ; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = ; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = ; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = ; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = ; - }; - spi0_tx: spi0-tx { - rockchip,pins = ; - }; - spi0_rx: spi0-rx { - rockchip,pins = ; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = ; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = ; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = ; - }; - spi1_rx: spi1-rx { - rockchip,pins = ; - }; - spi1_tx: spi1-tx { - rockchip,pins = ; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = ; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = , - ; - }; - - uart0_cts: uart0-cts { - rockchip,pins = ; - }; - - uart0_rts: uart0-rts { - rockchip,pins = ; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = , - ; - }; - - uart1_cts: uart1-cts { - rockchip,pins = ; - }; - - uart1_rts: uart1-rts { - rockchip,pins = ; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = , - ; - }; - - uart3_cts: uart3-cts { - rockchip,pins = ; - }; - - uart3_rts: uart3-rts { - rockchip,pins = ; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = ; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = ; - }; - - sd0_cd: sd0-cd { - rockchip,pins = ; - }; - - sd0_wp: sd0-wp { - rockchip,pins = ; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = ; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = ; - }; - - sd1_cd: sd1-cd { - rockchip,pins = ; - }; - - sd1_wp: sd1-wp { - rockchip,pins = ; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = , - , - , - , - , - , - , - , - ; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = , - , - , - , - , - ; - }; - }; - - i2s2 { - i2s2_bus: i2s2-bus { - rockchip,pins = , - , - , - , - , - ; - }; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&wdt { - compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; -}; - -&emac { - compatible = "rockchip,rk3066-emac"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3188-radxarock.dts b/software/linux/kernel/arch/arm/boot/dts/rk3188-radxarock.dts deleted file mode 100644 index 1da46d138..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3188-radxarock.dts +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Copyright (c) 2013 Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "rk3188.dtsi" - -/ { - model = "Radxa Rock"; - compatible = "radxa,rock", "rockchip,rk3188"; - - memory { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green { - label = "rock:green:user1"; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue { - label = "rock:blue:user2"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - sleep { - label = "rock:red:power"; - gpios = <&gpio0 15 0>; - default-state = "off"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - ir_recv: gpio-ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 10 1>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_recv_pin>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd0: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 1 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&emac { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_arm>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - system-power-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&act8846_dvs0_ctl>; - - vp1-supply = <&vsys>; - vp2-supply = <&vsys>; - vp3-supply = <&vsys>; - vp4-supply = <&vsys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vsys>; - inl3-supply = <&vsys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_log: REG2 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_arm: REG3 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vcc_io: REG4 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG5 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_hdmi: REG6 { - regulator-name = "VDD_HDMI"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vcc18: REG7 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_rmii: REG9 { - regulator-name = "VCC_RMII"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccio_wl: REG10 { - regulator-name = "VCCIO_WL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC18_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc28: REG12 { - regulator-name = "VCC_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; -}; - -&mmc0 { - num-slots = <1>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - act8846_dvs0_ctl: act8846-dvs0-ctl { - rockchip,pins = ; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = ; - }; - }; - - lan8720a { - phy_int: phy-int { - rockchip,pins = ; - }; - }; - - ir-receiver { - ir_recv_pin: ir-recv-pin { - rockchip,pins = ; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3188.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3188.dtsi deleted file mode 100644 index 31f81b265..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3188.dtsi +++ /dev/null @@ -1,623 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3188"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - operating-points = < - /* kHz uV */ - 1608000 1350000 - 1416000 1250000 - 1200000 1150000 - 1008000 1075000 - 816000 975000 - 600000 950000 - 504000 925000 - 312000 875000 - >; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x3>; - }; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - i2s0: i2s@1011a000 { - compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - spdif: sound@1011e000 { - compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; - reg = <0x1011e000 0x2000>; - #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; - dmas = <&dmac1_s 8>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rockchip-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - usbphy: phy { - compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - #phy-cells = <0>; - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@11c { - #phy-cells = <0>; - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg_pull_up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg_pull_down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg_pull_none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = ; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = ; - }; - - emmc_rst: emmc-rst { - rockchip,pins = ; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = , /* tx_en */ - , /* txd1 */ - , /* txd0 */ - , /* rxd0 */ - , /* rxd1 */ - , /* mac_clk */ - , /* rx_err */ - ; /* crs_dvalid */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = , - ; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = , - ; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = , - ; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = , - ; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = , - ; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = , - ; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = ; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = ; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = ; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = ; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = ; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = ; - }; - spi0_tx: spi0-tx { - rockchip,pins = ; - }; - spi0_rx: spi0-rx { - rockchip,pins = ; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = ; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = ; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = ; - }; - spi1_rx: spi1-rx { - rockchip,pins = ; - }; - spi1_tx: spi1-tx { - rockchip,pins = ; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = ; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = , - ; - }; - - uart0_cts: uart0-cts { - rockchip,pins = ; - }; - - uart0_rts: uart0-rts { - rockchip,pins = ; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = , - ; - }; - - uart1_cts: uart1-cts { - rockchip,pins = ; - }; - - uart1_rts: uart1-rts { - rockchip,pins = ; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = , - ; - }; - - uart3_cts: uart3-cts { - rockchip,pins = ; - }; - - uart3_rts: uart3-rts { - rockchip,pins = ; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = ; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = ; - }; - - sd0_cd: sd0-cd { - rockchip,pins = ; - }; - - sd0_wp: sd0-wp { - rockchip,pins = ; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = ; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = ; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = ; - }; - - sd1_cd: sd1-cd { - rockchip,pins = ; - }; - - sd1_wp: sd1-wp { - rockchip,pins = ; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = , - , - , - , - , - ; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = ; - }; - }; - }; -}; - -&emac { - compatible = "rockchip,rk3188-emac"; -}; - -&global_timer { - interrupts = ; -}; - -&local_timer { - interrupts = ; -}; - -&i2c0 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&wdt { - compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3228-evb.dts b/software/linux/kernel/arch/arm/boot/dts/rk3228-evb.dts deleted file mode 100644 index 904668e2e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3228-evb.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rk322x.dtsi" - -/ { - model = "Rockchip RK3228 Evaluation board"; - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; -}; - -&emmc { - cap-mmc-highspeed; - mmc-ddr-1_8v; - disable-wp; - non-removable; - status = "okay"; -}; - -&tsadc { - status = "okay"; - - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ -}; - -&uart2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3229-evb.dts b/software/linux/kernel/arch/arm/boot/dts/rk3229-evb.dts deleted file mode 100644 index b6a12035a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3229-evb.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rk322x.dtsi" - -/ { - model = "Rockchip RK3229 Evaluation board"; - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk322x.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk322x.dtsi deleted file mode 100644 index 9e6bf0e31..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk322x.dtsi +++ /dev/null @@ -1,705 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - i2s1: i2s1@100b0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100b0000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - dmas = <&pdma 14>, <&pdma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s0: i2s0@100c0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100c0000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - dmas = <&pdma 11>, <&pdma 12>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2s2: i2s2@100e0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100e0000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - grf: syscon@11000000 { - compatible = "syscon"; - reg = <0x11000000 0x1000>; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <0>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - emmc: dwmmc@30020000 { - compatible = "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = ; - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rk3228-gmac"; - reg = <0x30200000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, - <2 12 RK_FUNC_1 &pcfg_pull_none>, - <2 25 RK_FUNC_1 &pcfg_pull_none>, - <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 17 RK_FUNC_1 &pcfg_pull_none>, - <2 16 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_2 &pcfg_pull_none>, - <2 20 RK_FUNC_2 &pcfg_pull_none>, - <2 11 RK_FUNC_1 &pcfg_pull_none>, - <2 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, - <2 12 RK_FUNC_1 &pcfg_pull_none>, - <2 25 RK_FUNC_1 &pcfg_pull_none>, - <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 17 RK_FUNC_1 &pcfg_pull_none>, - <2 16 RK_FUNC_1 &pcfg_pull_none>, - <2 8 RK_FUNC_1 &pcfg_pull_none>, - <2 15 RK_FUNC_1 &pcfg_pull_none>; - }; - - phy_pins: phy-pins { - rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, - <2 8 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, - <0 9 RK_FUNC_1 &pcfg_pull_none>, - <0 11 RK_FUNC_1 &pcfg_pull_none>, - <0 12 RK_FUNC_1 &pcfg_pull_none>, - <0 13 RK_FUNC_1 &pcfg_pull_none>, - <0 14 RK_FUNC_1 &pcfg_pull_none>, - <1 2 RK_FUNC_1 &pcfg_pull_none>, - <1 4 RK_FUNC_1 &pcfg_pull_none>, - <1 5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, - <2 27 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-evb-act8846.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-evb-act8846.dts deleted file mode 100644 index 041dd5d2d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; - - vcc_lcd: vcc-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_en>; - regulator-name = "vcc_lcd"; - vin-supply = <&vcc_io>; - }; - - vcc_wl: vcc-wl { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwr>; - regulator-name = "vcc_wl"; - vin-supply = <&vcc_18>; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&panel { - power-supply = <&vcc_lcd>; -}; - -&pinctrl { - lcd { - lcd_en: lcd-en { - rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_pwr: wifi-pwr { - rockchip,pins = <7 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-evb-rk808.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-evb-rk808.dts deleted file mode 100644 index 44ebc6e59..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ /dev/null @@ -1,239 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; -}; - -&i2c0 { - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vccio_pmu>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_codec: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&panel { - power-supply = <&vcc_lcd>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-evb.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288-evb.dtsi deleted file mode 100644 index d59208b5e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-evb.dtsi +++ /dev/null @@ -1,396 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include "rk3288.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <128>; - enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - panel: panel { - compatible ="lg,lp079qx1-sp0v", "simple-panel"; - backlight = <&backlight>; - enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&lcd_cs>; - - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */ - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_pwr>; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from - * vcc_io directly. Those boards won't be able to power cycle SD cards - * but it shouldn't hurt to toggle this pin there anyway. - */ - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&edp { - force-hpd; - status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp_phy { - status = "okay"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_cs: lcd-cs { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = ; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on EVB board so bump up to 8ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - eth_phy { - eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-fennec.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-fennec.dts deleted file mode 100644 index 2e3c34135..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-fennec.dts +++ /dev/null @@ -1,382 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rk3288.dtsi" - -/ { - model = "Rockchip RK3288 Fennec Board"; - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - - memory { - reg = <0x0 0x80000000>; - device_type = "memory"; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_io>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_33: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_wl: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_sd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lan: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lan"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = ; - }; - }; - - usbphy { - host_drv: host-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&host_drv>; - vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usb_hsic { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-beta.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-beta.dts deleted file mode 100644 index 75d77e38e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-beta.dts +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-firefly.dtsi" - -/ { - model = "Firefly-RK3288 Beta"; - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; -}; - -&ir { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; -}; - -&pinctrl { - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi deleted file mode 100644 index ec418c99d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Device tree file for Firefly Rockchip RK3288 Core board - * Copyright (c) 2016 Randy Li - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "rk3288.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_lan: REG9 { - regulator-name = "vcca_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vccio_wl: vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vccio_wl>; - bb-supply = <&vcc_io>; - dvp-supply = <&dovdd_1v8>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - pmic_vsel: pmic-vsel { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-reload.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-reload.dts deleted file mode 100644 index 751bee811..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ /dev/null @@ -1,403 +0,0 @@ -/* - * Device tree file for Firefly Rockchip RK3288 Core board - * Copyright (c) 2016 Randy Li - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-firefly-reload-core.dtsi" - -/ { - model = "Firefly-RK3288-reload"; - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; - - gpio-keys { - compatible = "gpio-keys"; - - power { - wakeup-source; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - power { - gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; - label = "firefly:blue:power"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led>; - panic-indicator; - }; - - work { - gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; - label = "firefly:blue:user"; - linux,default-trigger = "rc-feedback"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_5v: vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - dovdd_1v8: dovdd-1v8-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "dovdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_io>; - }; - - af_28: af_28-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "af_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_io>; - }; - - dvdd_1v2: af_28-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_pwr>; - regulator-name = "dvdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vcc_io>; - }; - - vbat_wl: wifi-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat_wl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; -}; - -&i2c0 { - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; -}; - -&i2c2 { - status = "okay"; - - codec: es8328@10 { - compatible = "everest,es8328"; - DVDD-supply = <&vcca_33>; - AVDD-supply = <&vcca_33>; - PVDD-supply = <&vcca_33>; - HPVDD-supply = <&vcca_33>; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - clock-names = "i2s_hclk", "i2s_clk"; - reg = <0x10>; - }; -}; - -&i2s { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - vmmc-supply = <&vbat_wl>; - vqmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&usbhub_rst>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cif_pwr: cif-pwr { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - power_led: power-led { - rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led: work-led { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_enable: wifi-enable { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbhub_rst: usbhub-rst { - rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly.dts deleted file mode 100644 index c07fe92dc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly.dts +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-firefly.dtsi" - -/ { - model = "Firefly-RK3288"; - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; -}; - -&ir { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; -}; - -&pinctrl { - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly.dtsi deleted file mode 100644 index 114c90fb6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-firefly.dtsi +++ /dev/null @@ -1,596 +0,0 @@ -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "rk3288.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0 0x80000000>; - }; - - dovdd_1v8: dovdd-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "dovdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - power { - wakeup-source; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; - label = "firefly:blue:user"; - linux,default-trigger = "rc-feedback"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led>; - }; - - power { - gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; - label = "firefly:green:power"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led>; - }; - }; - - vbat_wl: vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - /* - * A TT8142 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vccio_wl: vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&dovdd_1v8>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - power_led: power-led { - rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led: work-led { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbhub_rst: usbhub-rst { - rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; - vmmc-supply = <&vbat_wl>; - vqmmc-supply = <&vccio_wl>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&usbhub_rst>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-miqi.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-miqi.dts deleted file mode 100644 index 24488421f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-miqi.dts +++ /dev/null @@ -1,472 +0,0 @@ -/* - * Copyright (c) 2016 Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "rk3288.dtsi" - -/ { - model = "mqmaker MiQi"; - compatible = "mqmaker,miqi", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - label = "miqi:green:user"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&led_ctl>; - }; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pmic_int: pmic-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_sleep: pmic-sleep { - rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pmic_vsel: pmic-vsel { - rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - leds { - led_ctl: led-ctl { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - /* - * The otg controller is the only system power source, - * so needs to always stay in device mode. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-popmetal.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-popmetal.dts deleted file mode 100644 index 56dd377d5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-popmetal.dts +++ /dev/null @@ -1,535 +0,0 @@ -/* - * Copyright (c) 2014, 2015 Andy Yan - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "rk3288.dtsi" - -/ { - model = "PopMetal-RK3288"; - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - - memory{ - device_type = "memory"; - reg = <0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ - vcc18_dvp: vcc18-dvp-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc18-dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lan: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_lan"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - ldo5: LDO_REG5 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ldo5"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_33: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vccio_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - ak8963: ak8963@0d { - compatible = "asahi-kasei,ak8975"; - reg = <0x0d>; - interrupt-parent = <&gpio8>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&comp_int>; - vdd-supply = <&vcc_io>; - vid-supply = <&vcc_io>; - }; - - l3g4200d: l3g4200d@69 { - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x69>; - vdd-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - }; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&gpio8>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc18_dvp>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; -}; - -&pinctrl { - ak8963 { - comp_int: comp-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - mma8452 { - gsensor_int: gsensor-int { - rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = ; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-r89.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-r89.dts deleted file mode 100644 index 4b8a8adb2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-r89.dts +++ /dev/null @@ -1,425 +0,0 @@ -/* - * Copyright (c) 2015 Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include -#include "rk3288.dtsi" - -/ { - compatible = "netxeon,r89", "rockchip,rk3288"; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_otg: vcc-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sdmmc: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "sys-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "ok"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: pmic@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "VDD_CPU"; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: pmic@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "VDD_GPU"; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - }; - - act8846: pmic@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_wl: REG7 { - regulator-name = "VCC_WL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_lan: REG9 { - regulator-name = "VCC_LAN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pwr_hold: pwr-hold { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = ; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sdmmc>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288-rock2-som.dtsi deleted file mode 100644 index bb1f01e03..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x80000000>; - device_type = "memory"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <150>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - mmc-pwrseq = <&emmc_pwrseq>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vccio_pmu>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins &phy_rst>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - rx_delay = <0x10>; - tx_delay = <0x30>; -}; - -&i2c0 { - status = "okay"; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - system-power-controller; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcc_io>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vccio_pmu>; - gpio30-supply = <&vccio_pmu>; - gpio1830 = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <3 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-rock2-square.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-rock2-square.dts deleted file mode 100644 index dd3ad2e93..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-rock2-square.dts +++ /dev/null @@ -1,226 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-rock2-som.dtsi" - -/ { - model = "Radxa Rock 2 Square"; - compatible = "radxa,rock2-square", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - heartbeat { - gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; - label = "rock2:green:state1"; - linux,default-trigger = "heartbeat"; - }; - - mmc { - gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - label = "rock2:blue:state2"; - linux,default-trigger = "mmc0"; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - }; - - vcc_usb_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - /* Always on as the rockchip usb phy doesn't have a vbus-supply - * property - */ - regulator-always-on; - regulator-name = "vcc_host"; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - status = "ok"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - }; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio { - wifi_enable: wifi-enable { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi deleted file mode 100644 index 6d105914a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Google Veyron (and derivatives) fragment for the max98090 audio - * codec and analog headphone jack. - * - * Copyright 2016 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - sound { - compatible = "rockchip,rockchip-audio-max98090"; - pinctrl-names = "default"; - pinctrl-0 = <&mic_det>, <&hp_det>; - rockchip,model = "VEYRON-I2S"; - rockchip,i2s-controller = <&i2s>; - rockchip,audio-codec = <&max98090>; - rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; - rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - rockchip,headset-codec = <&headsetcodec>; - }; -}; - -&i2c2 { - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio6>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S0_OUT>; - pinctrl-names = "default"; - pinctrl-0 = <&int_codec>; - }; -}; - -&i2c4 { - headsetcodec: ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ts3a227e_int_l>; - ti,micbias = <7>; /* MICBIAS = 2.8V */ - }; -}; - -&i2s { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcc18_codec>; -}; - -&rk808 { - vcc10-supply = <&vcc33_sys>; - - regulators { - vcc18_codec: LDO_REG6 { - regulator-name = "vcc18_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&pinctrl { - codec { - hp_det: hp-det { - rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - /* - * HACK: We're going to _pull down_ this _active low_ interrupt - * so that it never fires. We don't need this interrupt because - * we've got a ts3a227e chip but the driver requires it. - */ - int_codec: int-codec { - rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - mic_det: mic-det { - rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headset { - ts3a227e_int_l: ts3a227e-int-l { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-brain.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-brain.dts deleted file mode 100644 index cf5311d26..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-brain.dts +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Google Veyron Brain Rev 0 board device tree source - * - * Copyright 2014 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron.dtsi" - -/ { - model = "Google Brain"; - compatible = "google,veyron-brain-rev0", "google,veyron-brain", - "google,veyron", "rockchip,rk3288"; - - vcc33_sys: vcc33-sys { - vin-supply = <&vcc_5v>; - }; - - vcc33_io: vcc33_io { - compatible = "regulator-fixed"; - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc33_sys>; - /* This is gated by vcc_18 too */ - }; - - /* This turns on vbus for host2 and otg (dwc2) */ - vcc5_host2: vcc5-host2-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pwr_en>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&pinctrl { - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb-host { - usb2_pwr_en: usb2-pwr-en { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - - /delete-property/ vcc6-supply; - - regulators { - /* vcc33_io is sourced directly from vcc33_sys */ - /delete-node/ LDO_REG1; - - /* This is not a pwren anymore, but the real power supply */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; - }; - - vcc18_hdmi: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc18_hdmi"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio7 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi deleted file mode 100644 index ce1f87980..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Google Veyron (and derivatives) board device tree source - * Chromebook specific parts - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include "rk3288-veyron.dtsi" -#include "rk3288-veyron-analog-audio.dtsi" -#include "rk3288-veyron-sdmmc.dtsi" - -/ { - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = &i2c_tunnel; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <128>; - enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - backlight-boot-off; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 0>; - pwm-delay-us = <10000>; - }; - - gpio-charger { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ac_present_ap>; - }; - - panel: panel { - compatible ="innolux,n116bge", "simple-panel"; - status = "okay"; - power-supply = <&vcc33_lcd>; - backlight = <&backlight>; - - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - }; - - /* A non-regulated voltage from power supply or battery */ - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - vcc33_sys: vcc33-sys { - vin-supply = <&vccsys>; - }; - - vcc_5v: vcc-5v { - vin-supply = <&vccsys>; - }; - - /* This turns on vbus for host1 (dwc2) */ - vcc5_host1: vcc5-host1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host1_pwr_en>; - regulator-name = "vcc5_host1"; - regulator-always-on; - regulator-boot-on; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usbotg_pwren_h>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&edp { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - edp_out_panel: endpoint { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp_phy { - status = "okay"; -}; - -&gpio_keys { - pinctrl-0 = <&pwr_key_l &ap_lid_int_l>; - lid { - label = "Lid"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = <0>; /* SW_LID */ - linux,input-type = <5>; /* EV_SW */ - debounce-interval = <1>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&rk808 { - vcc11-supply = <&vcc_5v>; - - regulators { - vcc33_ccd: LDO_REG8 { - regulator-name = "vcc33_ccd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - google,cros-ec-spi-pre-delay = <30>; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_int>; - spi-max-frequency = <3000000>; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c4 { - trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&pinctrl { - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &global_pwroff - - /* Wake only */ - &suspend_l_wake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - >; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - ap_lid_int_l: ap-lid-int-l { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - charger { - ac_present_ap: ac-present-ap { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - cros-ec { - ec_int: ec-int { - rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - suspend { - suspend_l_wake: suspend-l-wake { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>; - }; - - suspend_l_sleep: suspend-l-sleep { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - trackpad { - trackpad_int: trackpad-int { - rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-host { - host1_pwr_en: host1-pwr-en { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbotg_pwren_h: usbotg-pwren-h { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-jaq.dts deleted file mode 100644 index 3748abf56..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Google Veyron Jaq Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jaq"; - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", - "google,veyron-jaq-rev1", "google,veyron-jaq", - "google,veyron", "rockchip,rk3288"; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - startup-delay-us = <100000>; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; -}; - -&backlight { - /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ - brightness-levels = < - 0 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - power-supply = <&backlight_regulator>; -}; - -&panel { - power-supply = <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-name = "mic_vcc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-jerry.dts deleted file mode 100644 index f6b2eaaeb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Google Veyron Jerry Rev 3+ board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jerry"; - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - startup-delay-us = <100000>; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; -}; - -&backlight { - power-supply = <&backlight_regulator>; -}; - -&panel { - power-supply= <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-name = "mic_vcc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&i2c4 { - status = "okay"; - - /* - * Trackpad pin control is shared between Elan and Synaptics devices - * so we have to pull it up to the bus level. - */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer &trackpad_int>; - - trackpad@15 { - /* - * Remove the inherited pinctrl settings to avoid clashing - * with bus-wide ones. - */ - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - }; - - trackpad@2c { - compatible = "hid-over-i2c"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-mickey.dts deleted file mode 100644 index f36f6f459..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-mickey.dts +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Google Veyron Mickey Rev 0 board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron.dtsi" - -/ { - model = "Google Mickey"; - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - - vcc_5v: vcc-5v { - vin-supply = <&vcc33_sys>; - }; - - vcc33_io: vcc33_io { - compatible = "regulator-fixed"; - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc33_sys>; - }; -}; - -&cpu_thermal { - /delete-node/ trips; - /delete-node/ cooling-maps; - - trips { - cpu_alert_almost_warm: cpu_alert_almost_warm { - temperature = <63000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_warm: cpu_alert_warm { - temperature = <65000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_almost_hot: cpu_alert_almost_hot { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hot: cpu_alert_hot { - temperature = <82000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hotter: cpu_alert_hotter { - temperature = <84000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_very_hot: cpu_alert_very_hot { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * After 1st level, throttle the CPU down to as low as 1.4 GHz - * and don't let the GPU go faster than 400 MHz. Note that we - * won't throttle the GPU lower than 400 MHz due to CPU - * heat--we'll let the GPU do the rest itself. - */ - cpu_warm_limit_cpu { - trip = <&cpu_alert_warm>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 4>; - }; - - /* - * Add some discrete steps to help throttling system deal - * with the fact that there are two passive cooling devices: - * the CPU and the GPU. - * - * - 1.2 GHz - 1.0 GHz (almost hot) - * - 800 MHz (hot) - * - 800 MHz - 696 MHz (hotter) - * - 696 MHz - min (very hot) - * - * Note: - * - 800 MHz appears to be a "sweet spot" for me. I can run - * some pretty serious workload here and be happy. - * - After 696 MHz we stop lowering voltage, so throttling - * past there is less effective. - */ - cpu_almost_hot_limit_cpu { - trip = <&cpu_alert_almost_hot>; - cooling-device = - <&cpu0 5 6>; - }; - cpu_hot_limit_cpu { - trip = <&cpu_alert_hot>; - cooling-device = - <&cpu0 7 7>; - }; - cpu_hotter_limit_cpu { - trip = <&cpu_alert_hotter>; - cooling-device = - <&cpu0 7 8>; - }; - cpu_very_hot_limit_cpu { - trip = <&cpu_alert_very_hot>; - cooling-device = - <&cpu0 8 THERMAL_NO_LIMIT>; - }; - }; -}; - -&emmc { - /delete-property/mmc-hs200-1_8v; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c4 { - status = "disabled"; -}; - -&i2s { - status = "okay"; - clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - - /delete-property/ vcc6-supply; - /delete-property/ vcc12-supply; - - vcc11-supply = <&vcc33_sys>; - - regulators { - /* vcc33_io is sourced directly from vcc33_sys */ - /delete-node/ LDO_REG1; - /delete-node/ LDO_REG7; - - /* This is not a pwren anymore, but the real power supply */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&pinctrl { - hdmi { - power_hdmi_on: power-hdmi-on { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host1 { - status = "disabled"; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&power_hdmi_on>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-minnie.dts deleted file mode 100644 index f72d616d1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Google Veyron Minnie Rev 0+ board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" - -/ { - model = "Google Minnie"; - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - startup-delay-us = <100000>; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; -}; - -&backlight { - /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = < - 0 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - power-supply = <&backlight_regulator>; -}; - -&emmc { - /delete-property/mmc-hs200-1_8v; -}; - -&gpio_keys { - pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>; - - volum_down { - label = "Volum_down"; - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; - - volum_up { - label = "Volum_up"; - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; -}; - -&i2c_tunnel { - battery: bq27500@55 { - compatible = "ti,bq27500"; - reg = <0x55>; - }; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio2>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int &touch_rst>; - reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - vcc33-supply = <&vcc33_touch>; - vccio-supply = <&vcc33_touch>; - }; -}; - -&panel { - compatible = "auo,b101ean01", "simple-panel"; - power-supply= <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - - regulators { - vcc33_touch: LDO_REG2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v_touch: SWITCH_REG2 { - regulator-name = "vcc5v_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - volum_down_l: volum-down-l { - rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - volum_up_l: volum-up-l { - rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - prochot { - gpio_prochot: gpio-prochot { - rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touchscreen { - touch_int: touch-int { - rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - touch_rst: touch-rst { - rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-pinky.dts deleted file mode 100644 index d44351ec2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Google Veyron Pinky Rev 2 board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Pinky"; - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", - "google,veyron", "rockchip,rk3288"; - - /delete-node/emmc-pwrseq; -}; - -&emmc { - /* - * Use a pullup instead of a drive since the output is 3.3V and - * really should be 1.8V (oops). The external pulldown will help - * bring the voltage down if we only drive with a pullup here. - * Therefore disable the powerseq (and actual reset) for pinky. - */ - /delete-property/mmc-pwrseq; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>; -}; - -&edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - - force-hpd; -}; - -&gpio_keys { - pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; - - power { - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - }; -}; - -/* Touchpad connector */ -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; -}; - -&pinctrl { - buttons { - pwr_key_h: pwr-key-h { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { - rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&rk808 { - regulators { - vcc18_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_wp_gpio &sdmmc_bus4>; - wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; -}; - -&tsadc { - /* Some connection is flaky making the tsadc hang the system */ - status = "disabled"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi deleted file mode 100644 index fec076eb7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Google Veyron (and derivatives) fragment for sdmmc cards - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&io_domains { - sdcard-supply = <&vccio_sd>; -}; - -&pinctrl { - sdmmc { - /* - * We run sdmmc at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * Builtin CD line is hooked to ground to prevent JTAG at boot - * (and also to get the voltage rail correct). - * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't - * think there's a card inserted - */ - sdmmc_cd_disabled: sdmmc-cd-disabled { - rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* This is where we actually hook up CD */ - sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rk808 { - vcc9-supply = <&vcc_5v>; - - regulators { - vccio_sd: LDO_REG4 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc33_sd: LDO_REG5 { - regulator-name = "vcc33_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - status = "okay"; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - rockchip,default-sample-phase = <90>; - num-slots = <1>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc33_sd>; - vqmmc-supply = <&vccio_sd>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-speedy.dts deleted file mode 100644 index a0d033f6f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Google Veyron Speedy Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Speedy"; - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - startup-delay-us = <100000>; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; -}; - -&backlight { - power-supply = <&backlight_regulator>; -}; - -&cpu_alert0 { - temperature = <65000>; -}; - -&cpu_alert1 { - temperature = <70000>; -}; - -&edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - - force-hpd; -}; - -&panel { - power-supply= <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron.dtsi deleted file mode 100644 index 3dd2cca48..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288-veyron.dtsi +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Google Veyron (and derivatives) board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include "rk3288.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x0 0x80000000>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_l>; - power { - label = "Power"; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_warm_reset_h>; - priority = <200>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 RK808_CLKOUT1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - }; - - vcc_5v: vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc33_sys: vcc33-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc33_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc50_hdmi: vcc50-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vcc50_hdmi"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_5v>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; - operating-points = < - /* KHz uV */ - 1800000 1400000 - 1704000 1350000 - 1608000 1300000 - 1512000 1250000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 216000 900000 - 126000 900000 - >; -}; - -&emmc { - status = "okay"; - - bus-width = <8>; - cap-mmc-highspeed; - rockchip,default-sample-phase = <158>; - disable-wp; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 45ns measured */ - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - clock-output-names = "xin32k", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vcc33_sys>; - vcc2-supply = <&vcc33_sys>; - vcc3-supply = <&vcc33_sys>; - vcc4-supply = <&vcc33_sys>; - vcc6-supply = <&vcc_5v>; - vcc7-supply = <&vcc33_sys>; - vcc8-supply = <&vcc33_sys>; - vcc12-supply = <&vcc_18>; - vddio-supply = <&vcc33_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc135_ddr: DCDC_REG3 { - regulator-name = "vcc135_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - /* - * vcc_18 has several aliases. (vcc18_flashio and - * vcc18_wl). We'll add those aliases here just to - * make it easier to follow the schematic. The signals - * are actually hooked together and only separated for - * power measurement purposes). - */ - vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* - * Note that both vcc33_io and vcc33_pmuio are always - * powered together. To simplify the logic in the dts - * we just refer to vcc33_io every time something is - * powered from vcc33_pmuio. In fact, on later boards - * (such as danger) they're the same net. - */ - vcc33_io: LDO_REG1 { - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd10_lcd_pwren_h: LDO_REG7 { - regulator-name = "vdd10_lcd_pwren_h"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc33_lcd: SWITCH_REG1 { - regulator-name = "vcc33_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 40ns measured */ - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -&i2c2 { - status = "okay"; - - /* 100kHz since 4.7k resistors don't rise fast enough */ - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <50>; /* 10ns measured */ - i2c-scl-rising-time-ns = <800>; /* 600ns measured */ -}; - -&i2c4 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 11ns measured */ - i2c-scl-rising-time-ns = <300>; /* 225ns measured */ -}; - -&i2c5 { - status = "okay"; - - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <300>; - i2c-scl-rising-time-ns = <1000>; -}; - -&io_domains { - status = "okay"; - - bb-supply = <&vcc33_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc18_flashio>; - gpio1830-supply = <&vcc33_io>; - gpio30-supply = <&vcc33_io>; - lcdc-supply = <&vcc33_lcd>; - wifi-supply = <&vcc18_wl>; -}; - -&pwm1 { - status = "okay"; -}; - -&sdio0 { - status = "okay"; - - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc33_sys>; - vqmmc-supply = <&vcc18_wl>; -}; - -&spi2 { - status = "okay"; - - rx-sample-delay-ns = <12>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&tsadc { - status = "okay"; - - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ -}; - -&uart0 { - status = "okay"; - - /* We need to go faster than 24MHz, so adjust clock parents / rates */ - assigned-clocks = <&cru SCLK_UART0>; - assigned-clock-rates = <48000000>; - - /* Pins don't include flow control by default; add that in */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; - - needs-reset-on-resume; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; - - assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; - assigned-clock-parents = <&usbphy0>; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &global_pwroff - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &global_pwroff - >; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - buttons { - pwr_key_l: pwr-key-l { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = ; - }; - }; - - reboot { - ap_warm_reset_h: ap-warm-reset-h { - rockchip,pins = ; - }; - }; - - recovery-switch { - rec_mode_l: rec-mode-l { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio0 { - wifi_enable_h: wifienable-h { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* NOTE: mislabelled on schematic; should be bt_enable_h */ - bt_enable_l: bt-enable-l { - rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run sdio0 at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - }; - - tpm { - tpm_int_h: tpm-int-h { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - write-protect { - fw_wp_ap: fw-wp-ap { - rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3288.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3288.dtsi deleted file mode 100644 index 17ec2e2d7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3288.dtsi +++ /dev/null @@ -1,1691 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "rockchip,rk3288"; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio0; - mshc3 = &sdio1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - arm-pmu { - compatible = "arm,cortex-a12-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - rockchip,pmu = <&pmu>; - - cpu0: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x500>; - resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 1608000 1350000 - 1512000 1300000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 312000 900000 - 216000 900000 - 126000 900000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - cpu1: cpu@501 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x501>; - resets = <&cru SRST_CORE1>; - }; - cpu2: cpu@502 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x502>; - resets = <&cru SRST_CORE2>; - }; - cpu3: cpu@503 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x503>; - resets = <&cru SRST_CORE3>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xff250000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - - dmac_bus_ns: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xff600000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dmac_bus_s: dma-controller@ffb20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffb20000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * The rk3288 cannot use the memory area above 0xfe000000 - * for dma operations for some reason. While there is - * probably a better solution available somewhere, we - * haven't found it yet and while devices with 2GB of ram - * are not affected, this issue prevents 4GB from booting. - * So to make these devices at least bootable, block - * this area for the time being until the real solution - * is found. - */ - dma-unusable@fe000000 { - reg = <0xfe000000 0x1000000>; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - timer: timer@ff810000 { - compatible = "rockchip,rk3288-timer"; - reg = <0xff810000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; - }; - - sdmmc: dwmmc@ff0c0000 { - compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0xff0c0000 0x4000>; - status = "disabled"; - }; - - sdio0: dwmmc@ff0d0000 { - compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, - <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0xff0d0000 0x4000>; - status = "disabled"; - }; - - sdio1: dwmmc@ff0e0000 { - compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, - <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0xff0e0000 0x4000>; - status = "disabled"; - }; - - emmc: dwmmc@ff0f0000 { - compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0xff0f0000 0x4000>; - status = "disabled"; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,saradc"; - reg = <0xff100000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@ff110000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 11>, <&dmac_peri 12>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - reg = <0xff110000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff120000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 13>, <&dmac_peri 14>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - reg = <0xff120000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@ff130000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 15>, <&dmac_peri 16>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - reg = <0xff130000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff140000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0xff140000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff150000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0xff150000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - i2c4: i2c@ff160000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0xff160000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - status = "disabled"; - }; - - i2c5: i2c@ff170000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0xff170000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C5>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff180000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "disabled"; - }; - - uart1: serial@ff190000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff190000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@ff690000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff690000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff1b0000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - uart4: serial@ff1c0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff1c0000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "disabled"; - }; - - thermal-zones { - reserve_thermal: reserve_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - }; - - cpu_thermal: cpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 2>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0xff280000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - gmac: ethernet@ff290000 { - compatible = "rockchip,rk3288-gmac"; - reg = <0xff290000 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - resets = <&cru SRST_MAC>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff500000 { - compatible = "generic-ehci"; - reg = <0xff500000 0x100>; - interrupts = ; - clocks = <&cru HCLK_USBHOST0>; - clock-names = "usbhost"; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - /* NOTE: ohci@ff520000 doesn't actually work on hardware */ - - usb_host1: usb@ff540000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0xff540000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USBHOST1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy2>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_otg: usb@ff580000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0xff580000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_hsic: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0xff5c0000 0x100>; - interrupts = ; - clocks = <&cru HCLK_HSIC>; - clock-names = "usbhost"; - status = "disabled"; - }; - - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0xff650000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c2: i2c@ff660000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0xff660000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - pwm0: pwm@ff680000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0xff680000 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm1: pwm@ff680010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0xff680010 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm2: pwm@ff680020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0xff680020 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm3: pwm@ff680030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0xff680030 0x10>; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - bus_intmem@ff700000 { - compatible = "mmio-sram"; - reg = <0xff700000 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff700000 0x18000>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x00 0x10>; - }; - }; - - sram@ff720000 { - compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; - reg = <0xff720000 0x1000>; - }; - - pmu: power-management@ff730000 { - compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; - reg = <0xff730000 0x100>; - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - - /* - * Note: Although SCLK_* are the working clocks - * of device without including on the NOC, needed for - * synchronous reset. - * - * The clocks on the which NOC: - * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. - * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. - * ACLK_RGA is on ACLK_RGA_NIU. - * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. - * - * Which clock are device clocks: - * clocks devices - * *_IEP IEP:Image Enhancement Processor - * *_ISP ISP:Image Signal Processing - * *_VIP VIP:Video Input Processor - * *_VOP* VOP:Visual Output Processor - * *_RGA RGA - * *_EDP* EDP - * *_LVDS_* LVDS - * *_HDMI HDMI - * *_MIPI_* MIPI - */ - pd_vio@RK3288_PD_VIO { - reg = ; - clocks = <&cru ACLK_IEP>, - <&cru ACLK_ISP>, - <&cru ACLK_RGA>, - <&cru ACLK_VIP>, - <&cru ACLK_VOP0>, - <&cru ACLK_VOP1>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru HCLK_IEP>, - <&cru HCLK_ISP>, - <&cru HCLK_RGA>, - <&cru HCLK_VIP>, - <&cru HCLK_VOP0>, - <&cru HCLK_VOP1>, - <&cru PCLK_EDP_CTRL>, - <&cru PCLK_HDMI_CTRL>, - <&cru PCLK_LVDS_PHY>, - <&cru PCLK_MIPI_CSI>, - <&cru PCLK_MIPI_DSI0>, - <&cru PCLK_MIPI_DSI1>, - <&cru SCLK_EDP_24M>, - <&cru SCLK_EDP>, - <&cru SCLK_ISP_JPE>, - <&cru SCLK_ISP>, - <&cru SCLK_RGA>; - }; - - /* - * Note: The following 3 are HEVC(H.265) clocks, - * and on the ACLK_HEVC_NIU (NOC). - */ - pd_hevc@RK3288_PD_HEVC { - reg = ; - clocks = <&cru ACLK_HEVC>, - <&cru SCLK_HEVC_CABAC>, - <&cru SCLK_HEVC_CORE>; - }; - - /* - * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC - * (video endecoder & decoder) clocks that on the - * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). - */ - pd_video@RK3288_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VCODEC>, - <&cru HCLK_VCODEC>; - }; - - /* - * Note: ACLK_GPU is the GPU clock, - * and on the ACLK_GPU_NIU (NOC). - */ - pd_gpu@RK3288_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x94>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - sgrf: syscon@ff740000 { - compatible = "rockchip,rk3288-sgrf", "syscon"; - reg = <0xff740000 0x1000>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3288-cru"; - reg = <0xff760000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <400000000>, - <500000000>, <300000000>, - <150000000>, <75000000>, - <300000000>, <150000000>, - <75000000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - reg = <0xff770000 0x1000>; - - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; - status = "disabled"; - }; - - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - status = "disabled"; - }; - - usbphy: usbphy { - compatible = "rockchip,rk3288-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@320 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@334 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy2: usb-phy@348 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - }; - - wdt: watchdog@ff800000 { - compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; - reg = <0xff800000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - spdif: sound@ff88b0000 { - compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; - reg = <0xff8b0000 0x10000>; - #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; - dmas = <&dmac_bus_s 3>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2s: i2s@ff890000 { - compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0xff890000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - crypto: cypto-controller@ff8a0000 { - compatible = "rockchip,rk3288-crypto"; - reg = <0xff8a0000 0x4000>; - interrupts = ; - clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, - <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; - clock-names = "aclk", "hclk", "sclk", "apb_pclk"; - resets = <&cru SRST_CRYPTO>; - reset-names = "crypto-rst"; - status = "okay"; - }; - - vopb: vop@ff930000 { - compatible = "rockchip,rk3288-vop"; - reg = <0xff930000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopb>; - }; - - vopb_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopb>; - }; - - vopb_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopb>; - }; - }; - }; - - vopb_mmu: iommu@ff930300 { - compatible = "rockchip,iommu"; - reg = <0xff930300 0x100>; - interrupts = ; - interrupt-names = "vopb_mmu"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff940000 { - compatible = "rockchip,rk3288-vop"; - reg = <0xff940000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopl_mmu>; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopl>; - }; - - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; - }; - - vopl_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopl>; - }; - }; - }; - - vopl_mmu: iommu@ff940300 { - compatible = "rockchip,iommu"; - reg = <0xff940300 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - mipi_dsi: mipi@ff960000 { - compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0xff960000 0x4000>; - interrupts = ; - clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; - clock-names = "ref", "pclk"; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - mipi_in: port { - #address-cells = <1>; - #size-cells = <0>; - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - }; - }; - - edp: dp@ff970000 { - compatible = "rockchip,rk3288-dp"; - reg = <0xff970000 0x4000>; - interrupts = ; - clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; - clock-names = "dp", "pclk"; - phys = <&edp_phy>; - phy-names = "dp"; - resets = <&cru SRST_EDP>; - reset-names = "dp"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - }; - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0xff980000 0x20000>; - reg-io-width = <4>; - rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; - clock-names = "iahb", "isfr"; - power-domains = <&power RK3288_PD_VIO>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0xffc01000 0x1000>, - <0xffc02000 0x1000>, - <0xffc04000 0x2000>, - <0xffc06000 0x2000>; - interrupts = ; - }; - - efuse: efuse@ffb40000 { - compatible = "rockchip,rockchip-efuse"; - reg = <0xffb40000 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3288-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@ff750000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff750000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff780000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff790000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@ff7a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff7a0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@ff7b0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff7b0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio5@ff7c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff7c0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO5>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio6@ff7d0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff7d0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio7@ff7e0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff7e0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO7>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio8@ff7f0000 { - compatible = "rockchip,gpio-bank"; - reg = <0xff7f0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO8>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hdmi { - hdmi_ddc: hdmi-ddc { - rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, - <7 20 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - sleep { - global_pwroff: global-pwroff { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; - }; - - ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; - }; - - ddr0_retention: ddr0-retention { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; - }; - - ddr1_retention: ddr1-retention { - rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - edp { - edp_hpd: edp-hpd { - rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, - <0 16 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, - <8 5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, - <6 10 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, - <2 17 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, - <7 18 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, - <7 20 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, - <6 1 RK_FUNC_1 &pcfg_pull_none>, - <6 2 RK_FUNC_1 &pcfg_pull_none>, - <6 3 RK_FUNC_1 &pcfg_pull_none>, - <6 4 RK_FUNC_1 &pcfg_pull_none>, - <6 8 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, - <6 17 RK_FUNC_1 &pcfg_pull_up>, - <6 18 RK_FUNC_1 &pcfg_pull_up>, - <6 19 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, - <4 21 RK_FUNC_1 &pcfg_pull_up>, - <4 22 RK_FUNC_1 &pcfg_pull_up>, - <4 23 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; - }; - - sdio0_cd: sdio0-cd { - rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio0_wp: sdio0-wp { - rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio0_pwr: sdio0-pwr { - rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio0_int: sdio0-int { - rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - sdio1 { - sdio1_bus1: sdio1-bus1 { - rockchip,pins = <3 24 4 &pcfg_pull_up>; - }; - - sdio1_bus4: sdio1-bus4 { - rockchip,pins = <3 24 4 &pcfg_pull_up>, - <3 25 4 &pcfg_pull_up>, - <3 26 4 &pcfg_pull_up>, - <3 27 4 &pcfg_pull_up>; - }; - - sdio1_cd: sdio1-cd { - rockchip,pins = <3 28 4 &pcfg_pull_up>; - }; - - sdio1_wp: sdio1-wp { - rockchip,pins = <3 29 4 &pcfg_pull_up>; - }; - - sdio1_bkpwr: sdio1-bkpwr { - rockchip,pins = <3 30 4 &pcfg_pull_up>; - }; - - sdio1_int: sdio1-int { - rockchip,pins = <3 31 4 &pcfg_pull_up>; - }; - - sdio1_cmd: sdio1-cmd { - rockchip,pins = <4 6 4 &pcfg_pull_up>; - }; - - sdio1_clk: sdio1-clk { - rockchip,pins = <4 7 4 &pcfg_pull_none>; - }; - - sdio1_pwr: sdio1-pwr { - rockchip,pins = <4 9 4 &pcfg_pull_up>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; - }; - - emmc_pwr: emmc-pwr { - rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, - <3 1 RK_FUNC_2 &pcfg_pull_up>, - <3 2 RK_FUNC_2 &pcfg_pull_up>, - <3 3 RK_FUNC_2 &pcfg_pull_up>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, - <3 1 RK_FUNC_2 &pcfg_pull_up>, - <3 2 RK_FUNC_2 &pcfg_pull_up>, - <3 3 RK_FUNC_2 &pcfg_pull_up>, - <3 4 RK_FUNC_2 &pcfg_pull_up>, - <3 5 RK_FUNC_2 &pcfg_pull_up>, - <3 6 RK_FUNC_2 &pcfg_pull_up>, - <3 7 RK_FUNC_2 &pcfg_pull_up>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; - }; - }; - - spi2 { - spi2_cs1: spi2-cs1 { - rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; - }; - spi2_clk: spi2-clk { - rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; - }; - spi2_cs0: spi2-cs0 { - rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; - }; - spi2_rx: spi2-rx { - rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; - }; - spi2_tx: spi2-tx { - rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, - <4 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, - <5 9 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, - <7 23 RK_FUNC_1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, - <7 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = <5 12 3 &pcfg_pull_up>, - <5 13 3 &pcfg_pull_none>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = <5 14 3 &pcfg_pull_up>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = <5 15 3 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <7 22 3 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <7 23 3 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <3 30 3 &pcfg_pull_none>, - <3 31 3 &pcfg_pull_none>, - <3 26 3 &pcfg_pull_none>, - <3 27 3 &pcfg_pull_none>, - <3 28 3 &pcfg_pull_none_12ma>, - <3 29 3 &pcfg_pull_none_12ma>, - <3 24 3 &pcfg_pull_none_12ma>, - <3 25 3 &pcfg_pull_none_12ma>, - <4 0 3 &pcfg_pull_none>, - <4 5 3 &pcfg_pull_none>, - <4 6 3 &pcfg_pull_none>, - <4 9 3 &pcfg_pull_none_12ma>, - <4 4 3 &pcfg_pull_none_12ma>, - <4 1 3 &pcfg_pull_none>, - <4 3 3 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <3 30 3 &pcfg_pull_none>, - <3 31 3 &pcfg_pull_none>, - <3 28 3 &pcfg_pull_none>, - <3 29 3 &pcfg_pull_none>, - <4 0 3 &pcfg_pull_none>, - <4 5 3 &pcfg_pull_none>, - <4 4 3 &pcfg_pull_none>, - <4 1 3 &pcfg_pull_none>, - <4 2 3 &pcfg_pull_none>, - <4 3 3 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/rk3xxx.dtsi b/software/linux/kernel/arch/arm/boot/dts/rk3xxx.dtsi deleted file mode 100644 index e15beb3c6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/rk3xxx.dtsi +++ /dev/null @@ -1,442 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &emac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - mshc0 = &emmc; - mshc1 = &mmc0; - mshc2 = &mmc1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - spi0 = &spi0; - spi1 = &spi1; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dmac1_s: dma-controller@20018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20018000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - }; - - dmac1_ns: dma-controller@2001c000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x2001c000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dmac2: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA2>; - clock-names = "apb_pclk"; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - clock-output-names = "xin24m"; - }; - - L2: l2-cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - global_timer: global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - local_timer: local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - status = "disabled"; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy1>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - emac: ethernet@10204000 { - compatible = "snps,arc-emac"; - reg = <0x10204000 0x3c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref"; - max-speed = <100>; - phy-mode = "rmii"; - - status = "disabled"; - }; - - mmc0: dwmmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <256>; - status = "disabled"; - }; - - mmc1: dwmmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; - clock-names = "biu", "ciu"; - fifo-depth = <256>; - status = "disabled"; - }; - - emmc: dwmmc@1021c000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x1021c000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <256>; - status = "disabled"; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; - reg = <0x20004000 0x100>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x40>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - grf: grf@20008000 { - compatible = "syscon"; - reg = <0x20008000 0x200>; - }; - - i2c0: i2c@2002d000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002d000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - - status = "disabled"; - }; - - i2c1: i2c@2002f000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002f000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C1>; - clock-names = "i2c"; - - status = "disabled"; - }; - - pwm0: pwm@20030000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030000 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - pwm1: pwm@20030010 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030010 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - wdt: watchdog@2004c000 { - compatible = "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - i2c2: i2c@20056000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C2>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c3: i2c@2005a000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C3>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c4: i2c@2005e000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C4>; - clock-names = "i2c"; - - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - status = "disabled"; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@20070000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - reg = <0x20070000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 10>, <&dmac2 11>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi1: spi@20074000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - reg = <0x20074000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 12>, <&dmac2 13>; - dma-names = "tx", "rx"; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/s3c2416-pinctrl.dtsi deleted file mode 100644 index 6274359fb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Samsung S3C2416 pinctrl settings - * - * Copyright (c) 2013 Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -&pinctrl_0 { - /* - * Pin banks - */ - - gpa: gpa { - gpio-controller; - #gpio-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe: gpe { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf: gpf { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg: gpg { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph: gph { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj: gpj { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk: gpk { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl: gpl { - gpio-controller; - #gpio-cells = <2>; - }; - - gpm: gpm { - gpio-controller; - #gpio-cells = <2>; - }; - - /* - * Pin groups - */ - - uart0_data: uart0-data { - samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; - }; - - extuart_clk: extuart-clk { - samsung,pins = "gph-12"; - samsung,pin-function = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpe-5"; - samsung,pin-function = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpe-6"; - samsung,pin-function = ; - }; - - sd0_bus1: sd0-bus1 { - samsung,pins = "gpe-7"; - samsung,pin-function = ; - }; - - sd0_bus4: sd0-bus4 { - samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpl-8"; - samsung,pin-function = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpl-9"; - samsung,pin-function = ; - }; - - sd1_bus1: sd1-bus1 { - samsung,pins = "gpl-0"; - samsung,pin-function = ; - }; - - sd1_bus4: sd1-bus4 { - samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c2416-smdk2416.dts b/software/linux/kernel/arch/arm/boot/dts/s3c2416-smdk2416.dts deleted file mode 100644 index f257926c1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * SAMSUNG SMDK2416 board device tree source - * - * Copyright (c) 2013 Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "s3c2416.dtsi" - -/ { - model = "SMDK2416"; - compatible = "samsung,s3c2416"; - - memory { - reg = <0x30000000 0x4000000>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - xti: xti { - compatible = "fixed-clock"; - clock-frequency = <12000000>; - clock-output-names = "xti"; - #clock-cells = <0>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdhci_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, - <&sd1_bus1>, <&sd1_bus4>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&sdhci_1 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, - <&sd0_bus1>, <&sd0_bus4>; - bus-width = <4>; - cd-gpios = <&gpf 1 0>; - cd-inverted; - status = "okay"; -}; - -&uart_0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; -}; - -&uart_1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; -}; - -&uart_2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; -}; - -&uart_3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; -}; - -&watchdog { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c2416.dtsi b/software/linux/kernel/arch/arm/boot/dts/s3c2416.dtsi deleted file mode 100644 index 80f007550..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c2416.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Samsung's S3C2416 SoC device tree source - * - * Copyright (c) 2013 Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include "s3c24xx.dtsi" -#include "s3c2416-pinctrl.dtsi" - -/ { - model = "Samsung S3C2416 SoC"; - compatible = "samsung,s3c2416"; - - aliases { - serial3 = &uart_3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - }; - }; - - interrupt-controller@4a000000 { - compatible = "samsung,s3c2416-irq"; - }; - - clocks: clock-controller@0x4c000000 { - compatible = "samsung,s3c2416-clock"; - reg = <0x4c000000 0x40>; - #clock-cells = <1>; - }; - - pinctrl@56000000 { - compatible = "samsung,s3c2416-pinctrl"; - }; - - timer@51000000 { - clocks = <&clocks PCLK_PWM>; - clock-names = "timers"; - }; - - uart_0: serial@50000000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; - - uart_1: serial@50004000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - }; - - uart_2: serial@50008000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - }; - - uart_3: serial@5000C000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x5000C000 0x4000>; - interrupts = <1 18 24 4>, <1 18 25 4>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - sdhci_1: sdhci@4AC00000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x4AC00000 0x100>; - interrupts = <0 0 21 3>; - clock-names = "hsmmc", "mmc_busclk.0", - "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, - <&clocks MUX_HSMMC0>; - status = "disabled"; - }; - - sdhci_0: sdhci@4A800000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x4A800000 0x100>; - interrupts = <0 0 20 3>; - clock-names = "hsmmc", "mmc_busclk.0", - "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, - <&clocks MUX_HSMMC1>; - status = "disabled"; - }; - - watchdog: watchdog@53000000 { - interrupts = <1 9 27 3>; - clocks = <&clocks PCLK_WDT>; - clock-names = "watchdog"; - }; - - rtc: rtc@57000000 { - compatible = "samsung,s3c2416-rtc"; - clocks = <&clocks PCLK_RTC>; - clock-names = "rtc"; - }; - - i2c@54000000 { - compatible = "samsung,s3c2440-i2c"; - clocks = <&clocks PCLK_I2C0>; - clock-names = "i2c"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c24xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/s3c24xx.dtsi deleted file mode 100644 index 5ed43b857..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c24xx.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Samsung's S3C24XX family device tree source - * - * Copyright (c) 2013 Heiko Stuebner - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "skeleton.dtsi" - -/ { - compatible = "samsung,s3c24xx"; - interrupt-parent = <&intc>; - - aliases { - pinctrl0 = &pinctrl_0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - intc:interrupt-controller@4a000000 { - compatible = "samsung,s3c2410-irq"; - reg = <0x4a000000 0x100>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - pinctrl_0: pinctrl@56000000 { - reg = <0x56000000 0x1000>; - - wakeup-interrupt-controller { - compatible = "samsung,s3c2410-wakeup-eint"; - interrupts = <0 0 0 3>, - <0 0 1 3>, - <0 0 2 3>, - <0 0 3 3>, - <0 0 4 4>, - <0 0 5 4>; - }; - }; - - timer@51000000 { - compatible = "samsung,s3c2410-pwm"; - reg = <0x51000000 0x1000>; - interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; - #pwm-cells = <4>; - }; - - uart0: serial@50000000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50000000 0x4000>; - interrupts = <1 28 0 4>, <1 28 1 4>; - status = "disabled"; - }; - - uart1: serial@50004000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - status = "disabled"; - }; - - uart2: serial@50008000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50008000 0x4000>; - interrupts = <1 15 6 4>, <1 15 7 4>; - status = "disabled"; - }; - - watchdog@53000000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x53000000 0x100>; - interrupts = <0 0 9 3>; - status = "disabled"; - }; - - rtc@57000000 { - compatible = "samsung,s3c2410-rtc"; - reg = <0x57000000 0x100>; - interrupts = <0 0 30 3>, <0 0 8 3>; - status = "disabled"; - }; - - i2c@54000000 { - compatible = "samsung,s3c2410-i2c"; - reg = <0x54000000 0x100>; - interrupts = <0 0 27 3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c6400.dtsi b/software/linux/kernel/arch/arm/boot/dts/s3c6400.dtsi deleted file mode 100644 index a7d1c8ec1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c6400.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Samsung's S3C6400 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6400"; -}; - -&vic0 { - valid-mask = <0xfffffe1f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6400-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c6410-mini6410.dts b/software/linux/kernel/arch/arm/boot/dts/s3c6410-mini6410.dts deleted file mode 100644 index f4afda359..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c6410-mini6410.dts +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Samsung's S3C6410 based Mini6410 board device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Device tree source file for FriendlyARM Mini6410 board which is based on - * Samsung's S3C6410 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; - -#include -#include - -#include "s3c6410.dtsi" - -/ { - model = "FriendlyARM Mini6410 board based on S3C6410"; - compatible = "friendlyarm,mini6410", "samsung,s3c6410"; - - memory { - reg = <0x50000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - srom-cs1@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; - interrupt-parent = <&gpn>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - davicom,no-eeprom; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys>; - autorepeat; - - button-k1 { - label = "K1"; - gpios = <&gpn 0 GPIO_ACTIVE_LOW>; - linux,code = <2>; - debounce-interval = <20>; - }; - - button-k2 { - label = "K2"; - gpios = <&gpn 1 GPIO_ACTIVE_LOW>; - linux,code = <3>; - debounce-interval = <20>; - }; - - button-k3 { - label = "K3"; - gpios = <&gpn 2 GPIO_ACTIVE_LOW>; - linux,code = <4>; - debounce-interval = <20>; - }; - - button-k4 { - label = "K4"; - gpios = <&gpn 3 GPIO_ACTIVE_LOW>; - linux,code = <5>; - debounce-interval = <20>; - }; - - button-k5 { - label = "K5"; - gpios = <&gpn 4 GPIO_ACTIVE_LOW>; - linux,code = <6>; - debounce-interval = <20>; - }; - - button-k6 { - label = "K6"; - gpios = <&gpn 5 GPIO_ACTIVE_LOW>; - linux,code = <7>; - debounce-interval = <20>; - }; - - button-k7 { - label = "K7"; - gpios = <&gpl 11 GPIO_ACTIVE_LOW>; - linux,code = <8>; - debounce-interval = <20>; - }; - - button-k8 { - label = "K8"; - gpios = <&gpl 12 GPIO_ACTIVE_LOW>; - linux,code = <9>; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds>; - - led-1 { - label = "LED1"; - gpios = <&gpk 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "LED2"; - gpios = <&gpk 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - led-3 { - label = "LED3"; - gpios = <&gpk 6 GPIO_ACTIVE_LOW>; - }; - - led-4 { - label = "LED4"; - gpios = <&gpk 7 GPIO_ACTIVE_LOW>; - }; - }; - - buzzer { - compatible = "pwm-beeper"; - pwms = <&pwm 0 1000000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; - }; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; - -&pinctrl0 { - gpio_leds: gpio-leds { - samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-pud = ; - }; - - gpio_keys: gpio-keys { - samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", - "gpn-4", "gpn-5", "gpl-11", "gpl-12"; - samsung,pin-pud = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c6410-smdk6410.dts b/software/linux/kernel/arch/arm/boot/dts/s3c6410-smdk6410.dts deleted file mode 100644 index ecf35ec46..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Samsung S3C6410 based SMDK6410 board device tree source. - * - * Copyright (c) 2013 Tomasz Figa - * - * Device tree source file for SAMSUNG SMDK6410 board which is based on - * Samsung's S3C6410 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; - -#include -#include - -#include "s3c6410.dtsi" - -/ { - model = "SAMSUNG SMDK6410 board based on S3C6410"; - compatible = "samsung,mini6410", "samsung,s3c6410"; - - memory { - reg = <0x50000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - srom-cs1@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "smsc,lan9115"; - reg = <0x18000000 0x10000>; - interrupt-parent = <&gpn>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,force-internal-phy; - }; - }; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c6410.dtsi b/software/linux/kernel/arch/arm/boot/dts/s3c6410.dtsi deleted file mode 100644 index eb4226b34..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c6410.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Samsung's S3C6410 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6410"; - - aliases { - i2c1 = &i2c1; - }; -}; - -&vic0 { - valid-mask = <0xffffff7f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6410-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - - i2c1: i2c@7f00f000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f00f000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi deleted file mode 100644 index 4e8e802b4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ /dev/null @@ -1,685 +0,0 @@ -/* - * Samsung's S3C64xx SoC series common device tree source - * - pin control-related definitions - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are - * listed as device tree nodes in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -&pinctrl0 { - /* - * Pin banks - */ - - gpa: gpa { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe: gpe { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf: gpf { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg: gpg { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph: gph { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpi: gpi { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj: gpj { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk: gpk { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl: gpl { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm: gpm { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpn: gpn { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpo: gpo { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpp: gpp { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpq: gpq { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* - * Pin groups - */ - - uart0_data: uart0-data { - samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ext_dma_0: ext-dma-0 { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ext_dma_1: ext-dma-1 { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_data_0: irda-data-0 { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_data_1: irda-data-1 { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - irda_sdbw: irda-sdbw { - samsung,pins = "gpb-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2c1_bus: i2c1-bus { - /* S3C6410-only */ - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi0_cs: spi0-cs { - samsung,pins = "gpc-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - spi1_cs: spi1-cs { - samsung,pins = "gpc-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpg-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpg-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_bus1: sd0-bus1 { - samsung,pins = "gpg-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_bus4: sd0-bus4 { - samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpg-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gph-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gph-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus1: sd1-bus1 { - samsung,pins = "gph-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus4: sd1-bus4 { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_bus8: sd1-bus8 { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", - "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpg-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_bus1: sd2-bus1 { - samsung,pins = "gph-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_bus4: sd2-bus4 { - samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s0_cdclk: i2s0-cdclk { - samsung,pins = "gpd-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s1_cdclk: i2s1-cdclk { - samsung,pins = "gpe-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s2_bus: i2s2-bus { - /* S3C6410-only */ - samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", - "gph-8", "gph-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - i2s2_cdclk: i2s2-cdclk { - /* S3C6410-only */ - samsung,pins = "gph-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm0_extclk: pcm0-extclk { - samsung,pins = "gpd-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pcm1_extclk: pcm1-extclk { - samsung,pins = "gpe-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ac97_bus_0: ac97-bus-0 { - samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - ac97_bus_1: ac97-bus-1 { - samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_port: cam-port { - samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", - "gpf-5", "gpf-6", "gpf-7", "gpf-8", - "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_rst: cam-rst { - samsung,pins = "gpf-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - cam_field: cam-field { - /* S3C6410-only */ - samsung,pins = "gpb-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm_extclk: pwm-extclk { - samsung,pins = "gpf-13"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpf-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpf-15"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - clkout0: clkout-0 { - samsung,pins = "gpf-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col0_0: keypad-col0-0 { - samsung,pins = "gph-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col1_0: keypad-col1-0 { - samsung,pins = "gph-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col2_0: keypad-col2-0 { - samsung,pins = "gph-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col3_0: keypad-col3-0 { - samsung,pins = "gph-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col4_0: keypad-col4-0 { - samsung,pins = "gph-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col5_0: keypad-col5-0 { - samsung,pins = "gph-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col6_0: keypad-col6-0 { - samsung,pins = "gph-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col7_0: keypad-col7-0 { - samsung,pins = "gph-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col0_1: keypad-col0-1 { - samsung,pins = "gpl-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col1_1: keypad-col1-1 { - samsung,pins = "gpl-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col2_1: keypad-col2-1 { - samsung,pins = "gpl-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col3_1: keypad-col3-1 { - samsung,pins = "gpl-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col4_1: keypad-col4-1 { - samsung,pins = "gpl-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col5_1: keypad-col5-1 { - samsung,pins = "gpl-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col6_1: keypad-col6-1 { - samsung,pins = "gpl-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_col7_1: keypad-col7-1 { - samsung,pins = "gpl-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row0_0: keypad-row0-0 { - samsung,pins = "gpk-8"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row1_0: keypad-row1-0 { - samsung,pins = "gpk-9"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row2_0: keypad-row2-0 { - samsung,pins = "gpk-10"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row3_0: keypad-row3-0 { - samsung,pins = "gpk-11"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row4_0: keypad-row4-0 { - samsung,pins = "gpk-12"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row5_0: keypad-row5-0 { - samsung,pins = "gpk-13"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row6_0: keypad-row6-0 { - samsung,pins = "gpk-14"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row7_0: keypad-row7-0 { - samsung,pins = "gpk-15"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row0_1: keypad-row0-1 { - samsung,pins = "gpn-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row1_1: keypad-row1-1 { - samsung,pins = "gpn-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row2_1: keypad-row2-1 { - samsung,pins = "gpn-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row3_1: keypad-row3-1 { - samsung,pins = "gpn-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row4_1: keypad-row4-1 { - samsung,pins = "gpn-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row5_1: keypad-row5-1 { - samsung,pins = "gpn-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row6_1: keypad-row6-1 { - samsung,pins = "gpn-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - keypad_row7_1: keypad-row7-1 { - samsung,pins = "gpn-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", - "gpi-7", "gpi-10", "gpi-11", "gpi-12", - "gpi-13", "gpi-14", "gpi-15", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", - "gpi-6", "gpi-7", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-2", "gpj-3", "gpj-4", "gpj-5", - "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", - "gpi-4", "gpi-5", "gpi-6", "gpi-7", - "gpi-8", "gpi-9", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-0", "gpj-1", "gpj-2", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - hsi_bus: hsi-bus { - samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", - "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s3c64xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/s3c64xx.dtsi deleted file mode 100644 index 0ccb414cd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s3c64xx.dtsi +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Samsung's S3C64xx SoC series common device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C64xx SoC series device nodes are listed in this file. - * Particular SoCs from S3C64xx series can include this file and provide - * values for SoCs specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - i2c0 = &i2c0; - pinctrl0 = &pinctrl0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm1176jzf-s", "arm,arm1176"; - reg = <0x0>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic0: interrupt-controller@71200000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71200000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@71300000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71300000 0x1000>; - #interrupt-cells = <1>; - }; - - sdhci0: sdhci@7c200000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c200000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <24>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, - <&clocks SCLK_MMC0>; - status = "disabled"; - }; - - sdhci1: sdhci@7c300000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c300000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <25>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, - <&clocks SCLK_MMC1>; - status = "disabled"; - }; - - sdhci2: sdhci@7c400000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c400000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <17>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>, - <&clocks SCLK_MMC2>; - status = "disabled"; - }; - - watchdog: watchdog@7e004000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x7e004000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - clock-names = "watchdog"; - clocks = <&clocks PCLK_WDT>; - status = "disabled"; - }; - - i2c0: i2c@7f004000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f004000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <18>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@7f005000 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <5>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart1: serial@7f005400 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005400 0x100>; - interrupt-parent = <&vic1>; - interrupts = <6>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart2: serial@7f005800 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005800 0x100>; - interrupt-parent = <&vic1>; - interrupts = <7>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart3: serial@7f005c00 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005c00 0x100>; - interrupt-parent = <&vic1>; - interrupts = <8>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - pwm: pwm@7f006000 { - compatible = "samsung,s3c6400-pwm"; - reg = <0x7f006000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <23>, <24>, <25>, <27>, <28>; - clock-names = "timers"; - clocks = <&clocks PCLK_PWM>; - samsung,pwm-outputs = <0>, <1>; - #pwm-cells = <3>; - }; - - pinctrl0: pinctrl@7f008000 { - compatible = "samsung,s3c64xx-pinctrl"; - reg = <0x7f008000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <21>; - - pctrl_int_map: pinctrl-interrupt-map { - interrupt-map = <0 &vic0 0>, - <1 &vic0 1>, - <2 &vic1 0>, - <3 &vic1 1>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <1>; - }; - - wakeup-interrupt-controller { - compatible = "samsung,s3c64xx-wakeup-eint"; - interrupts = <0>, <1>, <2>, <3>; - interrupt-parent = <&pctrl_int_map>; - }; - }; - }; -}; - -#include "s3c64xx-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/s5pv210-aquila.dts b/software/linux/kernel/arch/arm/boot/dts/s5pv210-aquila.dts deleted file mode 100644 index 40139923e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s5pv210-aquila.dts +++ /dev/null @@ -1,393 +0,0 @@ -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Samsung Aquila board. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "Samsung Aquila based on S5PC110"; - compatible = "samsung,aquila", "samsung,s5pv210"; - - aliases { - i2c3 = &i2c_pmic; - }; - - chosen { - bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x18000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vtf_reg: fixed-regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&mp05 4 0>; - enable-active-high; - }; - - pda_reg: fixed-regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - reg = <1>; - }; - - bat_reg: fixed-regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - reg = <2>; - }; - }; - - i2c_pmic: i2c-pmic { - compatible = "i2c-gpio"; - gpios = <&gpj4 0 0>, /* sda */ - <&gpj4 3 0>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - pmic@66 { - compatible = "national,lp3974"; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>, - <&gph0 4 0>; - max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VCC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VCC_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC+VCAM_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_IO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "CAM_ISP_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_A_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_CIF_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_8M_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VARM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VINT_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "CAM_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vichg_reg: ENVICHG { - regulator-name = "VICHG"; - }; - - safeout1_reg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - regulator-always-on; - }; - - safeout2_reg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gph2 6 1>; - linux,code = ; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; - status = "okay"; - - key_1 { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <2>; - linux,code = ; - }; - - key_3 { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key_4 { - keypad,row = <1>; - keypad,column = <2>; - linux,code = ; - }; - - key_5 { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; - - key_6 { - keypad,row = <2>; - keypad,column = <2>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&sdhci0 { - bus-width = <4>; - non-removable; - status = "okay"; - vmmc-supply = <&ldo5_reg>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; - pinctrl-names = "default"; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gph3 4 1>; - vmmc-supply = <&vtf_reg>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>; - pinctrl-names = "default"; - status = "okay"; -}; - -&onenand { - status = "okay"; -}; - -&hsotg { - vusb_a-supply = <&ldo3_reg>; - vusb_d-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <0>; - hactive = <800>; - vactive = <480>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vback-porch = <3>; - vfront-porch = <28>; - vsync-len = <1>; - }; - }; -}; - -&pinctrl0 { - t_flash_detect: t-flash-detect { - samsung,pins = "gph3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s5pv210-goni.dts b/software/linux/kernel/arch/arm/boot/dts/s5pv210-goni.dts deleted file mode 100644 index c56f51ee7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s5pv210-goni.dts +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Samsung Goni board. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "Samsung Goni based on S5PC110"; - compatible = "samsung,goni", "samsung,s5pv210"; - - aliases { - i2c3 = &i2c_pmic; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vtf_reg: fixed-regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - reg = <0>; - gpio = <&mp05 4 0>; - enable-active-high; - }; - - pda_reg: fixed-regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - reg = <1>; - }; - - bat_reg: fixed-regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - reg = <2>; - }; - - tsp_reg: fixed-regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "TSP_VDD"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - reg = <3>; - gpio = <&gpj1 3 0>; - enable-active-high; - }; - }; - - i2c_pmic: i2c-pmic { - compatible = "i2c-gpio"; - gpios = <&gpj4 0 0>, /* sda */ - <&gpj4 3 0>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - pmic@66 { - compatible = "national,lp3974"; - reg = <0x66>; - - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>, - <&gph0 4 0>; - max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>; - - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>; - max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; - - regulators { - ldo2_reg: LDO2 { - regulator-name = "VALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VUSB+MIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VCC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VLCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VCC+VCAM_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "CAM_IO_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "CAM_ISP_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "CAM_A_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "CAM_CIF_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "CAM_AF_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo17_reg: LDO17 { - regulator-name = "CAM_8M_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VARM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - buck2_reg: BUCK2 { - regulator-name = "VINT_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - buck3_reg: BUCK3 { - regulator-name = "VCC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "CAM_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gph2 6 1>; - linux,code = ; - label = "power"; - debounce-interval = <1>; - wakeup-source; - }; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; - status = "okay"; - - key_1 { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <2>; - linux,code = ; - }; - - key_3 { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; - - key_4 { - keypad,row = <1>; - keypad,column = <2>; - linux,code = ; - }; - - key_5 { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; - }; - - key_6 { - keypad,row = <2>; - keypad,column = <2>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&sdhci0 { - bus-width = <4>; - non-removable; - vmmc-supply = <&ldo5_reg>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - cd-gpios = <&gph3 4 1>; - vmmc-supply = <&vtf_reg>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hsotg { - vusb_a-supply = <&ldo3_reg>; - vusb_d-supply = <&ldo8_reg>; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&i2c2 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - samsung,i2c-slave-addr = <0x10>; - status = "okay"; - - tsp@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpj0>; - interrupts = <5 2>; - - atmel,x-line = <17>; - atmel,y-line = <11>; - atmel,x-size = <800>; - atmel,y-size = <480>; - atmel,burst-length = <0x21>; - atmel,threshold = <0x28>; - atmel,orientation = <1>; - - vdd-supply = <&tsp_reg>; - }; -}; - -&i2c0 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; - samsung,i2c-slave-addr = <0x10>; - status = "okay"; - - noon010pc30: sensor@30 { - compatible = "siliconfile,noon010pc30"; - reg = <0x30>; - vddio-supply = <&ldo11_reg>; - vdda-supply = <&ldo13_reg>; - vdd_core-supply = <&ldo14_reg>; - - clock-frequency = <16000000>; - clocks = <&clock_cam 0>; - clock-names = "mclk"; - nreset-gpios = <&gpb 2 0>; - nstby-gpios = <&gpb 0 0>; - - port { - noon010pc30_ep: endpoint { - remote-endpoint = <&fimc0_ep>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <1>; - pclk-sample = <1>; - }; - }; - }; -}; - -&camera { - pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>; - pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>; - pinctrl-names = "default", "idle"; - - parallel-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* camera A input */ - port@1 { - reg = <1>; - fimc0_ep: endpoint { - remote-endpoint = <&noon010pc30_ep>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - /* 480x800@55Hz */ - clock-frequency = <23439570>; - hactive = <480>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vactive = <800>; - vback-porch = <2>; - vfront-porch = <28>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; -}; - -&onenand { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/s5pv210-pinctrl.dtsi deleted file mode 100644 index 9a3e851e2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ /dev/null @@ -1,841 +0,0 @@ -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -&pinctrl0 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg3: gpg3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj2: gpj2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj3: gpj3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpj4: gpj4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpgi: gpgi { - gpio-controller; - #gpio-cells = <2>; - }; - - mp01: mp01 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp02: mp02 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp03: mp03 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp04: mp04 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp05: mp05 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp06: mp06 { - gpio-controller; - #gpio-cells = <2>; - }; - - mp07: mp07 { - gpio-controller; - #gpio-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - interrupt-controller; - interrupt-parent = <&vic0>; - interrupts = <0>, <1>, <2>, <3>, - <4>, <5>, <6>, <7>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - interrupt-controller; - interrupt-parent = <&vic0>; - interrupts = <8>, <9>, <10>, <11>, - <12>, <13>, <14>, <15>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gph2: gph2 { - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gph3: gph3 { - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_audio: uart-audio { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", - "gpi-4", "gpi-5", "gpi-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", - "gpc0-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", - "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row0: keypad-row-0 { - samsung,pins = "gph3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row1: keypad-row-1 { - samsung,pins = "gph3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row2: keypad-row-2 { - samsung,pins = "gph3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row3: keypad-row-3 { - samsung,pins = "gph3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row4: keypad-row-4 { - samsung,pins = "gph3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row5: keypad-row-5 { - samsung,pins = "gph3-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row6: keypad-row-6 { - samsung,pins = "gph3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_row7: keypad-row-7 { - samsung,pins = "gph3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col0: keypad-col-0 { - samsung,pins = "gph2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col1: keypad-col-1 { - samsung,pins = "gph2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col2: keypad-col-2 { - samsung,pins = "gph2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col3: keypad-col-3 { - samsung,pins = "gph2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col4: keypad-col-4 { - samsung,pins = "gph2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col5: keypad-col-5 { - samsung,pins = "gph2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col6: keypad-col-6 { - samsung,pins = "gph2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - keypad_col7: keypad-col-7 { - samsung,pins = "gph2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpg0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpg0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpg0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpg0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpg1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpg1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpg1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpg1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpg2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpg2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpg2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpg2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpg3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpg3-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpg3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpg3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint0: ext-int0 { - samsung,pins = "gph0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint8: ext-int8 { - samsung,pins = "gph1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint15: ext-int15 { - samsung,pins = "gph1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint16: ext-int16 { - samsung,pins = "gph2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - eint31: ext-int31 { - samsung,pins = "gph3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_io: cam-port-a-io { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_active: cam-port-a-clk-active { - samsung,pins = "gpe1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_a_clk_idle: cam-port-a-clk-idle { - samsung,pins = "gpe1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_io: cam-port-b-io { - samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", - "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_active: cam-port-b-clk-active { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - cam_port_b_clk_idle: cam-port-b-clk-idle { - samsung,pins = "gpj1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_sync: lcd-sync { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_clk: lcd-clk { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s5pv210-smdkc110.dts b/software/linux/kernel/arch/arm/boot/dts/s5pv210-smdkc110.dts deleted file mode 100644 index 5d14da911..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s5pv210-smdkc110.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for YIC System SMDC110 board. - * - * NOTE: This file is completely based on original board file for mach-smdkc110 - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "YIC System SMDKC110 based on S5PC110"; - compatible = "yic,smdkc110", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - audio-codec@1b { - compatible = "wlf,wm8580"; - reg = <0x1b>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s5pv210-smdkv210.dts b/software/linux/kernel/arch/arm/boot/dts/s5pv210-smdkv210.dts deleted file mode 100644 index 75398318e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for YIC System SMDV210 board. - * - * NOTE: This file is completely based on original board file for mach-smdkv210 - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "YIC System SMDKV210 based on S5PV210"; - compatible = "yic,smdkv210", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x40000000>; - }; - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0xA8000000 0x2 0xA8000002 0x2>; - interrupt-parent = <&gph1>; - interrupts = <1 4>; - local-mac-address = [00 00 de ad be ef]; - davicom,no-eeprom; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&keypad { - linux,input-no-autorepeat; - wakeup-source; - samsung,keypad-num-rows = <8>; - samsung,keypad-num-columns = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>, - <&keypad_row3>, <&keypad_row4>, <&keypad_row5>, - <&keypad_row6>, <&keypad_row7>, - <&keypad_col0>, <&keypad_col1>, <&keypad_col2>, - <&keypad_col3>, <&keypad_col4>, <&keypad_col5>, - <&keypad_col6>, <&keypad_col7>; - status = "okay"; - - key_1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = ; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = ; - }; - - key_3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = ; - }; - - key_4 { - keypad,row = <0>; - keypad,column = <6>; - linux,code = ; - }; - - key_5 { - keypad,row = <0 - >; - keypad,column = <7>; - linux,code = ; - }; - - key_6 { - keypad,row = <1>; - keypad,column = <3>; - linux,code = ; - }; - key_7 { - keypad,row = <1>; - keypad,column = <4>; - linux,code = ; - }; - - key_8 { - keypad,row = <1>; - keypad,column = <5>; - linux,code = ; - }; - - key_9 { - keypad,row = <1>; - keypad,column = <6>; - linux,code = ; - }; - - key_10 { - keypad,row = <1>; - keypad,column = <7>; - linux,code = ; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdhci0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci1 { - bus-width = <4>; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci3 { - bus-width = <4>; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hsotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&fimd { - pinctrl-0 = <&lcd_clk &lcd_data24>; - pinctrl-names = "default"; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - - timing0: timing { - /* 800x480@60Hz */ - clock-frequency = <24373920>; - hactive = <800>; - vactive = <480>; - hfront-porch = <8>; - hback-porch = <13>; - hsync-len = <3>; - vback-porch = <7>; - vfront-porch = <5>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; -}; - -&pwm { - samsung,pwm-outputs = <3>; -}; - -&i2c0 { - status = "okay"; - - audio-codec@1b { - compatible = "wlf,wm8580"; - reg = <0x1b>; - }; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s5pv210-torbreck.dts b/software/linux/kernel/arch/arm/boot/dts/s5pv210-torbreck.dts deleted file mode 100644 index 7cb50bcee..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s5pv210-torbreck.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Board device tree source for Torbreck board. - * - * NOTE: This file is completely based on original board file for mach-torbreck - * available in Linux 3.15 and intends to provide equivalent level of hardware - * support. Due to lack of hardware, _no_ testing has been performed. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include "s5pv210.dtsi" - -/ { - model = "aESOP Torbreck based on S5PV210"; - compatible = "aesop,torbreck", "samsung,s5pv210"; - - chosen { - bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x20000000 0x20000000>; - }; -}; - -&xusbxti { - clock-frequency = <24000000>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdhci0 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci1 { - bus-width = <4>; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci2 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhci3 { - bus-width = <4>; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/s5pv210.dtsi b/software/linux/kernel/arch/arm/boot/dts/s5pv210.dtsi deleted file mode 100644 index 0c10ba517..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/s5pv210.dtsi +++ /dev/null @@ -1,636 +0,0 @@ -/* - * Samsung's S5PV210 SoC device tree source - * - * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. - * - * Mateusz Krawczuk - * Tomasz Figa - * - * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - csis0 = &csis0; - fimc0 = &fimc0; - fimc1 = &fimc1; - fimc2 = &fimc2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2s0 = &i2s0; - i2s1 = &i2s1; - i2s2 = &i2s2; - pinctrl0 = &pinctrl0; - spi0 = &spi0; - spi1 = &spi1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - external-clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - xxti: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <0>; - clock-output-names = "xxti"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - clock-output-names = "xusbxti"; - #clock-cells = <0>; - }; - }; - - onenand: onenand@b0000000 { - compatible = "samsung,s5pv210-onenand"; - reg = <0xb0600000 0x2000>, - <0xb0000000 0x20000>, - <0xb0040000 0x20000>; - interrupt-parent = <&vic1>; - interrupts = <31>; - clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>; - clock-names = "bus", "onenand"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - chipid@e0000000 { - compatible = "samsung,s5pv210-chipid"; - reg = <0xe0000000 0x1000>; - }; - - clocks: clock-controller@e0100000 { - compatible = "samsung,s5pv210-clock", "simple-bus"; - reg = <0xe0100000 0x10000>; - clock-names = "xxti", "xusbxti"; - clocks = <&xxti>, <&xusbxti>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pmu_syscon: syscon@e0108000 { - compatible = "samsung-s5pv210-pmu", "syscon"; - reg = <0xe0108000 0x8000>; - }; - }; - - pinctrl0: pinctrl@e0200000 { - compatible = "samsung,s5pv210-pinctrl"; - reg = <0xe0200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <30>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupts = <16>; - interrupt-parent = <&vic0>; - }; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - pdma0: dma@e0900000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0900000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <19>; - clocks = <&clocks CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: dma@e0a00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0a00000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <20>; - clocks = <&clocks CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - spi0: spi@e1300000 { - compatible = "samsung,s5pv210-spi"; - reg = <0xe1300000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <15>; - dmas = <&pdma0 7>, <&pdma0 6>; - dma-names = "tx", "rx"; - clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@e1400000 { - compatible = "samsung,s5pv210-spi"; - reg = <0xe1400000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <16>; - dmas = <&pdma1 7>, <&pdma1 6>; - dma-names = "tx", "rx"; - clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - keypad: keypad@e1600000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0xe1600000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <25>; - clocks = <&clocks CLK_KEYIF>; - clock-names = "keypad"; - status = "disabled"; - }; - - i2c0: i2c@e1800000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <14>; - clocks = <&clocks CLK_I2C0>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e1a00000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xe1a00000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <19>; - clocks = <&clocks CLK_I2C2>; - clock-names = "i2c"; - pinctrl-0 = <&i2c2_bus>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - audio-subsystem { - compatible = "samsung,s5pv210-audss", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_audss: clock-controller@eee10000 { - compatible = "samsung,s5pv210-audss-clock"; - reg = <0xeee10000 0x1000>; - clock-names = "hclk", "xxti", - "fout_epll", - "sclk_audio0"; - clocks = <&clocks DOUT_HCLKP>, <&xxti>, - <&clocks FOUT_EPLL>, - <&clocks SCLK_AUDIO0>; - #clock-cells = <1>; - }; - - i2s0: i2s@eee30000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0xeee30000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <16>; - dma-names = "rx", "tx", "tx-sec"; - dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; - clock-names = "iis", - "i2s_opclk0", - "i2s_opclk1"; - clocks = <&clk_audss CLK_I2S>, - <&clk_audss CLK_I2S>, - <&clk_audss CLK_DOUT_AUD_BUS>; - samsung,idma-addr = <0xc0010000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - }; - - i2s1: i2s@e2100000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0xe2100000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <17>; - dma-names = "rx", "tx"; - dmas = <&pdma1 12>, <&pdma1 13>; - clock-names = "iis", "i2s_opclk0"; - clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@e2a00000 { - compatible = "samsung,s3c6410-i2s"; - reg = <0xe2a00000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <18>; - dma-names = "rx", "tx"; - dmas = <&pdma1 14>, <&pdma1 15>; - clock-names = "iis", "i2s_opclk0"; - clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@e2500000 { - compatible = "samsung,s5pc100-pwm"; - reg = <0xe2500000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <21>, <22>, <23>, <24>, <25>; - clock-names = "timers"; - clocks = <&clocks CLK_PWM>; - #pwm-cells = <3>; - }; - - watchdog: watchdog@e2700000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0xe2700000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - clock-names = "watchdog"; - clocks = <&clocks CLK_WDT>; - }; - - rtc: rtc@e2800000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0xe2800000 0x100>; - interrupt-parent = <&vic0>; - interrupts = <28>, <29>; - clocks = <&clocks CLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - uart0: serial@e2900000 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900000 0x400>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>, - <&clocks SCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@e2900400 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900400 0x400>; - interrupt-parent = <&vic1>; - interrupts = <11>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>, - <&clocks SCLK_UART1>; - status = "disabled"; - }; - - uart2: serial@e2900800 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900800 0x400>; - interrupt-parent = <&vic1>; - interrupts = <12>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>, - <&clocks SCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@e2900c00 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900c00 0x400>; - interrupt-parent = <&vic1>; - interrupts = <13>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>, - <&clocks SCLK_UART3>; - status = "disabled"; - }; - - sdhci0: sdhci@eb000000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb000000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <26>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>, - <&clocks SCLK_MMC0>; - status = "disabled"; - }; - - sdhci1: sdhci@eb100000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb100000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <27>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>, - <&clocks SCLK_MMC1>; - status = "disabled"; - }; - - sdhci2: sdhci@eb200000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb200000 0x100000>; - interrupt-parent = <&vic1>; - interrupts = <28>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>, - <&clocks SCLK_MMC2>; - status = "disabled"; - }; - - sdhci3: sdhci@eb300000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0xeb300000 0x100000>; - interrupt-parent = <&vic3>; - interrupts = <2>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3"; - clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>, - <&clocks SCLK_MMC3>; - status = "disabled"; - }; - - hsotg: hsotg@ec000000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0xec000000 0x20000>; - interrupt-parent = <&vic1>; - interrupts = <24>; - clocks = <&clocks CLK_USB_OTG>; - clock-names = "otg"; - phy-names = "usb2-phy"; - phys = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: usbphy@ec100000 { - compatible = "samsung,s5pv210-usb2-phy"; - reg = <0xec100000 0x100>; - samsung,pmureg-phandle = <&pmu_syscon>; - clocks = <&clocks CLK_USB_OTG>, <&xusbxti>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - status = "disabled"; - }; - - ehci: ehci@ec200000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0xec200000 0x100>; - interrupts = <23>; - interrupt-parent = <&vic1>; - clocks = <&clocks CLK_USB_HOST>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; - }; - - ohci: ohci@ec300000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0xec300000 0x100>; - interrupts = <23>; - interrupt-parent = <&vic1>; - clocks = <&clocks CLK_USB_HOST>; - clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; - }; - - mfc: codec@f1700000 { - compatible = "samsung,mfc-v5"; - reg = <0xf1700000 0x10000>; - interrupt-parent = <&vic2>; - interrupts = <14>; - clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>; - clock-names = "sclk_mfc", "mfc"; - }; - - vic0: interrupt-controller@f2000000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2000000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@f2100000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2100000 0x1000>; - #interrupt-cells = <1>; - }; - - vic2: interrupt-controller@f2200000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2200000 0x1000>; - #interrupt-cells = <1>; - }; - - vic3: interrupt-controller@f2300000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0xf2300000 0x1000>; - #interrupt-cells = <1>; - }; - - fimd: fimd@f8000000 { - compatible = "samsung,exynos4210-fimd"; - interrupt-parent = <&vic2>; - reg = <0xf8000000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <0>, <1>, <2>; - clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>; - clock-names = "sclk_fimd", "fimd"; - status = "disabled"; - }; - - g2d: g2d@fa000000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0xfa000000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <9>; - clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - }; - - mdma1: mdma@fa200000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xfa200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <18>; - clocks = <&clocks CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - i2c1: i2c@fab00000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0xfab00000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <13>; - clocks = <&clocks CLK_I2C1>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - camera: camera { - compatible = "samsung,fimc", "simple-bus"; - pinctrl-names = "default"; - pinctrl-0 = <>; - clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; - clock-names = "sclk_cam0", "sclk_cam1"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock_cam: clock-controller { - #clock-cells = <1>; - }; - - csis0: csis@fa600000 { - compatible = "samsung,s5pv210-csis"; - reg = <0xfa600000 0x4000>; - interrupt-parent = <&vic2>; - interrupts = <29>; - clocks = <&clocks CLK_CSIS>, - <&clocks SCLK_CSIS>; - clock-names = "clk_csis", - "sclk_csis"; - bus-width = <4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - fimc0: fimc@fb200000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb200000 0x1000>; - interrupts = <5>; - interrupt-parent = <&vic2>; - clocks = <&clocks CLK_FIMC0>, - <&clocks SCLK_FIMC0>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; - }; - - fimc1: fimc@fb300000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb300000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <6>; - clocks = <&clocks CLK_FIMC1>, - <&clocks SCLK_FIMC1>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,cam-if; - }; - - fimc2: fimc@fb400000 { - compatible = "samsung,s5pv210-fimc"; - reg = <0xfb400000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <7>; - clocks = <&clocks CLK_FIMC2>, - <&clocks SCLK_FIMC2>; - clock-names = "fimc", - "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; - }; - }; - }; -}; - -#include "s5pv210-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d2-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/sama5d2-pinfunc.h deleted file mode 100644 index 8a394f336..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d2-pinfunc.h +++ /dev/null @@ -1,880 +0,0 @@ -#define PINMUX_PIN(no, func, ioset) \ -(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) - -#define PIN_PA0 0 -#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) -#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) -#define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) -#define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) -#define PIN_PA1 1 -#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) -#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) -#define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) -#define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) -#define PIN_PA2 2 -#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) -#define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) -#define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) -#define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) -#define PIN_PA3 3 -#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) -#define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) -#define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) -#define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) -#define PIN_PA4 4 -#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) -#define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) -#define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) -#define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) -#define PIN_PA5 5 -#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) -#define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) -#define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) -#define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) -#define PIN_PA6 6 -#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) -#define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) -#define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) -#define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) -#define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) -#define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) -#define PIN_PA7 7 -#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) -#define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) -#define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) -#define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) -#define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) -#define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) -#define PIN_PA8 8 -#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) -#define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) -#define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) -#define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) -#define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) -#define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) -#define PIN_PA9 9 -#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) -#define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) -#define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) -#define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) -#define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) -#define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) -#define PIN_PA10 10 -#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) -#define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) -#define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) -#define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) -#define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) -#define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) -#define PIN_PA11 11 -#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) -#define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) -#define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) -#define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) -#define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) -#define PIN_PA12 12 -#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) -#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) -#define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) -#define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) -#define PIN_PA13 13 -#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) -#define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) -#define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) -#define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) -#define PIN_PA14 14 -#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) -#define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) -#define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) -#define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) -#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) -#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) -#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) -#define PIN_PA15 15 -#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) -#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) -#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) -#define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) -#define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) -#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) -#define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) -#define PIN_PA16 16 -#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) -#define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) -#define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) -#define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) -#define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) -#define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) -#define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) -#define PIN_PA17 17 -#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) -#define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) -#define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) -#define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) -#define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) -#define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) -#define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) -#define PIN_PA18 18 -#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) -#define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) -#define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) -#define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) -#define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) -#define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) -#define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) -#define PIN_PA19 19 -#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) -#define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) -#define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) -#define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) -#define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) -#define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) -#define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) -#define PIN_PA20 20 -#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) -#define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) -#define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) -#define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) -#define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) -#define PIN_PA21 21 -#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) -#define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) -#define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) -#define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) -#define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) -#define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) -#define PIN_PA22 22 -#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) -#define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) -#define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) -#define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) -#define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) -#define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) -#define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) -#define PIN_PA23 23 -#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) -#define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) -#define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) -#define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) -#define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) -#define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) -#define PIN_PA24 24 -#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) -#define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) -#define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) -#define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) -#define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) -#define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) -#define PIN_PA25 25 -#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) -#define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) -#define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) -#define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) -#define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) -#define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) -#define PIN_PA26 26 -#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) -#define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) -#define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) -#define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) -#define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) -#define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) -#define PIN_PA27 27 -#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) -#define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) -#define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) -#define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) -#define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) -#define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) -#define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) -#define PIN_PA28 28 -#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) -#define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) -#define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) -#define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) -#define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) -#define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) -#define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) -#define PIN_PA29 29 -#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) -#define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) -#define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) -#define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) -#define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) -#define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) -#define PIN_PA30 30 -#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) -#define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) -#define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) -#define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) -#define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) -#define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) -#define PIN_PA31 31 -#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) -#define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) -#define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) -#define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) -#define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) -#define PIN_PB0 32 -#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) -#define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) -#define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) -#define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) -#define PIN_PB1 33 -#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) -#define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) -#define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) -#define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) -#define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) -#define PIN_PB2 34 -#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) -#define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) -#define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) -#define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) -#define PIN_PB3 35 -#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) -#define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) -#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) -#define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) -#define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) -#define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) -#define PIN_PB4 36 -#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) -#define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) -#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) -#define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) -#define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) -#define PIN_PB5 37 -#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) -#define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) -#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) -#define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) -#define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) -#define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) -#define PIN_PB6 38 -#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) -#define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) -#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) -#define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) -#define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) -#define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) -#define PIN_PB7 39 -#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) -#define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) -#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) -#define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) -#define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) -#define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) -#define PIN_PB8 40 -#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) -#define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) -#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) -#define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) -#define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) -#define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) -#define PIN_PB9 41 -#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) -#define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) -#define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) -#define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) -#define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) -#define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) -#define PIN_PB10 42 -#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) -#define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) -#define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) -#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) -#define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) -#define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) -#define PIN_PB11 43 -#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) -#define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) -#define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) -#define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) -#define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) -#define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) -#define PIN_PB12 44 -#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) -#define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) -#define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) -#define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) -#define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) -#define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) -#define PIN_PB13 45 -#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) -#define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) -#define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) -#define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) -#define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) -#define PIN_PB14 46 -#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) -#define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) -#define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) -#define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) -#define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) -#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) -#define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) -#define PIN_PB15 47 -#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) -#define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) -#define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) -#define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) -#define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) -#define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) -#define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) -#define PIN_PB16 48 -#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) -#define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) -#define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) -#define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) -#define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) -#define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) -#define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) -#define PIN_PB17 49 -#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) -#define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) -#define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) -#define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) -#define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) -#define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) -#define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) -#define PIN_PB18 50 -#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) -#define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) -#define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) -#define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) -#define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) -#define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) -#define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) -#define PIN_PB19 51 -#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) -#define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) -#define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) -#define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) -#define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) -#define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) -#define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) -#define PIN_PB20 52 -#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) -#define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) -#define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) -#define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) -#define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) -#define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) -#define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) -#define PIN_PB21 53 -#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) -#define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) -#define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) -#define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) -#define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) -#define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) -#define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) -#define PIN_PB22 54 -#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) -#define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) -#define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) -#define PIN_PB22__TDO PINMUX_PIN(PIN_PB22, 3, 1) -#define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) -#define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) -#define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) -#define PIN_PB23 55 -#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) -#define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) -#define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) -#define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) -#define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) -#define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) -#define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) -#define PIN_PB24 56 -#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) -#define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) -#define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) -#define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) -#define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) -#define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) -#define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) -#define PIN_PB25 57 -#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) -#define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) -#define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) -#define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) -#define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) -#define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) -#define PIN_PB26 58 -#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) -#define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) -#define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) -#define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) -#define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) -#define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) -#define PIN_PB27 59 -#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) -#define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) -#define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) -#define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) -#define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) -#define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) -#define PIN_PB28 60 -#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) -#define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) -#define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) -#define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) -#define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) -#define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) -#define PIN_PB29 61 -#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) -#define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) -#define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) -#define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) -#define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) -#define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) -#define PIN_PB30 62 -#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) -#define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) -#define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) -#define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) -#define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) -#define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) -#define PIN_PB31 63 -#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) -#define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) -#define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) -#define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) -#define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) -#define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) -#define PIN_PC0 64 -#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) -#define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) -#define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) -#define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) -#define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) -#define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) -#define PIN_PC1 65 -#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) -#define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) -#define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) -#define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) -#define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) -#define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) -#define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) -#define PIN_PC2 66 -#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) -#define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) -#define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) -#define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) -#define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) -#define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) -#define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) -#define PIN_PC3 67 -#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) -#define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) -#define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) -#define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) -#define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) -#define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) -#define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) -#define PIN_PC4 68 -#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) -#define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) -#define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) -#define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) -#define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) -#define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) -#define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) -#define PIN_PC5 69 -#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) -#define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) -#define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) -#define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) -#define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) -#define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) -#define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) -#define PIN_PC6 70 -#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) -#define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) -#define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) -#define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) -#define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) -#define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) -#define PIN_PC7 71 -#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) -#define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) -#define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) -#define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) -#define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) -#define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) -#define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) -#define PIN_PC8 72 -#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) -#define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) -#define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) -#define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) -#define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) -#define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) -#define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) -#define PIN_PC9 73 -#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) -#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) -#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) -#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 2, 1) -#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) -#define PIN_PC10 74 -#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) -#define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) -#define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) -#define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) -#define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) -#define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) -#define PIN_PC11 75 -#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) -#define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) -#define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) -#define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) -#define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) -#define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) -#define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) -#define PIN_PC12 76 -#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) -#define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) -#define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) -#define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) -#define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) -#define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) -#define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) -#define PIN_PC13 77 -#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) -#define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) -#define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) -#define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) -#define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) -#define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) -#define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) -#define PIN_PC14 78 -#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) -#define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) -#define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) -#define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) -#define PIN_PC14__TDO PINMUX_PIN(PIN_PC14, 5, 2) -#define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) -#define PIN_PC15 79 -#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -#define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) -#define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) -#define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) -#define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) -#define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) -#define PIN_PC16 80 -#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) -#define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) -#define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) -#define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) -#define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) -#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) -#define PIN_PC17 81 -#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) -#define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) -#define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) -#define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) -#define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) -#define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) -#define PIN_PC18 82 -#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) -#define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) -#define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) -#define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) -#define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) -#define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) -#define PIN_PC19 83 -#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) -#define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) -#define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) -#define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) -#define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) -#define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) -#define PIN_PC20 84 -#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) -#define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) -#define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) -#define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) -#define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) -#define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) -#define PIN_PC21 85 -#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) -#define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) -#define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) -#define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) -#define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) -#define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) -#define PIN_PC22 86 -#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) -#define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) -#define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) -#define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) -#define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) -#define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) -#define PIN_PC23 87 -#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) -#define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) -#define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) -#define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) -#define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) -#define PIN_PC24 88 -#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) -#define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) -#define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) -#define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) -#define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) -#define PIN_PC25 89 -#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) -#define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) -#define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) -#define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) -#define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) -#define PIN_PC26 90 -#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) -#define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) -#define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) -#define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) -#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) -#define PIN_PC27 91 -#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) -#define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) -#define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) -#define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) -#define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) -#define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) -#define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) -#define PIN_PC28 92 -#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) -#define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) -#define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) -#define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) -#define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) -#define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) -#define PIN_PC29 93 -#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) -#define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) -#define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) -#define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) -#define PIN_PC30 94 -#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) -#define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) -#define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) -#define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) -#define PIN_PC31 95 -#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) -#define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) -#define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) -#define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) -#define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) -#define PIN_PD0 96 -#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) -#define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) -#define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) -#define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) -#define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) -#define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) -#define PIN_PD1 97 -#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) -#define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) -#define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) -#define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) -#define PIN_PD2 98 -#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) -#define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) -#define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) -#define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) -#define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) -#define PIN_PD3 99 -#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) -#define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) -#define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) -#define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) -#define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) -#define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) -#define PIN_PD4 100 -#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) -#define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) -#define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) -#define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) -#define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) -#define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) -#define PIN_PD5 101 -#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) -#define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) -#define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) -#define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) -#define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) -#define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) -#define PIN_PD6 102 -#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) -#define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) -#define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) -#define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) -#define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) -#define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) -#define PIN_PD7 103 -#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) -#define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) -#define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) -#define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) -#define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) -#define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) -#define PIN_PD8 104 -#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) -#define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) -#define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) -#define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) -#define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) -#define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) -#define PIN_PD9 105 -#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) -#define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) -#define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) -#define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) -#define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) -#define PIN_PD10 106 -#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) -#define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) -#define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) -#define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) -#define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) -#define PIN_PD11 107 -#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) -#define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) -#define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) -#define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) -#define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) -#define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) -#define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) -#define PIN_PD12 108 -#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) -#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) -#define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) -#define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) -#define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) -#define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) -#define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) -#define PIN_PD13 109 -#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) -#define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) -#define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) -#define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) -#define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) -#define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) -#define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) -#define PIN_PD14 110 -#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) -#define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) -#define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) -#define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) -#define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) -#define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) -#define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) -#define PIN_PD15 111 -#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) -#define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) -#define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) -#define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) -#define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) -#define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) -#define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) -#define PIN_PD16 112 -#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) -#define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) -#define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) -#define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) -#define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) -#define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) -#define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) -#define PIN_PD17 113 -#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) -#define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) -#define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) -#define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) -#define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) -#define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) -#define PIN_PD18 114 -#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) -#define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) -#define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) -#define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) -#define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) -#define PIN_PD19 115 -#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) -#define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) -#define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) -#define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) -#define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) -#define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) -#define PIN_PD20 116 -#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) -#define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) -#define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) -#define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) -#define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) -#define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) -#define PIN_PD21 117 -#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -#define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) -#define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) -#define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) -#define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) -#define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) -#define PIN_PD22 118 -#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) -#define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) -#define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) -#define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) -#define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) -#define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) -#define PIN_PD23 119 -#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) -#define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) -#define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) -#define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) -#define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) -#define PIN_PD24 120 -#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD24, 1, 2) -#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD24, 3, 3) -#define PIN_PD25 121 -#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) -#define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) -#define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) -#define PIN_PD26 122 -#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) -#define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) -#define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) -#define PIN_PD27 123 -#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) -#define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) -#define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) -#define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) -#define PIN_PD28 124 -#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) -#define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) -#define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) -#define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) -#define PIN_PD29 125 -#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) -#define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) -#define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) -#define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) -#define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) -#define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) -#define PIN_PD30 126 -#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) -#define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) -#define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) -#define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) -#define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) -#define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) -#define PIN_PD31 127 -#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) -#define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) -#define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) -#define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) -#define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) -#define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d2.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d2.dtsi deleted file mode 100644 index 8158c873b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d2.dtsi +++ /dev/null @@ -1,1285 +0,0 @@ -/* - * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC - * - * Copyright (C) 2015 Atmel, - * 2015 Ludovic Desroches - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include -#include -#include - -/ { - model = "Atmel SAMA5D2 family SoC"; - compatible = "atmel,sama5d2"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &uart1; - serial1 = &uart3; - tcb0 = &tcb0; - tcb1 = &tcb1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; - }; - - etb { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x740000 0x1000>; - - clocks = <&mck>; - clock-names = "apb_pclk"; - - port { - etb_in: endpoint { - slave-mode; - remote-endpoint = <&etm_out>; - }; - }; - }; - - etm { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x73C000 0x1000>; - - clocks = <&mck>; - clock-names = "apb_pclk"; - - port { - etm_out: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - }; - - ns_sram: sram@00200000 { - compatible = "mmio-sram"; - reg = <0x00200000 0x20000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usb0: gadget@00300000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,sama5d3-udc"; - reg = <0x00300000 0x100000 - 0xfc02c000 0x400>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - }; - - usb1: ohci@00400000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00400000 0x100000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@00500000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00500000 0x100000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - L2: cache-controller@00a00000 { - compatible = "arm,pl310-cache"; - reg = <0x00a00000 0x1000>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; - cache-unified; - cache-level = <2>; - }; - - nand0: nand@80000000 { - compatible = "atmel,sama5d2-nand"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = < /* EBI CS3 */ - 0x80000000 0x08000000 - /* SMC PMECC regs */ - 0xf8014070 0x00000490 - /* SMC PMECC Error Location regs */ - 0xf8014500 0x00000200 - /* ROM Galois tables */ - 0x00040000 0x00018000 - >; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - atmel,has-pmecc; - atmel,pmecc-lookup-table-offset = <0x0 0x8000>; - status = "disabled"; - - nfc@c0000000 { - compatible = "atmel,sama5d3-nfc"; - #address-cells = <1>; - #size-cells = <1>; - reg = < /* NFC Command Registers */ - 0xc0000000 0x08000000 - /* NFC HSMC regs */ - 0xf8014000 0x00000070 - /* NFC SRAM banks */ - 0x00100000 0x00100000 - >; - clocks = <&hsmc_clk>; - atmel,write-by-sram; - }; - }; - - sdmmc0: sdio-host@a0000000 { - compatible = "atmel,sama5d2-sdhci"; - reg = <0xa0000000 0x300>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; - clock-names = "hclock", "multclk", "baseclk"; - status = "disabled"; - }; - - sdmmc1: sdio-host@b0000000 { - compatible = "atmel,sama5d2-sdhci"; - reg = <0xb0000000 0x300>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>; - clock-names = "hclock", "multclk", "baseclk"; - status = "disabled"; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hlcdc: hlcdc@f0000000 { - compatible = "atmel,sama5d2-hlcdc"; - reg = <0xf0000000 0x2000>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - #pwm-cells = <3>; - }; - }; - - ramc0: ramc@f000c000 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xf000c000 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; - clock-names = "ddrck", "mpddr"; - }; - - dma0: dma-controller@f0010000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0010000 0x1000>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - pmc: pmc@f0014000 { - compatible = "atmel,sama5d2-pmc", "syscon"; - reg = <0xf0014000 0x160>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clock-frequency = <12000000>; - clock-accuracy = <100000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <12000000 12000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <124000000 166000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - h32ck: h32mxck { - #clock-cells = <0>; - compatible = "atmel,sama5d4-clk-h32mx"; - clocks = <&mck>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - iscck: iscck { - #clock-cells = <0>; - reg = <18>; - clocks = <&mck>; - }; - }; - - periph32ck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&h32ck>; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <5>; - atmel,clk-output-range = <0 83000000>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <11>; - atmel,clk-output-range = <0 83000000>; - }; - - matrix1_clk: matrix1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <18>; - atmel,clk-output-range = <0 83000000>; - }; - - flx0_clk: flx0_clk { - #clock-cells = <0>; - reg = <19>; - atmel,clk-output-range = <0 83000000>; - }; - - flx1_clk: flx1_clk { - #clock-cells = <0>; - reg = <20>; - atmel,clk-output-range = <0 83000000>; - }; - - flx2_clk: flx2_clk { - #clock-cells = <0>; - reg = <21>; - atmel,clk-output-range = <0 83000000>; - }; - - flx3_clk: flx3_clk { - #clock-cells = <0>; - reg = <22>; - atmel,clk-output-range = <0 83000000>; - }; - - flx4_clk: flx4_clk { - #clock-cells = <0>; - reg = <23>; - atmel,clk-output-range = <0 83000000>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <24>; - atmel,clk-output-range = <0 83000000>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <25>; - atmel,clk-output-range = <0 83000000>; - }; - - uart2_clk: uart2_clk { - #clock-cells = <0>; - reg = <26>; - atmel,clk-output-range = <0 83000000>; - }; - - uart3_clk: uart3_clk { - #clock-cells = <0>; - reg = <27>; - atmel,clk-output-range = <0 83000000>; - }; - - uart4_clk: uart4_clk { - #clock-cells = <0>; - reg = <28>; - atmel,clk-output-range = <0 83000000>; - }; - - twi0_clk: twi0_clk { - reg = <29>; - #clock-cells = <0>; - atmel,clk-output-range = <0 83000000>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <30>; - atmel,clk-output-range = <0 83000000>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <33>; - atmel,clk-output-range = <0 83000000>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <34>; - atmel,clk-output-range = <0 83000000>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <35>; - atmel,clk-output-range = <0 83000000>; - }; - - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <36>; - atmel,clk-output-range = <0 83000000>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <40>; - atmel,clk-output-range = <0 83000000>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <41>; - atmel,clk-output-range = <0 83000000>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <42>; - atmel,clk-output-range = <0 83000000>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <43>; - atmel,clk-output-range = <0 83000000>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <44>; - atmel,clk-output-range = <0 83000000>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <47>; - atmel,clk-output-range = <0 83000000>; - }; - - pdmic_clk: pdmic_clk { - #clock-cells = <0>; - reg = <48>; - atmel,clk-output-range = <0 83000000>; - }; - - i2s0_clk: i2s0_clk { - #clock-cells = <0>; - reg = <54>; - atmel,clk-output-range = <0 83000000>; - }; - - i2s1_clk: i2s1_clk { - #clock-cells = <0>; - reg = <55>; - atmel,clk-output-range = <0 83000000>; - }; - - classd_clk: classd_clk { - #clock-cells = <0>; - reg = <59>; - atmel,clk-output-range = <0 83000000>; - }; - }; - - periph64ck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <9>; - }; - - aesb_clk: aesb_clk { - #clock-cells = <0>; - reg = <10>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <12>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <13>; - }; - - matrix0_clk: matrix0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - sdmmc0_hclk: sdmmc0_hclk { - #clock-cells = <0>; - reg = <31>; - }; - - sdmmc1_hclk: sdmmc1_hclk { - #clock-cells = <0>; - reg = <32>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <45>; - }; - - isc_clk: isc_clk { - #clock-cells = <0>; - reg = <46>; - }; - - qspi0_clk: qspi0_clk { - #clock-cells = <0>; - reg = <52>; - }; - - qspi1_clk: qspi1_clk { - #clock-cells = <0>; - reg = <53>; - }; - }; - - gck { - compatible = "atmel,sama5d2-clk-generated"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - sdmmc0_gclk: sdmmc0_gclk { - #clock-cells = <0>; - reg = <31>; - }; - - sdmmc1_gclk: sdmmc1_gclk { - #clock-cells = <0>; - reg = <32>; - }; - - tcb0_gclk: tcb0_gclk { - #clock-cells = <0>; - reg = <35>; - atmel,clk-output-range = <0 83000000>; - }; - - tcb1_gclk: tcb1_gclk { - #clock-cells = <0>; - reg = <36>; - atmel,clk-output-range = <0 83000000>; - }; - - pwm_gclk: pwm_gclk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - - pdmic_gclk: pdmic_gclk { - #clock-cells = <0>; - reg = <48>; - }; - - i2s0_gclk: i2s0_gclk { - #clock-cells = <0>; - reg = <54>; - }; - - i2s1_gclk: i2s1_gclk { - #clock-cells = <0>; - reg = <55>; - }; - }; - }; - - sha@f0028000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf0028000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(30))>; - dma-names = "tx"; - clocks = <&sha_clk>; - clock-names = "sha_clk"; - status = "okay"; - }; - - aes@f002c000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf002c000 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(26))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(27))>; - dma-names = "tx", "rx"; - clocks = <&aes_clk>; - clock-names = "aes_clk"; - status = "okay"; - }; - - spi0: spi@f8000000 { - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8000000 0x100>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(6))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - macb0: ethernet@f8008000 { - compatible = "atmel,sama5d2-gem"; - reg = <0xf8008000 0x1000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ - 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ - 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ - #address-cells = <1>; - #size-cells = <0>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - tcb0: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf800c000 0x100>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - tcb1: timer@f8010000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf8010000 0x100>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - pdmic: pdmic@f8018000 { - compatible = "atmel,sama5d2-pdmic"; - reg = <0xf8018000 0x124>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(50))>; - dma-names = "rx"; - clocks = <&pdmic_clk>, <&pdmic_gclk>; - clock-names = "pclk", "gclk"; - status = "disabled"; - }; - - uart0: serial@f801c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf801c000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(35))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(36))>; - dma-names = "tx", "rx"; - clocks = <&uart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(37))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(38))>; - dma-names = "tx", "rx"; - clocks = <&uart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart2: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(39))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(40))>; - dma-names = "tx", "rx"; - clocks = <&uart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - i2c0: i2c@f8028000 { - compatible = "atmel,sama5d2-i2c"; - reg = <0xf8028000 0x100>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(0))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(1))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - sfr: sfr@f8030000 { - compatible = "atmel,sama5d2-sfr", "syscon"; - reg = <0xf8030000 0x98>; - }; - - flx0: flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&flx0_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - status = "disabled"; - }; - - flx1: flexcom@f8038000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8038000 0x200>; - clocks = <&flx1_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8038000 0x800>; - status = "disabled"; - }; - - rstc@f8048000 { - compatible = "atmel,sama5d3-rstc"; - reg = <0xf8048000 0x10>; - clocks = <&clk32k>; - }; - - shdwc@f8048010 { - compatible = "atmel,sama5d2-shdwc"; - reg = <0xf8048010 0x10>; - clocks = <&clk32k>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - }; - - pit: timer@f8048030 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xf8048030 0x10>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&h32ck>; - }; - - watchdog@f8048040 { - compatible = "atmel,sama5d4-wdt"; - reg = <0xf8048040 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - sckc@f8048050 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xf8048050 0x4>; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <250000000>; - atmel,startup-time-usec = <75>; - }; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - atmel,startup-time-usec = <1200000>; - }; - - clk32k: slowck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; - }; - - rtc@f80480b0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xf80480b0 0x30>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - - spi1: spi@fc000000 { - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc000000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(8))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(9))>; - dma-names = "tx", "rx"; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart3: serial@fc008000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc008000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(41))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(42))>; - dma-names = "tx", "rx"; - clocks = <&uart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart4: serial@fc00c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc00c000 0x100>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(43))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(44))>; - dma-names = "tx", "rx"; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&uart4_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - flx2: flexcom@fc010000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc010000 0x200>; - clocks = <&flx2_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc010000 0x800>; - status = "disabled"; - }; - - flx3: flexcom@fc014000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc014000 0x200>; - clocks = <&flx3_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc014000 0x800>; - status = "disabled"; - }; - - flx4: flexcom@fc018000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xfc018000 0x200>; - clocks = <&flx4_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xfc018000 0x800>; - status = "disabled"; - }; - - trng@fc01c000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfc01c000 0x100>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; - }; - - aic: interrupt-controller@fc020000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d2-aic"; - interrupt-controller; - reg = <0xfc020000 0x200>; - atmel,external-irqs = <49>; - }; - - i2c1: i2c@fc028000 { - compatible = "atmel,sama5d2-i2c"; - reg = <0xfc028000 0x100>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(2))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - adc: adc@fc030000 { - compatible = "atmel,sama5d2-adc"; - reg = <0xfc030000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&adc_clk>; - clock-names = "adc_clk"; - atmel,min-sample-rate-hz = <200000>; - atmel,max-sample-rate-hz = <20000000>; - atmel,startup-time-ms = <4>; - status = "disabled"; - }; - - pioA: pinctrl@fc038000 { - compatible = "atmel,sama5d2-pinctrl"; - reg = <0xfc038000 0x600>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, - <68 IRQ_TYPE_LEVEL_HIGH 7>, - <69 IRQ_TYPE_LEVEL_HIGH 7>, - <70 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&pioA_clk>; - }; - - tdes@fc044000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xfc044000 0x100>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(28))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(29))>; - dma-names = "tx", "rx"; - clocks = <&tdes_clk>; - clock-names = "tdes_clk"; - status = "okay"; - }; - - chipid@fc069000 { - compatible = "atmel,sama5d2-chipid"; - reg = <0xfc069000 0x8>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3.dtsi deleted file mode 100644 index 4c84d333f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3.dtsi +++ /dev/null @@ -1,1496 +0,0 @@ -/* - * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC - * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Licensed under GPLv2 or later. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Atmel SAMA5D3 family SoC"; - compatible = "atmel,sama5d3", "atmel,sama5"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &dbgu; - serial1 = &usart0; - serial2 = &usart1; - serial3 = &usart2; - serial4 = &usart3; - serial5 = &uart0; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - tcb0 = &tcb0; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - ssc0 = &ssc0; - ssc1 = &ssc1; - pwm0 = &pwm0; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0x0>; - }; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; - }; - - memory { - reg = <0x20000000 0x8000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - sram: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x20000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mmc0: mmc@f0000000 { - compatible = "atmel,hsmci"; - reg = <0xf0000000 0x600>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - }; - - spi0: spi@f0004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf0004000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ssc0: ssc@f0008000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0008000 0x4000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - tcb0: timer@f0010000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf0010000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - i2c0: i2c@f0014000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf0014000 0x4000>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@f0018000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf0018000 0x4000>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, - <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f0020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0020000 0x100>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart0: serial@f0024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0024000 0x100>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - pwm0: pwm@f002c000 { - compatible = "atmel,sama5d3-pwm"; - reg = <0xf002c000 0x300>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - status = "disabled"; - }; - - isi: isi@f0034000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf0034000 0x4000>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sfr: sfr@f0038000 { - compatible = "atmel,sama5d3-sfr", "syscon"; - reg = <0xf0038000 0x60>; - }; - - mmc1: mmc@f8000000 { - compatible = "atmel,hsmci"; - reg = <0xf8000000 0x600>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci1_clk>; - clock-names = "mci_clk"; - }; - - spi1: spi@f8008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8008000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - ssc1: ssc@f800c000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf800c000 0x4000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - adc0: adc@f8018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9x5-adc"; - reg = <0xf8018000 0x100>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - &pinctrl_adc0_ad5 - &pinctrl_adc0_ad6 - &pinctrl_adc0_ad7 - &pinctrl_adc0_ad8 - &pinctrl_adc0_ad9 - &pinctrl_adc0_ad10 - &pinctrl_adc0_ad11 - >; - clocks = <&adc_clk>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0xfff>; - atmel,adc-startup-time = <40>; - atmel,adc-use-external-triggers; - atmel,adc-vref = <3000>; - atmel,adc-res = <10 12>; - atmel,adc-sample-hold-time = <11>; - atmel,adc-res-names = "lowres", "highres"; - status = "disabled"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; - }; - - i2c2: i2c@f801c000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf801c000 0x4000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi2_clk>; - status = "disabled"; - }; - - usart2: serial@f8020000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8020000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@f8024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8024000 0x100>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - sha@f8034000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf8034000 0x100>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; - dma-names = "tx"; - clocks = <&sha_clk>; - clock-names = "sha_clk"; - }; - - aes@f8038000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf8038000 0x100>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; - dma-names = "tx", "rx"; - clocks = <&aes_clk>; - clock-names = "aes_clk"; - }; - - tdes@f803c000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xf803c000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, - <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; - dma-names = "tx", "rx"; - clocks = <&tdes_clk>; - clock-names = "tdes_clk"; - }; - - trng@f8040000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xf8040000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; - }; - - dma0: dma-controller@ffffe600 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffe600 0x200>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - dma1: dma-controller@ffffe800 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffe800 0x200>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <2>; - clocks = <&dma1_clk>; - clock-names = "dma_clk"; - }; - - ramc0: ramc@ffffea00 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xffffea00 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; - clock-names = "ddrck", "mpddr"; - }; - - dbgu: serial@ffffee00 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xffffee00 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, - <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&dbgu_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - aic: interrupt-controller@fffff000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d3-aic"; - interrupt-controller; - reg = <0xfffff000 0x200>; - atmel,external-irqs = <47>; - }; - - pinctrl@fffff200 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; - ranges = <0xfffff200 0xfffff200 0xa00>; - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ - 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ - 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ - 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ - 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ - >; - - /* shared pinctrl settings */ - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = - ; /* PD19 periph A ADTRG */ - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = - ; /* PD20 periph A AD0 */ - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = - ; /* PD21 periph A AD1 */ - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = - ; /* PD22 periph A AD2 */ - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = - ; /* PD23 periph A AD3 */ - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = - ; /* PD24 periph A AD4 */ - }; - pinctrl_adc0_ad5: adc0_ad5 { - atmel,pins = - ; /* PD25 periph A AD5 */ - }; - pinctrl_adc0_ad6: adc0_ad6 { - atmel,pins = - ; /* PD26 periph A AD6 */ - }; - pinctrl_adc0_ad7: adc0_ad7 { - atmel,pins = - ; /* PD27 periph A AD7 */ - }; - pinctrl_adc0_ad8: adc0_ad8 { - atmel,pins = - ; /* PD28 periph A AD8 */ - }; - pinctrl_adc0_ad9: adc0_ad9 { - atmel,pins = - ; /* PD29 periph A AD9 */ - }; - pinctrl_adc0_ad10: adc0_ad10 { - atmel,pins = - ; /* PD30 periph A AD10, conflicts with PCK0 */ - }; - pinctrl_adc0_ad11: adc0_ad11 { - atmel,pins = - ; /* PD31 periph A AD11, conflicts with PCK1 */ - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - ; /* PB31 periph A with pullup */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ - }; - - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ - }; - - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ - }; - }; - - mmc0 { - pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { - atmel,pins = - ; /* PD1 periph A MCI0_DA0 with pullup */ - }; - pinctrl_mmc0_dat1_3: mmc0_dat1_3 { - atmel,pins = - ; /* PD4 periph A MCI0_DA3 with pullup */ - }; - pinctrl_mmc0_dat4_7: mmc0_dat4_7 { - atmel,pins = - ; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ - }; - }; - - mmc1 { - pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { - atmel,pins = - ; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ - }; - pinctrl_mmc1_dat1_3: mmc1_dat1_3 { - atmel,pins = - ; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ - }; - }; - - nand0 { - pinctrl_nand0_ale_cle: nand0_ale_cle-0 { - atmel,pins = - ; /* PE22 periph A with pullup */ - }; - }; - - pwm0 { - pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { - atmel,pins = - ; /* conflicts with ISI_D4 and LCDDAT20 */ - }; - pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { - atmel,pins = - ; /* conflicts with GTX0 */ - }; - pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { - atmel,pins = - ; /* conflicts with ISI_D5 and LCDDAT21 */ - }; - pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { - atmel,pins = - ; /* conflicts with GTX1 */ - }; - - pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { - atmel,pins = - ; /* conflicts with ISI_D6 and LCDDAT22 */ - }; - pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { - atmel,pins = - ; /* conflicts with GRX0 */ - }; - pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { - atmel,pins = - ; /* conflicts with G125CKO and RTS1 */ - }; - pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { - atmel,pins = - ; /* conflicts with ISI_D7 and LCDDAT23 */ - }; - pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { - atmel,pins = - ; /* conflicts with GRX1 */ - }; - pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { - atmel,pins = - ; /* conflicts with IRQ */ - }; - - pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { - atmel,pins = - ; /* conflicts with GTXCK */ - }; - pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { - atmel,pins = - ; /* conflicts with MCI0_DA4 and TIOA0 */ - }; - pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { - atmel,pins = - ; /* conflicts with GTXEN */ - }; - pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { - atmel,pins = - ; /* conflicts with MCI0_DA5 and TIOB0 */ - }; - - pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { - atmel,pins = - ; /* conflicts with GRXDV */ - }; - pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { - atmel,pins = - ; /* conflicts with MCI0_DA6 and TCLK0 */ - }; - pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { - atmel,pins = - ; /* conflicts with GRXER */ - }; - pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { - atmel,pins = - ; /* conflicts with MCI0_DA7 */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; /* PD12 periph A SPI0_SPCK pin */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; /* PC24 periph A SPI1_SPCK pin */ - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx { - atmel,pins = - ; /* PC18 periph A TD0 */ - }; - - pinctrl_ssc0_rx: ssc0_rx { - atmel,pins = - ; /* PC21 periph A RD0 */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx { - atmel,pins = - ; /* PB6 periph B TD1, conflicts with TD1 */ - }; - - pinctrl_ssc1_rx: ssc1_rx { - atmel,pins = - ; /* PB11 periph B RD1, conflicts with GRXCK */ - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* conflicts with ISI_PCK */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* conflicts with TWCK0, ISI_HSYNC */ - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; /* PD18 periph A with pullup */ - }; - - pinctrl_usart0_rts_cts: usart0_rts_cts-0 { - atmel,pins = - ; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; /* PB29 periph A with pullup */ - }; - - pinctrl_usart1_rts_cts: usart1_rts_cts-0 { - atmel,pins = - ; /* PB27 periph A, conflicts with G125CKO */ - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; /* PE26 periph B with pullup, conflicts NCS0 */ - }; - - pinctrl_usart2_rts_cts: usart2_rts_cts-0 { - atmel,pins = - ; /* PE24 periph B, conflicts with A24 */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; /* PE19 periph B with pullup, conflicts with A19 */ - }; - - pinctrl_usart3_rts_cts: usart3_rts_cts-0 { - atmel,pins = - ; /* PE17 periph B, conflicts with A17 */ - }; - }; - - - pioA: gpio@fffff200 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioE_clk>; - }; - }; - - pmc: pmc@fffffc00 { - compatible = "atmel,sama5d3-pmc", "syscon"; - reg = <0xfffffc00 0x120>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <8000000 50000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 166000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dbgu_clk: dbgu_clk { - #clock-cells = <0>; - reg = <2>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <5>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <6>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <7>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <8>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <9>; - }; - - pioE_clk: pioE_clk { - #clock-cells = <0>; - reg = <10>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <12>; - atmel,clk-output-range = <0 66000000>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <13>; - atmel,clk-output-range = <0 66000000>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <14>; - atmel,clk-output-range = <0 66000000>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <15>; - atmel,clk-output-range = <0 66000000>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 66000000>; - }; - - twi0_clk: twi0_clk { - reg = <18>; - #clock-cells = <0>; - atmel,clk-output-range = <0 16625000>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <19>; - atmel,clk-output-range = <0 16625000>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <20>; - atmel,clk-output-range = <0 16625000>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <22>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <24>; - atmel,clk-output-range = <0 133000000>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <25>; - atmel,clk-output-range = <0 133000000>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <26>; - atmel,clk-output-range = <0 133000000>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <28>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <29>; - atmel,clk-output-range = <0 66000000>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <30>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <31>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <32>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <33>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <37>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 66000000>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <39>; - atmel,clk-output-range = <0 66000000>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <42>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <43>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <44>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <45>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <48>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <49>; - }; - }; - }; - - rstc@fffffe00 { - compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; - reg = <0xfffffe00 0x10>; - clocks = <&clk32k>; - }; - - shutdown-controller@fffffe10 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfffffe10 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fffffe30 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfffffe30 0xf>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&mck>; - }; - - watchdog@fffffe40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffe40 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - status = "disabled"; - }; - - sckc@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - atmel,startup-time-usec = <75>; - }; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - atmel,startup-time-usec = <1200000>; - }; - - clk32k: slowck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; - }; - - rtc@fffffeb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffeb0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - }; - - usb0: gadget@00500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,sama5d3-udc"; - reg = <0x00500000 0x100000 - 0xf8030000 0x4000>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - }; - - usb1: ohci@00600000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00600000 0x100000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@00700000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00700000 0x100000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - nand0: nand@60000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = < 0x60000000 0x01000000 /* EBI CS3 */ - 0xffffc070 0x00000490 /* SMC PMECC regs */ - 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ - 0x00110000 0x00018000 /* ROM code */ - >; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand0_ale_cle>; - atmel,pmecc-lookup-table-offset = <0x0 0x8000>; - status = "disabled"; - - nfc@70000000 { - compatible = "atmel,sama5d3-nfc"; - #address-cells = <1>; - #size-cells = <1>; - reg = < - 0x70000000 0x08000000 /* NFC Command Registers */ - 0xffffc000 0x00000070 /* NFC HSMC regs */ - 0x00200000 0x00100000 /* NFC SRAM banks */ - >; - clocks = <&hsmc_clk>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d31.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d31.dtsi deleted file mode 100644 index 883878b32..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d31.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* - * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_uart.dtsi" - -/ { - compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d31ek.dts b/software/linux/kernel/arch/arm/boot/dts/sama5d31ek.dts deleted file mode 100644 index 25e4c0b2d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d31ek.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "sama5d31.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D31-EK"; - compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - leds { - d3 { - label = "d3"; - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d33.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d33.dtsi deleted file mode 100644 index 4b4434aca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d33.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -/* - * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_gmac.dtsi" - -/ { - compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d33ek.dts b/software/linux/kernel/arch/arm/boot/dts/sama5d33ek.dts deleted file mode 100644 index c517b87a1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d33ek.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "sama5d33.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_gmac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D33-EK"; - compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d34.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d34.dtsi deleted file mode 100644 index aa01573fd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d34.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* - * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_mci2.dtsi" - -/ { - compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d34ek.dts b/software/linux/kernel/arch/arm/boot/dts/sama5d34ek.dts deleted file mode 100644 index c8b8449fd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d34ek.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* - * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "sama5d34.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_gmac.dtsi" -#include "sama5d3xdm.dtsi" - -/ { - model = "Atmel SAMA5D34-EK"; - compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - - 24c256@50 { - compatible = "24c256"; - reg = <0x50>; - pagesize = <64>; - }; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - }; - }; - - leds { - d3 { - label = "d3"; - gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d35.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d35.dtsi deleted file mode 100644 index 16c39f4c9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d35.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* - * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_uart.dtsi" -#include "sama5d3_tcb1.dtsi" - -/ { - compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d35ek.dts b/software/linux/kernel/arch/arm/boot/dts/sama5d35ek.dts deleted file mode 100644 index 6e261fcf5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d35ek.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "sama5d35.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xmb_gmac.dtsi" - -/ { - model = "Atmel SAMA5D35-EK"; - compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - - isi: isi@f0034000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - pb_user1 { - label = "pb_user1"; - gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; - linux,code = <0x100>; - wakeup-source; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d36.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d36.dtsi deleted file mode 100644 index e85139ef4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d36.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -/* - * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC - * - * Copyright (C) 2013 Atmel, - * 2013 Josh Wu - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_tcb1.dtsi" -#include "sama5d3_uart.dtsi" - -/ { - compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d36ek.dts b/software/linux/kernel/arch/arm/boot/dts/sama5d36ek.dts deleted file mode 100644 index cd458b85a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d36ek.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board - * - * Copyright (C) 2013 Atmel, - * 2013 Josh Wu - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "sama5d36.dtsi" -#include "sama5d3xmb.dtsi" -#include "sama5d3xdm.dtsi" -#include "sama5d3xmb_emac.dtsi" -#include "sama5d3xmb_gmac.dtsi" - -/ { - model = "Atmel SAMA5D36-EK"; - compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - spi0: spi@f0004000 { - status = "okay"; - }; - - ssc0: ssc@f0008000 { - status = "okay"; - }; - - can0: can@f000c000 { - status = "okay"; - }; - - i2c0: i2c@f0014000 { - status = "okay"; - }; - - i2c1: i2c@f0018000 { - status = "okay"; - }; - - macb0: ethernet@f0028000 { - status = "okay"; - }; - - macb1: ethernet@f802c000 { - status = "okay"; - }; - }; - }; - - sound { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3_can.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3_can.dtsi deleted file mode 100644 index c5a377274..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3_can.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -/* - * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with - * CAN support - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - ; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - ; /* PB15 periph B TX, conflicts with GCOL */ - }; - }; - - }; - - pmc: pmc@fffffc00 { - periphck { - can0_clk: can0_clk { - #clock-cells = <0>; - reg = <40>; - atmel,clk-output-range = <0 66000000>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <41>; - atmel,clk-output-range = <0 66000000>; - }; - }; - }; - - can0: can@f000c000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf000c000 0x300>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&can0_clk>; - clock-names = "can_clk"; - status = "disabled"; - }; - - can1: can@f8010000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8010000 0x300>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&can1_clk>; - clock-names = "can_clk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3_emac.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3_emac.dtsi deleted file mode 100644 index 7cb235ef0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3_emac.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -/* - * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with - * Ethernet. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; /* PC9 periph A EMDIO */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <35>; - }; - }; - }; - - macb1: ethernet@f802c000 { - compatible = "cdns,at91sam9260-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&macb1_clk>, <&macb1_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3_gmac.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3_gmac.dtsi deleted file mode 100644 index 23f225fbb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -/* - * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with - * Gigabit Ethernet. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - macb0 { - pinctrl_macb0_data_rgmii: macb0_data_rgmii { - atmel,pins = - ; /* PB7 periph A GRX3, conflicts with RK1 */ - }; - pinctrl_macb0_data_gmii: macb0_data_gmii { - atmel,pins = - ; /* PB26 periph B GRX7, conflicts with CTS1 */ - }; - pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { - atmel,pins = - ; /* PB18 periph A G125CK */ - }; - pinctrl_macb0_signal_gmii: macb0_signal_gmii { - atmel,pins = - ; /* PB27 periph B G125CKO */ - }; - - }; - }; - - pmc: pmc@fffffc00 { - periphck { - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <34>; - }; - }; - }; - - macb0: ethernet@f0028000 { - compatible = "atmel,sama5d3-gem"; - reg = <0xf0028000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3_lcd.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3_lcd.dtsi deleted file mode 100644 index be7cfefc6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -/* - * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with - * LCD support - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include - -/ { - ahb { - apb { - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - pinctrl@fffff200 { - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { - atmel,pins = - ; /* LCDD17 pin */ - }; - - pinctrl_lcd_rgb888: lcd-rgb-3 { - atmel,pins = - ; /* LCDD23 pin */ - }; - - pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <36>; - }; - }; - - systemck { - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3_mci2.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3_mci2.dtsi deleted file mode 100644 index e21099a1a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -/* - * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with - * 3 MMC ports - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include -#include - -/ { - ahb { - apb { - pinctrl@fffff200 { - mmc2 { - pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { - atmel,pins = - ; /* PC11 periph A MCI2_DA0 with pullup */ - }; - pinctrl_mmc2_dat1_3: mmc2_dat1_3 { - atmel,pins = - ; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - mci2_clk: mci2_clk { - #clock-cells = <0>; - reg = <23>; - }; - }; - }; - - mmc2: mmc@f8004000 { - compatible = "atmel,hsmci"; - reg = <0xf8004000 0x600>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; - clocks = <&mci2_clk>; - clock-names = "mci_clk"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3_tcb1.dtsi deleted file mode 100644 index 801f9745e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with - * 2 TC blocks. - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include -#include - -/ { - aliases { - tcb1 = &tcb1; - }; - - ahb { - apb { - pmc: pmc@fffffc00 { - periphck { - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <27>; - }; - }; - }; - - tcb1: timer@f8014000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf8014000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3_uart.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3_uart.dtsi deleted file mode 100644 index 2511d7488..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3_uart.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -/* - * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with - * UART support - * - * Copyright (C) 2013 Boris BREZILLON - * - * Licensed under GPLv2. - */ - -#include -#include -#include - -/ { - aliases { - serial5 = &uart0; - serial6 = &uart1; - }; - - ahb { - apb { - pinctrl@fffff200 { - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; /* PC30 periph A with pullup, conflicts with ISI_PCK */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ - }; - }; - }; - - pmc: pmc@fffffc00 { - periphck { - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 66000000>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <17>; - atmel,clk-output-range = <0 66000000>; - }; - }; - }; - - uart0: serial@f0024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0024000 0x200>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - uart1: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3xcm.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3xcm.dtsi deleted file mode 100644 index b5e111b29..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3xcm.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -/* - * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Licensed under GPLv2 or later. - */ - -/ { - compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; - - chosen { - bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - spi0: spi@f0004000 { - cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; - }; - }; - - nand0: nand@60000000 { - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - atmel,has-pmecc; - atmel,pmecc-cap = <4>; - atmel,pmecc-sector-size = <512>; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x40000>; - }; - - bootloader@40000 { - label = "bootloader"; - reg = <0x40000 0x80000>; - }; - - bootloaderenv@c0000 { - label = "bootloader env"; - reg = <0xc0000 0xc0000>; - }; - - dtb@180000 { - label = "device tree"; - reg = <0x180000 0x80000>; - }; - - kernel@200000 { - label = "kernel"; - reg = <0x200000 0x600000>; - }; - - rootfs@800000 { - label = "rootfs"; - reg = <0x800000 0x0f800000>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - d2 { - label = "d2"; - gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3xdm.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3xdm.dtsi deleted file mode 100644 index 035ab72b3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3xdm.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * sama5d3dm.dtsi - Device Tree file for SAMA5 display module - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Licensed under GPLv2 or later. - */ - -/ { - ahb { - apb { - i2c1: i2c@f0018000 { - qt1070: keyboard@1b { - compatible = "qt1070"; - reg = <0x1b>; - interrupt-parent = <&pioE>; - interrupts = <31 0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qt1070_irq>; - wakeup-source; - }; - }; - - adc0: adc@f8018000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_qt1070_irq: qt1070_irq { - atmel,pins = - ; /* PE31 GPIO with pull up deglith */ - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb.dtsi deleted file mode 100644 index 6d252ad05..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb.dtsi +++ /dev/null @@ -1,209 +0,0 @@ -/* - * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3xcm.dtsi" - -/ { - compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; - - ahb { - apb { - mmc0: mmc@f0000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; - }; - }; - - spi0: spi@f0004000 { - dmas = <0>, <0>; /* Do not use DMA for spi0 */ - - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - ssc0: ssc@f0008000 { - atmel,clk-from-rk-pin; - }; - - /* - * i2c0 conflicts with ISI: - * disable it to allow the use of ISI - * can not enable audio when i2c0 disabled - */ - i2c0: i2c@f0014000 { - wm8904: wm8904@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pck0>; - clock-names = "mclk"; - }; - }; - - i2c1: i2c@f0018000 { - ov2640: camera@0x30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; - /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; - clock-names = "xvclk"; - assigned-clocks = <&pck1>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; - }; - - usart1: serial@f0020000 { - dmas = <0>, <0>; /* Do not use DMA for usart1 */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; - status = "okay"; - }; - - isi: isi@f0034000 { - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; - }; - - mmc1: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; - }; - }; - - adc0: adc@f8018000 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_adc0_adtrg - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - status = "okay"; - }; - - pinctrl@fffff200 { - board { - pinctrl_mmc0_cd: mmc0_cd { - atmel,pins = - ; /* PD17 GPIO with pullup deglitch */ - }; - - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = - ; /* PD18 GPIO with pullup deglitch */ - }; - - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - ; /* PD30 periph B */ - }; - - pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { - atmel,pins = - ; /* PD31 periph B ISI_MCK */ - }; - - pinctrl_sensor_reset: sensor_reset-0 { - atmel,pins = - ; /* PE24 gpio */ - }; - - pinctrl_sensor_power: sensor_power-0 { - atmel,pins = - ; /* PE29 gpio */ - }; - - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - ; /* PD29 GPIO with deglitch */ - }; - }; - }; - - dbgu: serial@ffffee00 { - dmas = <0>, <0>; /* Do not use DMA for dbgu */ - status = "okay"; - }; - - watchdog@fffffe40 { - status = "okay"; - }; - }; - - usb0: gadget@00500000 { - atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usba_vbus>; - status = "okay"; - }; - - usb1: ohci@00600000 { - num-ports = <3>; - atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH - &pioD 26 GPIO_ACTIVE_LOW - &pioD 27 GPIO_ACTIVE_LOW - >; - status = "okay"; - }; - - usb2: ehci@00700000 { - status = "okay"; - }; - }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ SAMA5D3EK"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb_emac.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb_emac.dtsi deleted file mode 100644 index 2fd14f371..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb_emac.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -/* - * sama5d3xmb_emac.dts - Device Tree Include file for SAMA5D3x mother board - * Ethernet - * - * Copyright (C) 2016 Atmel, - * - * Licensed under GPLv2 or later. - */ - -/ { - ahb { - apb { - macb1: ethernet@f802c000 { - phy-mode = "rmii"; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@1 { - interrupt-parent = <&pioE>; - interrupts = <30 IRQ_TYPE_EDGE_FALLING>; - reg = <1>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi deleted file mode 100644 index 65aea7a75..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -/* - * sama5d3xmb_gmac.dtsi - Device Tree Include file for SAMA5D3x motherboard - * Gigabit Ethernet - * - * Copyright (C) 2016 Atmel, - * - * Licensed under GPLv2 or later. - */ - -/ { - ahb { - apb { - macb0: ethernet@f0028000 { - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - - ethernet-phy@1 { - reg = <0x1>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - - ethernet-phy@7 { - reg = <0x7>; - interrupt-parent = <&pioB>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sama5d4.dtsi b/software/linux/kernel/arch/arm/boot/dts/sama5d4.dtsi deleted file mode 100644 index 65e725fb5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sama5d4.dtsi +++ /dev/null @@ -1,1899 +0,0 @@ -/* - * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC - * - * Copyright (C) 2014 Atmel, - * 2014 Nicolas Ferre - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Atmel SAMA5D4 family SoC"; - compatible = "atmel,sama5d4"; - interrupt-parent = <&aic>; - - aliases { - serial0 = &usart3; - serial1 = &usart4; - serial2 = &usart2; - serial3 = &usart0; - serial4 = &usart1; - serial5 = &uart0; - serial6 = &uart1; - gpio0 = &pioA; - gpio1 = &pioB; - gpio2 = &pioC; - gpio3 = &pioD; - gpio4 = &pioE; - pwm0 = &pwm0; - ssc0 = &ssc0; - ssc1 = &ssc1; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - }; - - memory { - reg = <0x20000000 0x20000000>; - }; - - clocks { - slow_xtal: slow_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - main_xtal: main_xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - adc_op_clk: adc_op_clk{ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - }; - - ns_sram: sram@00210000 { - compatible = "mmio-sram"; - reg = <0x00210000 0x10000>; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usb0: gadget@00400000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,sama5d3-udc"; - reg = <0x00400000 0x100000 - 0xfc02c000 0x4000>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; - clock-names = "pclk", "hclk"; - status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - }; - - usb1: ohci@00500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - status = "disabled"; - }; - - usb2: ehci@00600000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00600000 0x100000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; - clock-names = "usb_clk", "ehci_clk"; - status = "disabled"; - }; - - L2: cache-controller@00a00000 { - compatible = "arm,pl310-cache"; - reg = <0x00a00000 0x1000>; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; - cache-unified; - cache-level = <2>; - }; - - nand0: nand@80000000 { - compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = < 0x80000000 0x08000000 /* EBI CS3 */ - 0xfc05c070 0x00000490 /* SMC PMECC regs */ - 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ - >; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; - atmel,nand-addr-offset = <21>; - atmel,nand-cmd-offset = <22>; - atmel,nand-has-dma; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - status = "disabled"; - - nfc@90000000 { - compatible = "atmel,sama5d3-nfc"; - #address-cells = <1>; - #size-cells = <1>; - reg = < - 0x90000000 0x08000000 /* NFC Command Registers */ - 0xfc05c000 0x00000070 /* NFC HSMC regs */ - 0x00100000 0x00100000 /* NFC SRAM banks */ - >; - clocks = <&hsmc_clk>; - atmel,write-by-sram; - }; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - hlcdc: hlcdc@f0000000 { - compatible = "atmel,sama5d4-hlcdc"; - reg = <0xf0000000 0x4000>; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - - dma1: dma-controller@f0004000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0004000 0x200>; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&dma1_clk>; - clock-names = "dma_clk"; - }; - - isi: isi@f0008000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf0008000 0x4000>; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; - clock-names = "isi_clk"; - status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ramc0: ramc@f0010000 { - compatible = "atmel,sama5d3-ddramc"; - reg = <0xf0010000 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; - clock-names = "ddrck", "mpddr"; - }; - - dma0: dma-controller@f0014000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0014000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; - #dma-cells = <1>; - clocks = <&dma0_clk>; - clock-names = "dma_clk"; - }; - - pmc: pmc@f0018000 { - compatible = "atmel,sama5d3-pmc", "syscon"; - reg = <0xf0018000 0x120>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clock-frequency = <12000000>; - clock-accuracy = <100000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <12000000 12000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <125000000 200000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - h32ck: h32mxck { - #clock-cells = <0>; - compatible = "atmel,sama5d4-clk-h32mx"; - clocks = <&mck>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - }; - - periph32ck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&h32ck>; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - icm_clk: icm_clk { - #clock-cells = <0>; - reg = <9>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <12>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <14>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <15>; - }; - - matrix1_clk: matrix1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <22>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <23>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <24>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <25>; - }; - - pioE_clk: pioE_clk { - #clock-cells = <0>; - reg = <26>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <27>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <28>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <29>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <30>; - }; - - usart4_clk: usart4_clk { - #clock-cells = <0>; - reg = <31>; - }; - - twi0_clk: twi0_clk { - reg = <32>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <33>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <34>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <35>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <36>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <37>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <38>; - }; - - spi2_clk: spi2_clk { - #clock-cells = <0>; - reg = <39>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <40>; - }; - - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <41>; - }; - - tcb2_clk: tcb2_clk { - #clock-cells = <0>; - reg = <42>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <43>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <44>; - }; - - dbgu_clk: dbgu_clk { - #clock-cells = <0>; - reg = <45>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <46>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <47>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <48>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <49>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <53>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <54>; - }; - - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <55>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <57>; - }; - - securam_clk: securam_clk { - #clock-cells = <0>; - reg = <59>; - }; - - smd_clk: smd_clk { - #clock-cells = <0>; - reg = <61>; - }; - - twi3_clk: twi3_clk { - #clock-cells = <0>; - reg = <62>; - }; - - catb_clk: catb_clk { - #clock-cells = <0>; - reg = <63>; - }; - }; - - periph64ck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <8>; - }; - - cpkcc_clk: cpkcc_clk { - #clock-cells = <0>; - reg = <10>; - }; - - aesb_clk: aesb_clk { - #clock-cells = <0>; - reg = <13>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <16>; - }; - - matrix0_clk: matrix0_clk { - #clock-cells = <0>; - reg = <18>; - }; - - vdec_clk: vdec_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <50>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <51>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <52>; - }; - }; - }; - - mmc0: mmc@f8000000 { - compatible = "atmel,hsmci"; - reg = <0xf8000000 0x600>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(0))>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci0_clk>; - clock-names = "mci_clk"; - }; - - uart0: serial@f8004000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8004000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(22))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(23))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc0: ssc@f8008000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf8008000 0x4000>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(26))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(27))>; - dma-names = "tx", "rx"; - clocks = <&ssc0_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - pwm0: pwm@f800c000 { - compatible = "atmel,sama5d3-pwm"; - reg = <0xf800c000 0x300>; - interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; - #pwm-cells = <3>; - clocks = <&pwm_clk>; - status = "disabled"; - }; - - spi0: spi@f8010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xf8010000 0x100>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(10))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(11))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - i2c0: i2c@f8014000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8014000 0x4000>; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(2))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(3))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - status = "disabled"; - }; - - i2c1: i2c@f8018000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8018000 0x4000>; - interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(4))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(5))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi1_clk>; - status = "disabled"; - }; - - tcb0: timer@f801c000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf801c000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - macb0: ethernet@f8020000 { - compatible = "atmel,sama5d4-gem"; - reg = <0xf8020000 0x100>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&macb0_clk>, <&macb0_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - i2c2: i2c@f8024000 { - compatible = "atmel,sama5d4-i2c"; - reg = <0xf8024000 0x4000>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(6))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi2_clk>; - status = "disabled"; - }; - - sfr: sfr@f8028000 { - compatible = "atmel,sama5d4-sfr", "syscon"; - reg = <0xf8028000 0x60>; - }; - - usart0: serial@f802c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf802c000 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(36))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(37))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; - clocks = <&usart0_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart1: serial@f8030000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8030000 0x100>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(38))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(39))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; - clocks = <&usart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - mmc1: mmc@fc000000 { - compatible = "atmel,hsmci"; - reg = <0xfc000000 0x600>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(1))>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mci1_clk>; - clock-names = "mci_clk"; - }; - - uart1: serial@fc004000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc004000 0x100>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(24))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(25))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart2: serial@fc008000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc008000 0x100>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(16))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(17))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; - clocks = <&usart2_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart3: serial@fc00c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc00c000 0x100>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(18))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(19))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - usart4: serial@fc010000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfc010000 0x100>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(20))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(21))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart4>; - clocks = <&usart4_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - ssc1: ssc@fc014000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xfc014000 0x4000>; - interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(28))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(29))>; - dma-names = "tx", "rx"; - clocks = <&ssc1_clk>; - clock-names = "pclk"; - status = "disabled"; - }; - - spi1: spi@fc018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc018000 0x100>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(12))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(13))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - spi2: spi@fc01c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-spi"; - reg = <0xfc01c000 0x100>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(14))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(15))>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - clocks = <&spi2_clk>; - clock-names = "spi_clk"; - status = "disabled"; - }; - - tcb1: timer@fc020000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xfc020000 0x100>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - macb1: ethernet@fc028000 { - compatible = "atmel,sama5d4-gem"; - reg = <0xfc028000 0x100>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&macb1_clk>, <&macb1_clk>; - clock-names = "hclk", "pclk"; - status = "disabled"; - }; - - trng@fc030000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfc030000 0x100>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; - }; - - adc0: adc@fc034000 { - compatible = "atmel,at91sam9x5-adc"; - reg = <0xfc034000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&adc_clk>, - <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0x01f>; - atmel,adc-startup-time = <40>; - atmel,adc-use-external-triggers; - atmel,adc-vref = <3000>; - atmel,adc-res = <8 10>; - atmel,adc-sample-hold-time = <11>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-ts-pressure-threshold = <10000>; - status = "disabled"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; - }; - - aes@fc044000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xfc044000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(41))>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(40))>; - dma-names = "tx", "rx"; - clocks = <&aes_clk>; - clock-names = "aes_clk"; - status = "okay"; - }; - - tdes@fc04c000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xfc04c000 0x100>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(42))>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(43))>; - dma-names = "tx", "rx"; - clocks = <&tdes_clk>; - clock-names = "tdes_clk"; - status = "okay"; - }; - - sha@fc050000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xfc050000 0x100>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(44))>; - dma-names = "tx"; - clocks = <&sha_clk>; - clock-names = "sha_clk"; - status = "okay"; - }; - - rstc@fc068600 { - compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; - reg = <0xfc068600 0x10>; - clocks = <&clk32k>; - }; - - shdwc@fc068610 { - compatible = "atmel,at91sam9x5-shdwc"; - reg = <0xfc068610 0x10>; - clocks = <&clk32k>; - }; - - pit: timer@fc068630 { - compatible = "atmel,at91sam9260-pit"; - reg = <0xfc068630 0x10>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&h32ck>; - }; - - watchdog@fc068640 { - compatible = "atmel,sama5d4-wdt"; - reg = <0xfc068640 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - status = "disabled"; - }; - - sckc@fc068650 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfc068650 0x4>; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <250000000>; - atmel,startup-time-usec = <75>; - }; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - atmel,startup-time-usec = <1200000>; - }; - - clk32k: slowck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; - }; - - rtc@fc0686b0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfc0686b0 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - }; - - dbgu: serial@fc069000 { - compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0xfc069000 0x200>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&dbgu_clk>; - clock-names = "usart"; - status = "disabled"; - }; - - - pinctrl@fc06a000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfc068000 0xfc068000 0x100 - 0xfc06a000 0xfc06a000 0x4000>; - /* WARNING: revisit as pin spec has changed */ - atmel,mux-mask = < - /* A B C */ - 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ - 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ - 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ - 0x0003ff00 0x8002a800 0x00000000 /* pioD */ - 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ - >; - - pioA: gpio@fc06a000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06a000 0x100>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fc06b000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06b000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fc06c000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06c000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; - - pioD: gpio@fc068000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc068000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - }; - - pioE: gpio@fc06d000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06d000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioE_clk>; - }; - - /* pinctrl pin settings */ - adc0 { - pinctrl_adc0_adtrg: adc0_adtrg { - atmel,pins = - ; /* conflicts with USBA_VBUS */ - }; - pinctrl_adc0_ad0: adc0_ad0 { - atmel,pins = - ; - }; - pinctrl_adc0_ad1: adc0_ad1 { - atmel,pins = - ; - }; - pinctrl_adc0_ad2: adc0_ad2 { - atmel,pins = - ; - }; - pinctrl_adc0_ad3: adc0_ad3 { - atmel,pins = - ; - }; - pinctrl_adc0_ad4: adc0_ad4 { - atmel,pins = - ; - }; - }; - - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - , /* conflicts with D14 and TDI */ - ; /* conflicts with D15 and TDO */ - }; - }; - - i2c0 { - pinctrl_i2c0: i2c0-0 { - atmel,pins = - ; - }; - }; - - i2c1 { - pinctrl_i2c1: i2c1-0 { - atmel,pins = - ; /* TWCK1, conflicts with UART0 TX and DIBN */ - }; - }; - - i2c2 { - pinctrl_i2c2: i2c2-0 { - atmel,pins = - ; /* TWCK2, conflicts with RF0 */ - }; - }; - - isi { - pinctrl_isi_data_0_7: isi-0-data-0-7 { - atmel,pins = - ; /* ISI_HSYNC */ - }; - pinctrl_isi_data_8_9: isi-0-data-8-9 { - atmel,pins = - ; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ - }; - pinctrl_isi_data_10_11: isi-0-data-10-11 { - atmel,pins = - ; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ - }; - }; - - lcd { - pinctrl_lcd_base: lcd-base-0 { - atmel,pins = - ; /* LCDPCK */ - }; - pinctrl_lcd_pwm: lcd-pwm-0 { - atmel,pins = ; /* LCDPWM */ - }; - pinctrl_lcd_rgb444: lcd-rgb-0 { - atmel,pins = - ; /* LCDD11 pin */ - }; - pinctrl_lcd_rgb565: lcd-rgb-1 { - atmel,pins = - ; /* LCDD15 pin */ - }; - pinctrl_lcd_rgb666: lcd-rgb-2 { - atmel,pins = - ; /* LCDD23 pin */ - }; - pinctrl_lcd_rgb777: lcd-rgb-3 { - atmel,pins = - /* LCDDAT0 conflicts with TMS */ - ; /* LCDD23 pin */ - }; - pinctrl_lcd_rgb888: lcd-rgb-4 { - atmel,pins = - ; /* LCDD23 pin */ - }; - }; - - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - ; - }; - }; - - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - ; - }; - }; - - mmc0 { - pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { - atmel,pins = - ; - }; - pinctrl_mmc0_dat1_3: mmc0_dat1_3 { - atmel,pins = - ; - }; - pinctrl_mmc0_dat4_7: mmc0_dat4_7 { - atmel,pins = - ; - }; - }; - - mmc1 { - pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { - atmel,pins = - ; - }; - pinctrl_mmc1_dat1_3: mmc1_dat1_3 { - atmel,pins = - ; - }; - }; - - nand0 { - pinctrl_nand: nand-0 { - atmel,pins = - ; /* PC12 periph A Data bit 7 */ - }; - }; - - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - ; - }; - }; - - ssc0 { - pinctrl_ssc0_tx: ssc0_tx { - atmel,pins = - ; /* TD0 */ - }; - - pinctrl_ssc0_rx: ssc0_rx { - atmel,pins = - ; /* RD0 */ - }; - }; - - ssc1 { - pinctrl_ssc1_tx: ssc1_tx { - atmel,pins = - ; /* TD1 */ - }; - - pinctrl_ssc1_rx: ssc1_rx { - atmel,pins = - ; /* RD1 */ - }; - }; - - spi1 { - pinctrl_spi1: spi1-0 { - atmel,pins = - ; - }; - }; - - spi2 { - pinctrl_spi2: spi2-0 { - atmel,pins = - ; - }; - }; - - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - ; - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - ; - }; - }; - - usart0 { - pinctrl_usart0: usart0-0 { - atmel,pins = - ; - }; - pinctrl_usart0_rts: usart0_rts-0 { - atmel,pins = ; - }; - pinctrl_usart0_cts: usart0_cts-0 { - atmel,pins = ; - }; - }; - - usart1 { - pinctrl_usart1: usart1-0 { - atmel,pins = - ; - }; - pinctrl_usart1_rts: usart1_rts-0 { - atmel,pins = ; - }; - pinctrl_usart1_cts: usart1_cts-0 { - atmel,pins = ; - }; - }; - - usart2 { - pinctrl_usart2: usart2-0 { - atmel,pins = - ; - }; - pinctrl_usart2_rts: usart2_rts-0 { - atmel,pins = ; /* conflicts with G0_RX3, PWMH1 */ - }; - pinctrl_usart2_cts: usart2_cts-0 { - atmel,pins = ; /* conflicts with G0_TXER, ISI_VSYNC */ - }; - }; - - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - ; - }; - }; - - usart4 { - pinctrl_usart4: usart4-0 { - atmel,pins = - ; - }; - pinctrl_usart4_rts: usart4_rts-0 { - atmel,pins = ; /* conflicts with NWAIT, A19 */ - }; - pinctrl_usart4_cts: usart4_cts-0 { - atmel,pins = ; /* conflicts with A0/NBS0, MCI0_CDB */ - }; - }; - }; - - aic: interrupt-controller@fc06e000 { - #interrupt-cells = <3>; - compatible = "atmel,sama5d4-aic"; - interrupt-controller; - reg = <0xfc06e000 0x200>; - atmel,external-irqs = <56>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/software/linux/kernel/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi deleted file mode 100644 index 9657a5cbc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Timings and Geometry for Samsung K3PE0E000B memory part - */ - -/ { - samsung_K3PE0E000B: lpddr2 { - compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4"; - density = <4096>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <533333333>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - - timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <266666666>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - tDQSCK-max-derated = <6000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sh73a0-kzm9g.dts b/software/linux/kernel/arch/arm/boot/dts/sh73a0-kzm9g.dts deleted file mode 100644 index 3d65f1f6d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Device Tree Source for the KZM-A9-GT board - * - * Copyright (C) 2012 Horms Solutions Ltd. - * - * Based on sh73a0-kzm9g.dts - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "sh73a0.dtsi" -#include -#include -#include - -/ { - model = "KZM-A9-GT"; - compatible = "renesas,kzm9g", "renesas,sh73a0"; - - aliases { - serial0 = &scifa4; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1196000 1315000 - 598000 1175000 - 398667 1065000 - >; - voltage-tolerance = <1>; /* 1% */ - }; - }; - - chosen { - bootargs = "root=/dev/nfs ip=dhcp ignore_loglevel rw"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc_sdhi0: regulator-vmmc-sdhi0 { - compatible = "regulator-fixed"; - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vmmc_sdhi2: regulator-vmmc-sdhi2 { - compatible = "regulator-fixed"; - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - label = "LED1"; - }; - led2 { - gpios = <&pfc 21 GPIO_ACTIVE_LOW>; - label = "LED2"; - }; - led3 { - gpios = <&pfc 22 GPIO_ACTIVE_LOW>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 23 GPIO_ACTIVE_LOW>; - label = "LED4"; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - back-key { - gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - }; - - right-key { - gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-R"; - }; - - left-key { - gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-L"; - }; - - enter-key { - gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-P"; - }; - - up-key { - gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-U"; - }; - - down-key { - gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-D"; - }; - - home-key { - gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW1"; - wakeup-source; - }; - - wakeup-key { - gpios = <&pfc 159 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "NMI"; - wakeup-source; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "left_j"; - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - }; - simple-audio-card,codec { - sound-dai = <&ak4648>; - bitclock-master; - frame-master; - system-clock-frequency = <11289600>; - }; - }; -}; - -&bsc { - ethernet@10000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x10000000 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg-io-width = <4>; - smsc,irq-push-pull; - smsc,save-mac-address; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; -}; - -&cmt1 { - status = "okay"; -}; - -&extal2_clk { - clock-frequency = <48000000>; -}; - -&i2c0 { - status = "okay"; - - compass@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - interrupt-parent = <&irqpin3>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; - - ak4648: codec@12 { - compatible = "asahi-kasei,ak4648"; - reg = <0x12>; - #sound-dai-cells = <0>; - }; - - accelerometer@1d { - compatible = "adi,adxl345"; - reg = <0x1d>; - interrupt-parent = <&irqpin3>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - rtc@32 { - compatible = "ricoh,r2025sd"; - reg = <0x32>; - }; - - as3711@40 { - compatible = "ams,as3711"; - reg = <0x40>; - - regulators { - vdd_dvfs: sd1 { - regulator-name = "1.315V CPU"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - sd2 { - regulator-name = "1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - sd4 { - regulator-name = "1.215V"; - regulator-min-microvolt = <1215000>; - regulator-max-microvolt = <1235000>; - regulator-always-on; - regulator-boot-on; - }; - ldo2 { - regulator-name = "2.8V CPU"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo3 { - regulator-name = "3.0V CPU"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - ldo4 { - regulator-name = "2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo5 { - regulator-name = "2.8V #2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo7 { - regulator-name = "1.15V CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - ldo8 { - regulator-name = "1.15V CPU #2"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupt-parent = <&irqpin1>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - status = "okay"; - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - status = "okay"; -}; - -&pfc { - i2c3_pins: i2c3 { - groups = "i2c3_1"; - function = "i2c3"; - }; - - mmcif_pins: mmc { - mux { - groups = "mmc0_data8_0", "mmc0_ctrl_0"; - function = "mmc0"; - }; - cfg { - groups = "mmc0_data8_0"; - pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: scifa4 { - groups = "scifa4_data", "scifa4_ctrl"; - function = "scifa4"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; - function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - }; - - fsia_pins: sounda { - groups = "fsia_mclk_in", "fsia_sclk_in", - "fsia_data_in", "fsia_data_out"; - function = "fsia"; - }; -}; - -&scifa4 { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi0>; - bus-width = <4>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi2>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sh73a0.dtsi b/software/linux/kernel/arch/arm/boot/dts/sh73a0.dtsi deleted file mode 100644 index 032fe2f14..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sh73a0.dtsi +++ /dev/null @@ -1,938 +0,0 @@ -/* - * Device Tree Source for the SH73A0 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -#include -#include -#include - -/ { - compatible = "renesas,sh73a0"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - clock-frequency = <1196000000>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - clock-frequency = <1196000000>; - power-domains = <&pd_a2sl>; - next-level-cache = <&L2>; - }; - }; - - timer@f0000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf0000600 0x20>; - interrupts = ; - clocks = <&twd_clk>; - }; - - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; - - L2: cache-controller@f0100000 { - compatible = "arm,pl310-cache"; - reg = <0xf0100000 0x1000>; - interrupts = ; - power-domains = <&pd_a3sm>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - arm,shared-override; - cache-unified; - cache-level = <2>; - }; - - sbsc2: memory-controller@fb400000 { - compatible = "renesas,sbsc-sh73a0"; - reg = <0xfb400000 0x400>; - interrupts = , - ; - interrupt-names = "sec", "temp"; - power-domains = <&pd_a4bc1>; - }; - - sbsc1: memory-controller@fe400000 { - compatible = "renesas,sbsc-sh73a0"; - reg = <0xfe400000 0x400>; - interrupts = , - ; - interrupt-names = "sec", "temp"; - power-domains = <&pd_a4bc0>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - }; - - cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; - reg = <0xe6138000 0x200>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_CMT1>; - clock-names = "fck"; - power-domains = <&pd_c5>; - - renesas,channels-mask = <0x3f>; - - status = "disabled"; - }; - - irqpin0: interrupt-controller@e6900000 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900000 4>, - <0xe6900010 4>, - <0xe6900020 1>, - <0xe6900040 1>, - <0xe6900060 1>; - interrupts = ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin2: interrupt-controller@e6900008 { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900008 4>, - <0xe6900018 4>, - <0xe6900028 1>, - <0xe6900048 1>, - <0xe6900068 1>; - interrupts = ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - irqpin3: interrupt-controller@e690000c { - compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe690000c 4>, - <0xe690001c 4>, - <0xe690002c 1>, - <0xe690004c 1>, - <0xe690006c 1>; - interrupts = ; - clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; - power-domains = <&pd_a4s>; - control-parent; - }; - - i2c0: i2c@e6820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6820000 0x425>; - interrupts = ; - clocks = <&mstp1_clks SH73A0_CLK_IIC0>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c1: i2c@e6822000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6822000 0x425>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_IIC1>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c2: i2c@e6824000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6824000 0x425>; - interrupts = ; - clocks = <&mstp0_clks SH73A0_CLK_IIC2>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c3: i2c@e6826000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6826000 0x425>; - interrupts = ; - clocks = <&mstp4_clks SH73A0_CLK_IIC3>; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - i2c4: i2c@e6828000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; - reg = <0xe6828000 0x425>; - interrupts = ; - clocks = <&mstp4_clks SH73A0_CLK_IIC4>; - power-domains = <&pd_c5>; - status = "disabled"; - }; - - mmcif: mmc@e6bd0000 { - compatible = "renesas,sh-mmcif"; - reg = <0xe6bd0000 0x100>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; - power-domains = <&pd_a3sp>; - reg-io-width = <4>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e20000 0x0064>; - interrupts = ; - clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e10000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6e00000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; - reg = <0xe6c90000 0x0064>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>; - power-domains = <&pd_a3sp>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee100000 0x100>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; - power-domains = <&pd_a3sp>; - cap-sd-highspeed; - status = "disabled"; - }; - - /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee120000 0x100>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; - power-domains = <&pd_a3sp>; - toshiba,mmc-wrprotect-disable; - cap-sd-highspeed; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-sh73a0"; - reg = <0xee140000 0x100>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; - power-domains = <&pd_a3sp>; - toshiba,mmc-wrprotect-disable; - cap-sd-highspeed; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c40000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c50000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c60000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c70000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa4: serial@e6c80000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c80000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa5: serial@e6cb0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cb0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa6: serial@e6cc0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cc0000 0x100>; - interrupts = ; - clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifa7: serial@e6cd0000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6cd0000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - scifb: serial@e6c30000 { - compatible = "renesas,scifb-sh73a0", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - status = "disabled"; - }; - - pfc: pfc@e6050000 { - compatible = "renesas,pfc-sh73a0"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = - <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, - <&pfc 288 288 22>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - power-domains = <&pd_c5>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; - reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_c4: c4@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_d4: d4@1 { - reg = <1>; - #power-domain-cells = <0>; - }; - - pd_a4bc0: a4bc0@4 { - reg = <4>; - #power-domain-cells = <0>; - }; - - pd_a4bc1: a4bc1@5 { - reg = <5>; - #power-domain-cells = <0>; - }; - - pd_a4lc0: a4lc0@6 { - reg = <6>; - #power-domain-cells = <0>; - }; - - pd_a4lc1: a4lc1@7 { - reg = <7>; - #power-domain-cells = <0>; - }; - - pd_a4mp: a4mp@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3mp: a3mp@9 { - reg = <9>; - #power-domain-cells = <0>; - }; - - pd_a3vc: a3vc@10 { - reg = <10>; - #power-domain-cells = <0>; - }; - }; - - pd_a4rm: a4rm@12 { - reg = <12>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3r: a3r@13 { - reg = <13>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2rv: a2rv@14 { - reg = <14>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - }; - }; - }; - - pd_a4s: a4s@16 { - reg = <16>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sp: a3sp@17 { - reg = <17>; - #power-domain-cells = <0>; - }; - - pd_a3sg: a3sg@18 { - reg = <18>; - #power-domain-cells = <0>; - }; - - pd_a3sm: a3sm@19 { - reg = <19>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a2sl: a2sl@20 { - reg = <20>; - #power-domain-cells = <0>; - }; - }; - }; - }; - }; - }; - - sh_fsi2: sound@ec230000 { - #sound-dai-cells = <1>; - compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; - reg = <0xec230000 0x400>; - interrupts = ; - power-domains = <&pd_a4mp>; - status = "disabled"; - }; - - bsc: bus@fec10000 { - compatible = "renesas,bsc-sh73a0", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20000000>; - reg = <0xfec10000 0x400>; - interrupts = ; - clocks = <&zb_clk>; - power-domains = <&pd_a4s>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* External root clocks */ - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - extal1_clk: extal1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - extal2_clk: extal2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - extcki_clk: extcki { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - fsiack_clk: fsiack { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - fsibck_clk: fsibck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,sh73a0-cpg-clocks"; - reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll3", "dsi0phy", "dsi1phy", - "zg", "m3", "b", "m1", "m2", - "z", "zx", "hp"; - }; - - /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1@e6150008 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150008 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - vclk2_clk: vclk2@e615000c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615000c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - vclk3_clk: vclk3@e615001c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615001c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, - <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, - <0>; - #clock-cells = <0>; - }; - zb_clk: zb_clk@e6150010 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150010 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - clock-output-names = "zb"; - }; - flctl_clk: flctlck@e6150014 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150014 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - sdhi0_clk: sdhi0ck@e6150074 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150074 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - sdhi1_clk: sdhi1ck@e6150078 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150078 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - sdhi2_clk: sdhi2ck@e615007c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615007c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div13_clk>, <0>; - #clock-cells = <0>; - }; - fsia_clk: fsia@e6150018 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150018 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&fsiack_clk>, <&fsiack_clk>; - #clock-cells = <0>; - }; - fsib_clk: fsib@e6150090 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150090 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&fsibck_clk>, <&fsibck_clk>; - #clock-cells = <0>; - }; - sub_clk: sub@e6150080 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150080 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - spua_clk: spua@e6150084 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150084 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - spuv_clk: spuv@e6150094 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150094 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&extal2_clk>, <&extal2_clk>; - #clock-cells = <0>; - }; - msu_clk: msu@e6150088 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150088 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - hsi_clk: hsi@e615008c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615008c 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&pll1_div7_clk>, <0>; - #clock-cells = <0>; - }; - mfg1_clk: mfg1@e6150098 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150098 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - mfg2_clk: mfg2@e615009c { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe615009c 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - dsit_clk: dsit@e6150060 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150060 4>; - clocks = <&pll1_div2_clk>, <0>, - <&cpg_clocks SH73A0_CLK_PLL2>, <0>; - #clock-cells = <0>; - }; - dsi0p_clk: dsi0pck@e6150064 { - compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; - reg = <0xe6150064 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, - <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, - <&extcki_clk>, <0>, <0>, <0>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - main_div2_clk: main_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_MAIN>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - pll1_div7_clk: pll1_div7 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <7>; - clock-mult = <1>; - }; - pll1_div13_clk: pll1_div13 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <13>; - clock-mult = <1>; - }; - twd_clk: twd { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks SH73A0_CLK_Z>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150130 4>, <0xe6150030 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0 - >; - clock-output-names = - "iic2", "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150134 4>, <0xe6150038 4>; - clocks = <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_B>, - <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, - <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_ZG>, - <&cpg_clocks SH73A0_CLK_B>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 - SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 - SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 - SH73A0_CLK_IIC0 SH73A0_CLK_SGX - SH73A0_CLK_LCDC0 - >; - clock-output-names = - "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", - "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150138 4>, <0xe6150040 4>; - clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>, - <&sub_clk>, <&sub_clk>, <&sub_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC - SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3 - SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5 - SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2 - SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1 - SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3 - SH73A0_CLK_SCIFA4 - >; - clock-output-names = - "scifa7", "sy_dmac", "mp_dmac", "msiof3", - "msiof1", "scifa5", "scifb", "msiof2", - "scifa0", "scifa1", "scifa2", "scifa3", - "scifa4"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe615013c 4>, <0xe6150048 4>; - clocks = <&sub_clk>, <&extalr_clk>, - <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, - <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, - <&sdhi0_clk>, <&sdhi1_clk>, - <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, - <&main_div2_clk>, <&main_div2_clk>, - <&main_div2_clk>, <&main_div2_clk>, - <&main_div2_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 - SH73A0_CLK_FSI SH73A0_CLK_IRDA - SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL - SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 - SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 - SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 - SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 - SH73A0_CLK_TPU4 - >; - clock-output-names = - "scifa6", "cmt1", "fsi", "irda", "iic1", - "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", - "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150140 4>, <0xe615004c 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>, - <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 - SH73A0_CLK_KEYSC - >; - clock-output-names = - "iic3", "iic4", "keysc"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0xe6150144 4>, <0xe615003c 4>; - clocks = <&cpg_clocks SH73A0_CLK_HP>; - #clock-cells = <1>; - clock-indices = < - SH73A0_CLK_INTCA0 - >; - clock-output-names = - "intca0"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/skeleton64.dtsi b/software/linux/kernel/arch/arm/boot/dts/skeleton64.dtsi deleted file mode 100644 index b5d7f36f3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/skeleton64.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Skeleton device tree in the 64 bits version; the bare minimum - * needed to boot; just include and add a compatible value. The - * bootloader will typically populate the memory node. - */ - -/ { - #address-cells = <2>; - #size-cells = <2>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0 0 0>; }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga.dtsi b/software/linux/kernel/arch/arm/boot/dts/socfpga.dtsi deleted file mode 100644 index 9f4814127..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga.dtsi +++ /dev/null @@ -1,870 +0,0 @@ -/* - * Copyright (C) 2012 Altera - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "skeleton.dtsi" -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - serial0 = &uart0; - serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "altr,socfpga-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - intc: intc@fffed000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffed000 0x1000>, - <0xfffec100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@ffe01000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffe01000 0x1000>; - interrupts = <0 104 4>, - <0 105 4>, - <0 106 4>, - <0 107 4>, - <0 108 4>, - <0 109 4>, - <0 110 4>, - <0 111 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&l4_main_clk>; - clock-names = "apb_pclk"; - }; - }; - - can0: can@ffc00000 { - compatible = "bosch,d_can"; - reg = <0xffc00000 0x1000>; - interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; - clocks = <&can0_clk>; - status = "disabled"; - }; - - can1: can@ffc01000 { - compatible = "bosch,d_can"; - reg = <0xffc01000 0x1000>; - interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; - clocks = <&can1_clk>; - status = "disabled"; - }; - - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc2: osc2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_periph_ref_clk: f2s_periph_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_sdram_ref_clk: f2s_sdram_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - main_pll: main_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>; - reg = <0x40>; - - mpuclk: mpuclk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe0 0 9>; - reg = <0x48>; - }; - - mainclk: mainclk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe4 0 9>; - reg = <0x4C>; - }; - - dbg_base_clk: dbg_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>, <&osc1>; - div-reg = <0xe8 0 9>; - reg = <0x50>; - }; - - main_qspi_clk: main_qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x54>; - }; - - main_nand_sdmmc_clk: main_nand_sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x58>; - }; - - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x5C>; - }; - }; - - periph_pll: periph_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; - reg = <0x80>; - - emac0_clk: emac0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x88>; - }; - - emac1_clk: emac1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x8C>; - }; - - per_qspi_clk: per_qsi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x90>; - }; - - per_nand_mmc_clk: per_nand_mmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x94>; - }; - - per_base_clk: per_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x98>; - }; - - h2f_usr1_clk: h2f_usr1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x9C>; - }; - }; - - sdram_pll: sdram_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; - reg = <0xC0>; - - ddr_dqs_clk: ddr_dqs_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xC8>; - }; - - ddr_2x_dqs_clk: ddr_2x_dqs_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xCC>; - }; - - ddr_dq_clk: ddr_dq_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xD0>; - }; - - h2f_usr2_clk: h2f_usr2_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xD4>; - }; - }; - - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <4>; - }; - - mpu_l2_ram_clk: mpu_l2_ram_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <2>; - }; - - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - clk-gate = <0x60 0>; - }; - - l3_main_clk: l3_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mainclk>; - fixed-divider = <1>; - }; - - l3_mp_clk: l3_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 0 2>; - clk-gate = <0x60 1>; - }; - - l3_sp_clk: l3_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&l3_mp_clk>; - div-reg = <0x64 2 2>; - }; - - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 4 3>; - clk-gate = <0x60 2>; - }; - - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 7 3>; - clk-gate = <0x60 3>; - }; - - dbg_at_clk: dbg_at_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 0 2>; - clk-gate = <0x60 4>; - }; - - dbg_clk: dbg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_at_clk>; - div-reg = <0x68 2 2>; - clk-gate = <0x60 5>; - }; - - dbg_trace_clk: dbg_trace_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x6C 0 3>; - clk-gate = <0x60 6>; - }; - - dbg_timer_clk: dbg_timer_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - clk-gate = <0x60 7>; - }; - - cfg_clk: cfg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 8>; - }; - - h2f_user0_clk: h2f_user0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 9>; - }; - - emac_0_clk: emac_0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac0_clk>; - clk-gate = <0xa0 0>; - }; - - emac_1_clk: emac_1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac1_clk>; - clk-gate = <0xa0 1>; - }; - - usb_mp_clk: usb_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 2>; - div-reg = <0xa4 0 3>; - }; - - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 3>; - div-reg = <0xa4 3 3>; - }; - - can0_clk: can0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 4>; - div-reg = <0xa4 6 3>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 5>; - div-reg = <0xa4 9 3>; - }; - - gpio_db_clk: gpio_db_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 6>; - div-reg = <0xa8 0 24>; - }; - - h2f_user1_clk: h2f_user1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&h2f_usr1_clk>; - clk-gate = <0xa0 7>; - }; - - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 8>; - clk-phase = <0 135>; - }; - - sdmmc_clk_divided: sdmmc_clk_divided { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&sdmmc_clk>; - clk-gate = <0xa0 8>; - fixed-divider = <4>; - }; - - nand_x_clk: nand_x_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 9>; - }; - - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 10>; - fixed-divider = <4>; - }; - - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; - clk-gate = <0xa0 11>; - }; - - ddr_dqs_clk_gate: ddr_dqs_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_dqs_clk>; - clk-gate = <0xd8 0>; - }; - - ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_2x_dqs_clk>; - clk-gate = <0xd8 1>; - }; - - ddr_dq_clk_gate: ddr_dq_clk_gate { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&ddr_dq_clk>; - clk-gate = <0xd8 2>; - }; - - h2f_user2_clk: h2f_user2_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&h2f_usr2_clk>; - clk-gate = <0xd8 3>; - }; - - }; - }; - - fpgamgr0: fpgamgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xff706000 0x1000 - 0xffb90000 0x1000>; - interrupts = <0 175 4>; - }; - - gmac0: ethernet@ff700000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 0>; - reg = <0xff700000 0x2000>; - interrupts = <0 115 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac0_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <4096>; - status = "disabled"; - }; - - gmac1: ethernet@ff702000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 2>; - reg = <0xff702000 0x2000>; - interrupts = <0 120 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac1_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <4096>; - status = "disabled"; - }; - - gpio0: gpio@ff708000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff708000 0x1000>; - clocks = <&l4_mp_clk>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 164 4>; - }; - }; - - gpio1: gpio@ff709000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff709000 0x1000>; - clocks = <&l4_mp_clk>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 165 4>; - }; - }; - - gpio2: gpio@ff70a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff70a000 0x1000>; - clocks = <&l4_mp_clk>; - status = "disabled"; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <27>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 166 4>; - }; - }; - - i2c0: i2c@ffc04000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc04000 0x1000>; - clocks = <&l4_sp_clk>; - interrupts = <0 158 0x4>; - status = "disabled"; - }; - - i2c1: i2c@ffc05000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc05000 0x1000>; - clocks = <&l4_sp_clk>; - interrupts = <0 159 0x4>; - status = "disabled"; - }; - - i2c2: i2c@ffc06000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc06000 0x1000>; - clocks = <&l4_sp_clk>; - interrupts = <0 160 0x4>; - status = "disabled"; - }; - - i2c3: i2c@ffc07000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc07000 0x1000>; - clocks = <&l4_sp_clk>; - interrupts = <0 161 0x4>; - status = "disabled"; - }; - - eccmgr: eccmgr@ffd08140 { - compatible = "altr,socfpga-ecc-manager"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - l2-ecc@ffd08140 { - compatible = "altr,socfpga-l2-ecc"; - reg = <0xffd08140 0x4>; - interrupts = <0 36 1>, <0 37 1>; - }; - - ocram-ecc@ffd08144 { - compatible = "altr,socfpga-ocram-ecc"; - reg = <0xffd08144 0x4>; - iram = <&ocram>; - interrupts = <0 178 1>, <0 179 1>; - }; - }; - - L2: l2-cache@fffef000 { - compatible = "arm,pl310-cache"; - reg = <0xfffef000 0x1000>; - interrupts = <0 38 0x04>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <2 1 1>; - prefetch-data = <1>; - prefetch-instr = <1>; - }; - - mmc: dwmmc0@ff704000 { - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff704000 0x1000>; - interrupts = <0 139 4>; - fifo-depth = <0x400>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - ocram: sram@ffff0000 { - compatible = "mmio-sram"; - reg = <0xffff0000 0x10000>; - }; - - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - altr,modrst-offset = <0x10>; - }; - - scu: snoop-control-unit@fffec000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfffec000 0x100>; - }; - - sdr: sdr@ffc25000 { - compatible = "syscon"; - reg = <0xffc25000 0x1000>; - }; - - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; - }; - - spi0: spi@fff00000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff00000 0x1000>; - interrupts = <0 154 4>; - num-cs = <4>; - clocks = <&spi_m_clk>; - status = "disabled"; - }; - - spi1: spi@fff01000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff01000 0x1000>; - interrupts = <0 155 4>; - num-cs = <4>; - clocks = <&spi_m_clk>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd08000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd08000 0x4000>; - }; - - /* Local timer */ - timer@fffec600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfffec600 0x100>; - interrupts = <1 13 0xf04>; - clocks = <&mpu_periph_clk>; - }; - - timer0: timer0@ffc08000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 167 4>; - reg = <0xffc08000 0x1000>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - }; - - timer1: timer1@ffc09000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 168 4>; - reg = <0xffc09000 0x1000>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 169 4>; - reg = <0xffd00000 0x1000>; - clocks = <&osc1>; - clock-names = "timer"; - }; - - timer3: timer3@ffd01000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; - reg = <0xffd01000 0x1000>; - clocks = <&osc1>; - clock-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x1000>; - interrupts = <0 162 4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - dmas = <&pdma 28>, - <&pdma 29>; - dma-names = "tx", "rx"; - }; - - uart1: serial1@ffc03000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc03000 0x1000>; - interrupts = <0 163 4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - dmas = <&pdma 30>, - <&pdma 31>; - dma-names = "tx", "rx"; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0xffff>; - interrupts = <0 125 4>; - clocks = <&usb_mp_clk>; - clock-names = "otg"; - resets = <&rst USB0_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0xffff>; - interrupts = <0 128 4>; - clocks = <&usb_mp_clk>; - clock-names = "otg"; - resets = <&rst USB1_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - watchdog0: watchdog@ffd02000 { - compatible = "snps,dw-wdt"; - reg = <0xffd02000 0x1000>; - interrupts = <0 171 4>; - clocks = <&osc1>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd03000 { - compatible = "snps,dw-wdt"; - reg = <0xffd03000 0x1000>; - interrupts = <0 172 4>; - clocks = <&osc1>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10.dtsi b/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10.dtsi deleted file mode 100644 index f520cbff5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10.dtsi +++ /dev/null @@ -1,786 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "skeleton.dtsi" -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "altr,socfpga-a10-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - intc: intc@ffffd000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xffffd000 0x1000>, - <0xffffc100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@ffda1000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda1000 0x1000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, - <0 84 IRQ_TYPE_LEVEL_HIGH>, - <0 85 IRQ_TYPE_LEVEL_HIGH>, - <0 86 IRQ_TYPE_LEVEL_HIGH>, - <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>, - <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>, - <0 91 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&l4_main_clk>; - clock-names = "apb_pclk"; - }; - }; - - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb_intosc_ls_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s_free_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - main_pll: main_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-a10-pll-clock"; - clocks = <&osc1>, <&cb_intosc_ls_clk>, - <&f2s_free_clk>; - reg = <0x40>; - - main_mpu_base_clk: main_mpu_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - div-reg = <0x140 0 11>; - }; - - main_noc_base_clk: main_noc_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - div-reg = <0x144 0 11>; - }; - - main_emaca_clk: main_emaca_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x68>; - }; - - main_emacb_clk: main_emacb_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x6C>; - }; - - main_emac_ptp_clk: main_emac_ptp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x70>; - }; - - main_gpio_db_clk: main_gpio_db_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x74>; - }; - - main_sdmmc_clk: main_sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk" -; - clocks = <&main_pll>; - reg = <0x78>; - }; - - main_s2f_usr0_clk: main_s2f_usr0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x7C>; - }; - - main_s2f_usr1_clk: main_s2f_usr1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x80>; - }; - - main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x84>; - }; - - main_periph_ref_clk: main_periph_ref_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x9C>; - }; - }; - - periph_pll: periph_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-a10-pll-clock"; - clocks = <&osc1>, <&cb_intosc_ls_clk>, - <&f2s_free_clk>, <&main_periph_ref_clk>; - reg = <0xC0>; - - peri_mpu_base_clk: peri_mpu_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - div-reg = <0x140 16 11>; - }; - - peri_noc_base_clk: peri_noc_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - div-reg = <0x144 16 11>; - }; - - peri_emaca_clk: peri_emaca_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xE8>; - }; - - peri_emacb_clk: peri_emacb_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xEC>; - }; - - peri_emac_ptp_clk: peri_emac_ptp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF0>; - }; - - peri_gpio_db_clk: peri_gpio_db_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF4>; - }; - - peri_sdmmc_clk: peri_sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF8>; - }; - - peri_s2f_usr0_clk: peri_s2f_usr0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xFC>; - }; - - peri_s2f_usr1_clk: peri_s2f_usr1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0x100>; - }; - - peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0x104>; - }; - }; - - mpu_free_clk: mpu_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x60>; - }; - - noc_free_clk: noc_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x64>; - }; - - s2f_user1_free_clk: s2f_user1_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x104>; - }; - - sdmmc_free_clk: sdmmc_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - fixed-divider = <4>; - reg = <0xF8>; - }; - - l4_sys_free_clk: l4_sys_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&noc_free_clk>; - fixed-divider = <4>; - }; - - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 0 2>; - clk-gate = <0x48 1>; - }; - - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 8 2>; - clk-gate = <0x48 2>; - }; - - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 16 2>; - clk-gate = <0x48 3>; - }; - - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&mpu_free_clk>; - fixed-divider = <4>; - clk-gate = <0x48 0>; - }; - - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&sdmmc_free_clk>; - clk-gate = <0xC8 5>; - clk-phase = <0 135>; - }; - - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_main_clk>; - clk-gate = <0xC8 11>; - }; - - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_mp_clk>; - clk-gate = <0xC8 10>; - }; - - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_main_clk>; - clk-gate = <0xC8 9>; - }; - - usb_clk: usb_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_mp_clk>; - clk-gate = <0xC8 8>; - }; - - s2f_usr1_clk: s2f_usr1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&peri_s2f_usr1_clk>; - clk-gate = <0xC8 6>; - }; - }; - }; - - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - reg = <0xff800000 0x2000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x48 0>; - reg = <0xff802000 0x2000>; - interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x4C 0>; - reg = <0xff804000 0x2000>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - tx-fifo-depth = <4096>; - rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; - status = "disabled"; - }; - - gpio0: gpio@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02900 0x100>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02a00 0x100>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio2: gpio@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02b00 0x100>; - status = "disabled"; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <27>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - i2c0: i2c@ffc02200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02200 0x100>; - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - status = "disabled"; - }; - - i2c1: i2c@ffc02300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02300 0x100>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - status = "disabled"; - }; - - i2c2: i2c@ffc02400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02400 0x100>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - status = "disabled"; - }; - - i2c3: i2c@ffc02500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02500 0x100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - status = "disabled"; - }; - - i2c4: i2c@ffc02600 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02600 0x100>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sp_clk>; - status = "disabled"; - }; - - sdr: sdr@ffc25000 { - compatible = "syscon"; - reg = <0xffcfb100 0x80>; - }; - - L2: l2-cache@fffff000 { - compatible = "arm,pl310-cache"; - reg = <0xfffff000 0x1000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - fifo-depth = <0x400>; - clocks = <&l4_mp_clk>, <&sdmmc_clk>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x40000>; - }; - - eccmgr: eccmgr@ffd06000 { - compatible = "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-a10"; - altr,sdr-syscon = <&sdr>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, - <49 IRQ_TYPE_LEVEL_HIGH>; - }; - - l2-ecc@ffd06010 { - compatible = "altr,socfpga-a10-l2-ecc"; - reg = <0xffd06010 0x4>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, - <32 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram-ecc@ff8c3000 { - compatible = "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8c3000 0x400>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, - <33 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-rx-ecc@ff8c0800 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0800 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, - <36 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-tx-ecc@ff8c0c00 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0c00 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, - <37 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma-ecc@ff8c8000 { - compatible = "altr,socfpga-dma-ecc"; - reg = <0xff8c8000 0x400>; - altr,ecc-parent = <&pdma>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <42 IRQ_TYPE_LEVEL_HIGH>; - }; - - usb0-ecc@ff8c8800 { - compatible = "altr,socfpga-usb-ecc"; - reg = <0xff8c8800 0x400>; - altr,ecc-parent = <&usb0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <34 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x100>; - altr,modrst-offset = <0x20>; - }; - - scu: snoop-control-unit@ffffc000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xffffc000 0x100>; - }; - - sysmgr: sysmgr@ffd06000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd06000 0x300>; - cpu1-start-addr = <0xffd06230>; - }; - - /* Local timer */ - timer@ffffc600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xffffc600 0x100>; - interrupts = <1 13 0xf04>; - clocks = <&mpu_periph_clk>; - }; - - timer0: timer0@ffc02700 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffc02700 0x100>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - }; - - timer1: timer1@ffc02800 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffc02800 0x100>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd00000 0x100>; - clocks = <&l4_sys_free_clk>; - clock-names = "timer"; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd01000 0x100>; - clocks = <&l4_sys_free_clk>; - clock-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - status = "disabled"; - }; - - uart1: serial1@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - status = "disabled"; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0xffff>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk>; - clock-names = "otg"; - resets = <&rst USB0_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0xffff>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk>; - clock-names = "otg"; - resets = <&rst USB1_RESET>; - reset-names = "dwc2"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sys_free_clk>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_sys_free_clk>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi deleted file mode 100644 index 8e3a4adc3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2015 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include "socfpga_arria10.dtsi" - -/ { - model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - serial0 = &uart1; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - - /* - * These skews assume the user's FPGA design is adding 600ps of delay - * for TX_CLK on Arria 10. - * - * All skews are offset since hardware skew values for the ksz9031 - * range from a negative skew to a positive skew. - * See the micrel-ksz90x1.txt Documentation file for details. - */ - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - max-frame-size = <3800>; - status = "okay"; -}; - -&i2c1 { - speed-mode = <0>; - status = "okay"; - - /* - * adjust the falling times to decrease the i2c frequency to 50Khz - * because the LCD module does not work at the standard 100Khz - */ - i2c-sda-falling-time-ns = <6000>; - i2c-scl-falling-time-ns = <6000>; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts deleted file mode 100644 index 040a164ba..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2014-2015 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/dts-v1/; -#include "socfpga_arria10_socdk.dtsi" - -&mmc { - status = "okay"; - num-slots = <1>; - cap-sd-highspeed; - broken-cd; - bus-width = <4>; -}; - -&eccmgr { - sdmmca-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria5.dtsi b/software/linux/kernel/arch/arm/boot/dts/socfpga_arria5.dtsi deleted file mode 100644 index 1907cc600..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria5.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -/dts-v1/; -/* First 4KB has trampoline code for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; -#include "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - mmc0: dwmmc0@ff704000 { - num-slots = <1>; - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_arria5_socdk.dts deleted file mode 100644 index 3c8867862..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_arria5.dtsi" - -/ { - model = "Altera SOCFPGA Arria V SoC Development Kit"; - compatible = "altr,socfpga-arria5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5.dtsi deleted file mode 100644 index a05e3df23..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/dts-v1/; -/* First 4KB has trampoline code for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; -#include "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - mmc0: dwmmc0@ff704000 { - num-slots = <1>; - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts deleted file mode 100644 index afea3645a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic DE-0(Atlas)"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - ethernet0 = &gmac1; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 24 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - - max-frame-size = <3800>; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - speed-mode = <0>; - - adxl345: adxl345@0 { - compatible = "adi,adxl345"; - reg = <0x53>; - - interrupt-parent = <&portc>; - interrupts = <3 2>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi deleted file mode 100644 index f86f9c060..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "DENX MCV"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 GiB */ - }; -}; - -&mmc0 { /* On-SoM eMMC */ - bus-width = <8>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts deleted file mode 100644 index 7186a29b8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_cyclone5_mcv.dtsi" - -/ { - model = "DENX MCV EVK"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - stmpe-i2c0 = &stmpe1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&gmac0 { - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpio0 { /* GPIO 0 ... 28 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 29 ... 57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c0 { - status = "okay"; - speed-mode = <0>; - - stmpe1: stmpe811@41 { - compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - id = <0>; - blocks = <0x5>; - irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */ - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - reg = <0>; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <3>; - ts,settling = <4>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts deleted file mode 100644 index 15e43f43f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - cd-gpios = <&portb 18 0>; - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts deleted file mode 100644 index 02e22f554..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (C) 2013 Steffen Trumtrar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic SoCkit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - - hps_led0 { - label = "hps:blue:led0"; - gpios = <&portb 24 0>; /* HPS_GPIO53 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led1 { - label = "hps:blue:led1"; - gpios = <&portb 25 0>; /* HPS_GPIO54 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led2 { - label = "hps:blue:led2"; - gpios = <&portb 26 0>; /* HPS_GPIO55 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led3 { - label = "hps:blue:led3"; - gpios = <&portb 27 0>; /* HPS_GPIO56 */ - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - hps_sw0 { - label = "hps_sw0"; - gpios = <&portc 20 0>; /* HPS_GPI7 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x0>; /* SW_LID */ - }; - - hps_sw1 { - label = "hps_sw1"; - gpios = <&portc 19 0>; /* HPS_GPI6 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x5>; /* SW_DOCK */ - }; - - hps_sw2 { - label = "hps_sw2"; - gpios = <&portc 18 0>; /* HPS_GPI5 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ - }; - - hps_sw3 { - label = "hps_sw3"; - gpios = <&portc 17 0>; /* HPS_GPI4 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0xc>; /* SW_ROTATE_LOCK */ - }; - - hps_hkey0 { - label = "hps_hkey0"; - gpios = <&portc 21 1>; /* HPS_GPI8 */ - linux,code = <187>; /* KEY_F17 */ - }; - - hps_hkey1 { - label = "hps_hkey1"; - gpios = <&portc 22 1>; /* HPS_GPI9 */ - linux,code = <188>; /* KEY_F18 */ - }; - - hps_hkey2 { - label = "hps_hkey2"; - gpios = <&portc 23 1>; /* HPS_GPI10 */ - linux,code = <189>; /* KEY_F19 */ - }; - - hps_hkey3 { - label = "hps_hkey3"; - gpios = <&portc 24 1>; /* HPS_GPI11 */ - linux,code = <190>; /* KEY_F20 */ - }; - }; - - regulator_3_3v: vcc3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VCC3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio0 { /* GPIO 0..29 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 30..57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - accel1: accelerometer@53 { - compatible = "adi,adxl345"; - reg = <0x53>; - - interrupt-parent = <&portc>; - interrupts = <3 2>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts deleted file mode 100644 index d79853775..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2014 Steffen Trumtrar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "EBV SOCrates"; - compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - leds: gpio-leds { - }; -}; - -&gmac1 { - phy-mode = "rgmii"; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rtc: rtc@68 { - compatible = "st,m41t82"; - reg = <0x68>; - }; -}; - -&leds { - compatible = "gpio-leds"; - - led@0 { - label = "led:green:heartbeat"; - gpios = <&porta 28 1>; - linux,default-trigger = "heartbeat"; - }; - - led@1 { - label = "led:green:D7"; - gpios = <&portb 19 1>; - }; - - led@2 { - label = "led:green:D8"; - gpios = <&portb 25 1>; - }; -}; - -&mmc { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts deleted file mode 100644 index b84447360..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "socfpga_cyclone5.dtsi" -#include -#include - -/ { - model = "samtec VIN|ING FPGA"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* - * This allow the ethaddr uboot environment variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - - hps_led0 { - label = "hps:green:led0"; /* ALIVE_LED_GR */ - gpios = <&portb 19 0>; /* HPS_GPIO48 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led1 { - label = "hps:red:led0"; /* ALIVE_LED_RD */ - gpios = <&portb 24 0>; /* HPS_GPIO53 */ - linux,default-trigger = "none"; - }; - - hps_led2 { - label = "hps:green:led1"; /* LINK2HOST_LED_GR */ - gpios = <&portb 25 0>; /* HPS_GPIO54 */ - linux,default-trigger = "heartbeat"; - }; - - hps_led3 { - label = "hps:red:led1"; /* LINK2HOST_LED_RD */ - gpios = <&portc 7 0>; /* HPS_GPIO65 */ - linux,default-trigger = "none"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - hps_temp0 { - label = "BTN_0"; /* TEMP_OS */ - gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */ - linux,code = ; - }; - - hps_hkey0 { - label = "BTN_1"; /* DIS_PWR */ - gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */ - linux,code = ; - }; - - hps_hkey1 { - label = "hps_hkey1"; /* POWER_DOWN */ - gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */ - linux,code = ; - }; - }; - - regulator-usb-nrst { - compatible = "regulator-fixed"; - regulator-name = "usb_nrst"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&portb 5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - regulator-always-on; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - - snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <10000 10000 10000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: ethernet-phy@1 { - reg = <1>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; - }; - }; -}; - -&gpio0 { /* GPIO 0..29 */ - status = "okay"; -}; - -&gpio1 { /* GPIO 30..57 */ - status = "okay"; -}; - -&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - gpio: pca9557@1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - gpio-controller; - #gpio-cells = <2>; - }; - - temp: lm75@48 { - compatible = "lm75"; - reg = <0x48>; - }; - - at24@50 { - compatible = "at24,24c01"; - pagesize = <8>; - reg = <0x50>; - }; - - i2cswitch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - eeprom@51 { - compatible = "at,24c01"; - pagesize = <8>; - reg = <0x51>; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - - at24@50 { - compatible = "at24,24c02"; - pagesize = <8>; - reg = <0x50>; - }; -}; - -&usb0 { - dr_mode = "host"; - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/socfpga_vt.dts b/software/linux/kernel/arch/arm/boot/dts/socfpga_vt.dts deleted file mode 100644 index f9345e02c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/socfpga_vt.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/dts-v1/; -#include "socfpga.dtsi" - -/ { - model = "Altera SOCFPGA VT"; - compatible = "altr,socfpga-vt", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 GB */ - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <10000000>; - }; - }; - }; - - dwmmc0@ff704000 { - num-slots = <1>; - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - ethernet@ff700000 { - phy-mode = "gmii"; - status = "okay"; - }; - - timer0@ffc08000 { - clock-frequency = <7000000>; - }; - - timer1@ffc09000 { - clock-frequency = <7000000>; - }; - - timer2@ffd00000 { - clock-frequency = <7000000>; - }; - - timer3@ffd01000 { - clock-frequency = <7000000>; - }; - - serial0@ffc02000 { - clock-frequency = <7372800>; - }; - - serial1@ffc03000 { - clock-frequency = <7372800>; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd08010>; - }; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "gmii"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear1310-evb.dts b/software/linux/kernel/arch/arm/boot/dts/spear1310-evb.dts deleted file mode 100644 index 0f5f37932..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear1310-evb.dts +++ /dev/null @@ -1,427 +0,0 @@ -/* - * DTS file for SPEAr1310 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear1310.dtsi" - -/ { - model = "ST SPEAr1310 Evaluation Board"; - compatible = "st,spear1310-evb", "st,spear1310"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@e0700000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - i2s0 { - st,pins = "i2s0_grp"; - st,function = "i2s0"; - }; - i2s1 { - st,pins = "i2s1_grp"; - st,function = "i2s1"; - }; - gpio { - st,pins = "arm_gpio_grp"; - st,function = "arm_gpio"; - }; - clcd { - st,pins = "clcd_grp" , "clcd_high_res"; - st,function = "clcd"; - }; - eth { - st,pins = "gmii_grp"; - st,function = "gmii"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - kbd { - st,pins = "keyboard_6x6_grp"; - st,function = "keyboard"; - }; - sdhci { - st,pins = "sdhci_grp"; - st,function = "sdhci"; - }; - smi-pmx { - st,pins = "smi_2_chips_grp"; - st,function = "smi"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - rs485 { - st,pins = "rs485_0_1_tdm_0_1_grp"; - st,function = "rs485_0_1_tdm_0_1"; - }; - i2c1_2 { - st,pins = "i2c_1_2_grp"; - st,function = "i2c_1_2"; - }; - smii { - st,pins = "smii_0_1_2_grp"; - st,function = "smii_0_1_2"; - }; - nand { - st,pins = "nand_8bit_grp", - "nand_16bit_grp"; - st,function = "nand"; - }; - sata { - st,pins = "sata0_grp"; - st,function = "sata"; - }; - pcie { - st,pins = "pcie1_grp", "pcie2_grp"; - st,function = "pci_express"; - }; - }; - }; - - ahci@b1000000 { - status = "okay"; - }; - - miphy@eb800000 { - status = "okay"; - }; - - cf@b2800000 { - status = "okay"; - }; - - dma@ea800000 { - status = "okay"; - }; - - dma@eb000000 { - status = "okay"; - }; - - fsmc: flash@b0000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x80000>; - }; - partition@80000 { - label = "u-boot"; - reg = <0x80000 0x140000>; - }; - partition@1C0000 { - label = "environment"; - reg = <0x1C0000 0x40000>; - }; - partition@200000 { - label = "dtb"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "linux"; - reg = <0x240000 0xC00000>; - }; - partition@E40000 { - label = "rootfs"; - reg = <0xE40000 0x0>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "wakeup"; - linux,code = <0x100>; - gpios = <&gpio0 7 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - gmac0: eth@e2000000 { - phy-mode = "gmii"; - status = "okay"; - }; - - sdhci@b3000000 { - status = "okay"; - }; - - smi: flash@ea000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@e6000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xe6000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - ehci@e4800000 { - status = "okay"; - }; - - ehci@e5800000 { - status = "okay"; - }; - - ohci@e4000000 { - status = "okay"; - }; - - ohci@e5000000 { - status = "okay"; - }; - - apb { - adc@e0080000 { - status = "okay"; - }; - - gpio0: gpio@e0600000 { - status = "okay"; - }; - - gpio1: gpio@e0680000 { - status = "okay"; - }; - - gpio@d8400000 { - status = "okay"; - }; - - i2c0: i2c@e0280000 { - status = "okay"; - }; - - kbd@e0300000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - suspended_rate = <2000000>; - status = "okay"; - }; - - rtc@e0580000 { - status = "okay"; - }; - - serial@e0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - spi0: spi@e0100000 { - status = "okay"; - num-cs = <3>; - cs-gpios = <&gpio1 7 0>, <&spics 0 0>, <&spics 1 0>; - - stmpe610@0 { - compatible = "st,stmpe610"; - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <1000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x7>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - interrupts = <6 0x4>; - interrupt-parent = <&gpio1>; - irq-trigger = <0x2>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <2>; - ts,settling = <2>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - - m25p80@1 { - compatible = "st,m25p80"; - reg = <1>; - spi-max-frequency = <12000000>; - spi-cpol; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - }; - - wdt@ec800620 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear1310.dtsi b/software/linux/kernel/arch/arm/boot/dts/spear1310.dtsi deleted file mode 100644 index 54bc6d3cf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear1310.dtsi +++ /dev/null @@ -1,316 +0,0 @@ -/* - * DTS file for all SPEAr1310 SoCs - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear13xx.dtsi" - -/ { - compatible = "st,spear1310"; - - ahb { - spics: spics@e0700000{ - compatible = "st,spear-spics-gpio"; - reg = <0xe0700000 0x1000>; - st-spics,peripcfg-reg = <0x3b0>; - st-spics,sw-enable-bit = <12>; - st-spics,cs-value-bit = <11>; - st-spics,cs-enable-mask = <3>; - st-spics,cs-enable-shift = <8>; - gpio-controller; - #gpio-cells = <2>; - }; - - miphy0: miphy@eb800000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb800000 0x4000>; - misc = <&misc>; - phy-id = <0>; - #phy-cells = <1>; - status = "disabled"; - }; - - miphy1: miphy@eb804000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb804000 0x4000>; - misc = <&misc>; - phy-id = <1>; - #phy-cells = <1>; - status = "disabled"; - }; - - miphy2: miphy@eb808000 { - compatible = "st,spear1310-miphy"; - reg = <0xeb808000 0x4000>; - misc = <&misc>; - phy-id = <2>; - #phy-cells = <1>; - status = "disabled"; - }; - - ahci0: ahci@b1000000 { - compatible = "snps,spear-ahci"; - reg = <0xb1000000 0x10000>; - interrupts = <0 68 0x4>; - phys = <&miphy0 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - ahci1: ahci@b1800000 { - compatible = "snps,spear-ahci"; - reg = <0xb1800000 0x10000>; - interrupts = <0 69 0x4>; - phys = <&miphy1 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - ahci2: ahci@b4000000 { - compatible = "snps,spear-ahci"; - reg = <0xb4000000 0x10000>; - interrupts = <0 70 0x4>; - phys = <&miphy2 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - pcie0: pcie@b1000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 68 0x4>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 0 68 0x4>; - num-lanes = <1>; - phys = <&miphy0 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - status = "disabled"; - }; - - pcie1: pcie@b1800000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1800000 0x4000>, <0x90000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 69 0x4>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 0 69 0x4>; - num-lanes = <1>; - phys = <&miphy1 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ - status = "disabled"; - }; - - pcie2: pcie@b4000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 70 0x4>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 0 70 0x4>; - num-lanes = <1>; - phys = <&miphy2 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - status = "disabled"; - }; - - gmac1: eth@5c400000 { - compatible = "st,spear600-gmac"; - reg = <0x5c400000 0x8000>; - interrupts = <0 95 0x4>; - interrupt-names = "macirq"; - phy-mode = "mii"; - status = "disabled"; - }; - - gmac2: eth@5c500000 { - compatible = "st,spear600-gmac"; - reg = <0x5c500000 0x8000>; - interrupts = <0 96 0x4>; - interrupt-names = "macirq"; - phy-mode = "mii"; - status = "disabled"; - }; - - gmac3: eth@5c600000 { - compatible = "st,spear600-gmac"; - reg = <0x5c600000 0x8000>; - interrupts = <0 97 0x4>; - interrupt-names = "macirq"; - phy-mode = "rmii"; - status = "disabled"; - }; - - gmac4: eth@5c700000 { - compatible = "st,spear600-gmac"; - reg = <0x5c700000 0x8000>; - interrupts = <0 98 0x4>; - interrupt-names = "macirq"; - phy-mode = "rgmii"; - status = "disabled"; - }; - - pinmux: pinmux@e0700000 { - compatible = "st,spear1310-pinmux"; - reg = <0xe0700000 0x1000>; - #gpio-range-cells = <3>; - }; - - apb { - i2c1: i2c@5cd00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5cd00000 0x1000>; - interrupts = <0 87 0x4>; - status = "disabled"; - }; - - i2c2: i2c@5ce00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5ce00000 0x1000>; - interrupts = <0 88 0x4>; - status = "disabled"; - }; - - i2c3: i2c@5cf00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5cf00000 0x1000>; - interrupts = <0 89 0x4>; - status = "disabled"; - }; - - i2c4: i2c@5d000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d000000 0x1000>; - interrupts = <0 90 0x4>; - status = "disabled"; - }; - - i2c5: i2c@5d100000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d100000 0x1000>; - interrupts = <0 91 0x4>; - status = "disabled"; - }; - - i2c6: i2c@5d200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d200000 0x1000>; - interrupts = <0 92 0x4>; - status = "disabled"; - }; - - i2c7: i2c@5d300000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x5d300000 0x1000>; - interrupts = <0 93 0x4>; - status = "disabled"; - }; - - spi1: spi@5d400000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x5d400000 0x1000>; - interrupts = <0 99 0x4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - serial@5c800000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5c800000 0x1000>; - interrupts = <0 82 0x4>; - status = "disabled"; - }; - - serial@5c900000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5c900000 0x1000>; - interrupts = <0 83 0x4>; - status = "disabled"; - }; - - serial@5ca00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5ca00000 0x1000>; - interrupts = <0 84 0x4>; - status = "disabled"; - }; - - serial@5cb00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5cb00000 0x1000>; - interrupts = <0 85 0x4>; - status = "disabled"; - }; - - serial@5cc00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x5cc00000 0x1000>; - interrupts = <0 86 0x4>; - status = "disabled"; - }; - - thermal@e07008c4 { - st,thermal-flags = <0x7000>; - }; - - gpiopinctrl: gpio@d8400000 { - compatible = "st,spear-plgpio"; - reg = <0xd8400000 0x1000>; - interrupts = <0 100 0x4>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 246>; - status = "disabled"; - - st-plgpio,ngpio = <246>; - st-plgpio,enb-reg = <0xd0>; - st-plgpio,wdata-reg = <0x90>; - st-plgpio,dir-reg = <0xb0>; - st-plgpio,ie-reg = <0x30>; - st-plgpio,rdata-reg = <0x70>; - st-plgpio,mis-reg = <0x10>; - st-plgpio,eit-reg = <0x50>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear1340-evb.dts b/software/linux/kernel/arch/arm/boot/dts/spear1340-evb.dts deleted file mode 100644 index 6565f3cb8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear1340-evb.dts +++ /dev/null @@ -1,525 +0,0 @@ -/* - * DTS file for SPEAr1340 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear1340.dtsi" - -/ { - model = "ST SPEAr1340 Evaluation Board"; - compatible = "st,spear1340-evb", "st,spear1340"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@e0700000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pads_as_gpio { - st,pins = "pads_as_gpio_grp"; - st,function = "pads_as_gpio"; - }; - fsmc { - st,pins = "fsmc_8bit_grp"; - st,function = "fsmc"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - i2c1 { - st,pins = "i2c1_grp"; - st,function = "i2c1"; - }; - spdif-in { - st,pins = "spdif_in_grp"; - st,function = "spdif_in"; - }; - spdif-out { - st,pins = "spdif_out_grp"; - st,function = "spdif_out"; - }; - ssp0 { - st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp"; - st,function = "ssp0"; - }; - smi-pmx { - st,pins = "smi_grp"; - st,function = "smi"; - }; - i2s { - st,pins = "i2s_in_grp", "i2s_out_grp"; - st,function = "i2s"; - }; - gmac { - st,pins = "gmii_grp", "rgmii_grp"; - st,function = "gmac"; - }; - cam0 { - st,pins = "cam0_grp"; - st,function = "cam0"; - }; - cam1 { - st,pins = "cam1_grp"; - st,function = "cam1"; - }; - cam2 { - st,pins = "cam2_grp"; - st,function = "cam2"; - }; - cam3 { - st,pins = "cam3_grp"; - st,function = "cam3"; - }; - cec0 { - st,pins = "cec0_grp"; - st,function = "cec0"; - }; - cec1 { - st,pins = "cec1_grp"; - st,function = "cec1"; - }; - sdhci { - st,pins = "sdhci_grp"; - st,function = "sdhci"; - }; - clcd { - st,pins = "clcd_grp"; - st,function = "clcd"; - }; - sata { - st,pins = "sata_grp"; - st,function = "sata"; - }; - pcie { - st,pins = "pcie_grp"; - st,function = "pcie"; - }; - - }; - }; - - ahci@b1000000 { - status = "okay"; - }; - - miphy@eb800000 { - status = "okay"; - }; - - dma@ea800000 { - status = "okay"; - }; - - dma@eb000000 { - status = "okay"; - }; - - fsmc: flash@b0000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "u-boot"; - reg = <0x200000 0x200000>; - }; - partition@400000 { - label = "environment"; - reg = <0x400000 0x100000>; - }; - partition@500000 { - label = "dtb"; - reg = <0x500000 0x100000>; - }; - partition@600000 { - label = "linux"; - reg = <0x600000 0xC00000>; - }; - partition@1200000 { - label = "rootfs"; - reg = <0x1200000 0x0>; - }; - }; - - gmac0: eth@e2000000 { - phy-mode = "rgmii"; - status = "okay"; - }; - - sdhci@b3000000 { - status = "okay"; - }; - - smi: flash@ea000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@e6000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xe6000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - ehci@e4800000 { - status = "okay"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "wakeup"; - linux,code = <0x100>; - gpios = <&gpio1 1 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - ehci@e5800000 { - status = "okay"; - }; - - i2s0: i2s-play@b2400000 { - status = "okay"; - }; - - i2s1: i2s-rec@b2000000 { - status = "okay"; - }; - - incodec: dir-hifi { - compatible = "dummy,dir-hifi"; - status = "okay"; - }; - - ohci@e4000000 { - status = "okay"; - }; - - ohci@e5000000 { - status = "okay"; - }; - - outcodec: dit-hifi { - compatible = "dummy,dit-hifi"; - status = "okay"; - }; - - sound { - compatible = "spear,spear-evb"; - audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>; - audio-codecs = <&incodec &outcodec &sta529 &sta529>; - codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio"; - stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap"; - dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm"; - nr_controllers = <4>; - status = "okay"; - }; - - spdif0: spdif-in@d0100000 { - status = "okay"; - }; - - spdif1: spdif-out@d0000000 { - status = "okay"; - }; - - apb { - adc@e0080000 { - status = "okay"; - }; - - i2s-play@b2400000 { - status = "okay"; - }; - - i2s-rec@b2000000 { - status = "okay"; - }; - - gpio0: gpio@e0600000 { - status = "okay"; - }; - - gpio1: gpio@e0680000 { - status = "okay"; - }; - - gpio@e2800000 { - status = "okay"; - }; - - i2c0: i2c@e0280000 { - status = "okay"; - - sta529: sta529@1a { - compatible = "st,sta529"; - reg = <0x1a>; - }; - }; - - i2c1: i2c@b4000000 { - status = "okay"; - - eeprom0@56 { - compatible = "st,eeprom"; - reg = <0x56>; - }; - - stmpe801@41 { - compatible = "st,stmpe801"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - interrupts = <4 0x4>; - interrupt-parent = <&gpio0>; - irq-trigger = <0x2>; - - stmpegpio: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - - kbd@e0300000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - suspended_rate = <2000000>; - status = "okay"; - }; - - rtc@e0580000 { - status = "okay"; - }; - - serial@e0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b4100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - spi0: spi@e0100000 { - status = "okay"; - num-cs = <3>; - cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>, - <&gpiopinctrl 85 0>; - - m25p80@0 { - compatible = "m25p80"; - reg = <0>; - spi-max-frequency = <12000000>; - spi-cpol; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - - stmpe610@1 { - compatible = "st,stmpe610"; - spi-max-frequency = <1000000>; - spi-cpha; - reg = <1>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x7>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - interrupts = <100 0>; - interrupt-parent = <&gpiopinctrl>; - irq-trigger = <0x2>; - #address-cells = <1>; - #size-cells = <0>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <2>; - ts,settling = <2>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - - spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - spi-cpha; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - }; - - timer@ec800600 { - status = "okay"; - }; - - wdt@ec800620 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear1340.dtsi b/software/linux/kernel/arch/arm/boot/dts/spear1340.dtsi deleted file mode 100644 index 6361cbfcb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear1340.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -/* - * DTS file for all SPEAr1340 SoCs - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear13xx.dtsi" - -/ { - compatible = "st,spear1340"; - - ahb { - - spics: spics@e0700000{ - compatible = "st,spear-spics-gpio"; - reg = <0xe0700000 0x1000>; - st-spics,peripcfg-reg = <0x42c>; - st-spics,sw-enable-bit = <21>; - st-spics,cs-value-bit = <20>; - st-spics,cs-enable-mask = <3>; - st-spics,cs-enable-shift = <18>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - miphy0: miphy@eb800000 { - compatible = "st,spear1340-miphy"; - reg = <0xeb800000 0x4000>; - misc = <&misc>; - #phy-cells = <1>; - status = "disabled"; - }; - - ahci0: ahci@b1000000 { - compatible = "snps,spear-ahci"; - reg = <0xb1000000 0x10000>; - interrupts = <0 72 0x4>; - phys = <&miphy0 0>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - pcie0: pcie@b1000000 { - compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; - reg-names = "dbi", "config"; - interrupts = <0 68 0x4>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 0 68 0x4>; - num-lanes = <1>; - phys = <&miphy0 1>; - phy-names = "pcie-phy"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ - status = "disabled"; - }; - - i2s-play@b2400000 { - compatible = "snps,designware-i2s"; - reg = <0xb2400000 0x10000>; - interrupt-names = "play_irq"; - interrupts = <0 98 0x4 - 0 99 0x4>; - play; - channel = <8>; - status = "disabled"; - }; - - i2s-rec@b2000000 { - compatible = "snps,designware-i2s"; - reg = <0xb2000000 0x10000>; - interrupt-names = "record_irq"; - interrupts = <0 100 0x4 - 0 101 0x4>; - record; - channel = <8>; - status = "disabled"; - }; - - pinmux: pinmux@e0700000 { - compatible = "st,spear1340-pinmux"; - reg = <0xe0700000 0x1000>; - #gpio-range-cells = <3>; - }; - - pwm: pwm@e0180000 { - compatible ="st,spear13xx-pwm"; - reg = <0xe0180000 0x1000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - spdif-in@d0100000 { - compatible = "st,spdif-in"; - reg = < 0xd0100000 0x20000 - 0xd0110000 0x10000 >; - interrupts = <0 84 0x4>; - status = "disabled"; - }; - - spdif-out@d0000000 { - compatible = "st,spdif-out"; - reg = <0xd0000000 0x20000>; - interrupts = <0 85 0x4>; - status = "disabled"; - }; - - spi1: spi@5d400000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x5d400000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 99 0x4>; - status = "disabled"; - }; - - apb { - i2c1: i2c@b4000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xb4000000 0x1000>; - interrupts = <0 104 0x4>; - write-16bit; - status = "disabled"; - }; - - serial@b4100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb4100000 0x1000>; - interrupts = <0 105 0x4>; - status = "disabled"; - dmas = <&dwdma0 12 0 1>, - <&dwdma0 13 1 0>; - dma-names = "tx", "rx"; - }; - - thermal@e07008c4 { - st,thermal-flags = <0x2a00>; - }; - - gpiopinctrl: gpio@e2800000 { - compatible = "st,spear-plgpio"; - reg = <0xe2800000 0x1000>; - interrupts = <0 107 0x4>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 252>; - status = "disabled"; - - st-plgpio,ngpio = <250>; - st-plgpio,wdata-reg = <0x40>; - st-plgpio,dir-reg = <0x00>; - st-plgpio,ie-reg = <0x80>; - st-plgpio,rdata-reg = <0x20>; - st-plgpio,mis-reg = <0xa0>; - st-plgpio,eit-reg = <0x60>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear13xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/spear13xx.dtsi deleted file mode 100644 index 9564337c1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear13xx.dtsi +++ /dev/null @@ -1,343 +0,0 @@ -/* - * DTS file for all SPEAr13xx SoCs - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - gic: interrupt-controller@ec801000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0xec801000 0x1000 >, - < 0xec800100 0x0100 >; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 6 0x04 - 0 7 0x04>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xed000000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0 0x40000000>; - }; - - chosen { - bootargs = "console=ttyAMA0,115200"; - }; - - cpufreq { - compatible = "st,cpufreq-spear"; - cpufreq_tbl = < 166000 - 200000 - 250000 - 300000 - 400000 - 500000 - 600000 >; - status = "disabled"; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x50000000 0x50000000 0x10000000 - 0x80000000 0x80000000 0x20000000 - 0xb0000000 0xb0000000 0x22000000 - 0xd8000000 0xd8000000 0x01000000 - 0xe0000000 0xe0000000 0x10000000>; - - sdhci@b3000000 { - compatible = "st,sdhci-spear"; - reg = <0xb3000000 0x100>; - interrupts = <0 28 0x4>; - status = "disabled"; - }; - - cf@b2800000 { - compatible = "arasan,cf-spear1340"; - reg = <0xb2800000 0x1000>; - interrupts = <0 29 0x4>; - status = "disabled"; - dmas = <&dwdma0 0 0 0>; - dma-names = "data"; - }; - - dwdma0: dma@ea800000 { - compatible = "snps,dma-spear1340"; - reg = <0xea800000 0x1000>; - interrupts = <0 19 0x4>; - status = "disabled"; - - dma-channels = <8>; - #dma-cells = <3>; - dma-requests = <32>; - chan_allocation_order = <1>; - chan_priority = <1>; - block_size = <0xfff>; - dma-masters = <2>; - data-width = <8 8>; - }; - - dma@eb000000 { - compatible = "snps,dma-spear1340"; - reg = <0xeb000000 0x1000>; - interrupts = <0 59 0x4>; - status = "disabled"; - - dma-requests = <32>; - dma-channels = <8>; - dma-masters = <2>; - #dma-cells = <3>; - chan_allocation_order = <1>; - chan_priority = <1>; - block_size = <0xfff>; - data-width = <8 8>; - }; - - fsmc: flash@b0000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xb0000000 0x1000 /* FSMC Register*/ - 0xb0800000 0x0010 /* NAND Base DATA */ - 0xb0820000 0x0010 /* NAND Base ADDR */ - 0xb0810000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - interrupts = <0 20 0x4 - 0 21 0x4 - 0 22 0x4 - 0 23 0x4>; - st,mode = <2>; - status = "disabled"; - }; - - gmac0: eth@e2000000 { - compatible = "st,spear600-gmac"; - reg = <0xe2000000 0x8000>; - interrupts = <0 33 0x4 - 0 34 0x4>; - interrupt-names = "macirq", "eth_wake_irq"; - status = "disabled"; - }; - - pcm { - compatible = "st,pcm-audio"; - #address-cells = <0>; - #size-cells = <0>; - status = "disabled"; - }; - - smi: flash@ea000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xea000000 0x1000>; - interrupts = <0 30 0x4>; - status = "disabled"; - }; - - ehci@e4800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe4800000 0x1000>; - interrupts = <0 64 0x4>; - usbh0_id = <0>; - status = "disabled"; - }; - - ehci@e5800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe5800000 0x1000>; - interrupts = <0 66 0x4>; - usbh1_id = <1>; - status = "disabled"; - }; - - ohci@e4000000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe4000000 0x1000>; - interrupts = <0 65 0x4>; - usbh0_id = <0>; - status = "disabled"; - }; - - ohci@e5000000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe5000000 0x1000>; - interrupts = <0 67 0x4>; - usbh1_id = <1>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 - 0xd8000000 0xd8000000 0x01000000 - 0xe0000000 0xe0000000 0x10000000>; - - misc: syscon@e0700000 { - compatible = "st,spear1340-misc", "syscon"; - reg = <0xe0700000 0x1000>; - }; - - gpio0: gpio@e0600000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xe0600000 0x1000>; - interrupts = <0 24 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@e0680000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xe0680000 0x1000>; - interrupts = <0 25 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - kbd@e0300000 { - compatible = "st,spear300-kbd"; - reg = <0xe0300000 0x1000>; - interrupts = <0 52 0x4>; - status = "disabled"; - }; - - i2c0: i2c@e0280000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xe0280000 0x1000>; - interrupts = <0 41 0x4>; - status = "disabled"; - }; - - i2s@e0180000 { - compatible = "st,designware-i2s"; - reg = <0xe0180000 0x1000>; - interrupt-names = "play_irq", "record_irq"; - interrupts = <0 10 0x4 - 0 11 0x4 >; - status = "disabled"; - }; - - i2s@e0200000 { - compatible = "st,designware-i2s"; - reg = <0xe0200000 0x1000>; - interrupt-names = "play_irq", "record_irq"; - interrupts = <0 26 0x4 - 0 53 0x4>; - status = "disabled"; - }; - - spi0: spi@e0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xe0100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 31 0x4>; - status = "disabled"; - dmas = <&dwdma0 4 0 0>, - <&dwdma0 5 0 0>; - dma-names = "tx", "rx"; - }; - - rtc@e0580000 { - compatible = "st,spear600-rtc"; - reg = <0xe0580000 0x1000>; - interrupts = <0 36 0x4>; - status = "disabled"; - }; - - serial@e0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xe0000000 0x1000>; - interrupts = <0 35 0x4>; - status = "disabled"; - }; - - adc@e0080000 { - compatible = "st,spear600-adc"; - reg = <0xe0080000 0x1000>; - interrupts = <0 12 0x4>; - status = "disabled"; - }; - - timer@e0380000 { - compatible = "st,spear-timer"; - reg = <0xe0380000 0x400>; - interrupts = <0 37 0x4>; - }; - - timer@ec800600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xec800600 0x20>; - interrupts = <1 13 0x4>; - status = "disabled"; - }; - - wdt@ec800620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xec800620 0x20>; - status = "disabled"; - }; - - thermal@e07008c4 { - compatible = "st,thermal-spear1340"; - reg = <0xe07008c4 0x4>; - thermal_flags = <0x7000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear300-evb.dts b/software/linux/kernel/arch/arm/boot/dts/spear300-evb.dts deleted file mode 100644 index e859e8288..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear300-evb.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* - * DTS file for SPEAr300 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear300.dtsi" - -/ { - model = "ST SPEAr300 Evaluation Board"; - compatible = "st,spear300-evb", "st,spear300"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@99000000 { - st,pinmux-mode = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - clcd { - st,pins = "clcd_pfmode_grp"; - st,function = "clcd"; - }; - sdhci { - st,pins = "sdhci_4bit_grp"; - st,function = "sdhci"; - }; - gpio1 { - st,pins = "gpio1_4_to_7_grp", - "gpio1_0_to_3_grp"; - st,function = "gpio1"; - }; - }; - }; - - clcd@60000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@94000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - cd-gpios = <&gpio1 0 0>; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio1: gpio@a9000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - kbd@a0000000 { - linux,keymap = < 0x00000001 - 0x00010002 - 0x00020003 - 0x00030004 - 0x00040005 - 0x00050006 - 0x00060007 - 0x00070008 - 0x00080009 - 0x0100000a - 0x0101000c - 0x0102000d - 0x0103000e - 0x0104000f - 0x01050010 - 0x01060011 - 0x01070012 - 0x01080013 - 0x02000014 - 0x02010015 - 0x02020016 - 0x02030017 - 0x02040018 - 0x02050019 - 0x0206001a - 0x0207001b - 0x0208001c - 0x0300001d - 0x0301001e - 0x0302001f - 0x03030020 - 0x03040021 - 0x03050022 - 0x03060023 - 0x03070024 - 0x03080025 - 0x04000026 - 0x04010027 - 0x04020028 - 0x04030029 - 0x0404002a - 0x0405002b - 0x0406002c - 0x0407002d - 0x0408002e - 0x0500002f - 0x05010030 - 0x05020031 - 0x05030032 - 0x05040033 - 0x05050034 - 0x05060035 - 0x05070036 - 0x05080037 - 0x06000038 - 0x06010039 - 0x0602003a - 0x0603003b - 0x0604003c - 0x0605003d - 0x0606003e - 0x0607003f - 0x06080040 - 0x07000041 - 0x07010042 - 0x07020043 - 0x07030044 - 0x07040045 - 0x07050046 - 0x07060047 - 0x07070048 - 0x07080049 - 0x0800004a - 0x0801004b - 0x0802004c - 0x0803004d - 0x0804004e - 0x0805004f - 0x08060050 - 0x08070051 - 0x08080052 >; - autorepeat; - st,mode = <0>; - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear300.dtsi b/software/linux/kernel/arch/arm/boot/dts/spear300.dtsi deleted file mode 100644 index f4e92e599..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear300.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -/* - * DTS file for SPEAr300 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x60000000 0x60000000 0x50000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux@99000000 { - compatible = "st,spear300-pinmux"; - reg = <0x99000000 0x1000>; - }; - - clcd@60000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x60000000 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - - fsmc: flash@94000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x94000000 0x1000 /* FSMC Register */ - 0x80000000 0x0010 /* NAND Base DATA */ - 0x80020000 0x0010 /* NAND Base ADDR */ - 0x80010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <1>; - status = "disabled"; - }; - - shirq: interrupt-controller@0x50000000 { - compatible = "st,spear300-shirq"; - reg = <0x50000000 0x1000>; - interrupts = <28>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - gpio1: gpio@a9000000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xa9000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - kbd@a0000000 { - compatible = "st,spear300-kbd"; - reg = <0xa0000000 0x1000>; - interrupts = <7>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear310-evb.dts b/software/linux/kernel/arch/arm/boot/dts/spear310-evb.dts deleted file mode 100644 index 070f2c1b7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear310-evb.dts +++ /dev/null @@ -1,208 +0,0 @@ -/* - * DTS file for SPEAr310 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear310.dtsi" - -/ { - model = "ST SPEAr310 Evaluation Board"; - compatible = "st,spear310-evb", "st,spear310"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b4000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - gpio0 { - st,pins = "gpio0_pin0_grp", - "gpio0_pin1_grp", - "gpio0_pin2_grp", - "gpio0_pin3_grp", - "gpio0_pin4_grp", - "gpio0_pin5_grp"; - st,function = "gpio0"; - }; - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - emi { - st,pins = "emi_cs_0_to_5_grp"; - st,function = "emi"; - }; - fsmc { - st,pins = "fsmc_grp"; - st,function = "fsmc"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - uart3 { - st,pins = "uart3_grp"; - st,function = "uart3"; - }; - uart4 { - st,pins = "uart4_grp"; - st,function = "uart4"; - }; - uart5 { - st,pins = "uart5_grp"; - st,function = "uart5"; - }; - }; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@44000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2080000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2180000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@b2200000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear310.dtsi b/software/linux/kernel/arch/arm/boot/dts/spear310.dtsi deleted file mode 100644 index da210b454..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear310.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * DTS file for SPEAr310 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux: pinmux@b4000000 { - compatible = "st,spear310-pinmux"; - reg = <0xb4000000 0x1000>; - #gpio-range-cells = <3>; - }; - - fsmc: flash@44000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x44000000 0x1000 /* FSMC Register */ - 0x40000000 0x0010 /* NAND Base DATA */ - 0x40020000 0x0010 /* NAND Base ADDR */ - 0x40010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - shirq: interrupt-controller@0xb4000000 { - compatible = "st,spear310-shirq"; - reg = <0xb4000000 0x1000>; - interrupts = <28 29 30 1>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - serial@b2000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2080000 0x1000>; - interrupts = <9>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2100000 0x1000>; - interrupts = <10>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2180000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2180000 0x1000>; - interrupts = <11>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@b2200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2200000 0x1000>; - interrupts = <12>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - gpiopinctrl: gpio@b4000000 { - compatible = "st,spear-plgpio"; - reg = <0xb4000000 0x1000>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 102>; - status = "disabled"; - - st-plgpio,ngpio = <102>; - st-plgpio,enb-reg = <0x10>; - st-plgpio,wdata-reg = <0x20>; - st-plgpio,dir-reg = <0x30>; - st-plgpio,ie-reg = <0x50>; - st-plgpio,rdata-reg = <0x40>; - st-plgpio,mis-reg = <0x60>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear320-evb.dts b/software/linux/kernel/arch/arm/boot/dts/spear320-evb.dts deleted file mode 100644 index 1b1034477..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear320-evb.dts +++ /dev/null @@ -1,207 +0,0 @@ -/* - * DTS file for SPEAr320 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear320.dtsi" - -/ { - model = "ST SPEAr320 Evaluation Board"; - compatible = "st,spear320-evb", "st,spear320"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b3000000 { - st,pinmux-mode = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - sdhci { - st,pins = "sdhci_cd_51_grp"; - st,function = "sdhci"; - }; - i2s { - st,pins = "i2s_grp"; - st,function = "i2s"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - can0 { - st,pins = "can0_grp"; - st,function = "can0"; - }; - can1 { - st,pins = "can1_grp"; - st,function = "can1"; - }; - mii2 { - st,pins = "mii2_grp"; - st,function = "mii2"; - }; - pwm0_1 { - st,pins = "pwm0_1_pin_37_38_grp"; - st,function = "pwm0_1"; - }; - }; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@4c000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - power-gpio = <&gpiopinctrl 61 1>; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - spi1: spi@a5000000 { - status = "okay"; - }; - - spi2: spi@a6000000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio@b3000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - i2c1: i2c@a7000000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a3000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a4000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear320-hmi.dts b/software/linux/kernel/arch/arm/boot/dts/spear320-hmi.dts deleted file mode 100644 index 0d0da1f65..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear320-hmi.dts +++ /dev/null @@ -1,305 +0,0 @@ -/* - * DTS file for SPEAr320 Evaluation Baord - * - * Copyright 2012 Shiraz Hashim - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear320.dtsi" - -/ { - model = "ST SPEAr320 HMI Board"; - compatible = "st,spear320-hmi", "st,spear320"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - pinmux@b3000000 { - st,pinmux-mode = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - clcd { - st,pins = "clcd_grp"; - st,function = "clcd"; - }; - fsmc { - st,pins = "fsmc_8bit_grp"; - st,function = "fsmc"; - }; - sdhci { - st,pins = "sdhci_cd_12_grp"; - st,function = "sdhci"; - }; - i2s { - st,pins = "i2s_grp"; - st,function = "i2s"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - can0 { - st,pins = "can0_grp"; - st,function = "can0"; - }; - can1 { - st,pins = "can1_grp"; - st,function = "can1"; - }; - mii0_1 { - st,pins = "rmii0_1_grp"; - st,function = "mii0_1"; - }; - pwm0_1 { - st,pins = "pwm0_1_pin_37_38_grp"; - st,function = "pwm0_1"; - }; - pwm2 { - st,pins = "pwm2_pin_34_grp"; - st,function = "pwm2"; - }; - }; - }; - - clcd@90000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - fsmc: flash@4c000000 { - status = "okay"; - - partition@0 { - label = "xloader"; - reg = <0x0 0x80000>; - }; - partition@80000 { - label = "u-boot"; - reg = <0x80000 0x140000>; - }; - partition@1C0000 { - label = "environment"; - reg = <0x1C0000 0x40000>; - }; - partition@200000 { - label = "dtb"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "linux"; - reg = <0x240000 0xC00000>; - }; - partition@E40000 { - label = "rootfs"; - reg = <0xE40000 0x0>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "user button 1"; - linux,code = <0x100>; - gpios = <&stmpegpio 3 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - - button@2 { - label = "user button 2"; - linux,code = <0x200>; - gpios = <&stmpegpio 2 0x4>; - debounce-interval = <20>; - wakeup-source; - }; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - pwm: pwm@a8000000 { - status = "okay"; - }; - - sdhci@70000000 { - power-gpio = <&gpiopinctrl 50 1>; - power_always_enb; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - spi1: spi@a5000000 { - status = "okay"; - }; - - spi2: spi@a6000000 { - status = "okay"; - }; - - usbd@e1100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio@b3000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - - stmpe811@41 { - compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - irq-over-gpio; - irq-gpios = <&gpiopinctrl 29 0x4>; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - - stmpegpio: stmpe-gpio { - compatible = "stmpe,gpio"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - gpio,norequest-mask = <0xF3>; - }; - - stmpe610-ts { - compatible = "stmpe,ts"; - reg = <0>; - ts,sample-time = <4>; - ts,mod-12b = <1>; - ts,ref-sel = <0>; - ts,adc-freq = <1>; - ts,ave-ctrl = <1>; - ts,touch-det-delay = <3>; - ts,settling = <4>; - ts,fraction-z = <7>; - ts,i-drive = <1>; - }; - }; - }; - - i2c1: i2c@a7000000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a3000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@a4000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear320.dtsi b/software/linux/kernel/arch/arm/boot/dts/spear320.dtsi deleted file mode 100644 index 22be6e5ed..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear320.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * DTS file for SPEAr320 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x80000000 - 0xd0000000 0xd0000000 0x30000000>; - - pinmux: pinmux@b3000000 { - compatible = "st,spear320-pinmux"; - reg = <0xb3000000 0x1000>; - #gpio-range-cells = <3>; - }; - - clcd@90000000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x90000000 0x1000>; - interrupts = <8>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - fsmc: flash@4c000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4c000000 0x1000 /* FSMC Register */ - 0x50000000 0x0010 /* NAND Base DATA */ - 0x50020000 0x0010 /* NAND Base ADDR */ - 0x50010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <10>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - shirq: interrupt-controller@0xb3000000 { - compatible = "st,spear320-shirq"; - reg = <0xb3000000 0x1000>; - interrupts = <30 28 29 1>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - spi1: spi@a5000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa5000000 0x1000>; - interrupts = <15>; - interrupt-parent = <&shirq>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@a6000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa6000000 0x1000>; - interrupts = <16>; - interrupt-parent = <&shirq>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@a8000000 { - compatible ="st,spear-pwm"; - reg = <0xa8000000 0x1000>; - #pwm-cells = <2>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x20000000 - 0xd0000000 0xd0000000 0x30000000>; - - i2c1: i2c@a7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xa7000000 0x1000>; - interrupts = <21>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@a3000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa3000000 0x1000>; - interrupts = <13>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - serial@a4000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa4000000 0x1000>; - interrupts = <14>; - interrupt-parent = <&shirq>; - status = "disabled"; - }; - - gpiopinctrl: gpio@b3000000 { - compatible = "st,spear-plgpio"; - reg = <0xb3000000 0x1000>; - #interrupt-cells = <1>; - interrupt-controller; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 102>; - status = "disabled"; - - st-plgpio,ngpio = <102>; - st-plgpio,enb-reg = <0x24>; - st-plgpio,wdata-reg = <0x34>; - st-plgpio,dir-reg = <0x44>; - st-plgpio,ie-reg = <0x64>; - st-plgpio,rdata-reg = <0x54>; - st-plgpio,mis-reg = <0x84>; - st-plgpio,eit-reg = <0x94>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear3xx.dtsi b/software/linux/kernel/arch/arm/boot/dts/spear3xx.dtsi deleted file mode 100644 index 118135d75..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear3xx.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -/* - * DTS file for all SPEAr3xx SoCs - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "skeleton.dtsi" - -/ { - interrupt-parent = <&vic>; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - vic: interrupt-controller@f1100000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1100000 0x1000>; - #interrupt-cells = <1>; - }; - - dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <8>; - status = "disabled"; - }; - - gmac: eth@e0800000 { - compatible = "st,spear600-gmac"; - reg = <0xe0800000 0x8000>; - interrupts = <23 22>; - interrupt-names = "macirq", "eth_wake_irq"; - phy-mode = "mii"; - status = "disabled"; - }; - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupts = <9>; - status = "disabled"; - }; - - spi0: spi@d0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xd0100000 0x1000>; - interrupts = <20>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupts = <26>; - status = "disabled"; - }; - - ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1900000 0x1000>; - interrupts = <25>; - status = "disabled"; - }; - - ohci@e2100000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe2100000 0x1000>; - interrupts = <27>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - gpio0: gpio@fc980000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xfc980000 0x1000>; - interrupts = <11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - i2c0: i2c@d0180000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xd0180000 0x1000>; - interrupts = <21>; - status = "disabled"; - }; - - rtc@fc900000 { - compatible = "st,spear600-rtc"; - reg = <0xfc900000 0x1000>; - interrupts = <10>; - status = "disabled"; - }; - - serial@d0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0000000 0x1000>; - interrupts = <19>; - status = "disabled"; - }; - - wdt@fc880000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0xfc880000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupts = <2>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear600-evb.dts b/software/linux/kernel/arch/arm/boot/dts/spear600-evb.dts deleted file mode 100644 index d865a8917..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear600-evb.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear600.dtsi" - -/ { - model = "ST SPEAr600 Evaluation Board"; - compatible = "st,spear600-evb", "st,spear600"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0 0x10000000>; - }; - - ahb { - clcd@fc200000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ehci@e2000000 { - status = "okay"; - }; - - gmac: ethernet@e0800000 { - phy-mode = "gmii"; - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0xf8000000 0x800000>; - st,smi-fast-mode; - - partition@0 { - label = "xloader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "u-boot"; - reg = <0x10000 0x50000>; - }; - partition@60000 { - label = "environment"; - reg = <0x60000 0x10000>; - }; - partition@70000 { - label = "dtb"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "linux"; - reg = <0x80000 0x310000>; - }; - partition@390000 { - label = "rootfs"; - reg = <0x390000 0x0>; - }; - }; - }; - - apb { - serial@d0000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - serial@d0080000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; - }; - - rtc@fc900000 { - status = "okay"; - }; - - i2c@d0200000 { - clock-frequency = <400000>; - status = "okay"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/spear600.dtsi b/software/linux/kernel/arch/arm/boot/dts/spear600.dtsi deleted file mode 100644 index bd3790349..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/spear600.dtsi +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "st,spear600"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - vic0: interrupt-controller@f1100000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1100000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@f1000000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1000000 0x1000>; - #interrupt-cells = <1>; - }; - - clcd@fc200000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0xfc200000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - status = "disabled"; - }; - - dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - status = "disabled"; - }; - - gmac: ethernet@e0800000 { - compatible = "st,spear600-gmac"; - reg = <0xe0800000 0x8000>; - interrupt-parent = <&vic1>; - interrupts = <24 23>; - interrupt-names = "macirq", "eth_wake_irq"; - phy-mode = "gmii"; - status = "disabled"; - }; - - fsmc: flash@d1800000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd1800000 0x1000 /* FSMC Register */ - 0xd2000000 0x0010 /* NAND Base DATA */ - 0xd2020000 0x0010 /* NAND Base ADDR */ - 0xd2010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - status = "disabled"; - }; - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - status = "disabled"; - }; - - ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <27>; - status = "disabled"; - }; - - ehci@e2000000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe2000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <29>; - status = "disabled"; - }; - - ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1900000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <26>; - status = "disabled"; - }; - - ohci@e2100000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe2100000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <28>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - serial@d0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0000000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - status = "disabled"; - }; - - serial@d0080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0080000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <25>; - status = "disabled"; - }; - - /* local/cpu GPIO */ - gpio0: gpio@f0100000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xf0100000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <18>; - }; - - /* basic GPIO */ - gpio1: gpio@fc980000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xfc980000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <19>; - }; - - /* appl GPIO */ - gpio2: gpio@d8100000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xd8100000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <4>; - }; - - i2c@d0200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xd0200000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <28>; - status = "disabled"; - }; - - rtc@fc900000 { - compatible = "st,spear600-rtc"; - reg = <0xfc900000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <10>; - status = "disabled"; - }; - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupt-parent = <&vic0>; - interrupts = <16>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/st-pincfg.h b/software/linux/kernel/arch/arm/boot/dts/st-pincfg.h deleted file mode 100644 index 4851c387d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/st-pincfg.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _ST_PINCFG_H_ -#define _ST_PINCFG_H_ - -/* Alternate functions */ -#define ALT1 1 -#define ALT2 2 -#define ALT3 3 -#define ALT4 4 -#define ALT5 5 -#define ALT6 6 -#define ALT7 7 - -/* Output enable */ -#define OE (1 << 27) -/* Pull Up */ -#define PU (1 << 26) -/* Open Drain */ -#define OD (1 << 25) -#define RT (1 << 23) -#define INVERTCLK (1 << 22) -#define CLKNOTDATA (1 << 21) -#define DOUBLE_EDGE (1 << 20) -#define CLK_A (0 << 18) -#define CLK_B (1 << 18) -#define CLK_C (2 << 18) -#define CLK_D (3 << 18) - -/* User-frendly defines for Pin Direction */ - /* oe = 0, pu = 0, od = 0 */ -#define IN (0) - /* oe = 0, pu = 1, od = 0 */ -#define IN_PU (PU) - /* oe = 1, pu = 0, od = 0 */ -#define OUT (OE) - /* oe = 1, pu = 0, od = 1 */ -#define BIDIR (OE | OD) - /* oe = 1, pu = 1, od = 1 */ -#define BIDIR_PU (OE | PU | OD) - -/* RETIME_TYPE */ -/* - * B Mode - * Bypass retime with optional delay parameter - */ -#define BYPASS (0) -/* - * R0, R1, R0D, R1D modes - * single-edge data non inverted clock, retime data with clk - */ -#define SE_NICLK_IO (RT) -/* - * RIV0, RIV1, RIV0D, RIV1D modes - * single-edge data inverted clock, retime data with clk - */ -#define SE_ICLK_IO (RT | INVERTCLK) -/* - * R0E, R1E, R0ED, R1ED modes - * double-edge data, retime data with clk - */ -#define DE_IO (RT | DOUBLE_EDGE) -/* - * CIV0, CIV1 modes with inverted clock - * Retiming the clk pins will park clock & reduce the noise within the core. - */ -#define ICLK (RT | CLKNOTDATA | INVERTCLK) -/* - * CLK0, CLK1 modes with non-inverted clock - * Retiming the clk pins will park clock & reduce the noise within the core. - */ -#define NICLK (RT | CLKNOTDATA) -#endif /* _ST_PINCFG_H_ */ diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi deleted file mode 100644 index 52dba2e39..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include "ste-nomadik-pinctrl.dtsi" - -/ { - soc { - pinctrl { - uart0 { - uart0_default_mux: uart0_mux { - default_mux { - function = "u0"; - groups = "u0_a_1"; - }; - }; - - uart0_default_mode: uart0_default { - default_cfg1 { - pins = "GPIO0", "GPIO2"; - ste,config = <&in_pu>; - }; - - default_cfg2 { - pins = "GPIO1", "GPIO3"; - ste,config = <&out_hi>; - }; - }; - - uart0_sleep_mode: uart0_sleep { - sleep_cfg1 { - pins = "GPIO0", "GPIO2"; - ste,config = <&slpm_in_pu>; - }; - - sleep_cfg2 { - pins = "GPIO1", "GPIO3"; - ste,config = <&slpm_out_hi>; - }; - }; - }; - - uart2 { - uart2_default_mode: uart2_default { - default_mux { - function = "u2"; - groups = "u2txrx_a_1"; - }; - - default_cfg1 { - pins = "GPIO120"; - ste,config = <&in_pu>; - }; - - default_cfg2 { - pins = "GPIO121"; - ste,config = <&out_hi>; - }; - }; - - uart2_sleep_mode: uart2_sleep { - sleep_cfg1 { - pins = "GPIO120"; - ste,config = <&slpm_in_pu>; - }; - - sleep_cfg2 { - pins = "GPIO121"; - ste,config = <&slpm_out_hi>; - }; - }; - }; - - i2c0 { - i2c0_default_mux: i2c_mux { - default_mux { - function = "i2c0"; - groups = "i2c0_a_1"; - }; - }; - - i2c0_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO147", "GPIO148"; - ste,config = <&in_pu>; - }; - }; - - i2c0_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO147", "GPIO148"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - - i2c1 { - i2c1_default_mux: i2c_mux { - default_mux { - function = "i2c1"; - groups = "i2c1_b_2"; - }; - }; - - i2c1_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO16", "GPIO17"; - ste,config = <&in_pu>; - }; - }; - - i2c1_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO16", "GPIO17"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - - i2c2 { - i2c2_default_mux: i2c_mux { - default_mux { - function = "i2c2"; - groups = "i2c2_b_2"; - }; - }; - - i2c2_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO10", "GPIO11"; - ste,config = <&in_pu>; - }; - }; - - i2c2_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO11", "GPIO11"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - - i2c4 { - i2c4_default_mux: i2c_mux { - default_mux { - function = "i2c4"; - groups = "i2c4_b_2"; - }; - }; - - i2c4_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO122", "GPIO123"; - ste,config = <&in_pu>; - }; - }; - - i2c4_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO122", "GPIO123"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - - i2c5 { - i2c5_default_mux: i2c_mux { - default_mux { - function = "i2c5"; - groups = "i2c5_c_2"; - }; - }; - - i2c5_default_mode: i2c_default { - default_cfg1 { - pins = "GPIO118", "GPIO119"; - ste,config = <&in_pu>; - }; - }; - - i2c5_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO118", "GPIO119"; - ste,config = <&slpm_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-ccu8540.dts b/software/linux/kernel/arch/arm/boot/dts/ste-ccu8540.dts deleted file mode 100644 index 6eaaf638e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-ccu8540.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright 2013 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-dbx5x0.dtsi" -#include "ste-ccu8540-pinctrl.dtsi" - -/ { - model = "ST-Ericsson U8540 platform with Device Tree"; - compatible = "st-ericsson,ccu8540", "st-ericsson,u8540"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; - - memory@0 { - device_type = "memory"; - reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>; - }; - - soc { - pinctrl { - compatible = "stericsson,db8540-pinctrl"; - }; - - prcmu@80157000 { - reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>; - reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; - }; - - uart@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; - pinctrl-1 = <&uart0_sleep_mode>; - status = "okay"; - }; - - uart@80121000 { - status = "okay"; - }; - - uart@80007000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart2_default_mode>; - pinctrl-1 = <&uart2_sleep_mode>; - status = "okay"; - }; - - i2c0: i2c@80004000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; - pinctrl-1 = <&i2c0_sleep_mode>; - }; - - i2c1: i2c@80122000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; - pinctrl-1 = <&i2c1_sleep_mode>; - }; - - i2c2: i2c@80128000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c2_default_mux>, <&i2c2_default_mode>; - pinctrl-1 = <&i2c2_sleep_mode>; - }; - - i2c3: i2c@80110000 { - status = "disabled"; - }; - - i2c4: i2c@8012a000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c4_default_mux>, <&i2c4_default_mode>; - pinctrl-1 = <&i2c4_sleep_mode>; - }; - - i2c5: i2c@80001000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c5_default_mux>, <&i2c5_default_mode>; - pinctrl-1 = <&i2c5_sleep_mode>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-ccu9540.dts b/software/linux/kernel/arch/arm/boot/dts/ste-ccu9540.dts deleted file mode 100644 index b3b9bb8e1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-ccu9540.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-dbx5x0.dtsi" - -/ { - model = "ST-Ericsson CCU9540 platform with Device Tree"; - compatible = "st-ericsson,ccu9540", "st-ericsson,u9540"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - soc { - uart@80120000 { - status = "okay"; - }; - - uart@80121000 { - status = "okay"; - }; - - uart@80007000 { - status = "okay"; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - - cd-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; // 230 - cd-inverted; - - status = "okay"; - }; - - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-dbx5x0.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-dbx5x0.dtsi deleted file mode 100644 index d309314f3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ /dev/null @@ -1,1210 +0,0 @@ -/* - * Copyright 2012 Linaro Ltd - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include "skeleton.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "ste,dbx500-smp"; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - }; - }; - CPU0: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x300>; - }; - CPU1: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x301>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "stericsson,db8500"; - interrupt-parent = <&intc>; - ranges; - - ptm@801ae000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x801ae000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - cpu = <&CPU0>; - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - - ptm@801af000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x801af000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - cpu = <&CPU1>; - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - - funnel@801a6000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x801a6000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output ports */ - port@0 { - reg = <0>; - funnel_out_port: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - - /* funnel input ports */ - port@1 { - reg = <0>; - funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@2 { - reg = <1>; - funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&ptm1_out_port>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-replicator"; - clocks = <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "atclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&funnel_out_port>; - }; - }; - }; - }; - - tpiu@80190000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x80190000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - - etb@801a4000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0x801a4000 0x1000>; - - clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; - clock-names = "apb_pclk", "atclk"; - port { - etb_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - intc: interrupt-controller@a0411000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0xa0411000 0x1000>, - <0xa0410100 0x100>; - }; - - scu@a04100000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xa0410000 0x100>; - }; - - /* - * The backup RAM is used for retention during sleep - * and various things like spin tables - */ - backupram@80150000 { - compatible = "ste,dbx500-backupram"; - reg = <0x80150000 0x2000>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xa0412000 0x1000>; - interrupts = ; - cache-unified; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - pm_domains: pm_domains0 { - compatible = "stericsson,ux500-pm-domains"; - #power-domain-cells = <1>; - }; - - clocks { - compatible = "stericsson,u8500-clks"; - /* - * Registers for the CLKRST block on peripheral - * groups 1, 2, 3, 5, 6, - */ - reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, - <0x8000f000 0x1000>, <0xa03ff000 0x1000>, - <0xa03cf000 0x1000>; - - prcmu_clk: prcmu-clock { - #clock-cells = <1>; - }; - - prcc_pclk: prcc-periph-clock { - #clock-cells = <2>; - }; - - prcc_kclk: prcc-kernel-clock { - #clock-cells = <2>; - }; - - rtc_clk: rtc32k-clock { - #clock-cells = <0>; - }; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; - }; - - mtu@a03c6000 { - /* Nomadik System Timer */ - compatible = "st,nomadik-mtu"; - reg = <0xa03c6000 0x1000>; - interrupts = ; - - clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; - clock-names = "timclk", "apb_pclk"; - }; - - timer@a0410600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xa0410600 0x20>; - interrupts = ; - - clocks = <&smp_twd_clk>; - }; - - watchdog@a0410620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0xa0410620 0x20>; - interrupts = ; - clocks = <&smp_twd_clk>; - }; - - rtc@80154000 { - compatible = "arm,rtc-pl031", "arm,primecell"; - reg = <0x80154000 0x1000>; - interrupts = ; - - clocks = <&rtc_clk>; - clock-names = "apb_pclk"; - }; - - gpio0: gpio@8012e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8012e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - clocks = <&prcc_pclk 1 9>; - }; - - gpio1: gpio@8012e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8012e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 5>; - clocks = <&prcc_pclk 1 9>; - }; - - gpio2: gpio@8000e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <2>; - gpio-ranges = <&pinctrl 0 64 32>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio3: gpio@8000e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <3>; - gpio-ranges = <&pinctrl 0 96 2>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio4: gpio@8000e100 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e100 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <4>; - gpio-ranges = <&pinctrl 0 128 32>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio5: gpio@8000e180 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e180 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <5>; - gpio-ranges = <&pinctrl 0 160 12>; - clocks = <&prcc_pclk 3 8>; - }; - - gpio6: gpio@8011e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8011e000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <6>; - gpio-ranges = <&pinctrl 0 192 32>; - clocks = <&prcc_pclk 2 11>; - }; - - gpio7: gpio@8011e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8011e080 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <7>; - gpio-ranges = <&pinctrl 0 224 7>; - clocks = <&prcc_pclk 2 11>; - }; - - gpio8: gpio@a03fe000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0xa03fe000 0x80>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <8>; - gpio-ranges = <&pinctrl 0 256 12>; - clocks = <&prcc_pclk 5 1>; - }; - - pinctrl: pinctrl { - compatible = "stericsson,db8500-pinctrl"; - nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, - <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, - <&gpio8>; - prcm = <&prcmu>; - }; - - usb_per5@a03e0000 { - compatible = "stericsson,db8500-musb"; - reg = <0xa03e0000 0x10000>; - interrupts = ; - interrupt-names = "mc"; - - dr_mode = "otg"; - - dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ - <&dma 38 0 0x0>, /* Logical - MemToDev */ - <&dma 37 0 0x2>, /* Logical - DevToMem */ - <&dma 37 0 0x0>, /* Logical - MemToDev */ - <&dma 36 0 0x2>, /* Logical - DevToMem */ - <&dma 36 0 0x0>, /* Logical - MemToDev */ - <&dma 19 0 0x2>, /* Logical - DevToMem */ - <&dma 19 0 0x0>, /* Logical - MemToDev */ - <&dma 18 0 0x2>, /* Logical - DevToMem */ - <&dma 18 0 0x0>, /* Logical - MemToDev */ - <&dma 17 0 0x2>, /* Logical - DevToMem */ - <&dma 17 0 0x0>, /* Logical - MemToDev */ - <&dma 16 0 0x2>, /* Logical - DevToMem */ - <&dma 16 0 0x0>, /* Logical - MemToDev */ - <&dma 39 0 0x2>, /* Logical - DevToMem */ - <&dma 39 0 0x0>; /* Logical - MemToDev */ - - dma-names = "iep_1_9", "oep_1_9", - "iep_2_10", "oep_2_10", - "iep_3_11", "oep_3_11", - "iep_4_12", "oep_4_12", - "iep_5_13", "oep_5_13", - "iep_6_14", "oep_6_14", - "iep_7_15", "oep_7_15", - "iep_8", "oep_8"; - - clocks = <&prcc_pclk 5 0>; - }; - - dma: dma-controller@801C0000 { - compatible = "stericsson,db8500-dma40", "stericsson,dma40"; - reg = <0x801C0000 0x1000 0x40010000 0x800>; - reg-names = "base", "lcpa"; - interrupts = ; - - #dma-cells = <3>; - memcpy-channels = <56 57 58 59 60>; - - clocks = <&prcmu_clk PRCMU_DMACLK>; - }; - - prcmu: prcmu@80157000 { - compatible = "stericsson,db8500-prcmu"; - reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; - reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - prcmu-timer-4@80157450 { - compatible = "stericsson,db8500-prcmu-timer-4"; - reg = <0x80157450 0xC>; - }; - - cpufreq { - compatible = "stericsson,cpufreq-ux500"; - clocks = <&prcmu_clk PRCMU_ARMSS>; - clock-names = "armss"; - status = "disabled"; - }; - - thermal@801573c0 { - compatible = "stericsson,db8500-thermal"; - reg = <0x801573c0 0x40>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, - <22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; - status = "disabled"; - }; - - db8500-prcmu-regulators { - compatible = "stericsson,db8500-prcmu-regulator"; - - // DB8500_REGULATOR_VAPE - db8500_vape_reg: db8500_vape { - regulator-always-on; - }; - - // DB8500_REGULATOR_VARM - db8500_varm_reg: db8500_varm { - }; - - // DB8500_REGULATOR_VMODEM - db8500_vmodem_reg: db8500_vmodem { - }; - - // DB8500_REGULATOR_VPLL - db8500_vpll_reg: db8500_vpll { - }; - - // DB8500_REGULATOR_VSMPS1 - db8500_vsmps1_reg: db8500_vsmps1 { - }; - - // DB8500_REGULATOR_VSMPS2 - db8500_vsmps2_reg: db8500_vsmps2 { - }; - - // DB8500_REGULATOR_VSMPS3 - db8500_vsmps3_reg: db8500_vsmps3 { - }; - - // DB8500_REGULATOR_VRF1 - db8500_vrf1_reg: db8500_vrf1 { - }; - - // DB8500_REGULATOR_SWITCH_SVAMMDSP - db8500_sva_mmdsp_reg: db8500_sva_mmdsp { - }; - - // DB8500_REGULATOR_SWITCH_SVAMMDSPRET - db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { - }; - - // DB8500_REGULATOR_SWITCH_SVAPIPE - db8500_sva_pipe_reg: db8500_sva_pipe { - }; - - // DB8500_REGULATOR_SWITCH_SIAMMDSP - db8500_sia_mmdsp_reg: db8500_sia_mmdsp { - }; - - // DB8500_REGULATOR_SWITCH_SIAMMDSPRET - db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - }; - - // DB8500_REGULATOR_SWITCH_SIAPIPE - db8500_sia_pipe_reg: db8500_sia_pipe { - }; - - // DB8500_REGULATOR_SWITCH_SGA - db8500_sga_reg: db8500_sga { - vin-supply = <&db8500_vape_reg>; - }; - - // DB8500_REGULATOR_SWITCH_B2R2_MCDE - db8500_b2r2_mcde_reg: db8500_b2r2_mcde { - vin-supply = <&db8500_vape_reg>; - }; - - // DB8500_REGULATOR_SWITCH_ESRAM12 - db8500_esram12_reg: db8500_esram12 { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM12RET - db8500_esram12_ret_reg: db8500_esram12_ret { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM34 - db8500_esram34_reg: db8500_esram34 { - }; - - // DB8500_REGULATOR_SWITCH_ESRAM34RET - db8500_esram34_ret_reg: db8500_esram34_ret { - }; - }; - - ab8500 { - compatible = "stericsson,ab8500"; - interrupt-parent = <&intc>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - - ab8500_gpio: ab8500-gpio { - compatible = "stericsson,ab8500-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - ab8500-rtc { - compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "60S", "ALARM"; - }; - - ab8500-gpadc { - compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "HW_CONV_END", "SW_CONV_END"; - vddadc-supply = <&ab8500_ldo_tvout_reg>; - }; - - ab8500_battery: ab8500_battery { - stericsson,battery-type = "LIPO"; - thermistor-on-batctrl; - }; - - ab8500_fg { - compatible = "stericsson,ab8500-fg"; - battery = <&ab8500_battery>; - }; - - ab8500_btemp { - compatible = "stericsson,ab8500-btemp"; - battery = <&ab8500_battery>; - }; - - ab8500_charger { - compatible = "stericsson,ab8500-charger"; - battery = <&ab8500_battery>; - vddadc-supply = <&ab8500_ldo_tvout_reg>; - }; - - ab8500_chargalg { - compatible = "stericsson,ab8500-chargalg"; - battery = <&ab8500_battery>; - }; - - ab8500_usb { - compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ID_WAKEUP_R", - "ID_WAKEUP_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_ADP_PROBE_PLUG", - "USB_ADP_PROBE_UNPLUG"; - vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; - v-ape-supply = <&db8500_vape_reg>; - musb_1v8-supply = <&db8500_vsmps2_reg>; - }; - - ab8500-ponkey { - compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; - }; - - ab8500-sysctrl { - compatible = "stericsson,ab8500-sysctrl"; - }; - - ab8500-pwm { - compatible = "stericsson,ab8500-pwm"; - }; - - ab8500-debugfs { - compatible = "stericsson,ab8500-debug"; - }; - - codec: ab8500-codec { - compatible = "stericsson,ab8500-codec"; - - V-AUD-supply = <&ab8500_ldo_audio_reg>; - V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; - V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; - V-DMIC-supply = <&ab8500_ldo_dmic_reg>; - - stericsson,earpeice-cmv = <950>; /* Units in mV. */ - }; - - ext_regulators: ab8500-ext-regulators { - compatible = "stericsson,ab8500-ext-regulator"; - - ab8500_ext1_reg: ab8500_ext1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ab8500_ext2_reg: ab8500_ext2 { - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-boot-on; - regulator-always-on; - }; - - ab8500_ext3_reg: ab8500_ext3 { - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - }; - }; - - ab8500-regulators { - compatible = "stericsson,ab8500-regulator"; - vin-supply = <&ab8500_ext3_reg>; - - // supplies to the display/camera - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - /* BUG: If turned off MMC will be affected. */ - regulator-always-on; - }; - - // supplies to the on-board eMMC - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - // supply for VAUX3; SDcard slots - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - // supply for v-intcore12; VINTCORE12 LDO - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - }; - - // supply for tvout; gpadc; TVOUT LDO - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - }; - - // supply for ab8500-usb; USB LDO - ab8500_ldo_usb_reg: ab8500_ldo_usb { - }; - - // supply for ab8500-vaudio; VAUDIO LDO - ab8500_ldo_audio_reg: ab8500_ldo_audio { - }; - - // supply for v-anamic1 VAMIC1 LDO - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - }; - - // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - }; - - // supply for v-dmic; VDMIC LDO - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - }; - - // supply for U8500 CSI/DSI; VANA LDO - ab8500_ldo_ana_reg: ab8500_ldo_ana { - }; - }; - }; - }; - - i2c@80004000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80004000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - i2c@80122000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80122000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - i2c@80128000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80128000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - i2c@80110000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x80110000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - i2c@8012a000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; - reg = <0x8012a000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; - clock-names = "i2cclk", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - ssp@80002000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80002000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ - <&dma 8 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - ssp@80003000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80003000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ - <&dma 9 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - spi@8011a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x8011a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ - <&dma 0 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - spi@80112000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80112000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ - <&dma 35 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - spi@80111000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80111000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ - <&dma 33 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - spi@80129000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80129000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ - <&dma 40 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - power-domains = <&pm_domains DOMAIN_VAPE>; - }; - - ux500_serial0: uart@80120000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80120000 0x1000>; - interrupts = ; - - dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ - <&dma 13 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; - clock-names = "uart", "apb_pclk"; - - status = "disabled"; - }; - - ux500_serial1: uart@80121000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80121000 0x1000>; - interrupts = ; - - dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ - <&dma 12 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; - clock-names = "uart", "apb_pclk"; - - status = "disabled"; - }; - - ux500_serial2: uart@80007000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80007000 0x1000>; - interrupts = ; - - dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ - <&dma 11 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; - clock-names = "uart", "apb_pclk"; - - status = "disabled"; - }; - - sdi0_per1@80126000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80126000 0x1000>; - interrupts = ; - - dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ - <&dma 29 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi1_per2@80118000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80118000 0x1000>; - interrupts = ; - - dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ - <&dma 32 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi2_per3@80005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80005000 0x1000>; - interrupts = ; - - dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ - <&dma 28 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi3_per2@80119000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80119000 0x1000>; - interrupts = ; - - dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ - <&dma 41 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi4_per2@80114000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80114000 0x1000>; - interrupts = ; - - dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ - <&dma 42 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - sdi5_per3@80008000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80008000 0x1000>; - interrupts = ; - - dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ - <&dma 43 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; - clock-names = "sdi", "apb_pclk"; - power-domains = <&pm_domains DOMAIN_VAPE>; - - status = "disabled"; - }; - - msp0: msp@80123000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80123000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ - <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; - clock-names = "msp", "apb_pclk"; - - status = "disabled"; - }; - - msp1: msp@80124000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80124000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - /* This DMA channel only exist on DB8500 v1 */ - dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ - dma-names = "tx"; - - clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; - clock-names = "msp", "apb_pclk"; - - status = "disabled"; - }; - - // HDMI sound - msp2: msp@80117000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80117000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ - <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev - HighPrio - Fixed */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; - clock-names = "msp", "apb_pclk"; - - status = "disabled"; - }; - - msp3: msp@80125000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80125000 0x1000>; - interrupts = ; - v-ape-supply = <&db8500_vape_reg>; - - /* This DMA channel only exist on DB8500 v2 */ - dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ - dma-names = "rx"; - - clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; - clock-names = "msp", "apb_pclk"; - - status = "disabled"; - }; - - external-bus@50000000 { - compatible = "simple-bus"; - reg = <0x50000000 0x4000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x4000000>; - status = "disabled"; - }; - - cpufreq-cooling { - compatible = "stericsson,db8500-cpufreq-cooling"; - status = "disabled"; - }; - - mcde@a0350000 { - compatible = "stericsson,mcde"; - reg = <0xa0350000 0x1000>, /* MCDE */ - <0xa0351000 0x1000>, /* DSI link 1 */ - <0xa0352000 0x1000>, /* DSI link 2 */ - <0xa0353000 0x1000>; /* DSI link 3 */ - interrupts = ; - clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ - <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ - <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ - <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */ - <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */ - <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */ - <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */ - <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */ - }; - - cryp@a03cb000 { - compatible = "stericsson,ux500-cryp"; - reg = <0xa03cb000 0x1000>; - interrupts = ; - - v-ape-supply = <&db8500_vape_reg>; - clocks = <&prcc_pclk 6 1>; - }; - - hash@a03c2000 { - compatible = "stericsson,ux500-hash"; - reg = <0xa03c2000 0x1000>; - - v-ape-supply = <&db8500_vape_reg>; - clocks = <&prcc_pclk 6 2>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-href-ab8500.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-href-ab8500.dtsi deleted file mode 100644 index 9b69bce92..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright 2014 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/ { - soc { - prcmu@80157000 { - ab8500 { - ab8500-gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio2_default_mode>, - <&gpio4_default_mode>, - <&gpio10_default_mode>, - <&gpio11_default_mode>, - <&gpio12_default_mode>, - <&gpio13_default_mode>, - <&gpio16_default_mode>, - <&gpio24_default_mode>, - <&gpio25_default_mode>, - <&gpio36_default_mode>, - <&gpio37_default_mode>, - <&gpio38_default_mode>, - <&gpio39_default_mode>, - <&gpio42_default_mode>, - <&gpio26_default_mode>, - <&gpio35_default_mode>, - <&ycbcr_default_mode>, - <&pwm_default_mode>, - <&adi1_default_mode>, - <&usbuicc_default_mode>, - <&dmic_default_mode>, - <&extcpena_default_mode>, - <&modsclsda_default_mode>; - - /* - * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 - * are muxed in as GPIO, and configured as INPUT PULL DOWN - */ - gpio2 { - gpio2_default_mode: gpio2_default { - default_mux { - function = "gpio"; - groups = "gpio2_a_1"; - }; - default_cfg { - pins = "GPIO2_T9"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio4 { - gpio4_default_mode: gpio4_default { - default_mux { - function = "gpio"; - groups = "gpio4_a_1"; - }; - default_cfg { - pins = "GPIO4_W2"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio10 { - gpio10_default_mode: gpio10_default { - default_mux { - function = "gpio"; - groups = "gpio10_d_1"; - }; - default_cfg { - pins = "GPIO10_U17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio11 { - gpio11_default_mode: gpio11_default { - default_mux { - function = "gpio"; - groups = "gpio11_d_1"; - }; - default_cfg { - pins = "GPIO11_AA18"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio12 { - gpio12_default_mode: gpio12_default { - default_mux { - function = "gpio"; - groups = "gpio12_d_1"; - }; - default_cfg { - pins = "GPIO12_U16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio13 { - gpio13_default_mode: gpio13_default { - default_mux { - function = "gpio"; - groups = "gpio13_d_1"; - }; - default_cfg { - pins = "GPIO13_W17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio16 { - gpio16_default_mode: gpio16_default { - default_mux { - function = "gpio"; - groups = "gpio16_a_1"; - }; - default_cfg { - pins = "GPIO16_F15"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio24 { - gpio24_default_mode: gpio24_default { - default_mux { - function = "gpio"; - groups = "gpio24_a_1"; - }; - default_cfg { - pins = "GPIO24_T14"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio25 { - gpio25_default_mode: gpio25_default { - default_mux { - function = "gpio"; - groups = "gpio25_a_1"; - }; - default_cfg { - pins = "GPIO25_R16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio36 { - gpio36_default_mode: gpio36_default { - default_mux { - function = "gpio"; - groups = "gpio36_a_1"; - }; - default_cfg { - pins = "GPIO36_A17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio37 { - gpio37_default_mode: gpio37_default { - default_mux { - function = "gpio"; - groups = "gpio37_a_1"; - }; - default_cfg { - pins = "GPIO37_E15"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio38 { - gpio38_default_mode: gpio38_default { - default_mux { - function = "gpio"; - groups = "gpio38_a_1"; - }; - default_cfg { - pins = "GPIO38_C17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio39 { - gpio39_default_mode: gpio39_default { - default_mux { - function = "gpio"; - groups = "gpio39_a_1"; - }; - default_cfg { - pins = "GPIO39_E16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio42 { - gpio42_default_mode: gpio42_default { - default_mux { - function = "gpio"; - groups = "gpio42_a_1"; - }; - default_cfg { - pins = "GPIO42_U2"; - input-enable; - bias-pull-down; - }; - }; - }; - /* - * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW - */ - gpio26 { - gpio26_default_mode: gpio26_default { - default_mux { - function = "gpio"; - groups = "gpio26_d_1"; - }; - default_cfg { - pins = "GPIO26_M16"; - output-low; - }; - }; - }; - gpio35 { - gpio35_default_mode: gpio35_default { - default_mux { - function = "gpio"; - groups = "gpio35_d_1"; - }; - default_cfg { - pins = "GPIO35_W15"; - output-low; - }; - }; - }; - /* - * This sets up the YCBCR connector pins, i.e. analog video out. - * Set as input with no bias. - */ - ycbcr { - ycbcr_default_mode: ycbcr_default { - default_mux { - function = "ycbcr"; - groups = "ycbcr0123_d_1"; - }; - default_cfg { - pins = "GPIO6_Y18", - "GPIO7_AA20", - "GPIO8_W18", - "GPIO9_AA19"; - input-enable; - bias-disable; - }; - }; - }; - /* This sets up the PWM pins 14 and 15 */ - pwm { - pwm_default_mode: pwm_default { - default_mux { - function = "pwmout"; - groups = "pwmout1_d_1", "pwmout2_d_1"; - }; - default_cfg { - pins = "GPIO14_F14", - "GPIO15_B17"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up audio interface 1 */ - adi1 { - adi1_default_mode: adi1_default { - default_mux { - function = "adi1"; - groups = "adi1_d_1"; - }; - default_cfg { - pins = "GPIO17_P5", - "GPIO18_R5", - "GPIO19_U5", - "GPIO20_T5"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up the USB UICC pins */ - usbuicc { - usbuicc_default_mode: usbuicc_default { - default_mux { - function = "usbuicc"; - groups = "usbuicc_d_1"; - }; - default_cfg { - pins = "GPIO21_H19", - "GPIO22_G20", - "GPIO23_G19"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up the microphone pins */ - dmic { - dmic_default_mode: dmic_default { - default_mux { - function = "dmic"; - groups = "dmic12_d_1", - "dmic34_d_1", - "dmic56_d_1"; - }; - default_cfg { - pins = "GPIO27_J6", - "GPIO28_K6", - "GPIO29_G6", - "GPIO30_H6", - "GPIO31_F5", - "GPIO32_G5"; - input-enable; - bias-pull-down; - }; - }; - }; - extcpena { - extcpena_default_mode: extcpena_default { - default_mux { - function = "extcpena"; - groups = "extcpena_d_1"; - }; - default_cfg { - pins = "GPIO34_R17"; - input-enable; - bias-pull-down; - }; - }; - }; - /* Modem I2C setup (SCL and SDA pins) */ - modsclsda { - modsclsda_default_mode: modsclsda_default { - default_mux { - function = "modsclsda"; - groups = "modsclsda_d_1"; - }; - default_cfg { - pins = "GPIO40_T19", - "GPIO41_U19"; - input-enable; - bias-pull-down; - }; - }; - }; - /* - * Clock output pins associated with regulators. - */ - sysclkreq2 { - sysclkreq2_default_mode: sysclkreq2_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq2_d_1"; - }; - default_cfg { - pins = "GPIO1_T10"; - input-enable; - bias-disable; - }; - }; - sysclkreq2_sleep_mode: sysclkreq2_sleep { - default_mux { - function = "gpio"; - groups = "gpio1_a_1"; - }; - default_cfg { - pins = "GPIO1_T10"; - input-enable; - bias-pull-down; - }; - }; - }; - sysclkreq4 { - sysclkreq4_default_mode: sysclkreq4_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq4_d_1"; - }; - default_cfg { - pins = "GPIO3_U9"; - input-enable; - bias-disable; - }; - }; - sysclkreq4_sleep_mode: sysclkreq4_sleep { - default_mux { - function = "gpio"; - groups = "gpio3_a_1"; - }; - default_cfg { - pins = "GPIO3_U9"; - input-enable; - bias-pull-down; - }; - }; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-href-ab8505.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-href-ab8505.dtsi deleted file mode 100644 index ccf37a9df..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-href-ab8505.dtsi +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright 2014 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/ { - soc { - prcmu@80157000 { - ab8505 { - ab8505-gpio { - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&gpio2_default_mode>, - <&gpio10_default_mode>, - <&gpio11_default_mode>, - <&gpio13_default_mode>, - <&gpio34_default_mode>, - <&gpio50_default_mode>, - <&pwm_default_mode>, - <&adi2_default_mode>, - <&modsclsda_default_mode>, - <&resethw_default_mode>, - <&service_default_mode>; - - /* - * Pins 2, 10, 11, 13, 34 and 50 - * are muxed in as GPIO, and configured as INPUT PULL DOWN - */ - gpio2 { - gpio2_default_mode: gpio2_default { - default_mux { - function = "gpio"; - groups = "gpio2_a_1"; - }; - default_cfg { - pins = "GPIO2_R5"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio10 { - gpio10_default_mode: gpio10_default { - default_mux { - function = "gpio"; - groups = "gpio10_d_1"; - }; - default_cfg { - pins = "GPIO10_B16"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio11 { - gpio11_default_mode: gpio11_default { - default_mux { - function = "gpio"; - groups = "gpio11_d_1"; - }; - default_cfg { - pins = "GPIO11_B17"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio13 { - gpio13_default_mode: gpio13_default { - default_mux { - function = "gpio"; - groups = "gpio13_d_1"; - }; - default_cfg { - pins = "GPIO13_D17"; - input-enable; - bias-disable; - }; - }; - }; - gpio34 { - gpio34_default_mode: gpio34_default { - default_mux { - function = "gpio"; - groups = "gpio34_a_1"; - }; - default_cfg { - pins = "GPIO34_H14"; - input-enable; - bias-pull-down; - }; - }; - }; - gpio50 { - gpio50_default_mode: gpio50_default { - default_mux { - function = "gpio"; - groups = "gpio50_d_1"; - }; - default_cfg { - pins = "GPIO50_L4"; - input-enable; - bias-disable; - }; - }; - }; - /* This sets up the PWM pin 14 */ - pwm { - pwm_default_mode: pwm_default { - default_mux { - function = "pwmout"; - groups = "pwmout1_d_1"; - }; - default_cfg { - pins = "GPIO14_C16"; - input-enable; - bias-pull-down; - }; - }; - }; - /* This sets up audio interface 2 */ - adi2 { - adi2_default_mode: adi2_default { - default_mux { - function = "adi2"; - groups = "adi2_d_1"; - }; - default_cfg { - pins = "GPIO17_P2", - "GPIO18_N3", - "GPIO19_T1", - "GPIO20_P3"; - input-enable; - bias-pull-down; - }; - }; - }; - /* Modem I2C setup (SCL and SDA pins) */ - modsclsda { - modsclsda_default_mode: modsclsda_default { - default_mux { - function = "modsclsda"; - groups = "modsclsda_d_1"; - }; - default_cfg { - pins = "GPIO40_J15", - "GPIO41_J14"; - input-enable; - bias-pull-down; - }; - }; - }; - resethw { - resethw_default_mode: resethw_default { - default_mux { - function = "resethw"; - groups = "resethw_d_1"; - }; - default_cfg { - pins = "GPIO52_D16"; - input-enable; - bias-pull-down; - }; - }; - }; - service { - service_default_mode: service_default { - default_mux { - function = "service"; - groups = "service_d_1"; - }; - default_cfg { - pins = "GPIO53_D15"; - input-enable; - bias-pull-down; - }; - }; - }; - /* - * Clock output pins associated with regulators. - */ - sysclkreq2 { - sysclkreq2_default_mode: sysclkreq2_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq2_d_1"; - }; - default_cfg { - pins = "GPIO1_N4"; - input-enable; - bias-disable; - }; - }; - sysclkreq2_sleep_mode: sysclkreq2_sleep { - default_mux { - function = "gpio"; - groups = "gpio1_a_1"; - }; - default_cfg { - pins = "GPIO1_N4"; - input-enable; - bias-pull-down; - }; - }; - }; - sysclkreq4 { - sysclkreq4_default_mode: sysclkreq4_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq4_d_1"; - }; - default_cfg { - pins = "GPIO3_P5"; - input-enable; - bias-disable; - }; - }; - sysclkreq4_sleep_mode: sysclkreq4_sleep { - default_mux { - function = "gpio"; - groups = "gpio3_a_1"; - }; - default_cfg { - pins = "GPIO3_P5"; - input-enable; - bias-pull-down; - }; - }; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi deleted file mode 100644 index 5c5cea232..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ /dev/null @@ -1,745 +0,0 @@ -/* - * Copyright 2013 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "ste-nomadik-pinctrl.dtsi" - -/ { - soc { - pinctrl { - /* Settings for all UART default and sleep states */ - uart0 { - uart0_default_mode: uart0_default { - default_mux { - function = "u0"; - groups = "u0_a_1"; - }; - default_cfg1 { - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ - ste,config = <&in_pu>; - }; - - default_cfg2 { - pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ - ste,config = <&out_hi>; - }; - }; - - uart0_sleep_mode: uart0_sleep { - sleep_cfg1 { - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - - sleep_cfg2 { - pins = "GPIO1_AJ3"; /* RTS */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - - sleep_cfg3 { - pins = "GPIO3_AH3"; /* TXD */ - ste,config = <&slpm_out_wkup_pdis>; - }; - }; - }; - - uart1 { - uart1_default_mode: uart1_default { - default_mux { - function = "u1"; - groups = "u1rxtx_a_1"; - }; - default_cfg1 { - pins = "GPIO4_AH6"; /* RXD */ - ste,config = <&in_pu>; - }; - - default_cfg2 { - pins = "GPIO5_AG6"; /* TXD */ - ste,config = <&out_hi>; - }; - }; - - uart1_sleep_mode: uart1_sleep { - sleep_cfg1 { - pins = "GPIO4_AH6"; /* RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - - sleep_cfg2 { - pins = "GPIO5_AG6"; /* TXD */ - ste,config = <&slpm_out_wkup_pdis>; - }; - }; - }; - - uart2 { - uart2_default_mode: uart2_default { - default_mux { - function = "u2"; - groups = "u2rxtx_c_1"; - }; - default_cfg1 { - pins = "GPIO29_W2"; /* RXD */ - ste,config = <&in_pu>; - }; - - default_cfg2 { - pins = "GPIO30_W3"; /* TXD */ - ste,config = <&out_hi>; - }; - }; - - uart2_sleep_mode: uart2_sleep { - sleep_cfg1 { - pins = "GPIO29_W2"; /* RXD */ - ste,config = <&in_wkup_pdis>; - }; - - sleep_cfg2 { - pins = "GPIO30_W3"; /* TXD */ - ste,config = <&out_wkup_pdis>; - }; - }; - }; - - /* Settings for all I2C default and sleep states */ - i2c0 { - i2c0_default_mode: i2c_default { - default_mux { - function = "i2c0"; - groups = "i2c0_a_1"; - }; - default_cfg1 { - pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ - ste,config = <&in_pu>; - }; - }; - - i2c0_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c1 { - i2c1_default_mode: i2c_default { - default_mux { - function = "i2c1"; - groups = "i2c1_b_2"; - }; - default_cfg1 { - pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ - ste,config = <&in_pu>; - }; - }; - - i2c1_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c2 { - i2c2_default_mode: i2c_default { - default_mux { - function = "i2c2"; - groups = "i2c2_b_2"; - }; - default_cfg1 { - pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ - ste,config = <&in_pu>; - }; - }; - - i2c2_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - i2c3 { - i2c3_default_mode: i2c_default { - default_mux { - function = "i2c3"; - groups = "i2c3_c_2"; - }; - default_cfg1 { - pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ - ste,config = <&in_pu>; - }; - }; - - i2c3_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* - * Activating I2C4 will conflict with UART1 about the same pins so do not - * enable I2C4 and UART1 at the same time. - */ - i2c4 { - i2c4_default_mode: i2c_default { - default_mux { - function = "i2c4"; - groups = "i2c4_b_1"; - }; - default_cfg1 { - pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ - ste,config = <&in_pu>; - }; - }; - - i2c4_sleep_mode: i2c_sleep { - sleep_cfg1 { - pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* Settings for all SPI default and sleep states */ - spi2 { - spi2_default_mode: spi_default { - default_mux { - function = "spi2"; - groups = "spi2_oc1_2"; - }; - default_cfg1 { - pins = "GPIO216_AG12"; /* FRM */ - ste,config = <&gpio_out_hi>; - }; - default_cfg2 { - pins = "GPIO218_AH11"; /* RXD */ - ste,config = <&in_pd>; - }; - default_cfg3 { - pins = - "GPIO215_AH13", /* TXD */ - "GPIO217_AH12"; /* CLK */ - ste,config = <&out_lo>; - }; - }; - - spi2_idle_mode: spi_idle { - /* - * The idle mode is basically sleep mode sans wakeups. Also - * note that we have muxes the pins off the function here - * as we do not state any muxing. - */ - idle_cfg1 { - pins = "GPIO218_AH11"; /* RXD */ - ste,config = <&slpm_in_pdis>; - }; - idle_cfg2 { - pins = "GPIO215_AH13"; /* TXD */ - ste,config = <&slpm_out_lo_pdis>; - }; - idle_cfg3 { - pins = "GPIO217_AH12"; /* CLK */ - ste,config = <&slpm_pdis>; - }; - }; - - spi2_sleep_mode: spi_sleep { - sleep_cfg1 { - pins = - "GPIO216_AG12", /* FRM */ - "GPIO218_AH11"; /* RXD */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg2 { - pins = "GPIO215_AH13"; /* TXD */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - sleep_cfg3 { - pins = "GPIO217_AH12"; /* CLK */ - ste,config = <&slpm_wkup_pdis>; - }; - }; - }; - - /* Settings for all MMC/SD/SDIO default and sleep states */ - sdi0 { - /* This is the external SD card slot, 4 bits wide */ - sdi0_default_mode: sdi0_default { - default_mux { - function = "mc0"; - groups = "mc0_a_1"; - }; - default_cfg1 { - pins = - "GPIO18_AC2", /* CMDDIR */ - "GPIO19_AC1", /* DAT0DIR */ - "GPIO20_AB4"; /* DAT2DIR */ - ste,config = <&out_hi>; - }; - default_cfg2 { - pins = "GPIO22_AA3"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg4 { - pins = - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - sdi0_sleep_mode: sdi0_sleep { - sleep_cfg1 { - pins = - "GPIO18_AC2", /* CMDDIR */ - "GPIO19_AC1", /* DAT0DIR */ - "GPIO20_AB4"; /* DAT2DIR */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO22_AA3", /* FBCLK */ - "GPIO24_AB2", /* CMD */ - "GPIO25_Y4", /* DAT0 */ - "GPIO26_Y2", /* DAT1 */ - "GPIO27_AA2", /* DAT2 */ - "GPIO28_AA1"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - sleep_cfg3 { - pins = "GPIO23_AA4"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - }; - }; - - sdi1 { - /* This is the WLAN SDIO 4 bits wide */ - sdi1_default_mode: sdi1_default { - default_mux { - function = "mc1"; - groups = "mc1_a_1"; - }; - default_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO209_AG15"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&in_pu>; - }; - }; - - sdi1_sleep_mode: sdi1_sleep { - sleep_cfg1 { - pins = "GPIO208_AH16"; /* CLK */ - ste,config = <&slpm_out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO209_AG15", /* FBCLK */ - "GPIO210_AJ15", /* CMD */ - "GPIO211_AG14", /* DAT0 */ - "GPIO212_AF13", /* DAT1 */ - "GPIO213_AG13", /* DAT2 */ - "GPIO214_AH15"; /* DAT3 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - sdi2 { - /* This is the eMMC 8 bits wide, usually PoP eMMC */ - sdi2_default_mode: sdi2_default { - default_mux { - function = "mc2"; - groups = "mc2_a_1"; - }; - default_cfg1 { - pins = "GPIO128_A5"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO130_C8"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO129_B4", /* CMD */ - "GPIO131_A12", /* DAT0 */ - "GPIO132_C10", /* DAT1 */ - "GPIO133_B10", /* DAT2 */ - "GPIO134_B9", /* DAT3 */ - "GPIO135_A9", /* DAT4 */ - "GPIO136_C7", /* DAT5 */ - "GPIO137_A7", /* DAT6 */ - "GPIO138_C5"; /* DAT7 */ - ste,config = <&in_pu>; - }; - }; - - sdi2_sleep_mode: sdi2_sleep { - sleep_cfg1 { - pins = "GPIO128_A5"; /* CLK */ - ste,config = <&out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO130_C8", /* FBCLK */ - "GPIO129_B4"; /* CMD */ - ste,config = <&in_wkup_pdis_en>; - }; - sleep_cfg3 { - pins = - "GPIO131_A12", /* DAT0 */ - "GPIO132_C10", /* DAT1 */ - "GPIO133_B10", /* DAT2 */ - "GPIO134_B9", /* DAT3 */ - "GPIO135_A9", /* DAT4 */ - "GPIO136_C7", /* DAT5 */ - "GPIO137_A7", /* DAT6 */ - "GPIO138_C5"; /* DAT7 */ - ste,config = <&in_wkup_pdis>; - }; - }; - }; - - sdi4 { - /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ - sdi4_default_mode: sdi4_default { - default_mux { - function = "mc4"; - groups = "mc4_a_1"; - }; - default_cfg1 { - pins = "GPIO203_AE23"; /* CLK */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = "GPIO202_AF25"; /* FBCLK */ - ste,config = <&in_nopull>; - }; - default_cfg3 { - pins = - "GPIO201_AF24", /* CMD */ - "GPIO200_AH26", /* DAT0 */ - "GPIO199_AH23", /* DAT1 */ - "GPIO198_AG25", /* DAT2 */ - "GPIO197_AH24", /* DAT3 */ - "GPIO207_AJ23", /* DAT4 */ - "GPIO206_AG24", /* DAT5 */ - "GPIO205_AG23", /* DAT6 */ - "GPIO204_AF23"; /* DAT7 */ - ste,config = <&in_pu>; - }; - }; - - sdi4_sleep_mode: sdi4_sleep { - sleep_cfg1 { - pins = "GPIO203_AE23"; /* CLK */ - ste,config = <&out_lo_wkup_pdis>; - }; - sleep_cfg2 { - pins = - "GPIO202_AF25", /* FBCLK */ - "GPIO201_AF24", /* CMD */ - "GPIO200_AH26", /* DAT0 */ - "GPIO199_AH23", /* DAT1 */ - "GPIO198_AG25", /* DAT2 */ - "GPIO197_AH24", /* DAT3 */ - "GPIO207_AJ23", /* DAT4 */ - "GPIO206_AG24", /* DAT5 */ - "GPIO205_AG23", /* DAT6 */ - "GPIO204_AF23"; /* DAT7 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - /* - * Multi-rate serial ports (MSPs) - MSP3 output is internal and - * cannot be muxed onto any pins. - */ - msp0 { - msp0_default_mode: msp0_default { - default_msp0_mux { - function = "msp0"; - groups = "msp0txrx_a_1", "msp0tfstck_a_1"; - }; - default_msp0_cfg { - pins = - "GPIO12_AC4", /* TXD */ - "GPIO15_AC3", /* RXD */ - "GPIO13_AF3", /* TFS */ - "GPIO14_AE3"; /* TCK */ - ste,config = <&in_nopull>; - }; - }; - }; - - msp1 { - msp1_default_mode: msp1_default { - default_mux { - function = "msp1"; - groups = "msp1txrx_a_1", "msp1_a_1"; - }; - default_cfg1 { - pins = "GPIO33_AF2"; - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = - "GPIO34_AE1", - "GPIO35_AE2", - "GPIO36_AG2"; - ste,config = <&in_nopull>; - }; - - }; - }; - - msp2 { - msp2_default_mode: msp2_default { - /* MSP2 usually used for HDMI audio */ - default_mux { - function = "msp2"; - groups = "msp2_a_1"; - }; - default_cfg1 { - pins = - "GPIO193_AH27", /* TXD */ - "GPIO194_AF27", /* TCK */ - "GPIO195_AG28"; /* TFS */ - ste,config = <&in_pd>; - }; - default_cfg2 { - pins = "GPIO196_AG26"; /* RXD */ - ste,config = <&out_lo>; - }; - }; - }; - - - musb { - musb_default_mode: musb_default { - default_mux { - function = "usb"; - groups = "usb_a_1"; - }; - default_cfg1 { - pins = - "GPIO256_AF28", /* NXT */ - "GPIO258_AD29", /* XCLK */ - "GPIO259_AC29", /* DIR */ - "GPIO260_AD28", /* DAT7 */ - "GPIO261_AD26", /* DAT6 */ - "GPIO262_AE26", /* DAT5 */ - "GPIO263_AG29", /* DAT4 */ - "GPIO264_AE27", /* DAT3 */ - "GPIO265_AD27", /* DAT2 */ - "GPIO266_AC28", /* DAT1 */ - "GPIO267_AC27"; /* DAT0 */ - ste,config = <&in_nopull>; - }; - default_cfg2 { - pins = "GPIO257_AE29"; /* STP */ - ste,config = <&out_hi>; - }; - }; - - musb_sleep_mode: musb_sleep { - sleep_cfg1 { - pins = - "GPIO256_AF28", /* NXT */ - "GPIO258_AD29", /* XCLK */ - "GPIO259_AC29"; /* DIR */ - ste,config = <&slpm_wkup_pdis_en>; - }; - sleep_cfg2 { - pins = "GPIO257_AE29"; /* STP */ - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - sleep_cfg3 { - pins = - "GPIO260_AD28", /* DAT7 */ - "GPIO261_AD26", /* DAT6 */ - "GPIO262_AE26", /* DAT5 */ - "GPIO263_AG29", /* DAT4 */ - "GPIO264_AE27", /* DAT3 */ - "GPIO265_AD27", /* DAT2 */ - "GPIO266_AC28", /* DAT1 */ - "GPIO267_AC27"; /* DAT0 */ - ste,config = <&slpm_in_wkup_pdis_en>; - }; - }; - }; - - mcde { - lcd_default_mode: lcd_default { - default_mux { - /* Mux in VSI0 and all the data lines */ - function = "lcd"; - groups = - "lcdvsi0_a_1", /* VSI0 for LCD */ - "lcd_d0_d7_a_1", /* Data lines */ - "lcd_d8_d11_a_1", /* TV-out */ - "lcdaclk_b_1", /* Clock line for TV-out */ - "lcdvsi1_a_1"; /* VSI1 for HDMI */ - }; - default_cfg1 { - pins = - "GPIO68_E1", /* VSI0 */ - "GPIO69_E2"; /* VSI1 */ - ste,config = <&in_pu>; - }; - }; - lcd_sleep_mode: lcd_sleep { - sleep_cfg1 { - pins = "GPIO69_E2"; /* VSI1 */ - ste,config = <&slpm_in_wkup_pdis>; - }; - }; - }; - - ske { - /* SKE keys on position 2 in an 8x8 matrix */ - ske_kpa2_default_mode: ske_kpa2_default { - default_mux { - function = "kp"; - groups = "kp_a_2"; - }; - default_cfg1 { - pins = - "GPIO153_B17", /* I7 */ - "GPIO154_C16", /* I6 */ - "GPIO155_C19", /* I5 */ - "GPIO156_C17", /* I4 */ - "GPIO161_D21", /* I3 */ - "GPIO162_D20", /* I2 */ - "GPIO163_C20", /* I1 */ - "GPIO164_B21"; /* I0 */ - ste,config = <&in_pd>; - }; - default_cfg2 { - pins = - "GPIO157_A18", /* O7 */ - "GPIO158_C18", /* O6 */ - "GPIO159_B19", /* O5 */ - "GPIO160_B20", /* O4 */ - "GPIO165_C21", /* O3 */ - "GPIO166_A22", /* O2 */ - "GPIO167_B24", /* O1 */ - "GPIO168_C22"; /* O0 */ - ste,config = <&out_lo>; - }; - }; - ske_kpa2_sleep_mode: ske_kpa2_sleep { - sleep_cfg1 { - pins = - "GPIO153_B17", /* I7 */ - "GPIO154_C16", /* I6 */ - "GPIO155_C19", /* I5 */ - "GPIO156_C17", /* I4 */ - "GPIO161_D21", /* I3 */ - "GPIO162_D20", /* I2 */ - "GPIO163_C20", /* I1 */ - "GPIO164_B21"; /* I0 */ - ste,config = <&slpm_in_pu_wkup_pdis_en>; - }; - sleep_cfg2 { - pins = - "GPIO157_A18", /* O7 */ - "GPIO158_C18", /* O6 */ - "GPIO159_B19", /* O5 */ - "GPIO160_B20", /* O4 */ - "GPIO165_C21", /* O3 */ - "GPIO166_A22", /* O2 */ - "GPIO167_B24", /* O1 */ - "GPIO168_C22"; /* O0 */ - ste,config = <&slpm_out_lo_pdis>; - }; - }; - /* - * SKE keys on position 1 and "other C1" combi giving - * six rows of six keys. - */ - ske_kpaoc1_default_mode: ske_kpaoc1_default { - default_mux { - function = "kp"; - groups = "kp_a_1", "kp_oc1_1"; - }; - default_cfg1 { - pins = - "GPIO91_B6", /* KP_O0 */ - "GPIO90_A3", /* KP_O1 */ - "GPIO87_B3", /* KP_O2 */ - "GPIO86_C6", /* KP_O3 */ - "GPIO96_D8", /* KP_O6 */ - "GPIO94_D7"; /* KP_O7 */ - ste,config = <&out_lo>; - }; - default_cfg2 { - pins = - "GPIO93_B7", /* KP_I0 */ - "GPIO92_D6", /* KP_I1 */ - "GPIO89_E6", /* KP_I2 */ - "GPIO88_C4", /* KP_I3 */ - "GPIO97_D9", /* KP_I6 */ - "GPIO95_E8"; /* KP_I7 */ - ste,config = <&in_pu>; - }; - }; - }; - - wlan { - wlan_default_mode: wlan_default { - /* - * Activate this mode with the WLAN chip. - * These are plain GPIO pins used by WLAN - */ - default_cfg1 { - pins = - "GPIO226_AF8", /* WLAN_PMU_EN */ - "GPIO85_D5"; /* WLAN_ENA */ - ste,config = <&gpio_out_lo>; - }; - default_cfg2 { - pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-href-stuib.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-href-stuib.dtsi deleted file mode 100644 index 6f7207560..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-href-stuib.dtsi +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>; - - button@139 { - /* Proximity sensor */ - gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; - linux,code = <11>; /* SW_FRONT_PROXIMITY */ - label = "SFH7741 Proximity Sensor"; - }; - button@145 { - /* Hall sensor */ - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - linux,code = <0>; /* SW_LID */ - label = "HED54XXU11 Hall Effect Sensor"; - }; - }; - - soc { - i2c@80004000 { - stmpe1601: stmpe1601@40 { - compatible = "st,stmpe1601"; - reg = <0x40>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio6>; - interrupt-controller; - vcc-supply = <&db8500_vsmps2_reg>; - vio-supply = <&db8500_vsmps2_reg>; - - wakeup-source; - st,autosleep-timeout = <1024>; - - stmpe_keypad { - compatible = "st,stmpe-keypad"; - - debounce-interval = <64>; - st,scan-count = <8>; - st,no-autorepeat; - - linux,keymap = <0x205006b - 0x4010074 - 0x3050072 - 0x1030004 - 0x502006a - 0x500000a - 0x5008b - 0x706001c - 0x405000b - 0x6070003 - 0x3040067 - 0x303006c - 0x60400e7 - 0x602009e - 0x4020073 - 0x5050002 - 0x4030069 - 0x3020008>; - }; - }; - }; - - /* Sensors mounted on this board variant */ - i2c@80128000 { - lis331dl@1c { - /* Accelerometer */ - compatible = "st,lis331dl-accel"; - st,drdy-int-pin = <1>; - reg = <0x1c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_stuib_mode>; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; - }; - ak8974@0f { - /* Magnetometer */ - compatible = "asahi-kasei,ak8974"; - reg = <0x0f>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_stuib_mode>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c@80110000 { - bu21013_tp@5c { - compatible = "rohm,bu21013_tp"; - reg = <0x5c>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - pinctrl-names = "default"; - pinctrl-0 = <&touch_rohm_mode>; - }; - - bu21013_tp@5d { - compatible = "rohm,bu21013_tp"; - reg = <0x5d>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - pinctrl-names = "default"; - pinctrl-0 = <&touch_rohm_mode>; - }; - }; - - pinctrl { - prox { - prox_stuib_mode: prox_stuib { - stuib_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - hall { - hall_stuib_mode: stuib_tvk { - stuib_cfg { - pins = "GPIO145_C13"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - accelerometer { - accel_stuib_mode: accel_stuib { - /* Accelerometer interrupt lines 1 & 2 */ - stuib_cfg { - pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - magnetometer { - magneto_stuib_mode: magneto_stuib { - /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ - stuib_cfg1 { - pins = "GPIO31_V3"; - ste,config = <&gpio_in_pu>; - }; - stuib_cfg2 { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - touch { - touch_rohm_mode: touch_rohm { - /* - * ROHM touch screen uses GPIO 143 for - * RST1, GPIO 146 for RST2 and - * GPIO 67 for interrupts. Pull-up - * the IRQ line and drive both - * reset signals low. - */ - stuib_cfg1 { - pins = "GPIO143_D12", "GPIO146_D13"; - ste,config = <&gpio_out_lo>; - }; - stuib_cfg2 { - pins = "GPIO67_G2"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-href-tvk1281618.dtsi deleted file mode 100644 index 3c9f2f068..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Device Tree for the TVK1281618 UIB - */ - -#include - -/ { - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>; - - button@139 { - /* Proximity sensor */ - gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; - linux,code = <11>; /* SW_FRONT_PROXIMITY */ - label = "SFH7741 Proximity Sensor"; - }; - button@145 { - /* Hall sensor */ - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; - linux,code = <0>; /* SW_LID */ - label = "HED54XXU11 Hall Effect Sensor"; - }; - }; - - soc { - i2c@80004000 { - tc35893@44 { - compatible = "toshiba,tc35893"; - reg = <0x44>; - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tc35893_tvk_mode>; - - interrupt-controller; - #interrupt-cells = <1>; - - tc3589x_gpio { - compatible = "toshiba,tc3589x-gpio"; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - tc3589x_keypad { - compatible = "toshiba,tc3589x-keypad"; - interrupts = <6>; - debounce-delay-ms = <4>; - keypad,num-columns = <8>; - keypad,num-rows = <8>; - linux,no-autorepeat; - wakeup-source; - linux,keymap = <0x0301006b - 0x04010066 - 0x06040072 - 0x040200d7 - 0x0303006a - 0x0205000e - 0x0607008b - 0x0500001c - 0x0403000b - 0x03040034 - 0x05020067 - 0x0305006c - 0x040500e7 - 0x0005009e - 0x06020073 - 0x01030039 - 0x07060069 - 0x050500d9>; - }; - }; - }; - /* Sensors mounted on this board variant */ - i2c@80128000 { - lsm303dlh@18 { - /* Accelerometer */ - compatible = "st,lsm303dlh-accel"; - st,drdy-int-pin = <1>; - drive-open-drain; - reg = <0x18>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_tvk_mode>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; - */ - }; - lsm303dlh@1e { - /* Magnetometer */ - compatible = "st,lsm303dlh-magn"; - reg = <0x1e>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; - */ - }; - lis331dl@1c { - /* Accelerometer */ - compatible = "st,lis331dl-accel"; - st,drdy-int-pin = <1>; - reg = <0x1c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_tvk_mode>; - interrupt-parent = <&gpio2>; - /* INT2 would need to be open drain */ - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; - }; - ak8974@0f { - /* Magnetometer */ - compatible = "asahi-kasei,ak8974"; - reg = <0x0f>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - dvdd-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_magn_tvk_mode>; - /* - * These interrupts cannot be used: the other component - * ST-Micro L3D4200D gyro that is connected to the same lines - * cannot set its DRDY line to open drain, so it cannot be - * shared with other peripherals. The should be defined for - * the falling edge if they could be wired together. - * - * interrupts-extended = - * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, - * <&gpio0 31 IRQ_TYPE_EDGE_FALLING>; - */ - }; - l3g4200d@68 { - /* Gyroscope */ - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x68>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_magn_tvk_mode>; - interrupts-extended = - <&gpio1 0 IRQ_TYPE_EDGE_RISING>, - <&gpio0 31 IRQ_TYPE_EDGE_RISING>; - }; - lsp001wm@5c { - /* Barometer/pressure sensor */ - compatible = "st,lps001wp-press"; - reg = <0x5c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - }; - - i2c@80110000 { - synaptics@4b { - /* Synaptics RMI4 TM1217 touchscreen */ - compatible = "syna,rmi4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4b>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&synaptics_tvk_mode>; - interrupt-parent = <&gpio2>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - - rmi-f01@1 { - reg = <0x1>; - syna,nosleep = <1>; - }; - rmi-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - syna,sensor-type = <1>; - }; - }; - }; - - pinctrl { - /* Pull up this GPIO pin */ - tc35893 { - tc35893_tvk_mode: tc35893_tvk { - tvk_cfg { - pins = "GPIO218_AH11"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - prox { - prox_tvk_mode: prox_tvk { - tvk_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - hall { - hall_tvk_mode: hall_tvk { - tvk_cfg { - pins = "GPIO145_C13"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - accelerometer { - accel_tvk_mode: accel_tvk { - /* Accelerometer interrupt lines 1 & 2 */ - tvk_cfg { - pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - gyroscope { - /* - * These lines are shared between Gyroscope l3g400dh - * and AK8974 magnetometer. - */ - gyro_magn_tvk_mode: gyro_magn_tvk { - /* GPIO 31 used for INT pull down the line */ - tvk_cfg1 { - pins = "GPIO31_V3"; - ste,config = <&gpio_in_pd>; - }; - /* GPIO 32 used for DRDY, pull this down */ - tvk_cfg2 { - pins = "GPIO32_V2"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - synaptics { - synaptics_tvk_mode: synaptics_tvk { - /* Touchscreen uses GPIO 84 */ - tvk_cfg1 { - pins = "GPIO84_C2"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-href.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-href.dtsi deleted file mode 100644 index 48dc38482..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-href.dtsi +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include "ste-dbx5x0.dtsi" -#include "ste-href-family-pinctrl.dtsi" - -/ { - memory { - reg = <0x00000000 0x20000000>; - }; - - soc { - usb_per5@a03e0000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&musb_default_mode>; - pinctrl-1 = <&musb_sleep_mode>; - }; - - uart@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_default_mode>; - pinctrl-1 = <&uart0_sleep_mode>; - status = "okay"; - }; - - /* This UART is unused and thus left disabled */ - uart@80121000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart1_default_mode>; - pinctrl-1 = <&uart1_sleep_mode>; - }; - - uart@80007000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart2_default_mode>; - pinctrl-1 = <&uart2_sleep_mode>; - status = "okay"; - }; - - i2c@80004000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c0_default_mode>; - pinctrl-1 = <&i2c0_sleep_mode>; - }; - - i2c@80122000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_default_mode>; - pinctrl-1 = <&i2c1_sleep_mode>; - }; - - i2c@80128000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c2_default_mode>; - pinctrl-1 = <&i2c2_sleep_mode>; - lp5521@33 { - compatible = "national,lp5521"; - reg = <0x33>; - label = "lp5521_pri"; - clock-mode = /bits/ 8 <2>; - chan0 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - linux,default-trigger = "heartbeat"; - }; - chan1 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - chan2 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - }; - lp5521@34 { - compatible = "national,lp5521"; - reg = <0x34>; - label = "lp5521_sec"; - clock-mode = /bits/ 8 <2>; - chan0 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - chan1 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - chan2 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - }; - bh1780@29 { - compatible = "rohm,bh1780gli"; - reg = <0x29>; - }; - }; - - i2c@80110000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c3_default_mode>; - pinctrl-1 = <&i2c3_sleep_mode>; - }; - - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - enable-active-high; - - states = <1800000 0x1 - 2900000 0x0>; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - full-pwr-cycle; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-cmd; - st,sig-pin-fbclk; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&vmmci>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdi0_default_mode>; - pinctrl-1 = <&sdi0_sleep_mode>; - - status = "okay"; - }; - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - non-removable; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdi1_default_mode>; - pinctrl-1 = <&sdi1_sleep_mode>; - - status = "okay"; - }; - - // PoP:ed eMMC - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - vmmc-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdi2_default_mode>; - pinctrl-1 = <&sdi2_sleep_mode>; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdi4_default_mode>; - pinctrl-1 = <&sdi4_sleep_mode>; - - status = "okay"; - }; - - sound { - compatible = "stericsson,snd-soc-mop500"; - - stericsson,cpu-dai = <&msp1 &msp3>; - stericsson,audio-codec = <&codec>; - }; - - msp0: msp@80123000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp0_default_mode>; - status = "okay"; - }; - - msp1: msp@80124000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp1_default_mode>; - status = "okay"; - }; - - msp2: msp@80117000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp2_default_mode>; - }; - - msp3: msp@80125000 { - status = "okay"; - }; - - prcmu@80157000 { - ab8500 { - ab8500-gpio { - }; - - ab8500-regulators { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_usb_reg: ab8500_ldo_usb { - regulator-name = "dummy"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - - mcde@a0350000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_default_mode>; - pinctrl-1 = <&lcd_sleep_mode>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60-stuib.dts deleted file mode 100644 index 18e9795a9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60-stuib.dts +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-hrefprev60.dtsi" -#include "ste-href-stuib.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) and ST UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; - - soc { - /* Reset line for the BU21013 touchscreen */ - i2c@80110000 { - /* Only one of these will be used */ - bu21013_tp@5c { - touch-gpio = <&gpio2 12 0x4>; - reset-gpio = <&tc3589x_gpio 13 0x4>; - }; - bu21013_tp@5d { - touch-gpio = <&gpio2 12 0x4>; - reset-gpio = <&tc3589x_gpio 13 0x4>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60-tvk.dts deleted file mode 100644 index 24739914e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60-tvk.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-hrefprev60.dtsi" -#include "ste-href-tvk1281618.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) and TVK1281618 UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60.dtsi deleted file mode 100644 index ece222d51..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Device Tree for the HREF+ prior to the v60 variant. - */ - -#include "ste-dbx5x0.dtsi" -#include "ste-href-ab8500.dtsi" -#include "ste-href.dtsi" - -/ { - gpio_keys { - button@1 { - gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>; - }; - }; - - soc { - /* Enable UART1 on this board */ - uart@80121000 { - status = "okay"; - }; - - i2c@80004000 { - tps61052@33 { - compatible = "tps61052"; - reg = <0x33>; - }; - - tc35892@42 { - compatible = "toshiba,tc35892"; - reg = <0x42>; - interrupt-parent = <&gpio6>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&tc35892_hrefprev60_mode>; - - interrupt-controller; - #interrupt-cells = <1>; - - tc3589x_gpio: tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - - ssp@80002000 { - /* - * On the first generation boards, this SSP/SPI port was connected - * to the AB8500. - */ - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_hrefprev60_mode>; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>; - }; - - vmmci: regulator-gpio { - gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; - enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; - }; - - pinctrl { - /* Set this up using hogs */ - pinctrl-names = "default"; - pinctrl-0 = <&ipgpio_hrefprev60_mode>; - - ssp0 { - ssp0_hrefprev60_mode: ssp0_hrefprev60_default { - hrefprev60_mux { - function = "ssp0"; - groups = "ssp0_a_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO145_C13"; /* RXD */ - ste,config = <&in_pd>; - }; - - }; - }; - sdi0 { - /* This additional pin needed on early MOP500 and HREFs previous to v60 */ - sdi0_default_mode: sdi0_default { - hrefprev60_mux { - function = "mc0"; - groups = "mc0dat31dir_a_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO21_AB3"; /* DAT31DIR */ - ste,config = <&out_hi>; - }; - - }; - }; - tc35892 { - tc35892_hrefprev60_mode: tc35892_hrefprev60 { - hrefprev60_cfg { - pins = "GPIO217_AH12"; - ste,config = <&gpio_in_pu>; - }; - }; - }; - ipgpio { - ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { - hrefprev60_mux { - function = "ipgpio"; - groups = "ipgpio0_c_1", "ipgpio1_c_1"; - }; - hrefprev60_cfg1 { - pins = "GPIO6_AF6", "GPIO7_AG5"; - ste,config = <&in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts deleted file mode 100644 index c2e1ba019..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Device Tree for the HREF version 60 or later with the ST UIB - */ - -/dts-v1/; -#include "ste-hrefv60plus.dtsi" -#include "ste-href-stuib.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) and ST UIB"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; - - soc { - /* Reset line for the BU21013 touchscreen */ - i2c@80110000 { - /* Only one of these will be used */ - bu21013_tp@5c { - touch-gpio = <&gpio2 20 0x4>; - reset-gpio = <&gpio4 17 0x4>; - }; - bu21013_tp@5d { - touch-gpio = <&gpio2 20 0x4>; - reset-gpio = <&gpio4 17 0x4>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts deleted file mode 100644 index ebd8547e9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Device Tree for the HREF version 60 or later with the TVK1281618 UIB - */ - -/dts-v1/; -#include "ste-hrefv60plus.dtsi" -#include "ste-href-tvk1281618.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) and TVK1281618 UIB"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus.dtsi deleted file mode 100644 index 718767683..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "ste-dbx5x0.dtsi" -#include "ste-href-ab8500.dtsi" -#include "ste-href.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) platform with Device Tree"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - soc { - /* Name the GPIO muxed rails on the HREF boards */ - gpio@8012e000 { - /* GPIOs 0 - 31 */ - gpio-line-names = - /* GPIO0,1 used for UART0 BT RX/TX */ - "", "", - "UART_WAKE", - "BT_WAKE", - "", - "SDMMC_1V8_3V_SEL", - "FLASH_LED_SYNC (FLASH_CTRL_0)", - "XENON_READY (FLASH_CTRL_1)", - "", "", "", "", "", "", "", "", - "", "", "", "", - "", - "FLASH_LED_EN (FLASH_CTRL_3)", - "", "", - "", "", "", "", "", - /* Used by UART2 (console) */ - "", "", - "MAGNETOMETER_INT"; - }; - - gpio@8012e080 { - /* GPIOs 32 - 63 */ - gpio-line-names = - "MAGNETOMETER_DRDY", - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e000 { - /* GPIOs 64 - 95 */ - gpio-line-names = "XENON_EN2 (FLASH_CTRL_4)", - "DISP1_RST", - "DISP2_RST", - "TOUCH_INT2", - "LCD_VSI0_A", - "LCD_VSI1_A", - /* GPIO 70-77 used for ETM */ - "", "", "", "", "", "", "", "", - /* GPIO 78-81 used for YCBCR */ - "", "", "", "", - "ACCELEROMETER_INT1_RDY", - "ACCELEROMETER_INT2", - "TOUCH_INT", - "WLAN_ENA", - "", "", "", "", "", - "FORCE_SENSING_INT", - "FORCE_SENSING_RESET", - "", "", - "SDMMC_CD"; - }; - - gpio@8000e080 { - /* GPIOs 96 - 127 */ - gpio-line-names = "", - "FORCE_SENSING_WU", - "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e100 { - /* GPIOs 128 - 159 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", - "DIPRO_INT", /* GPIO139 */ - "XSHUTDOWN_SECONDARY_SENSOR", - "XSHUTDOWN_PRIMARY_SENSOR", - "NFC_RST (NFC_CTRL_", - "TOUCH_RST", - "NFC_IRQ (NFC_CTRL_1)", - "HAL_SW", - "TOUCH_RST2", - "", "", - "VAUDIO_HF_EN", /* GPIO149 */ - "", "", "", "", "", "", "", "", "", ""; - }; - - gpio@8000e180 { - /* GPIOs 160 - 191 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", - "SDMMC_EN", - "XENON_CHARGE (FLASH_CONTROL_5)", - "GBF_ENA_RESET", - "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8011e000 { - /* GPIOs 192 - 223 */ - gpio-line-names = "HDTV_INTN", - "", "", "", - "HDTV_RSTN", - "", "", "", - "", /* GPIO200 */ - "", "", "", "", "", "", "", - /* GPIO208-216 used for WGBF_MC1 */ - "", "", "", "", "", "", "", "", "", - "SW_FRONT_PROXIMITY", /* GPIO217 */ - "KPD_CTRL_INT", /* Keypad controller */ - "", "", "", "", ""; - }; - - gpio@8011e080 { - /* GPIOs 224 - 255 */ - gpio-line-names = "", "", - "HSIT_ACWAKE0", - "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95 - }; - - vmmci: regulator-gpio { - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; - }; - - pinctrl { - /* - * Set this up using hogs, as time goes by and as seems fit, these - * can be moved over to being controlled by respective device. - */ - pinctrl-names = "default"; - pinctrl-0 = <&ipgpio_hrefv60_mode>, - <&etm_hrefv60_mode>, - <&nahj_hrefv60_mode>, - <&nfc_hrefv60_mode>, - <&force_hrefv60_mode>, - <&dipro_hrefv60_mode>, - <&vaudio_hf_hrefv60_mode>, - <&gbf_hrefv60_mode>, - <&hdtv_hrefv60_mode>, - <&gpios_hrefv60_mode>; - - sdi0 { - sdi0_default_mode: sdi0_default { - /* SD card detect GPIO pin, extend default state */ - default_hrefv60_cfg1 { - pins = "GPIO95_E8"; - ste,config = <&gpio_in_pu>; - }; - /* VMMCI level-shifter enable */ - default_hrefv60_cfg2 { - pins = "GPIO169_D22"; - ste,config = <&gpio_out_hi>; - }; - /* VMMCI level-shifter voltage select */ - default_hrefv60_cfg3 { - pins = "GPIO5_AG6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - ipgpio { - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant - * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias - * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. - */ - ipgpio_hrefv60_mode: ipgpio_hrefv60 { - hrefv60_mux { - function = "ipgpio"; - groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; - }; - hrefv60_cfg1 { - pins = "GPIO6_AF6", "GPIO7_AG5"; - ste,config = <&in_pu>; - }; - hrefv60_cfg2 { - pins = "GPIO21_AB3"; - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg3 { - pins = "GPIO64_F3"; - ste,config = <&out_lo>; - }; - }; - }; - etm { - /* - * Drive D19-D23 for the ETM PTM trace interface low, - * (presumably pins are unconnected therefore grounded here, - * the "other alt C1" setting enables these pins) - */ - etm_hrefv60_mode: etm_hrefv60 { - hrefv60_cfg1 { - pins = - "GPIO70_G5", - "GPIO71_G4", - "GPIO72_H4", - "GPIO73_H3", - "GPIO74_J3"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - nahj { - nahj_hrefv60_mode: nahj_hrefv60 { - /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ - hrefv60_cfg1 { - pins = "GPIO76_J2"; - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg2 { - pins = "GPIO216_AG12"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - nfc { - nfc_hrefv60_mode: nfc_hrefv60 { - /* NFC ENA and RESET to low, pulldown IRQ line */ - hrefv60_cfg1 { - pins = - "GPIO77_H1", /* NFC_ENA */ - "GPIO142_C11"; /* NFC_RESET */ - ste,config = <&gpio_out_lo>; - }; - hrefv60_cfg2 { - pins = "GPIO144_B13"; /* NFC_IRQ */ - ste,config = <&gpio_in_pd>; - }; - }; - }; - force { - force_hrefv60_mode: force_hrefv60 { - hrefv60_cfg1 { - pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ - ste,config = <&gpio_in_pu>; - }; - hrefv60_cfg2 { - pins = - "GPIO92_D6", /* FORCE_SENSING_RST */ - "GPIO97_D9"; /* FORCE_SENSING_WU */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - dipro { - dipro_hrefv60_mode: dipro_hrefv60 { - hrefv60_cfg1 { - pins = "GPIO139_C9"; /* DIPRO_INT */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - vaudio_hf { - vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { - /* Audio Amplifier HF enable GPIO */ - hrefv60_cfg1 { - pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ - ste,config = <&gpio_out_hi>; - }; - }; - }; - gbf { - gbf_hrefv60_mode: gbf_hrefv60 { - /* - * GBF (GPS, Bluetooth, FM-radio) interface, - * pull low to reset state - */ - hrefv60_cfg1 { - pins = "GPIO171_D23"; /* GBF_ENA_RESET */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - hdtv { - hdtv_hrefv60_mode: hdtv_hrefv60 { - /* MSP : HDTV INTERFACE GPIO line */ - hrefv60_cfg1 { - pins = "GPIO192_AJ27"; - ste,config = <&gpio_in_pd>; - }; - }; - }; - mcde { - lcd_hrefv60_mode: lcd_hrefv60 { - /* - * Display Interface 1 uses GPIO 65 for RST (reset). - * Display Interface 2 uses GPIO 66 for RST (reset). - * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) - */ - hrefv60_cfg1 { - pins ="GPIO65_F1"; - ste,config = <&gpio_out_hi>; - }; - hrefv60_cfg2 { - pins ="GPIO66_G3"; - ste,config = <&gpio_out_lo>; - }; - }; - }; - gpios { - /* Dangling GPIO pins */ - gpios_hrefv60_mode: gpios_hrefv60 { - default_cfg1 { - /* Normally UART1 RXD, now dangling */ - pins = "GPIO4_AH6"; - ste,config = <&in_pu>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-nhk15.dts deleted file mode 100644 index 1ec46a794..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Device Tree for the ST-Ericsson Nomadik S8815 board - * Produced by Calao Systems - */ - -/dts-v1/; -#include -#include -#include "ste-nomadik-stn8815.dtsi" - -/ { - model = "Nomadik STN8815NHK"; - compatible = "st,nomadik-nhk-15"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - stmpe-i2c0 = &stmpe0; - stmpe-i2c1 = &stmpe1; - }; - - pinctrl { - uart0 { - uart0_nhk_mode: uart0_mux { - u0_default_mux { - function = "u0"; - groups = "u0txrx_a_1", "u0ctsrts_a_1"; - }; - }; - }; - - stmpe2401_1 { - stmpe2401_1_nhk_mode: stmpe2401_1_nhk { - nhk_cfg1 { - pins = "GPIO76_B20"; // IRQ line - ste,input = <0>; - }; - nhk_cfg2 { - pins = "GPIO77_B8"; // reset line - ste,output = <1>; - }; - }; - }; - stmpe2401_2 { - stmpe2401_2_nhk_mode: stmpe2401_2_nhk { - nhk_cfg1 { - pins = "GPIO78_A8"; // IRQ line - ste,input = <0>; - }; - nhk_cfg2 { - pins = "GPIO79_C9"; // reset line - ste,output = <1>; - }; - }; - }; - lis3lv02dl { - lis3lv02dl_nhk_mode: lis3lv02dl_nhk { - nhk_cfg1 { - pins = "GPIO82_C10"; // IRQ line - ste,input = <0>; - }; - }; - }; - }; - src@101e0000 { - /* These chrystal outputs are not used on this board */ - disable-sxtalo; - disable-mxtalo; - }; - - /* This is where the interrupt is routed on the NHK-15 debug board */ - external-bus@34000000 { - compatible = "simple-bus"; - reg = <0x34000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x34000000 0x1000000>; - ethernet@300 { - compatible = "smsc,lan91c111"; - reg = <0x300 0x0fd00>; - reg-io-width = <2>; - reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&stmpe_gpio44>; - interrupts = <11 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c0 { - lis3lv02dl@1d { - /* Accelerometer */ - compatible = "st,lis3lv02dl-accel"; - interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>; // GPIO 82 - pinctrl-0 = <&lis3lv02dl_nhk_mode>; - pinctrl-names = "default"; - reg = <0x1d>; - }; - stmpe0: stmpe2401@43 { - compatible = "st,stmpe2401"; - reg = <0x43>; - reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 - interrupt-parent = <&gpio2>; - interrupt-controller; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&stmpe2401_1_nhk_mode>; - stmpe_gpio43: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - /* Some pins in alternate functions */ - st,norequest-mask = <0xf0f002>; - }; - stmpe_keypad { - compatible = "st,stmpe-keypad"; - debounce-interval = <64>; - st,scan-count = <8>; - st,no-autorepeat; - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = <0x00020072 // Vol down - 0x00030073 // Vol up - 0x0100009e // Back - 0x010100e3 // TV out - 0x01020098 // Lock - 0x0103013b // Start - 0x020000a3 // Next - 0x020100a4 // Play - 0x020200a5 // Prev - 0x02030160 // OK - 0x03000069 // Left - 0x0301006a // Right - 0x03020067 // Up - 0x0303006c>; // Down - }; - stmpe0_pwm: stmpe_pwm { - compatible = "st,stmpe-pwm"; - #pwm-cells = <2>; - }; - }; - stmpe1: stmpe2401@44 { - compatible = "st,stmpe2401"; - reg = <0x44>; - reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 - interrupt-parent = <&gpio2>; - interrupt-controller; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&stmpe2401_2_nhk_mode>; - stmpe_gpio44: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - /* - * This will turn off SATA so that MMC/SD - * can thrive - */ - mmcsd-gpio { - gpio-hog; - gpios = <2 0x0>; - output-low; - line-name = "SATA EN"; - }; - }; - }; - }; - - amba { - clcd@10120000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&clcd_24bit_mux>; - port { - nomadik_clcd_pads: endpoint { - remote-endpoint = <&nomadik_clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <16 8 0>; - }; - }; - - /* - * WVGA connector 21 - * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB - * with TPO touch screen. - */ - panel { - compatible = "tpo,tpg110", "panel-dpi"; - grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; - scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - backlight = <&bl>; - - port { - nomadik_clcd_panel: endpoint { - remote-endpoint = <&nomadik_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <33200000>; - hactive = <800>; - hback-porch = <216>; - hfront-porch = <40>; - hsync-len = <1>; - vactive = <480>; - vback-porch = <35>; - vfront-porch = <10>; - vsync-len = <1>; - }; - }; - }; - - /* Activate RX/TX and CTS/RTS on UART 0 */ - uart0: uart@101fd000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_nhk_mode>; - status = "okay"; - }; - mmcsd: sdi@101f6000 { - cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pwms = <&stmpe0_pwm 0 500000>; - pwm-names = "backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100 - >; - default-brightness-level = <100>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi deleted file mode 100644 index e6f22b266..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include - -/ { - in_nopull: in_nopull { - ste,input = ; - }; - - in_pu: input_pull_up { - ste,input = ; - }; - - in_pd: input_pull_down { - ste,input = ; - }; - - out_hi: output_high { - ste,output = ; - }; - - out_lo: output_low { - ste,output = ; - }; - - gpio_in_pu: gpio_input_pull_up { - ste,gpio = ; - ste,input = ; - }; - - gpio_in_pd: gpio_input_pull_down { - ste,gpio = ; - ste,input = ; - }; - - gpio_out_lo: gpio_output_low { - ste,gpio = ; - ste,output = ; - }; - - gpio_out_hi: gpio_output_high { - ste,gpio = ; - ste,output = ; - }; - - slpm_pdis: slpm_pdis { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_wkup_pdis: slpm_wkup_pdis { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_wkup_pdis_en: slpm_wkup_pdis_en { - ste,sleep = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_pu: slpm_in_pu { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - }; - - slpm_in_pdis: slpm_in_pdis { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_wkup_pdis: slpm_in_wkup_pdis { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en { - ste,sleep = ; - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo: slpm_out_lo { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - }; - - slpm_out_hi: slpm_out_hi { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - }; - - slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo_pdis: slpm_out_lo_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - slpm_out_wkup_pdis: slpm_out_wkup_pdis { - ste,sleep = ; - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - in_wkup_pdis: in_wkup_pdis { - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - in_wkup_pdis_en: in_wkup_pdis_en { - ste,sleep-input = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_lo_wkup_pdis: out_lo_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_hi_wkup_pdis: out_hi_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; - - out_wkup_pdis: out_wkup_pdis { - ste,sleep-output = ; - ste,sleep-wakeup = ; - ste,sleep-pull-disable = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-s8815.dts b/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-s8815.dts deleted file mode 100644 index 789329030..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Device Tree for the ST-Ericsson Nomadik S8815 board - * Produced by Calao Systems - */ - -/dts-v1/; -#include -#include "ste-nomadik-stn8815.dtsi" - -/ { - model = "Calao Systems USB-S8815"; - compatible = "calaosystems,usb-s8815"; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - gpio3: gpio@101e7000 { - /* This hog will bias the MMC/SD card detect line */ - mmcsd-gpio { - gpio-hog; - gpios = <16 0x0>; - output-low; - line-name = "card detect bias"; - }; - }; - - src@101e0000 { - /* These chrystal drivers are not used on this board */ - disable-sxtalo; - disable-mxtalo; - }; - - pinctrl { - /* Hog CD pins */ - pinctrl-names = "default"; - pinctrl-0 = <&cd_default_mode>; - - uart0 { - /* Only use RX/TX pins */ - uart0_s8815_mode: uart0_mux { - u0_default_mux { - function = "u0"; - groups = "u0txrx_a_1"; - }; - }; - }; - mmcsd-cd { - cd_default_mode: cd_default { - cd_default_cfg1 { - /* CD input GPIO */ - pins = "GPIO111_H21"; - ste,input = <0>; - }; - cd_default_cfg2 { - /* CD GPIO biasing */ - pins = "GPIO112_J21"; - ste,output = <0>; - }; - }; - }; - gpioi2c { - gpioi2c_default_mode: gpioi2c_default { - gpioi2c_default_cfg { - pins = "GPIO73_C21", "GPIO74_C20"; - ste,input = <0>; - }; - }; - }; - user-led { - user_led_default_mode: user_led_default { - user_led_default_cfg { - pins = "GPIO2_C5"; - ste,output = <1>; - }; - }; - }; - user-button { - user_button_default_mode: user_button_default { - user_button_default_cfg { - pins = "GPIO3_A4"; - ste,input = <0>; - }; - }; - }; - }; - - /* Ethernet */ - external-bus@34000000 { - compatible = "simple-bus"; - reg = <0x34000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x34000000 0x1000000>; - ethernet@300 { - compatible = "smsc,lan91c111"; - reg = <0x300 0x0fd00>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - }; - }; - - i2c1 { - lis3lv02dl@1d { - /* Accelerometer */ - compatible = "st,lis3lv02dl-accel"; - reg = <0x1d>; - }; - }; - - /* GPIO I2C connected to the USB portions of the STw4811 only */ - gpio-i2c { - compatible = "i2c-gpio"; - gpios = <&gpio2 10 0>, /* sda */ - <&gpio2 9 0>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&gpioi2c_default_mode>; - - stw4811@2d { - compatible = "st,stw4811-usb"; - reg = <0x2d>; - }; - }; - - - amba { - /* Activate RXTX on UART 0 */ - uart0: uart@101fd000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_s8815_mode>; - status = "okay"; - }; - /* Configure card detect for the uSD slot */ - mmcsd: sdi@101f6000 { - cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - }; - - /* The user LED on the board is set up to be used for heartbeat */ - leds { - compatible = "gpio-leds"; - user-led { - label = "user_led"; - gpios = <&gpio0 2 0x1>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led_default_mode>; - }; - }; - - /* User key mapped in as "escape" */ - gpio-keys { - compatible = "gpio-keys"; - user-button { - label = "user_button"; - gpios = <&gpio0 3 0x1>; - linux,code = <1>; /* KEY_ESC */ - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&user_button_default_mode>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi deleted file mode 100644 index 1077ceebb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ /dev/null @@ -1,884 +0,0 @@ -/* - * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC - */ - -#include -#include "skeleton.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0x00000000 0x04000000>, - <0x08000000 0x04000000>; - }; - - L2: l2-cache { - compatible = "arm,l210-cache"; - reg = <0x10210000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <30>; - cache-unified; - cache-level = <2>; - cache-size = <131072>; - cache-sets = <512>; - cache-line-size = <32>; - /* At full speed latency must be >=2 */ - arm,tag-latency = <8>; - arm,data-latency = <8 8>; - arm,dirty-latency = <8>; - }; - - mtu0: mtu@101e2000 { - /* Nomadik system timer */ - compatible = "st,nomadik-mtu"; - reg = <0x101e2000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <4>; - clocks = <&timclk>, <&pclk>; - clock-names = "timclk", "apb_pclk"; - }; - - mtu1: mtu@101e3000 { - /* Secondary timer */ - reg = <0x101e3000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <5>; - clocks = <&timclk>, <&pclk>; - clock-names = "timclk", "apb_pclk"; - }; - - gpio0: gpio@101e4000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e4000 0x80>; - interrupt-parent = <&vica>; - interrupts = <6>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - clocks = <&pclk>; - }; - - gpio1: gpio@101e5000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e5000 0x80>; - interrupt-parent = <&vica>; - interrupts = <7>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 32>; - clocks = <&pclk>; - }; - - gpio2: gpio@101e6000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e6000 0x80>; - interrupt-parent = <&vica>; - interrupts = <8>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <2>; - gpio-ranges = <&pinctrl 0 64 32>; - clocks = <&pclk>; - }; - - gpio3: gpio@101e7000 { - compatible = "st,nomadik-gpio"; - reg = <0x101e7000 0x80>; - ngpio = <28>; - interrupt-parent = <&vica>; - interrupts = <9>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <3>; - gpio-ranges = <&pinctrl 0 96 28>; - clocks = <&pclk>; - }; - - pinctrl: pinctrl { - compatible = "stericsson,stn8815-pinctrl"; - nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; - /* Pin configurations */ - uart1 { - uart1_default_mux: uart1_mux { - u1_default_mux { - function = "u1"; - groups = "u1_a_1"; - }; - }; - }; - mmcsd { - mmcsd_default_mux: mmcsd_mux { - mmcsd_default_mux { - function = "mmcsd"; - groups = "mmcsd_a_1", "mmcsd_b_1"; - }; - }; - mmcsd_default_mode: mmcsd_default { - mmcsd_default_cfg1 { - /* - * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 - * MCCMD, MCDAT3-0, MCMSFBCLK - */ - pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11", - "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12", - "GPIO16_C13", "GPIO23_D15", "GPIO24_C15"; - ste,output = <2>; - }; - }; - }; - i2c0 { - i2c0_default_mux: i2c0_mux { - i2c0_default_mux { - function = "i2c0"; - groups = "i2c0_a_1"; - }; - }; - i2c0_default_mode: i2c0_default { - i2c0_default_cfg { - pins = "GPIO62_D3", "GPIO63_D2"; - ste,input = <0>; - }; - }; - }; - i2c1 { - i2c1_default_mux: i2c1_mux { - i2c1_default_mux { - function = "i2c1"; - groups = "i2c1_a_1"; - }; - }; - i2c1_default_mode: i2c1_default { - i2c1_default_cfg { - pins = "GPIO53_L4", "GPIO54_L3"; - ste,input = <0>; - }; - }; - }; - clcd { - /* - * This should be activated to use the additional - * 8 lines for bits 16 thru 23 from the CLCD block. - */ - clcd_24bit_mux: clcd_mux { - clcd_24bit_mux { - function = "clcd"; - groups = "clcd_16_23_b_1"; - }; - }; - }; - }; - - /* Power Management Unit */ - pmu: pmu@101e9000 { - compatible = "stericsson,nomadik-pmu", "syscon"; - reg = <0x101e0000 0x1000>; - }; - - src: src@101e0000 { - compatible = "stericsson,nomadik-src"; - reg = <0x101e0000 0x1000>; - - /* - * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz - * that is parent of TIMCLK, PLL1 and PLL2 - */ - mxtal: mxtal@19.2M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - /* - * The 2.4 MHz TIMCLK reference clock is active at - * boot time, this is actually the MXTALCLK @19.2 MHz - * divided by 8. This clock is used by the timers and - * watchdog. See page 105 ff. - */ - timclk: timclk@2.4M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&mxtal>; - }; - - /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ - pll1: pll1@0 { - #clock-cells = <0>; - compatible = "st,nomadik-pll-clock"; - pll-id = <1>; - clocks = <&mxtal>; - }; - - /* HCLK divides the PLL1 with 1,2,3 or 4 */ - hclk: hclk@0 { - #clock-cells = <0>; - compatible = "st,nomadik-hclk-clock"; - clocks = <&pll1>; - }; - /* The PCLK domain uses HCLK right off */ - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&hclk>; - }; - - /* PLL2 is usually 864 MHz and divided into a few fixed rates */ - pll2: pll2@0 { - #clock-cells = <0>; - compatible = "st,nomadik-pll-clock"; - pll-id = <2>; - clocks = <&mxtal>; - }; - clk216: clk216@216M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk108: clk108@108M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&clk216>; - }; - clk72: clk72@72M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - /* The data sheet does not say how this is derived */ - clock-div = <12>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk48: clk48@48M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - /* The data sheet does not say how this is derived */ - clock-div = <18>; - clock-mult = <1>; - clocks = <&pll2>; - }; - clk27: clk27@27M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&clk108>; - }; - - /* This apparently exists as well */ - ulpiclk: ulpiclk@60M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - /* - * IP AMBA bus clocks, driving the bus side of the - * peripheral clocking, clock gates. - */ - - hclkdma0: hclkdma0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <0>; - clocks = <&hclk>; - }; - hclksmc: hclksmc@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <1>; - clocks = <&hclk>; - }; - hclksdram: hclksdram@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <2>; - clocks = <&hclk>; - }; - hclkdma1: hclkdma1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <3>; - clocks = <&hclk>; - }; - hclkclcd: hclkclcd@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <4>; - clocks = <&hclk>; - }; - pclkirda: pclkirda@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <5>; - clocks = <&pclk>; - }; - pclkssp: pclkssp@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <6>; - clocks = <&pclk>; - }; - pclkuart0: pclkuart0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <7>; - clocks = <&pclk>; - }; - pclksdi: pclksdi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <8>; - clocks = <&pclk>; - }; - pclki2c0: pclki2c0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <9>; - clocks = <&pclk>; - }; - pclki2c1: pclki2c1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <10>; - clocks = <&pclk>; - }; - pclkuart1: pclkuart1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <11>; - clocks = <&pclk>; - }; - pclkmsp0: pclkmsp0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <12>; - clocks = <&pclk>; - }; - hclkusb: hclkusb@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <13>; - clocks = <&hclk>; - }; - hclkdif: hclkdif@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <14>; - clocks = <&hclk>; - }; - hclksaa: hclksaa@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <15>; - clocks = <&hclk>; - }; - hclksva: hclksva@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <16>; - clocks = <&hclk>; - }; - pclkhsi: pclkhsi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <17>; - clocks = <&pclk>; - }; - pclkxti: pclkxti@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <18>; - clocks = <&pclk>; - }; - pclkuart2: pclkuart2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <19>; - clocks = <&pclk>; - }; - pclkmsp1: pclkmsp1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <20>; - clocks = <&pclk>; - }; - pclkmsp2: pclkmsp2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <21>; - clocks = <&pclk>; - }; - pclkowm: pclkowm@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <22>; - clocks = <&pclk>; - }; - hclkhpi: hclkhpi@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <23>; - clocks = <&hclk>; - }; - pclkske: pclkske@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <24>; - clocks = <&pclk>; - }; - pclkhsem: pclkhsem@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <25>; - clocks = <&pclk>; - }; - hclk3d: hclk3d@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <26>; - clocks = <&hclk>; - }; - hclkhash: hclkhash@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <27>; - clocks = <&hclk>; - }; - hclkcryp: hclkcryp@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <28>; - clocks = <&hclk>; - }; - pclkmshc: pclkmshc@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <29>; - clocks = <&pclk>; - }; - hclkusbm: hclkusbm@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <30>; - clocks = <&hclk>; - }; - hclkrng: hclkrng@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <31>; - clocks = <&hclk>; - }; - - /* IP kernel clocks */ - clcdclk: clcdclk@0 { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <36>; - clocks = <&clk72 &clk48>; - }; - irdaclk: irdaclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <37>; - clocks = <&clk48>; - }; - sspiclk: sspiclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <38>; - clocks = <&clk48>; - }; - uart0clk: uart0clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <39>; - clocks = <&clk48>; - }; - sdiclk: sdiclk@48M { - /* Also called MCCLK in some documents */ - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <40>; - clocks = <&clk48>; - }; - i2c0clk: i2c0clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <41>; - clocks = <&clk48>; - }; - i2c1clk: i2c1clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <42>; - clocks = <&clk48>; - }; - uart1clk: uart1clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <43>; - clocks = <&clk48>; - }; - mspclk0: mspclk0@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <44>; - clocks = <&clk48>; - }; - usbclk: usbclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <45>; - clocks = <&clk48>; /* 48 MHz not ULPI */ - }; - difclk: difclk@72M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <46>; - clocks = <&clk72>; - }; - ipi2cclk: ipi2cclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <47>; - clocks = <&clk48>; /* Guess */ - }; - ipbmcclk: ipbmcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <48>; - clocks = <&clk48>; /* Guess */ - }; - hsiclkrx: hsiclkrx@216M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <49>; - clocks = <&clk216>; - }; - hsiclktx: hsiclktx@108M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <50>; - clocks = <&clk108>; - }; - uart2clk: uart2clk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <51>; - clocks = <&clk48>; - }; - mspclk1: mspclk1@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <52>; - clocks = <&clk48>; - }; - mspclk2: mspclk2@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <53>; - clocks = <&clk48>; - }; - owmclk: owmclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <54>; - clocks = <&clk48>; /* Guess */ - }; - skeclk: skeclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <56>; - clocks = <&clk48>; /* Guess */ - }; - x3dclk: x3dclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <58>; - clocks = <&clk48>; /* Guess */ - }; - pclkmsp3: pclkmsp3@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <59>; - clocks = <&pclk>; - }; - mspclk3: mspclk3@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <60>; - clocks = <&clk48>; - }; - mshcclk: mshcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <61>; - clocks = <&clk48>; /* Guess */ - }; - usbmclk: usbmclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <62>; - /* Stated as "48 MHz not ULPI clock" */ - clocks = <&clk48>; - }; - rngcclk: rngcclk@48M { - #clock-cells = <0>; - compatible = "st,nomadik-src-clock"; - clock-id = <63>; - clocks = <&clk48>; /* Guess */ - }; - }; - - /* A NAND flash of 128 MiB */ - fsmc: flash@40000000 { - compatible = "stericsson,fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x10100000 0x1000>, /* FSMC Register*/ - <0x40000000 0x2000>, /* NAND Base DATA */ - <0x41000000 0x2000>, /* NAND Base ADDR */ - <0x40800000 0x2000>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - clocks = <&hclksmc>; - status = "okay"; - timings = /bits/ 8 <0 0 0 0x10 0x0a 0>; - - partition@0 { - label = "X-Loader(NAND)"; - reg = <0x0 0x40000>; - }; - partition@40000 { - label = "MemInit(NAND)"; - reg = <0x40000 0x40000>; - }; - partition@80000 { - label = "BootLoader(NAND)"; - reg = <0x80000 0x200000>; - }; - partition@280000 { - label = "Kernel zImage(NAND)"; - reg = <0x280000 0x300000>; - }; - partition@580000 { - label = "Root Filesystem(NAND)"; - reg = <0x580000 0x1600000>; - }; - partition@1b80000 { - label = "User Filesystem(NAND)"; - reg = <0x1b80000 0x6480000>; - }; - }; - - /* I2C0 connected to the STw4811 power management chip */ - i2c0 { - compatible = "st,nomadik-i2c", "arm,primecell"; - reg = <0x101f8000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <20>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&i2c0clk>, <&pclki2c0>; - clock-names = "mclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; - - stw4811@2d { - compatible = "st,stw4811"; - reg = <0x2d>; - vmmc_regulator: vmmc { - compatible = "st,stw481x-vmmc"; - regulator-name = "VMMC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - /* I2C1 connected to various sensors */ - i2c1 { - compatible = "st,nomadik-i2c", "arm,primecell"; - reg = <0x101f7000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <21>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&i2c1clk>, <&pclki2c1>; - clock-names = "mclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; - - camera@2d { - compatible = "st,camera"; - reg = <0x10>; - }; - stw5095@1a { - compatible = "st,stw5095"; - reg = <0x1a>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clcd@10120000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x10120000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - interrupt-parent = <&vica>; - clocks = <&clcdclk>, <&hclkclcd>; - clock-names = "clcdclk", "apb_pclk"; - status = "disabled"; - }; - - vica: intc@10140000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140000 0x20>; - }; - - vicb: intc@10140020 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140020 0x20>; - }; - - uart0: uart@101fd000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101fd000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <12>; - clocks = <&uart0clk>, <&pclkuart0>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - dmas = <&dmac0 14 1>, - <&dmac0 15 1>; - dma-names = "rx", "tx"; - }; - - uart1: uart@101fb000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101fb000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <17>; - clocks = <&uart1clk>, <&pclkuart1>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_default_mux>; - dmas = <&dmac1 22 1>, - <&dmac1 23 1>; - dma-names = "rx", "tx"; - }; - - uart2: uart@101f2000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f2000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <28>; - clocks = <&uart2clk>, <&pclkuart2>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - dmas = <&dmac1 30 1>, - <&dmac1 31 1>; - dma-names = "rx", "tx"; - }; - - rng: rng@101b0000 { - compatible = "arm,primecell"; - reg = <0x101b0000 0x1000>; - clocks = <&rngcclk>, <&hclkrng>; - clock-names = "rng", "apb_pclk"; - }; - - rtc: rtc@101e8000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x101e8000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - interrupt-parent = <&vica>; - interrupts = <10>; - }; - - mmcsd: sdi@101f6000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x101f6000 0x1000>; - clocks = <&sdiclk>, <&pclksdi>; - clock-names = "mclk", "apb_pclk"; - interrupt-parent = <&vica>; - interrupts = <22>; - max-frequency = <400000>; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - full-pwr-cycle; - /* - * The STw4811 circuit used with the Nomadik strictly - * requires that all of these signal direction pins be - * routed and used for its 4-bit levelshifter. - */ - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-dat31; - st,sig-dir-cmd; - st,sig-pin-fbclk; - pinctrl-names = "default"; - pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; - vmmc-supply = <&vmmc_regulator>; - }; - - dmac0: dma-controller@10130000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x10130000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <15>; - clocks = <&hclkdma0>; - clock-names = "apb_pclk"; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; - dmac1: dma-controller@10150000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x10150000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <13>; - clocks = <&hclkdma1>; - clock-names = "apb_pclk"; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-snowball.dts b/software/linux/kernel/arch/arm/boot/dts/ste-snowball.dts deleted file mode 100644 index 386eee6de..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-snowball.dts +++ /dev/null @@ -1,671 +0,0 @@ -/* - * Copyright 2011 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-dbx5x0.dtsi" -#include "ste-href-ab8500.dtsi" -#include "ste-href-family-pinctrl.dtsi" - -/ { - model = "Calao Systems Snowball platform with device tree"; - compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500"; - - /* This stablilizes the serial port enumeration */ - aliases { - serial0 = &ux500_serial0; - serial1 = &ux500_serial1; - serial2 = &ux500_serial2; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - en_3v3_reg: en_3v3 { - compatible = "regulator-fixed"; - regulator-name = "en-3v3-fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */ - gpio = <&ab8500_gpio 25 0x4>; - startup-delay-us = <5000>; - enable-active-high; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - debounce_interval = <50>; - wakeup-source; - linux,code = <2>; - label = "userpb"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - button@2 { - debounce_interval = <50>; - wakeup-source; - linux,code = <3>; - label = "extkb1"; - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - button@3 { - debounce_interval = <50>; - wakeup-source; - linux,code = <4>; - label = "extkb2"; - gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; - }; - button@4 { - debounce_interval = <50>; - wakeup-source; - linux,code = <5>; - label = "extkb3"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - }; - button@5 { - debounce_interval = <50>; - wakeup-source; - linux,code = <6>; - label = "extkb4"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpioled_snowball_mode>; - used-led { - label = "user_led"; - gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; - - soc { - /* Name the GPIO muxed rails on the Snowball board */ - gpio@8012e000 { - /* GPIOs 0 - 31 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "AP_GPIO31"; - }; - - gpio@8012e080 { - /* GPIOs 32 - 63 */ - gpio-line-names = "USR PB", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e000 { - /* GPIOs 64 - 95 */ - gpio-line-names = "", "", "", "", "AP_GPIO68", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8000e100 { - /* GPIOs 128 - 159 */ - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "IRQ_LAN", "RSTn_LAN", - "USR_LED", "", "", "", "", "", "", - "", "", "AP_GPIO151", "AP_GPIO152", - "", "", "", "", "", "", ""; - }; - - gpio@8000e180 { - /* GPIOs 160 - 191 */ - gpio-line-names = "", "AP_GPIO161", "AP_GPIO162", - "ACCELEROMETER_INT1_RDY", - "ACCELEROMETER_INT2", "MAG_DRDY", - "GYRO_DRDY", "RSTn_MLC", "RSTn_SLC", - "GYRO_INT", "UART_WAKE", "GBF_RESET", - "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - gpio@8011e000 { - /* GPIOs 192 - 223 */ - gpio-line-names = "HDTV_INTn", "", "", "", "HDTV_RST", - "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", - "WLAN_RESETN", "WLAN_IRQ", "MMC_EN", - "MMC_CD", "", "", "", "", ""; - }; - - gpio@8011e080 { - /* GPIOs 224 - 255 */ - gpio-line-names = "", "", "", "", "SD_SEL", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; - }; - - usb_per5@a03e0000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&musb_default_mode>; - pinctrl-1 = <&musb_sleep_mode>; - }; - - sound { - compatible = "stericsson,snd-soc-mop500"; - - stericsson,cpu-dai = <&msp1 &msp3>; - stericsson,audio-codec = <&codec>; - }; - - msp0: msp@80123000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp0_default_mode>; - status = "okay"; - }; - - msp1: msp@80124000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp1_default_mode>; - status = "okay"; - }; - - msp2: msp@80117000 { - pinctrl-names = "default"; - pinctrl-0 = <&msp2_default_mode>; - }; - - msp3: msp@80125000 { - status = "okay"; - }; - - external-bus@50000000 { - status = "okay"; - - ethernet@0 { - compatible = "smsc,lan9115"; - reg = <0 0x10000>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpio4>; - vdd33a-supply = <&en_3v3_reg>; - vddvario-supply = <&db8500_vape_reg>; - pinctrl-names = "default"; - pinctrl-0 = <ð_snowball_mode>; - - reg-shift = <1>; - reg-io-width = <2>; - smsc,force-internal-phy; - smsc,irq-active-high; - smsc,irq-push-pull; - - clocks = <&prcc_pclk 3 0>; - }; - }; - - vmmci: regulator-gpio { - compatible = "regulator-gpio"; - - gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-name = "mmci-reg"; - regulator-type = "voltage"; - - startup-delay-us = <100>; - enable-active-high; - - states = <1800000 0x1 - 2900000 0x0>; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - /* All direction control is used */ - st,sig-dir-cmd; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-dat31; - st,sig-pin-fbclk; - full-pwr-cycle; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&vmmci>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdi0_default_mode>; - pinctrl-1 = <&sdi0_sleep_mode>; - - /* GPIO218 MMC_CD */ - cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; - - status = "okay"; - }; - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdi1_default_mode>; - pinctrl-1 = <&sdi1_sleep_mode>; - - status = "okay"; - }; - - // Unused PoP eMMC - register and put it to sleep by default */ - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - pinctrl-names = "default"; - pinctrl-0 = <&sdi2_sleep_mode>; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdi4_default_mode>; - pinctrl-1 = <&sdi4_sleep_mode>; - - status = "okay"; - }; - - uart@80120000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart0_default_mode>; - pinctrl-1 = <&uart0_sleep_mode>; - status = "okay"; - }; - - /* This UART is unused and thus left disabled */ - uart@80121000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart1_default_mode>; - pinctrl-1 = <&uart1_sleep_mode>; - }; - - uart@80007000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart2_default_mode>; - pinctrl-1 = <&uart2_sleep_mode>; - status = "okay"; - }; - - i2c@80004000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c0_default_mode>; - pinctrl-1 = <&i2c0_sleep_mode>; - }; - - i2c@80122000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c1_default_mode>; - pinctrl-1 = <&i2c1_sleep_mode>; - }; - - i2c@80128000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c2_default_mode>; - pinctrl-1 = <&i2c2_sleep_mode>; - lsm303dlh@18 { - /* Accelerometer */ - compatible = "st,lsm303dlh-accel"; - st,drdy-int-pin = <1>; - reg = <0x18>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&accel_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>, /* INT1 */ - <4 IRQ_TYPE_EDGE_RISING>; /* INT2 */ - }; - lsm303dlh@1e { - /* Magnetometer */ - compatible = "st,lsm303dlh-magn"; - reg = <0x1e>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <5 IRQ_TYPE_EDGE_RISING>; /* DRDY line */ - }; - l3g4200d@68 { - /* Gyroscope */ - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x68>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&gyro_snowball_mode>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ - <9 IRQ_TYPE_EDGE_RISING>; /* INT1 */ - }; - lsp001wm@5c { - /* Barometer/pressure sensor */ - compatible = "st,lps001wp-press"; - reg = <0x5c>; - vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; - }; - }; - - i2c@80110000 { - pinctrl-names = "default","sleep"; - pinctrl-0 = <&i2c3_default_mode>; - pinctrl-1 = <&i2c3_sleep_mode>; - }; - - ssp@80002000 { - pinctrl-names = "default"; - pinctrl-0 = <&ssp0_snowball_mode>; - }; - - cpufreq-cooling { - status = "okay"; - }; - - prcmu@80157000 { - cpufreq { - status = "okay"; - }; - - thermal@801573c0 { - num-trips = <4>; - - trip0-temp = <70000>; - trip0-type = "active"; - trip0-cdev-num = <1>; - trip0-cdev-name0 = "thermal-cpufreq-0"; - - trip1-temp = <75000>; - trip1-type = "active"; - trip1-cdev-num = <1>; - trip1-cdev-name0 = "thermal-cpufreq-0"; - - trip2-temp = <80000>; - trip2-type = "active"; - trip2-cdev-num = <1>; - trip2-cdev-name0 = "thermal-cpufreq-0"; - - trip3-temp = <85000>; - trip3-type = "critical"; - trip3-cdev-num = <0>; - - status = "okay"; - }; - - ab8500 { - ab8500-gpio { - /* - * AB8500 GPIOs are numbered starting from 1, so the first - * index 0 is what in the datasheet is called "GPIO1", and - * the second is "GPIO2" and so forth. Confusingly, the - * Snowball schematic then names the "GPIO2" line "PM_GPIO1". - * while later naming "GPIO4" as "PM_GPIO4". - */ - gpio-line-names = "", /* AB8500 GPIO1 */ - "PM_GPIO1", /* AB8500 GPIO2 */ - "WLAN_CLK_REQ", /* AB8500 GPIO3 */ - "PM_GPIO4", /* AB8500 GPIO4 */ - "", "", "", "", "", "", "", "", "", "", "", - "EN_3V6", /* AB8500 GPIO16 */ - "", "", "", "" ,"", "", "", "", "", - "EN_3V3", /* AB8500 GPIO26 */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "PM_GPIO40", /* AB8500 GPIO40 */ - "PM_GPIO41", /* AB8500 GPIO41 */ - "PM_GPIO42"; /* AB8500 GPIO42 */ - }; - - ext_regulators: ab8500-ext-regulators { - ab8500_ext1_reg: ab8500_ext1 { - regulator-name = "ab8500-ext-supply1"; - }; - - ab8500_ext2_reg_reg: ab8500_ext2 { - regulator-name = "ab8500-ext-supply2"; - }; - - ab8500_ext3_reg_reg: ab8500_ext3 { - regulator-name = "ab8500-ext-supply3"; - }; - }; - - ab8500-regulators { - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-name = "V-DISPLAY"; - }; - - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-name = "V-eMMC1"; - }; - - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-name = "V-MMC-SD"; - }; - - ab8500_ldo_intcore_reg: ab8500_ldo_intcore { - regulator-name = "V-INTCORE"; - }; - - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-name = "V-TVOUT"; - }; - - ab8500_ldo_usb_reg: ab8500_ldo_usb { - regulator-name = "dummy"; - }; - - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-name = "V-AUD"; - }; - - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-name = "V-AMIC1"; - }; - - ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { - regulator-name = "V-AMIC2"; - }; - - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-name = "V-DMIC"; - }; - - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - - pinctrl { - /* - * Set this up using hogs, as time goes by and as seems fit, these - * can be moved over to being controlled by respective device. - */ - pinctrl-names = "default"; - pinctrl-0 = <&gbf_snowball_mode>, - <&wlan_snowball_mode>; - - ethernet { - /* - * Mux in "SM" which is used for the - * SMSC911x Ethernet adapter - */ - eth_snowball_mode: eth_snowball { - snowball_mux { - function = "sm"; - groups = "sm_b_1"; - }; - /* LAN IRQ pin */ - snowball_cfg1 { - pins = "GPIO140_B11"; - ste,config = <&in_nopull>; - }; - /* LAN reset pin */ - snowball_cfg2 { - pins = "GPIO141_C12"; - ste,config = <&gpio_out_hi>; - }; - - }; - }; - sdi0 { - sdi0_default_mode: sdi0_default { - snowball_mux { - function = "mc0"; - groups = "mc0dat31dir_a_1"; - }; - snowball_cfg1 { - pins = "GPIO21_AB3"; /* DAT31DIR */ - ste,config = <&out_hi>; - }; - /* SD card detect GPIO pin, extend default state */ - snowball_cfg2 { - pins = "GPIO218_AH11"; - ste,config = <&gpio_in_pu>; - }; - /* VMMCI level-shifter enable */ - snowball_cfg3 { - pins = "GPIO217_AH12"; - ste,config = <&gpio_out_hi>; - }; - /* VMMCI level-shifter voltage select */ - snowball_cfg4 { - pins = "GPIO228_AJ6"; - ste,config = <&gpio_out_hi>; - }; - }; - }; - ssp0 { - ssp0_snowball_mode: ssp0_snowball_default { - snowball_mux { - function = "ssp0"; - groups = "ssp0_a_1"; - }; - snowball_cfg1 { - pins = "GPIO144_B13"; /* FRM */ - ste,config = <&gpio_out_hi>; - }; - snowball_cfg2 { - pins = "GPIO145_C13"; /* RXD */ - ste,config = <&in_pd>; - }; - snowball_cfg3 { - pins = - "GPIO146_D13", /* TXD */ - "GPIO143_D12"; /* CLK */ - ste,config = <&out_lo>; - }; - - }; - }; - gpio_led { - gpioled_snowball_mode: gpioled_default { - snowball_cfg1 { - pins = "GPIO142_C11"; - ste,config = <&gpio_out_hi>; - }; - - }; - }; - accelerometer { - accel_snowball_mode: accel_snowball { - /* Accelerometer lines */ - snowball_cfg1 { - pins = - "GPIO163_C20", /* ACCEL_IRQ1 */ - "GPIO164_B21"; /* ACCEL_IRQ2 */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - gyro { - gyro_snowball_mode: gyro_snowball { - snowball_cfg1 { - pins = - "GPIO166_A22", /* DRDY */ - "GPIO169_D22"; /* INT */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - magnetometer { - magneto_snowball_mode: magneto_snowball { - snowball_cfg1 { - pins = "GPIO165_C21"; /* MAG_DRDY */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - gbf { - gbf_snowball_mode: gbf_snowball { - /* - * GBF (GPS, Bluetooth, FM-radio) interface, - * pull low to reset state - */ - snowball_cfg1 { - pins = "GPIO171_D23"; /* GBF_ENA_RESET */ - ste,config = <&gpio_out_lo>; - }; - }; - }; - wlan { - wlan_snowball_mode: wlan_snowball { - /* - * Activate this mode with the WLAN chip. - * These are plain GPIO pins used by WLAN - */ - snowball_cfg1 { - pins = - "GPIO161_D21", /* WLAN_PMU_EN */ - "GPIO215_AH13"; /* WLAN_ENA */ - ste,config = <&gpio_out_lo>; - }; - snowball_cfg2 { - pins = "GPIO216_AG12"; /* WLAN_IRQ */ - ste,config = <&gpio_in_pu>; - }; - }; - }; - }; - - mcde@a0350000 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_default_mode>; - pinctrl-1 = <&lcd_sleep_mode>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/ste-u300.dts b/software/linux/kernel/arch/arm/boot/dts/ste-u300.dts deleted file mode 100644 index 2f5107ffe..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/ste-u300.dts +++ /dev/null @@ -1,463 +0,0 @@ -/* - * Device Tree for the ST-Ericsson U300 Machine and SoC - */ - -/dts-v1/; -/include/ "skeleton.dtsi" - -/ { - model = "ST-Ericsson U300"; - compatible = "stericsson,u300"; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - memory { - reg = <0x48000000 0x03c00000>; - }; - - s365 { - compatible = "stericsson,s365"; - vana15-supply = <&ab3100_ldo_d_reg>; - syscon = <&syscon>; - }; - - syscon: syscon@c0011000 { - compatible = "stericsson,u300-syscon", "syscon"; - reg = <0xc0011000 0x1000>; - clk32: app_32_clk@32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - pll13: pll13@13M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - /* Slow bridge clocks under PLL13 */ - slow_clk: slow_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <0>; - clocks = <&pll13>; - }; - uart0_clk: uart0_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <1>; - clocks = <&slow_clk>; - }; - gpio_clk: gpio_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <4>; - clocks = <&slow_clk>; - }; - rtc_clk: rtc_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <6>; - clocks = <&slow_clk>; - }; - apptimer_clk: app_tmr_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <7>; - clocks = <&slow_clk>; - }; - acc_tmr_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <8>; - clocks = <&slow_clk>; - }; - pll208: pll208@208M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <208000000>; - }; - app208: app_208_clk@208M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&pll208>; - }; - cpu_clk@208M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <3>; - clocks = <&app208>; - }; - app104: app_104_clk@104M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&pll208>; - }; - semi_clk@104M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <9>; - clocks = <&app104>; - }; - app52: app_52_clk@52M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll208>; - }; - /* AHB subsystem clocks */ - ahb_clk: ahb_subsys_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <10>; - clocks = <&app52>; - }; - intcon_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <12>; - clocks = <&ahb_clk>; - }; - emif_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <5>; - clocks = <&ahb_clk>; - }; - dmac_clk: dmac_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <4>; - clocks = <&app52>; - }; - fsmc_clk: fsmc_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <6>; - clocks = <&app52>; - }; - xgam_clk: xgam_clk@52M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <2>; /* Rest */ - clock-id = <8>; - clocks = <&app52>; - }; - app26: app_26_clk@26M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&app52>; - }; - /* Fast bridge clocks */ - fast_clk: fast_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <0>; - clocks = <&app26>; - }; - i2c0_clk: i2c0_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <1>; - clocks = <&fast_clk>; - }; - i2c1_clk: i2c1_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <2>; - clocks = <&fast_clk>; - }; - mmc_pclk: mmc_p_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <5>; - clocks = <&fast_clk>; - }; - mmc_mclk: mmc_mclk { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-mclk"; - clocks = <&mmc_pclk>; - }; - spi_clk: spi_p_clk@26M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <1>; /* Fast */ - clock-id = <6>; - clocks = <&fast_clk>; - }; - }; - - timer: timer@c0014000 { - compatible = "stericsson,u300-apptimer"; - reg = <0xc0014000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <24 25 26 27>; - clocks = <&apptimer_clk>; - }; - - gpio: gpio@c0016000 { - compatible = "stericsson,gpio-coh901"; - reg = <0xc0016000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <0 1 2 18 21 22 23>; - clocks = <&gpio_clk>; - interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pinctrl: pinctrl@c0011000 { - compatible = "stericsson,pinctrl-u300"; - reg = <0xc0011000 0x1000>; - }; - - watchdog: watchdog@c0012000 { - compatible = "stericsson,coh901327"; - reg = <0xc0012000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <3>; - clocks = <&clk32>; - }; - - rtc: rtc@c0017000 { - compatible = "stericsson,coh901331"; - reg = <0xc0017000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <10>; - clocks = <&rtc_clk>; - }; - - dmac: dma-controller@c00020000 { - compatible = "stericsson,coh901318"; - reg = <0xc0020000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <2>; - #dma-cells = <1>; - dma-channels = <40>; - clocks = <&dmac_clk>; - }; - - /* A NAND flash of 128 MiB */ - fsmc: flash@40000000 { - compatible = "stericsson,fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x9f800000 0x1000>, /* FSMC Register*/ - <0x80000000 0x4000>, /* NAND Base DATA */ - <0x80020000 0x4000>, /* NAND Base ADDR */ - <0x80010000 0x4000>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - nand-skip-bbtscan; - clocks = <&fsmc_clk>; - - partition@0 { - label = "boot records"; - reg = <0x0 0x20000>; - }; - partition@20000 { - label = "free"; - reg = <0x20000 0x7e0000>; - }; - partition@800000 { - label = "platform"; - reg = <0x800000 0xf800000>; - }; - }; - - i2c0: i2c@c0004000 { - compatible = "st,ddci2c"; - reg = <0xc0004000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <8>; - clocks = <&i2c0_clk>; - #address-cells = <1>; - #size-cells = <0>; - ab3100: ab3100@48 { - compatible = "stericsson,ab3100"; - reg = <0x48>; - interrupt-parent = <&vica>; - interrupts = <0>; /* EXT0 IRQ */ - ab3100-regulators { - compatible = "stericsson,ab3100-regulators"; - ab3100_ldo_a_reg: ab3100_ldo_a { - startup-delay-us = <200>; - regulator-always-on; - regulator-boot-on; - }; - ab3100_ldo_c_reg: ab3100_ldo_c { - startup-delay-us = <200>; - }; - ab3100_ldo_d_reg: ab3100_ldo_d { - startup-delay-us = <200>; - }; - ab3100_ldo_e_reg: ab3100_ldo_e { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <200>; - regulator-always-on; - regulator-boot-on; - }; - ab3100_ldo_f_reg: ab3100_ldo_f { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - startup-delay-us = <600>; - regulator-always-on; - regulator-boot-on; - }; - ab3100_ldo_g_reg: ab3100_ldo_g { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2850000>; - startup-delay-us = <400>; - }; - ab3100_ldo_h_reg: ab3100_ldo_h { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2750000>; - startup-delay-us = <200>; - }; - ab3100_ldo_k_reg: ab3100_ldo_k { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2750000>; - startup-delay-us = <200>; - }; - ab3100_ext_reg: ab3100_ext { - }; - ab3100_buck_reg: ab3100_buck { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <1000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; - - i2c1: i2c@c0005000 { - compatible = "st,ddci2c"; - reg = <0xc0005000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <9>; - clocks = <&i2c1_clk>; - #address-cells = <1>; - #size-cells = <0>; - fwcam0: fwcam@10 { - reg = <0x10>; - }; - fwcam1: fwcam@5d { - reg = <0x5d>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vica: interrupt-controller@a0001000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xa0001000 0x20>; - }; - - vicb: interrupt-controller@a0002000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xa0002000 0x20>; - }; - - uart0: serial@c0013000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xc0013000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <22>; - clocks = <&uart0_clk>, <&uart0_clk>; - clock-names = "apb_pclk", "uart0_clk"; - dmas = <&dmac 17 &dmac 18>; - dma-names = "tx", "rx"; - }; - - uart1: serial@c0007000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xc0007000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <20>; - dmas = <&dmac 38 &dmac 39>; - dma-names = "tx", "rx"; - }; - - mmcsd: mmcsd@c0001000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0xc0001000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <6 7>; - clocks = <&mmc_pclk>, <&mmc_mclk>; - clock-names = "apb_pclk", "mclk"; - max-frequency = <24000000>; - bus-width = <4>; // SD-card slot - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio 12 0x4>; - cd-inverted; - vmmc-supply = <&ab3100_ldo_g_reg>; - dmas = <&dmac 14>; - dma-names = "rx"; - }; - - spi: ssp@c0006000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xc0006000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <23>; - clocks = <&spi_clk>, <&spi_clk>; - clock-names = "SSPCLK", "apb_pclk"; - dmas = <&dmac 27 &dmac 28>; - dma-names = "tx", "rx"; - num-cs = <3>; - #address-cells = <1>; - #size-cells = <0>; - spi-dummy@1 { - compatible = "arm,pl022-dummy"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih407-b2120.dts b/software/linux/kernel/arch/arm/boot/dts/stih407-b2120.dts deleted file mode 100644 index c8ad905d0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih407-b2120.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Giuseppe Cavallaro - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; -#include "stih407.dtsi" -#include "stihxxx-b2120.dtsi" -/ { - model = "STiH407 B2120"; - compatible = "st,stih407-b2120", "st,stih407"; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial0; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - ttyAS0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih407-clock.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih407-clock.dtsi deleted file mode 100644 index 13029c03d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih407-clock.dtsi +++ /dev/null @@ -1,326 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; - }; - - clockgen-a@090ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0"; - }; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - }; - - clk_s_c0: clockgen-c@09103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-proc-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-ext2fa9", - "clk-ic-bdisp-0", - "clk-ic-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-disp-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phy", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp"; - }; - }; - - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; - }; - - clockgen-d0@09104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-audio", "st,flexgen"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-pcm-0", - "clk-pcm-1", - "clk-pcm-2", - "clk-spdiff"; - }; - }; - - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-video", "st,flexgen"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - - clock-output-names = "clk-pix-main-disp", - "clk-pix-pip", - "clk-pix-gdp1", - "clk-pix-gdp2", - "clk-pix-gdp3", - "clk-pix-gdp4", - "clk-pix-aux-disp", - "clk-denc", - "clk-pix-hddac", - "clk-hddac", - "clk-sddac", - "clk-pix-dvo", - "clk-dvo", - "clk-pix-hdmi", - "clk-tmds-hdmi", - "clk-ref-hdmiphy"; - }; - }; - - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-stfe-frc1", - "clk-tsout-0", - "clk-tsout-1", - "clk-mchi", - "clk-vsens-compo", - "clk-frc1-remote", - "clk-lpc-0", - "clk-lpc-1"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih407-family.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih407-family.dtsi deleted file mode 100644 index acdcbf99a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih407-family.dtsi +++ /dev/null @@ -1,1027 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Giuseppe Cavallaro - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih407-pinctrl.dtsi" -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gp0_reserved: rproc@40000000 { - compatible = "shared-dma-pool"; - reg = <0x40000000 0x01000000>; - no-map; - status = "disabled"; - }; - - gp1_reserved: rproc@41000000 { - compatible = "shared-dma-pool"; - reg = <0x41000000 0x01000000>; - no-map; - status = "disabled"; - }; - - audio_reserved: rproc@42000000 { - compatible = "shared-dma-pool"; - reg = <0x42000000 0x01000000>; - no-map; - status = "disabled"; - }; - - dmu_reserved: rproc@43000000 { - compatible = "shared-dma-pool"; - reg = <0x43000000 0x01000000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - - clocks = <&clk_m_a9>; - clock-names = "cpu"; - clock-latency = <100000>; - cpu0-supply = <&pwm_regulator>; - st,syscfg = <&syscfg_core 0x8e0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - }; - }; - - intc: interrupt-controller@08761000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x08761000 0x1000>, <0x08760100 0x100>; - }; - - scu@08760000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x08760000 0x1000>; - }; - - timer@08760200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0x08760200 0x100>; - interrupts = ; - clocks = <&arm_periph_clk>; - }; - - l2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0x08762000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-pmu"; - interrupts = ; - }; - - pwm_regulator: pwm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 3 8448>; - regulator-name = "CPU_1V0_AVS"; - regulator-min-microvolt = <784000>; - regulator-max-microvolt = <1299000>; - regulator-always-on; - max-duty-cycle = <255>; - status = "okay"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - restart { - compatible = "st,stih407-restart"; - st,syscfg = <&syscfg_sbc_reg>; - status = "okay"; - }; - - powerdown: powerdown-controller { - compatible = "st,stih407-powerdown"; - #reset-cells = <1>; - }; - - softreset: softreset-controller { - compatible = "st,stih407-softreset"; - #reset-cells = <1>; - }; - - picophyreset: picophyreset-controller { - compatible = "st,stih407-picophyreset"; - #reset-cells = <1>; - }; - - syscfg_sbc: sbc-syscfg@9620000 { - compatible = "st,stih407-sbc-syscfg", "syscon"; - reg = <0x9620000 0x1000>; - }; - - syscfg_front: front-syscfg@9280000 { - compatible = "st,stih407-front-syscfg", "syscon"; - reg = <0x9280000 0x1000>; - }; - - syscfg_rear: rear-syscfg@9290000 { - compatible = "st,stih407-rear-syscfg", "syscon"; - reg = <0x9290000 0x1000>; - }; - - syscfg_flash: flash-syscfg@92a0000 { - compatible = "st,stih407-flash-syscfg", "syscon"; - reg = <0x92a0000 0x1000>; - }; - - syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { - compatible = "st,stih407-sbc-reg-syscfg", "syscon"; - reg = <0x9600000 0x1000>; - }; - - syscfg_core: core-syscfg@92b0000 { - compatible = "st,stih407-core-syscfg", "syscon"; - reg = <0x92b0000 0x1000>; - }; - - syscfg_lpm: lpm-syscfg@94b5100 { - compatible = "st,stih407-lpm-syscfg", "syscon"; - reg = <0x94b5100 0x1000>; - }; - - irq-syscfg { - compatible = "st,stih407-irq-syscfg"; - st,syscfg = <&syscfg_core>; - st,irq-device = , - ; - st,fiq-device = , - ; - }; - - /* Display */ - vtg_main: sti-vtg-main@8d02800 { - compatible = "st,vtg"; - reg = <0x8d02800 0x200>; - interrupts = ; - }; - - vtg_aux: sti-vtg-aux@8d00200 { - compatible = "st,vtg"; - reg = <0x8d00200 0x100>; - interrupts = ; - }; - - serial@9830000 { - compatible = "st,asc"; - reg = <0x9830000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial0>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - serial@9831000 { - compatible = "st,asc"; - reg = <0x9831000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial1>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - serial@9832000 { - compatible = "st,asc"; - reg = <0x9832000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - /* SBC_ASC0 - UART10 */ - sbc_serial0: serial@9530000 { - compatible = "st,asc"; - reg = <0x9530000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial0>; - clocks = <&clk_sysin>; - - status = "disabled"; - }; - - serial@9531000 { - compatible = "st,asc"; - reg = <0x9531000 0x2c>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - - status = "disabled"; - }; - - i2c@9840000 { - compatible = "st,comms-ssc4-i2c"; - interrupts = ; - reg = <0x9840000 0x110>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9841000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9841000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9842000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9842000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9843000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9843000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9844000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9844000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9845000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9845000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - - /* SSCs on SBC */ - i2c@9540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - usb2_picophy0: phy1 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0x100 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY2_RESET>; - reset-names = "global", "port"; - }; - - miphy28lp_phy: miphy28lp@9b22000 { - compatible = "st,miphy28lp-phy"; - st,syscfg = <&syscfg_core>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@9b22000 { - reg = <0x9b22000 0xff>, - <0x9b09000 0xff>, - <0x9b04000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x114 0x818 0xe0 0xec>; - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY0_SOFTRESET>; - }; - - phy_port1: port@9b2a000 { - reg = <0x9b2a000 0xff>, - <0x9b19000 0xff>, - <0x9b14000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x118 0x81c 0xe4 0xf0>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY1_SOFTRESET>; - }; - - phy_port2: port@8f95000 { - reg = <0x8f95000 0xff>, - <0x8f90000 0xff>; - reg-names = "pipew", - "usb3-up"; - - st,syscfg = <0x11c 0x820>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY2_SOFTRESET>; - }; - }; - - spi@9840000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9840000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-0 = <&pinctrl_spi0_default>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9841000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9841000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - status = "disabled"; - }; - - spi@9842000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9842000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2_default>; - - status = "disabled"; - }; - - spi@9843000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9843000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi3_default>; - - status = "disabled"; - }; - - spi@9844000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9844000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4_default>; - - status = "disabled"; - }; - - /* SBC SSC */ - spi@9540000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi10_default>; - - status = "disabled"; - }; - - spi@9541000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi11_default>; - - status = "disabled"; - }; - - spi@9542000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9542000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi12_default>; - - status = "disabled"; - }; - - mmc0: sdhci@09060000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - status = "disabled"; - reg = <0x09060000 0x7ff>, <0x9061008 0x20>; - reg-names = "mmc", "top-mmc-delay"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc", "icn"; - clocks = <&clk_s_c0_flexgen CLK_MMC_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; - bus-width = <8>; - }; - - mmc1: sdhci@09080000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - status = "disabled"; - reg = <0x09080000 0x7ff>; - reg-names = "mmc"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clock-names = "mmc", "icn"; - clocks = <&clk_s_c0_flexgen CLK_MMC_1>, - <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; - resets = <&softreset STIH407_MMC1_SOFTRESET>; - bus-width = <4>; - }; - - /* Watchdog and Real-Time Clock */ - lpc@8787000 { - compatible = "st,stih407-lpc"; - reg = <0x8787000 0x1000>; - interrupts = ; - clocks = <&clk_s_d3_flexgen CLK_LPC_0>; - timeout-sec = <120>; - st,syscfg = <&syscfg_core>; - st,lpc-mode = ; - }; - - lpc@8788000 { - compatible = "st,stih407-lpc"; - reg = <0x8788000 0x1000>; - interrupts = ; - clocks = <&clk_s_d3_flexgen CLK_LPC_1>; - st,lpc-mode = ; - }; - - sata0: sata@9b20000 { - compatible = "st,ahci"; - reg = <0x9b20000 0x1000>; - - interrupts = ; - interrupt-names = "hostc"; - - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - - resets = <&powerdown STIH407_SATA0_POWERDOWN>, - <&softreset STIH407_SATA0_SOFTRESET>, - <&softreset STIH407_SATA0_PWR_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; - - clock-names = "ahci_clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - - ports-implemented = <0x1>; - - status = "disabled"; - }; - - sata1: sata@9b28000 { - compatible = "st,ahci"; - reg = <0x9b28000 0x1000>; - - interrupts = ; - interrupt-names = "hostc"; - - phys = <&phy_port1 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - - resets = <&powerdown STIH407_SATA1_POWERDOWN>, - <&softreset STIH407_SATA1_SOFTRESET>, - <&softreset STIH407_SATA1_PWR_SOFTRESET>; - reset-names = "pwr-dwn", - "sw-rst", - "pwr-rst"; - - clock-names = "ahci_clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - - ports-implemented = <0x1>; - - status = "disabled"; - }; - - - st_dwc3: dwc3@8f94000 { - compatible = "st,stih407-dwc3"; - reg = <0x08f94000 0x1000>, <0x110 0x4>; - reg-names = "reg-glue", "syscfg-reg"; - st,syscfg = <&syscfg_core>; - resets = <&powerdown STIH407_USB3_POWERDOWN>, - <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", "softreset"; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - ranges; - - status = "disabled"; - - dwc3: dwc3@9900000 { - compatible = "snps,dwc3"; - reg = <0x09900000 0x100000>; - interrupts = ; - dr_mode = "host"; - phy-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy0>, - <&phy_port2 PHY_TYPE_USB3>; - snps,dis_u3_susphy_quirk; - }; - }; - - /* COMMS PWM Module */ - pwm0: pwm@9810000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9810000 0x68>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <1>; - - status = "disabled"; - }; - - /* SBC PWM Module */ - pwm1: pwm@9510000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9510000 0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - &pinctrl_pwm1_chan1_default - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <4>; - - status = "disabled"; - }; - - rng10: rng@08a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@08a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - device_type = "network"; - status = "disabled"; - compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - reg = <0x9630000 0x8000>, <0x80 0x4>; - reg-names = "stmmaceth", "sti-ethconf"; - - st,syscon = <&syscfg_sbc_reg 0x80>; - st,gmac_en; - resets = <&softreset STIH407_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - - /* DMA Bus Mode */ - snps,pbl = <8>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>; - - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_ETH_PHY>; - }; - - cec: sti-cec@094a087c { - compatible = "st,stih-cec"; - reg = <0x94a087c 0x64>; - clocks = <&clk_sysin>; - clock-names = "cec-clk"; - interrupts = ; - interrupt-names = "cec-irq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cec0_default>; - resets = <&softreset STIH407_LPM_SOFTRESET>; - }; - - rng10: rng@08a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@08a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - mailbox0: mailbox@8f00000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f00000 0x1000>; - interrupts = ; - #mbox-cells = <2>; - mbox-name = "a9"; - status = "okay"; - }; - - mailbox1: mailbox@8f01000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f01000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_1"; - status = "okay"; - }; - - mailbox2: mailbox@8f02000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f02000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_0"; - status = "okay"; - }; - - mailbox3: mailbox@8f03000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f03000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_audio_video"; - status = "okay"; - }; - - st231_gp0: remote-processor { - compatible = "st,st231-rproc"; - memory-region = <&gp0_reserved>; - resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x22c>; - }; - - - st231_gp1: remote-processor { - compatible = "st,st231-rproc"; - memory-region = <&gp1_reserved>; - resets = <&softreset STIH407_ST231_GP1_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x220>; - }; - - st231_audio: remote-processor { - compatible = "st,st231-rproc"; - memory-region = <&audio_reserved>; - resets = <&softreset STIH407_ST231_AUD_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x228>; - }; - - st231_dmu: remote-processor { - compatible = "st,st231-rproc"; - memory-region = <&dmu_reserved>; - resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x224>; - }; - - /* fdma audio */ - fdma0: dma-controller@8e20000 { - compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; - reg = <0x8e20000 0x8000>, - <0x8e30000 0x3000>, - <0x8e37000 0x1000>, - <0x8e38000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - }; - - /* fdma app */ - fdma1: dma-controller@8e40000 { - compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; - reg = <0x8e40000 0x8000>, - <0x8e50000 0x3000>, - <0x8e57000 0x1000>, - <0x8e58000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, - <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - }; - - /* fdma free running */ - fdma2: dma-controller@8e60000 { - compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; - reg = <0x8e60000 0x8000>, - <0x8e70000 0x3000>, - <0x8e77000 0x1000>, - <0x8e78000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - }; - - sti_sasg_codec: sti-sasg-codec { - compatible = "st,stih407-sas-codec"; - #sound-dai-cells = <1>; - status = "disabled"; - st,syscfg = <&syscfg_core>; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - compatible = "st,sti-uni-player"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_0>; - assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; - assigned-clock-rates = <50000000>; - reg = <0x8d80000 0x158>; - interrupts = ; - dmas = <&fdma0 2 0 1>; - dai-name = "Uni Player #0 (HDMI)"; - dma-names = "tx"; - st,uniperiph-id = <0>; - st,version = <5>; - st,mode = "HDMI"; - - status = "disabled"; - }; - - sti_uni_player1: sti-uni-player@8d81000 { - compatible = "st,sti-uni-player"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_1>; - assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; - assigned-clock-rates = <50000000>; - reg = <0x8d81000 0x158>; - interrupts = ; - dmas = <&fdma0 3 0 1>; - dai-name = "Uni Player #1 (PIO)"; - dma-names = "tx"; - st,uniperiph-id = <1>; - st,version = <5>; - st,mode = "PCM"; - - status = "disabled"; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - compatible = "st,sti-uni-player"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; - assigned-clock-rates = <50000000>; - reg = <0x8d82000 0x158>; - interrupts = ; - dmas = <&fdma0 4 0 1>; - dai-name = "Uni Player #1 (DAC)"; - dma-names = "tx"; - st,uniperiph-id = <2>; - st,version = <5>; - st,mode = "PCM"; - - status = "disabled"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - compatible = "st,sti-uni-player"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; - assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; - assigned-clock-rates = <50000000>; - reg = <0x8d85000 0x158>; - interrupts = ; - dmas = <&fdma0 7 0 1>; - dma-names = "tx"; - dai-name = "Uni Player #1 (PIO)"; - st,uniperiph-id = <3>; - st,version = <5>; - st,mode = "SPDIF"; - - status = "disabled"; - }; - - sti_uni_reader0: sti-uni-reader@8d83000 { - compatible = "st,sti-uni-reader"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8d83000 0x158>; - interrupts = ; - dmas = <&fdma0 5 0 1>; - dma-names = "rx"; - dai-name = "Uni Reader #0 (PCM IN)"; - st,version = <3>; - - status = "disabled"; - }; - - sti_uni_reader1: sti-uni-reader@8d84000 { - compatible = "st,sti-uni-reader"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8d84000 0x158>; - interrupts = ; - dmas = <&fdma0 6 0 1>; - dma-names = "rx"; - dai-name = "Uni Reader #1 (HDMI RX)"; - st,version = <3>; - - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih407-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih407-pinctrl.dtsi deleted file mode 100644 index c325cc059..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ /dev/null @@ -1,1257 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Giuseppe Cavallaro - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - /* 0-5: PIO_SBC */ - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - /* 10-19: PIO_FRONT0 */ - gpio6 = &pio10; - gpio7 = &pio11; - gpio8 = &pio12; - gpio9 = &pio13; - gpio10 = &pio14; - gpio11 = &pio15; - gpio12 = &pio16; - gpio13 = &pio17; - gpio14 = &pio18; - gpio15 = &pio19; - /* 20: PIO_FRONT1 */ - gpio16 = &pio20; - /* 30-35: PIO_REAR */ - gpio17 = &pio30; - gpio18 = &pio31; - gpio19 = &pio32; - gpio20 = &pio33; - gpio21 = &pio34; - gpio22 = &pio35; - /* 40-42: PIO_FLASH */ - gpio23 = &pio40; - gpio24 = &pio41; - gpio25 = &pio42; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0x0961f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09610000 0x6000>; - - pio0: gpio@09610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@09611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@09612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@09613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@09614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - pio5: gpio@09615000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO5"; - st,retime-pin-mask = <0x3f>; - }; - - cec0 { - pinctrl_cec0_default: cec0-default { - st,pins { - hdmi_cec = <&pio2 4 ALT1 BIDIR>; - }; - }; - }; - - rc { - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - - pinctrl_uhf: uhf0 { - st,pins { - ir = <&pio4 1 ALT2 IN>; - }; - }; - - pinctrl_tx: tx0 { - st,pins { - tx = <&pio4 2 ALT2 OUT>; - }; - }; - - pinctrl_tx_od: tx_od0 { - st,pins { - tx_od = <&pio4 3 ALT2 OUT>; - }; - }; - }; - - /* SBC_ASC0 - UART10 */ - sbc_serial0 { - pinctrl_sbc_serial0: sbc_serial0-0 { - st,pins { - tx = <&pio3 4 ALT1 OUT>; - rx = <&pio3 5 ALT1 IN>; - }; - }; - }; - /* SBC_ASC1 - UART11 */ - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1-0 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - i2c10 { - pinctrl_i2c10_default: i2c10-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - i2c11 { - pinctrl_i2c11_default: i2c11-default { - st,pins { - sda = <&pio5 1 ALT1 BIDIR>; - scl = <&pio5 0 ALT1 BIDIR>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio4 0 ALT6 IN>; - keyin1 = <&pio4 5 ALT4 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio4 6 ALT4 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - gmac1 { - /* - * Almost all the boards based on STiH407 SoC have an embedded - * switch where the mdio/mdc have been used for managing the SMI - * iface via I2C. For this reason these lines can be allocated - * by using dedicated configuration (in case of there will be a - * standard PHY transceiver on-board). - */ - pinctrl_rgmii1: rgmii1-0 { - st,pins { - - txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; - }; - }; - - pinctrl_rgmii1_mdio: rgmii1-mdio { - st,pins { - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - }; - }; - - pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { - st,pins { - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_rmii1: rmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - - pinctrl_rmii1_phyclk: rmii1_phyclk { - st,pins { - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { - st,pins { - phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - pwm-capturein = <&pio3 2 ALT1 IN>; - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-capturein = <&pio4 3 ALT1 IN>; - pwm-out = <&pio4 4 ALT1 OUT>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - - spi10 { - pinctrl_spi10_default: spi10-4w-alt1-0 { - st,pins { - mtsr = <&pio4 6 ALT1 OUT>; - mrst = <&pio4 7 ALT1 IN>; - scl = <&pio4 5 ALT1 OUT>; - }; - }; - - pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 { - st,pins { - mtsr = <&pio4 6 ALT1 BIDIR_PU>; - scl = <&pio4 5 ALT1 OUT>; - }; - }; - }; - - spi11 { - pinctrl_spi11_default: spi11-4w-alt2-0 { - st,pins { - mtsr = <&pio3 1 ALT2 OUT>; - mrst = <&pio3 0 ALT2 IN>; - scl = <&pio3 2 ALT2 OUT>; - }; - }; - - pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 { - st,pins { - mtsr = <&pio3 1 ALT2 BIDIR_PU>; - scl = <&pio3 2 ALT2 OUT>; - }; - }; - }; - - spi12 { - pinctrl_spi12_default: spi12-4w-alt2-0 { - st,pins { - mtsr = <&pio3 6 ALT2 OUT>; - mrst = <&pio3 4 ALT2 IN>; - scl = <&pio3 7 ALT2 OUT>; - }; - }; - - pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 { - st,pins { - mtsr = <&pio3 6 ALT2 BIDIR_PU>; - scl = <&pio3 7 ALT2 OUT>; - }; - }; - }; - }; - - pin-controller-front0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0x0920f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09200000 0x10000>; - - pio10: pio@09200000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO10"; - }; - pio11: pio@09201000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: pio@09202000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO12"; - }; - pio13: pio@09203000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO13"; - }; - pio14: pio@09204000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: pio@09205000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: pio@09206000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: pio@09207000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: pio@09208000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO18"; - }; - pio19: pio@09209000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO19"; - }; - - /* Comms */ - serial0 { - pinctrl_serial0: serial0-0 { - st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; - }; - }; - }; - - serial1 { - pinctrl_serial1: serial1-0 { - st,pins { - tx = <&pio16 0 ALT1 OUT>; - rx = <&pio16 1 ALT1 IN>; - }; - }; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio15 0 ALT1 OUT>; - rx = <&pio15 1 ALT1 IN>; - }; - }; - }; - - mmc1 { - pinctrl_sd1: sd1-0 { - st,pins { - sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; - sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; - sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; - sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; - sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; - sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; - sd_led = <&pio16 6 ALT6 OUT>; - sd_pwren = <&pio16 7 ALT6 OUT>; - sd_cd = <&pio19 0 ALT6 IN>; - sd_wp = <&pio19 1 ALT6 IN>; - }; - }; - }; - - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio10 6 ALT2 BIDIR>; - scl = <&pio10 5 ALT2 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio11 1 ALT2 BIDIR>; - scl = <&pio11 0 ALT2 BIDIR>; - }; - }; - }; - - i2c2 { - pinctrl_i2c2_default: i2c2-default { - st,pins { - sda = <&pio15 6 ALT2 BIDIR>; - scl = <&pio15 5 ALT2 BIDIR>; - }; - }; - - pinctrl_i2c2_alt2_1: i2c2-alt2-1 { - st,pins { - sda = <&pio12 6 ALT2 BIDIR>; - scl = <&pio12 5 ALT2 BIDIR>; - }; - }; - }; - - i2c3 { - pinctrl_i2c3_default: i2c3-alt1-0 { - st,pins { - sda = <&pio18 6 ALT1 BIDIR>; - scl = <&pio18 5 ALT1 BIDIR>; - }; - }; - pinctrl_i2c3_alt1_1: i2c3-alt1-1 { - st,pins { - sda = <&pio17 7 ALT1 BIDIR>; - scl = <&pio17 6 ALT1 BIDIR>; - }; - }; - pinctrl_i2c3_alt3_0: i2c3-alt3-0 { - st,pins { - sda = <&pio13 6 ALT3 BIDIR>; - scl = <&pio13 5 ALT3 BIDIR>; - }; - }; - }; - - spi0 { - pinctrl_spi0_default: spi0-4w-alt2-0 { - st,pins { - mtsr = <&pio10 6 ALT2 OUT>; - mrst = <&pio10 7 ALT2 IN>; - scl = <&pio10 5 ALT2 OUT>; - }; - }; - - pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 { - st,pins { - mtsr = <&pio10 6 ALT2 BIDIR_PU>; - scl = <&pio10 5 ALT2 OUT>; - }; - }; - - pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 { - st,pins { - mtsr = <&pio19 7 ALT1 OUT>; - mrst = <&pio19 5 ALT1 IN>; - scl = <&pio19 6 ALT1 OUT>; - }; - }; - - pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 { - st,pins { - mtsr = <&pio19 7 ALT1 BIDIR_PU>; - scl = <&pio19 6 ALT1 OUT>; - }; - }; - }; - - spi1 { - pinctrl_spi1_default: spi1-4w-alt2-0 { - st,pins { - mtsr = <&pio11 1 ALT2 OUT>; - mrst = <&pio11 2 ALT2 IN>; - scl = <&pio11 0 ALT2 OUT>; - }; - }; - - pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 { - st,pins { - mtsr = <&pio11 1 ALT2 BIDIR_PU>; - scl = <&pio11 0 ALT2 OUT>; - }; - }; - - pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 { - st,pins { - mtsr = <&pio14 3 ALT1 OUT>; - mrst = <&pio14 4 ALT1 IN>; - scl = <&pio14 2 ALT1 OUT>; - }; - }; - - pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 { - st,pins { - mtsr = <&pio14 3 ALT1 BIDIR_PU>; - scl = <&pio14 2 ALT1 OUT>; - }; - }; - }; - - spi2 { - pinctrl_spi2_default: spi2-4w-alt2-0 { - st,pins { - mtsr = <&pio12 6 ALT2 OUT>; - mrst = <&pio12 7 ALT2 IN>; - scl = <&pio12 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 { - st,pins { - mtsr = <&pio12 6 ALT2 BIDIR_PU>; - scl = <&pio12 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 { - st,pins { - mtsr = <&pio14 6 ALT1 OUT>; - mrst = <&pio14 7 ALT1 IN>; - scl = <&pio14 5 ALT1 OUT>; - }; - }; - - pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 { - st,pins { - mtsr = <&pio14 6 ALT1 BIDIR_PU>; - scl = <&pio14 5 ALT1 OUT>; - }; - }; - - pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 { - st,pins { - mtsr = <&pio15 6 ALT2 OUT>; - mrst = <&pio15 7 ALT2 IN>; - scl = <&pio15 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 { - st,pins { - mtsr = <&pio15 6 ALT2 BIDIR_PU>; - scl = <&pio15 5 ALT2 OUT>; - }; - }; - }; - - spi3 { - pinctrl_spi3_default: spi3-4w-alt3-0 { - st,pins { - mtsr = <&pio13 6 ALT3 OUT>; - mrst = <&pio13 7 ALT3 IN>; - scl = <&pio13 5 ALT3 OUT>; - }; - }; - - pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 { - st,pins { - mtsr = <&pio13 6 ALT3 BIDIR_PU>; - scl = <&pio13 5 ALT3 OUT>; - }; - }; - - pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 { - st,pins { - mtsr = <&pio17 7 ALT1 OUT>; - mrst = <&pio17 5 ALT1 IN>; - scl = <&pio17 6 ALT1 OUT>; - }; - }; - - pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 { - st,pins { - mtsr = <&pio17 7 ALT1 BIDIR_PU>; - scl = <&pio17 6 ALT1 OUT>; - }; - }; - - pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 { - st,pins { - mtsr = <&pio18 6 ALT1 OUT>; - mrst = <&pio18 7 ALT1 IN>; - scl = <&pio18 5 ALT1 OUT>; - }; - }; - - pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 { - st,pins { - mtsr = <&pio18 6 ALT1 BIDIR_PU>; - scl = <&pio18 5 ALT1 OUT>; - }; - }; - }; - - tsin0 { - pinctrl_tsin0_parallel: tsin0_parallel { - st,pins { - DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin0_serial: tsin0_serial { - st,pins { - DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin1 { - pinctrl_tsin1_parallel: tsin1_parallel { - st,pins { - DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin1_serial: tsin1_serial { - st,pins { - DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin2 { - pinctrl_tsin2_parallel: tsin2_parallel { - st,pins { - DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin2_serial: tsin2_serial { - st,pins { - DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin3 { - pinctrl_tsin3_serial: tsin3_serial { - st,pins { - DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin4 { - pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { - st,pins { - DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; - ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; - PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin5 { - pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { - st,pins { - DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { - st,pins { - DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsout0 { - pinctrl_tsout0_parallel: tsout0_parallel { - st,pins { - DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; - VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsout0_serial: tsout0_serial { - st,pins { - DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; - VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsout1 { - pinctrl_tsout1_serial: tsout1_serial { - st,pins { - DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; - VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - mtsin0 { - pinctrl_mtsin0_parallel: mtsin0_parallel { - st,pins { - DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - systrace { - pinctrl_systrace_default: systrace-default { - st,pins { - trc_data0 = <&pio11 3 ALT5 OUT>; - trc_data1 = <&pio11 4 ALT5 OUT>; - trc_data2 = <&pio11 5 ALT5 OUT>; - trc_data3 = <&pio11 6 ALT5 OUT>; - trc_clk = <&pio11 7 ALT5 OUT>; - }; - }; - }; - }; - - pin-controller-front1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0x0921f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09210000 0x10000>; - - pio20: pio@09210000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO20"; - }; - - tsin4 { - pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { - st,pins { - DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0x0922f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09220000 0x6000>; - - pio30: gpio@09220000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@09221000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO31"; - }; - pio32: gpio@09222000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO32"; - }; - pio33: gpio@09223000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO33"; - }; - pio34: gpio@09224000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO34"; - }; - pio35: gpio@09225000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO35"; - st,retime-pin-mask = <0x7f>; - }; - - i2c4 { - pinctrl_i2c4_default: i2c4-default { - st,pins { - sda = <&pio30 1 ALT1 BIDIR>; - scl = <&pio30 0 ALT1 BIDIR>; - }; - }; - }; - - i2c5 { - pinctrl_i2c5_default: i2c5-default { - st,pins { - sda = <&pio34 4 ALT1 BIDIR>; - scl = <&pio34 3 ALT1 BIDIR>; - }; - }; - }; - - usb3 { - pinctrl_usb3: usb3-2 { - st,pins { - usb-oc-detect = <&pio35 4 ALT1 IN>; - usb-pwr-enable = <&pio35 5 ALT1 OUT>; - usb-vbus-valid = <&pio35 6 ALT1 IN>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-capturein = <&pio31 0 ALT1 IN>; - pwm-out = <&pio31 1 ALT1 OUT>; - }; - }; - }; - - spi4 { - pinctrl_spi4_default: spi4-4w-alt1-0 { - st,pins { - mtsr = <&pio30 1 ALT1 OUT>; - mrst = <&pio30 2 ALT1 IN>; - scl = <&pio30 0 ALT1 OUT>; - }; - }; - - pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 { - st,pins { - mtsr = <&pio30 1 ALT1 BIDIR_PU>; - scl = <&pio30 0 ALT1 OUT>; - }; - }; - - pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 { - st,pins { - mtsr = <&pio34 1 ALT3 OUT>; - mrst = <&pio34 2 ALT3 IN>; - scl = <&pio34 0 ALT3 OUT>; - }; - }; - - pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 { - st,pins { - mtsr = <&pio34 1 ALT3 BIDIR_PU>; - scl = <&pio34 0 ALT3 OUT>; - }; - }; - }; - - i2s_out { - pinctrl_i2s_8ch_out: i2s_8ch_out{ - st,pins { - mclk = <&pio33 5 ALT1 OUT>; - lrclk = <&pio33 7 ALT1 OUT>; - sclk = <&pio33 6 ALT1 OUT>; - data0 = <&pio33 4 ALT1 OUT>; - data1 = <&pio34 0 ALT1 OUT>; - data2 = <&pio34 1 ALT1 OUT>; - data3 = <&pio34 2 ALT1 OUT>; - }; - }; - - pinctrl_i2s_2ch_out: i2s_2ch_out{ - st,pins { - mclk = <&pio33 5 ALT1 OUT>; - lrclk = <&pio33 7 ALT1 OUT>; - sclk = <&pio33 6 ALT1 OUT>; - data0 = <&pio33 4 ALT1 OUT>; - }; - }; - }; - - i2s_in { - pinctrl_i2s_8ch_in: i2s_8ch_in{ - st,pins { - mclk = <&pio32 5 ALT1 IN>; - lrclk = <&pio32 7 ALT1 IN>; - sclk = <&pio32 6 ALT1 IN>; - data0 = <&pio32 4 ALT1 IN>; - data1 = <&pio33 0 ALT1 IN>; - data2 = <&pio33 1 ALT1 IN>; - data3 = <&pio33 2 ALT1 IN>; - data4 = <&pio33 3 ALT1 IN>; - }; - }; - - pinctrl_i2s_2ch_in: i2s_2ch_in{ - st,pins { - mclk = <&pio32 5 ALT1 IN>; - lrclk = <&pio32 7 ALT1 IN>; - sclk = <&pio32 6 ALT1 IN>; - data0 = <&pio32 4 ALT1 IN>; - }; - }; - }; - - spdif_out { - pinctrl_spdif_out: spdif_out{ - st,pins { - spdif_out = <&pio34 7 ALT1 OUT>; - }; - }; - }; - - serial3 { - pinctrl_serial3: serial3-0 { - st,pins { - tx = <&pio31 3 ALT1 OUT>; - rx = <&pio31 4 ALT1 IN>; - }; - }; - }; - }; - - pin-controller-flash { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-flash-pinctrl"; - st,syscfg = <&syscfg_flash>; - reg = <0x0923f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupts-names = "irqmux"; - ranges = <0 0x09230000 0x3000>; - - pio40: gpio@09230000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO40"; - }; - pio41: gpio@09231000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO41"; - }; - pio42: gpio@09232000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO42"; - }; - - mmc0 { - pinctrl_mmc0: mmc0-0 { - st,pins { - emmc_clk = <&pio40 6 ALT1 BIDIR>; - emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; - emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; - emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; - emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; - emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; - emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; - emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; - emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; - emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; - }; - }; - pinctrl_sd0: sd0-0 { - st,pins { - sd_clk = <&pio40 6 ALT1 BIDIR>; - sd_cmd = <&pio40 7 ALT1 BIDIR_PU>; - sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>; - sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>; - sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>; - sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>; - sd_led = <&pio42 0 ALT2 OUT>; - sd_pwren = <&pio42 2 ALT2 OUT>; - sd_vsel = <&pio42 3 ALT2 OUT>; - sd_cd = <&pio42 4 ALT2 IN>; - sd_wp = <&pio42 5 ALT2 IN>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio40 1 ALT1 OUT>; - spi-fsm-cs = <&pio40 0 ALT1 OUT>; - spi-fsm-mosi = <&pio40 2 ALT1 OUT>; - spi-fsm-miso = <&pio40 3 ALT1 IN>; - spi-fsm-hol = <&pio40 5 ALT1 OUT>; - spi-fsm-wp = <&pio40 4 ALT1 OUT>; - }; - }; - }; - - nand { - pinctrl_nand: nand { - st,pins { - nand_cs1 = <&pio40 6 ALT3 OUT>; - nand_cs0 = <&pio40 7 ALT3 OUT>; - nand_d0 = <&pio41 0 ALT3 BIDIR>; - nand_d1 = <&pio41 1 ALT3 BIDIR>; - nand_d2 = <&pio41 2 ALT3 BIDIR>; - nand_d3 = <&pio41 3 ALT3 BIDIR>; - nand_d4 = <&pio41 4 ALT3 BIDIR>; - nand_d5 = <&pio41 5 ALT3 BIDIR>; - nand_d6 = <&pio41 6 ALT3 BIDIR>; - nand_d7 = <&pio41 7 ALT3 BIDIR>; - nand_we = <&pio42 0 ALT3 OUT>; - nand_dqs = <&pio42 1 ALT3 OUT>; - nand_ale = <&pio42 2 ALT3 OUT>; - nand_cle = <&pio42 3 ALT3 OUT>; - nand_rnb = <&pio42 4 ALT3 IN>; - nand_oe = <&pio42 5 ALT3 OUT>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih407.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih407.dtsi deleted file mode 100644 index fe043d313..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih407.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (C) 2015 STMicroelectronics Limited. - * Author: Gabriel Fernandez - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih407-clock.dtsi" -#include "stih407-family.dtsi" -#include -/ { - soc { - sti-display-subsystem { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - - assigned-clock-rates = <297000000>, - <108000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; - #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - }; - - sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; - }; - - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih410-b2120.dts b/software/linux/kernel/arch/arm/boot/dts/stih410-b2120.dts deleted file mode 100644 index 118ac284f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih410-b2120.dts +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Peter Griffin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; -#include "stih410.dtsi" -#include "stihxxx-b2120.dtsi" -/ { - model = "STiH410 B2120"; - compatible = "st,stih410-b2120", "st,stih410"; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial0; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - ttyAS0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - - soc { - - mmc0: sdhci@09060000 { - max-frequency = <200000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - }; - - usb2_picophy1: phy2 { - status = "okay"; - }; - - usb2_picophy2: phy3 { - status = "okay"; - }; - - ohci0: usb@9a03c00 { - status = "okay"; - }; - - ehci0: usb@9a03e00 { - status = "okay"; - }; - - ohci1: usb@9a83c00 { - status = "okay"; - }; - - ehci1: usb@9a83e00 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih410-b2260.dts b/software/linux/kernel/arch/arm/boot/dts/stih410-b2260.dts deleted file mode 100644 index 7fb507fcb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih410-b2260.dts +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (C) 2016 STMicroelectronics (R&D) Limited. - * Author: Patrice Chotard - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; -#include "stih410.dtsi" -#include - -/ { - model = "STiH410 B2260"; - compatible = "st,stih410-b2260", "st,stih410"; - - chosen { - bootargs = "console=ttyAS1,115200 clk_ignore_unused"; - linux,stdout-path = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - aliases { - ttyAS1 = &uart1; - ethernet0 = ðernet0; - }; - - soc { - - leds { - compatible = "gpio-leds"; - user_green_1 { - label = "User_green_1"; - gpios = <&pio1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user_green_2 { - label = "User_green_2"; - gpios = <&pio4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - user_green_3 { - label = "User_green_3"; - gpios = <&pio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - user_green_4 { - label = "User_green_4"; - gpios = <&pio2 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - /* Low speed expansion connector */ - uart0: serial@9830000 { - label = "LS-UART0"; - status = "okay"; - }; - - /* Low speed expansion connector */ - uart1: serial@9831000 { - label = "LS-UART1"; - status = "okay"; - }; - - /* Low speed expansion connector */ - spi0: spi@9844000 { - label = "LS-SPI0"; - cs-gpios = <&pio30 3 0>; - status = "okay"; - }; - - /* Low speed expansion connector */ - i2c0: i2c@9840000 { - label = "LS-I2C0"; - status = "okay"; - }; - - /* Low speed expansion connector */ - i2c1: i2c@9841000 { - label = "LS-I2C1"; - status = "okay"; - }; - - /* high speed expansion connector */ - i2c2: i2c@9842000 { - label = "HS-I2C2"; - pinctrl-0 = <&pinctrl_i2c2_alt2_1>; - status = "okay"; - }; - - /* high speed expansion connector */ - i2c3: i2c@9843000 { - label = "HS-I2C3"; - pinctrl-0 = <&pinctrl_i2c3_alt3_0>; - status = "okay"; - }; - - mmc0: sdhci@09060000 { - pinctrl-0 = <&pinctrl_sd0>; - bus-width = <4>; - status = "okay"; - }; - - /* high speed expansion connector */ - mmc1: sdhci@09080000 { - status = "okay"; - }; - - pwm0: pwm@9810000 { - status = "okay"; - }; - - pwm1: pwm@9510000 { - status = "okay"; - }; - - usb2_picophy1: phy2 { - status = "okay"; - }; - - usb2_picophy2: phy3 { - status = "okay"; - }; - - ohci0: usb@9a03c00 { - status = "okay"; - }; - - ehci0: usb@9a03e00 { - status = "okay"; - }; - - ohci1: usb@9a83c00 { - status = "okay"; - }; - - ehci1: usb@9a83e00 { - status = "okay"; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - phy-mode = "rgmii"; - pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; - - snps,phy-bus-name = "stmmac"; - snps,phy-bus-id = <0>; - snps,phy-addr = <0>; - snps,reset-gpio = <&pio0 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - - status = "okay"; - }; - - /* SSC11 to HDMI */ - hdmiddc: i2c@9541000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - status = "okay"; - }; - - sti-display-subsystem { - sti_hdmi: sti-hdmi@8d04000 { - status = "okay"; - }; - }; - - miphy28lp_phy: miphy28lp@9b22000 { - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - sata1: sata@9b28000 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih410-clock.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih410-clock.dtsi deleted file mode 100644 index 8598effd6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih410-clock.dtsi +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - compatible = "st,stih410-clk", "simple-bus"; - - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; - }; - - clockgen-a@090ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0", - "clk-ic-lmi1"; - clock-critical = ; - }; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ - }; - - clk_s_c0: clockgen-c@09103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-proc-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-ext2fa9", - "clk-ic-bdisp-0", - "clk-ic-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-disp-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phy", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp", - "clk-tx-icn-hades", - "clk-rx-icn-hades", - "clk-icn-reg-16", - "clk-pp-hades", - "clk-clust-hades", - "clk-hwpe-hades", - "clk-fc-hades"; - clock-critical = , - , - , - , - ; - }; - }; - - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; - }; - - clockgen-d0@09104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-audio", "st,flexgen"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-pcm-0", - "clk-pcm-1", - "clk-pcm-2", - "clk-spdiff", - "clk-pcmr10-master", - "clk-usb2-phy"; - }; - }; - - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-video", "st,flexgen"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - - clock-output-names = "clk-pix-main-disp", - "clk-pix-pip", - "clk-pix-gdp1", - "clk-pix-gdp2", - "clk-pix-gdp3", - "clk-pix-gdp4", - "clk-pix-aux-disp", - "clk-denc", - "clk-pix-hddac", - "clk-hddac", - "clk-sddac", - "clk-pix-dvo", - "clk-dvo", - "clk-pix-hdmi", - "clk-tmds-hdmi", - "clk-ref-hdmiphy"; - }; - }; - - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-stfe-frc1", - "clk-tsout-0", - "clk-tsout-1", - "clk-mchi", - "clk-vsens-compo", - "clk-frc1-remote", - "clk-lpc-0", - "clk-lpc-1"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih410-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih410-pinctrl.dtsi deleted file mode 100644 index b3e9dfc81..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih410-pinctrl.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -/ { - - soc { - pin-controller-rear { - - usb0 { - pinctrl_usb0: usb2-0 { - st,pins { - usb-oc-detect = <&pio35 0 ALT1 IN>; - usb-pwr-enable = <&pio35 1 ALT1 OUT>; - }; - }; - }; - - usb1 { - pinctrl_usb1: usb2-1 { - st,pins { - usb-oc-detect = <&pio35 2 ALT1 IN>; - usb-pwr-enable = <&pio35 3 ALT1 OUT>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih410.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih410.dtsi deleted file mode 100644 index 3c118fc2b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih410.dtsi +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih410-clock.dtsi" -#include "stih407-family.dtsi" -#include "stih410-pinctrl.dtsi" -#include -/ { - aliases { - bdisp0 = &bdisp0; - }; - - soc { - usb2_picophy1: phy2 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - usb2_picophy2: phy3 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - ohci0: usb@9a03c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a03c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ehci0: usb@9a03e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a03e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ohci1: usb@9a83c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a83c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - - status = "disabled"; - }; - - ehci1: usb@9a83e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a83e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - - status = "disabled"; - }; - - sti-display-subsystem { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - - assigned-clock-rates = <297000000>, - <297000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; - #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - }; - - sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; - }; - - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; - }; - - bdisp0:bdisp@9f10000 { - compatible = "st,stih407-bdisp"; - reg = <0x9f10000 0x1000>; - interrupts = ; - clock-names = "bdisp"; - clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; - }; - - hva@8c85000 { - compatible = "st,st-hva"; - reg = <0x8c85000 0x400>, <0x6000000 0x40000>; - reg-names = "hva_registers", "hva_esram"; - interrupts = , - ; - clock-names = "clk_hva"; - clocks = <&clk_s_c0_flexgen CLK_HVA>; - }; - - thermal@91a0000 { - compatible = "st,stih407-thermal"; - reg = <0x91a0000 0x28>; - clock-names = "thermal"; - clocks = <&clk_sysin>; - interrupts = ; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih415-b2000.dts b/software/linux/kernel/arch/arm/boot/dts/stih415-b2000.dts deleted file mode 100644 index bdfbd3765..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih415-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH415 B2000 Board"; - compatible = "st,stih415-b2000", "st,stih415"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih415-b2020.dts b/software/linux/kernel/arch/arm/boot/dts/stih415-b2020.dts deleted file mode 100644 index 71903a87b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih415-b2020.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih415.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH415 B2020 Board"; - compatible = "st,stih415-b2020", "st,stih415"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih415-clock.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih415-clock.dtsi deleted file mode 100644 index 3ee34514b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih415-clock.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator input to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG1 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - ""; /* clk-s-stac-sys */ - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE41 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-apb-pm", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-disp", - ""; /* Unused */ - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-icn-dmu-0", - "clk-m-icn-dmu-1", - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-eram", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-fdma-12", - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-lmi", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-icn-gpu", - "clk-m-icn-vdp-0"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-icn-vdp-1", - "clk-m-icn-vdp-2", - "clk-m-icn-vdp-3", - "clk-m-prv-t1-bus", - "clk-m-icn-vdp-4", - "clk-m-icn-reg-10", - "", /* Unused */ - ""; /* clk-m-icn-st231 */ - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* Unused */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp-0", - "clk-m-icn-bdisp-1"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "", /* clk-m-icn-hqvdp0 */ - "", /* clk-m-icn-hqvdp1 */ - "clk-m-icn-compo", - "", /* clk-m-icn-vdpaux */ - "clk-m-icn-ts", - "clk-m-icn-reg-lp-10", - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = ""; /* Unused */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde00d8 { - reg = <0xfdde00d8 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde00d8 { - #clock-cells = <0>; - compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde00d8 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih415-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih415-pinctrl.dtsi deleted file mode 100644 index bd028ce98..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - gpio6 = &pio6; - gpio7 = &pio7; - gpio8 = &pio8; - gpio9 = &pio9; - gpio10 = &pio10; - gpio11 = &pio11; - gpio12 = &pio12; - gpio13 = &pio13; - gpio14 = &pio14; - gpio15 = &pio15; - gpio16 = &pio16; - gpio17 = &pio17; - gpio18 = &pio18; - gpio19 = &pio100; - gpio20 = &pio101; - gpio21 = &pio102; - gpio22 = &pio103; - gpio23 = &pio104; - gpio24 = &pio105; - gpio25 = &pio106; - gpio26 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x5000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - sbc_serial1 { - pinctrl_sbc_serial1:sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; - }; - }; - - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x8000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x8000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0{ - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; - - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - - - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - }; - - pin-controller-left { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-left-pinctrl"; - st,syscfg = <&syscfg_left>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-right { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih415-right-pinctrl"; - st,syscfg = <&syscfg_right>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih415.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih415.dtsi deleted file mode 100644 index 12427e651..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih415.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih415-clock.dtsi" -#include "stih415-pinctrl.dtsi" -#include -#include -/ { - - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 2 2>; - arm,tag-latency = <1 1 1>; - cache-unified; - cache-level = <2>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih415-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih415-softreset"; - }; - - syscfg_sbc: sbc-syscfg@fe600000{ - compatible = "st,stih415-sbc-syscfg", "syscon"; - reg = <0xfe600000 0xb4>; - }; - - syscfg_front: front-syscfg@fee10000{ - compatible = "st,stih415-front-syscfg", "syscon"; - reg = <0xfee10000 0x194>; - }; - - syscfg_rear: rear-syscfg@fe830000{ - compatible = "st,stih415-rear-syscfg", "syscon"; - reg = <0xfe830000 0x190>; - }; - - /* MPE syscfgs */ - syscfg_left: left-syscfg@fd690000{ - compatible = "st,stih415-left-syscfg", "syscon"; - reg = <0xfd690000 0x78>; - }; - - syscfg_right: right-syscfg@fd320000{ - compatible = "st,stih415-right-syscfg", "syscon"; - reg = <0xfd320000 0x180>; - }; - - syscfg_system: system-syscfg@fdde0000 { - compatible = "st,stih415-system-syscfg", "syscon"; - reg = <0xfdde0000 0x15c>; - }; - - syscfg_lpm: lpm-syscfg@fe4b5100{ - compatible = "st,stih415-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x08>; - }; - - serial2: serial@fed32000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - }; - - /* SBC comms block ASCs in SASG1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 147 0>, <0 148 0>, <0 149 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - resets = <&softreset STIH415_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_rear 0x148>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 150 0>, <0 151 0>, <0 152 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - snps,force_sf_dma_mode; - - st,syscon = <&syscfg_sbc 0x74>; - - resets = <&softreset STIH415_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - clocks = <&clk_sysin>; - rx-mode = "infrared"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH415_IRB_SOFTRESET>; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = ; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, - <&softreset STIH415_KEYSCAN_SOFTRESET>; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih416-b2000.dts b/software/linux/kernel/arch/arm/boot/dts/stih416-b2000.dts deleted file mode 100644 index 488e80a5d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih416-b2000.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2000.dtsi" -/ { - model = "STiH416 B2000"; - compatible = "st,stih416-b2000", "st,stih416"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih416-b2020.dts b/software/linux/kernel/arch/arm/boot/dts/stih416-b2020.dts deleted file mode 100644 index 200a81844..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih416-b2020.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -/ { - model = "STiH416 B2020"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih416-b2020e.dts b/software/linux/kernel/arch/arm/boot/dts/stih416-b2020e.dts deleted file mode 100644 index de320cd06..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih416-b2020e.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Lee Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/dts-v1/; -#include "stih416.dtsi" -#include "stih41x-b2020.dtsi" -#include -/ { - model = "STiH416 B2020 REV-E"; - compatible = "st,stih416-b2020", "st,stih416"; - - soc { - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - ethernet1: dwmac@fef08000 { - snps,reset-gpio = <&pio0 7>; - }; - - mmc1: sdhci@fe81f000 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - miphy365x_phy: phy@fe382000 { - phy_port0: port@fe382000 { - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - st,pcie-tx-pol-inv; - }; - }; - - sata0: sata@fe380000{ - status = "okay"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - status = "okay"; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - status = "okay"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih416-clock.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih416-clock.dtsi deleted file mode 100644 index 5b4fb838c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih416-clock.dtsi +++ /dev/null @@ -1,756 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics R&D Limited - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ClockGenAs on SASG2 - */ - clockgen-a@fee62000 { - reg = <0xfee62000 0xb48>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll0-hs", - "clk-s-a0-pll0-ls", - "clk-s-a0-pll1"; - }; - - clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-osc-prediv"; - }; - - clk_s_a0_hs: clk-s-a0-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 0>, /* PLL0 HS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-fdma-0", - "clk-s-fdma-1", - ""; /* clk-s-jit-sense */ - /* Fourth output unused */ - }; - - clk_s_a0_ls: clk-s-a0-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a0_osc_prediv>, - <&clk_s_a0_pll 1>, /* PLL0 LS */ - <&clk_s_a0_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-reg-0", - "clk-s-icn-if-0", - "clk-s-icn-reg-lp-0", - "clk-s-emiss", - "clk-s-eth1-phy", - "clk-s-mii-ref-out"; - /* Remaining outputs unused */ - }; - }; - - clockgen-a@fee81000 { - reg = <0xfee81000 0xb48>; - - clk_s_a1_pll: clk-s-a1-pll { - #clock-cells = <1>; - compatible = "st,clkgena-plls-c65"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-pll0-hs", - "clk-s-a1-pll0-ls", - "clk-s-a1-pll1"; - }; - - clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c65", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a1-osc-prediv"; - }; - - clk_s_a1_hs: clk-s-a1-hs { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-hs", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 0>, /* PLL0 HS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "", /* Reserved */ - "", /* Reserved */ - "clk-s-stac-phy", - "clk-s-vtac-tx-phy"; - }; - - clk_s_a1_ls: clk-s-a1-ls { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c65-ls", - "st,clkgena-divmux"; - - clocks = <&clk_s_a1_osc_prediv>, - <&clk_s_a1_pll 1>, /* PLL0 LS */ - <&clk_s_a1_pll 2>; /* PLL1 */ - - clock-output-names = "clk-s-icn-if-2", - "clk-s-card-mmc-0", - "clk-s-icn-if-1", - "clk-s-gmac0-phy", - "clk-s-nand-ctrl", - "", /* Reserved */ - "clk-s-mii0-ref-out", - "clk-s-stac-sys", - "clk-s-card-mmc-1"; - /* Remaining outputs unused */ - }; - }; - - /* - * ClockGenAs on MPE42 - */ - clockgen-a@fde12000 { - reg = <0xfde12000 0xb50>; - - clk_m_a0_pll0: clk-m-a0-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll0-phi0", - "clk-m-a0-pll0-phi1", - "clk-m-a0-pll0-phi2", - "clk-m-a0-pll0-phi3"; - }; - - clk_m_a0_pll1: clk-m-a0-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-pll1-phi0", - "clk-m-a0-pll1-phi1", - "clk-m-a0-pll1-phi2", - "clk-m-a0-pll1-phi3"; - }; - - clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a0-osc-prediv"; - }; - - clk_m_a0_div0: clk-m-a0-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "clk-m-fdma-12", - "", /* Unused */ - "clk-m-pp-dmu-0", - "clk-m-pp-dmu-1", - "clk-m-icm-lmi", - "clk-m-vid-dmu-0"; - }; - - clk_m_a0_div1: clk-m-a0-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-vid-dmu-1", - "", /* Unused */ - "clk-m-a9-ext2f", - "clk-m-st40rt", - "clk-m-st231-dmu-0", - "clk-m-st231-dmu-1", - "clk-m-st231-aud", - "clk-m-st231-gp-0"; - }; - - clk_m_a0_div2: clk-m-a0-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-st231-gp-1", - "clk-m-icn-cpu", - "clk-m-icn-stac", - "clk-m-tx-icn-dmu-0", - "clk-m-tx-icn-dmu-1", - "clk-m-tx-icn-ts", - "clk-m-icn-vdp-0", - "clk-m-icn-vdp-1"; - }; - - clk_m_a0_div3: clk-m-a0-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a0_osc_prediv>, - <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "clk-m-icn-vp8", - "", /* Unused */ - "clk-m-icn-reg-11", - "clk-m-a9-trace"; - }; - }; - - clockgen-a@fd6db000 { - reg = <0xfd6db000 0xb50>; - - clk_m_a1_pll0: clk-m-a1-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll0-phi0", - "clk-m-a1-pll0-phi1", - "clk-m-a1-pll0-phi2", - "clk-m-a1-pll0-phi3"; - }; - - clk_m_a1_pll1: clk-m-a1-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-pll1-phi0", - "clk-m-a1-pll1-phi1", - "clk-m-a1-pll1-phi2", - "clk-m-a1-pll1-phi3"; - }; - - clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a1-osc-prediv"; - }; - - clk_m_a1_div0: clk-m-a1-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "", /* Unused */ - "clk-m-fdma-10", - "clk-m-fdma-11", - "clk-m-hva-alt", - "clk-m-proc-sc", - "clk-m-tp", - "clk-m-rx-icn-dmu-0", - "clk-m-rx-icn-dmu-1"; - }; - - clk_m_a1_div1: clk-m-a1-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "clk-m-rx-icn-ts", - "clk-m-rx-icn-vdp-0", - "", /* Unused */ - "clk-m-prv-t1-bus", - "clk-m-icn-reg-12", - "clk-m-icn-reg-10", - "", /* Unused */ - "clk-m-icn-st231"; - }; - - clk_m_a1_div2: clk-m-a1-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-fvdp-proc-alt", - "clk-m-icn-reg-13", - "clk-m-tx-icn-gpu", - "clk-m-rx-icn-gpu", - "", /* Unused */ - "", /* Unused */ - "", /* clk-m-apb-pm-12 */ - ""; /* Unused */ - }; - - clk_m_a1_div3: clk-m-a1-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a1_osc_prediv>, - <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - "", /* Unused */ - ""; /* clk-m-gpu-alt */ - }; - }; - - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a0_div1 2>; - clock-div = <2>; - clock-mult = <1>; - }; - - clockgen-a@fd345000 { - reg = <0xfd345000 0xb50>; - - clk_m_a2_pll0: clk-m-a2-pll0 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll0-phi0", - "clk-m-a2-pll0-phi1", - "clk-m-a2-pll0-phi2", - "clk-m-a2-pll0-phi3"; - }; - - clk_m_a2_pll1: clk-m-a2-pll1 { - #clock-cells = <1>; - compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-pll1-phi0", - "clk-m-a2-pll1-phi1", - "clk-m-a2-pll1-phi2", - "clk-m-a2-pll1-phi3"; - }; - - clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { - #clock-cells = <0>; - compatible = "st,clkgena-prediv-c32", - "st,clkgena-prediv"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-m-a2-osc-prediv"; - }; - - clk_m_a2_div0: clk-m-a2-div0 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf0", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ - <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ - - clock-output-names = "clk-m-vtac-main-phy", - "clk-m-vtac-aux-phy", - "clk-m-stac-phy", - "clk-m-stac-sys", - "", /* clk-m-mpestac-pg */ - "", /* clk-m-mpestac-wc */ - "", /* clk-m-mpevtacaux-pg*/ - ""; /* clk-m-mpevtacmain-pg*/ - }; - - clk_m_a2_div1: clk-m-a2-div1 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf1", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ - <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ - - clock-output-names = "", /* clk-m-mpevtacrx0-wc */ - "", /* clk-m-mpevtacrx1-wc */ - "clk-m-compo-main", - "clk-m-compo-aux", - "clk-m-bdisp-0", - "clk-m-bdisp-1", - "clk-m-icn-bdisp", - "clk-m-icn-compo"; - }; - - clk_m_a2_div2: clk-m-a2-div2 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf2", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ - <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ - - clock-output-names = "clk-m-icn-vdp-2", - "", /* Unused */ - "clk-m-icn-reg-14", - "clk-m-mdtp", - "clk-m-jpegdec", - "", /* Unused */ - "clk-m-dcephy-impctrl", - ""; /* Unused */ - }; - - clk_m_a2_div3: clk-m-a2-div3 { - #clock-cells = <1>; - compatible = "st,clkgena-divmux-c32-odf3", - "st,clkgena-divmux"; - - clocks = <&clk_m_a2_osc_prediv>, - <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ - <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ - - clock-output-names = "", /* Unused */ - ""; /* clk-m-apb-pm-11 */ - /* Remaining outputs unused */ - }; - }; - - /* - * A9 PLL - */ - clockgen-a9@fdde08b0 { - reg = <0xfdde08b0 0x70>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks - */ - clk_m_a9: clk-m-a9@fdde08ac { - #clock-cells = <0>; - compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0xfdde08ac 0x4>; - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_m_a0_div1 2>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Frequency synthesizers on the SASG2 - */ - clockgen_b0: clockgen-b0@fee108b4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee108b4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-usb48", - "clk-s-dss", - "clk-s-stfe-frc-2", - "clk-s-thsens-scard"; - }; - - clockgen_b1: clockgen-b1@fe8308c4 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfe8308c4 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-pcm-0", - "clk-s-pcm-1", - "clk-s-pcm-2", - "clk-s-pcm-3"; - }; - - clockgen_c: clockgen-c@fe8307d0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs432", "st,quadfs"; - reg = <0xfe8307d0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-c-fs0-ch0", - "clk-s-c-vcc-sd", - "clk-s-c-fs0-ch2"; - }; - - clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; - reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ - - clocks = <&clk_sysin>, - <&clockgen_c 0>; - }; - - /* - * Add a dummy clock for the HDMI PHY for the VCC input mux - */ - clk_s_tmds_fromphy: clk-s-tmds-fromphy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_c_vcc: clockgen-c-vcc@fe8308ac { - #clock-cells = <1>; - compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; - reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ - - clocks = <&clk_s_vcc_hd>, - <&clockgen_c 1>, - <&clk_s_tmds_fromphy>, - <&clockgen_c 2>; - - clock-output-names = "clk-s-pix-hdmi", - "clk-s-pix-dvo", - "clk-s-out-dvo", - "clk-s-pix-hd", - "clk-s-hddac", - "clk-s-denc", - "clk-s-sddac", - "clk-s-pix-main", - "clk-s-pix-aux", - "clk-s-stfe-frc-0", - "clk-s-ref-mcru", - "clk-s-slave-mcru", - "clk-s-tmds-hdmi", - "clk-s-hdmi-reject-pll", - "clk-s-thsens"; - }; - - clockgen_d: clockgen-d@fee107e0 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs216", "st,quadfs"; - reg = <0xfee107e0 0x44>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-s-ccsc", - "clk-s-stfe-frc-1", - "clk-s-tsout-1", - "clk-s-mchi"; - }; - - /* - * Frequency synthesizers on the MPE42 - */ - clockgen_e: clockgen-e@fd3208bc { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-E", "st,quadfs"; - reg = <0xfd3208bc 0xb0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-pix-mdtp-0", - "clk-m-pix-mdtp-1", - "clk-m-pix-mdtp-2", - "clk-m-mpelpc"; - }; - - clockgen_f: clockgen-f@fd320878 { - #clock-cells = <1>; - compatible = "st,stih416-quadfs660-F", "st,quadfs"; - reg = <0xfd320878 0xf0>; - - clocks = <&clk_sysin>; - clock-output-names = "clk-m-main-vidfs", - "clk-m-hva-fs", - "clk-m-fvdp-vcpu", - "clk-m-fvdp-proc-fs"; - }; - - clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; - reg = <0xfd320910 0x4>; /* SYSCFG8580 */ - - clocks = <&clk_m_a1_div2 0>, - <&clockgen_f 3>; - }; - - clk_m_hva: clk-m-hva@fd690868 { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; - reg = <0xfd690868 0x4>; /* SYSCFG9538 */ - - clocks = <&clockgen_f 1>, - <&clk_m_a1_div0 3>; - }; - - clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 7>, - <&clockgen_f 0>; - }; - - clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c { - #clock-cells = <0>; - compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; - reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ - - clocks = <&clockgen_c_vcc 8>, - <&clockgen_f 1>; - }; - - /* - * Add a dummy clock for the HDMIRx external signal clock - */ - clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen_f_vcc: clockgen-f-vcc@fd32086c { - #clock-cells = <1>; - compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; - reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ - - clocks = <&clk_m_f_vcc_hd>, - <&clk_m_f_vcc_sd>, - <&clockgen_f 0>, - <&clk_m_pix_hdmirx_sas>; - - clock-output-names = "clk-m-pix-main-pipe", - "clk-m-pix-aux-pipe", - "clk-m-pix-main-cru", - "clk-m-pix-aux-cru", - "clk-m-xfer-be-compo", - "clk-m-xfer-pip-compo", - "clk-m-xfer-aux-compo", - "clk-m-vsens", - "clk-m-pix-hdmirx-0", - "clk-m-pix-hdmirx-1"; - }; - - /* - * DDR PLL - */ - clockgen-ddr@0xfdde07d8 { - reg = <0xfdde07d8 0x110>; - - clockgen_ddr_pll: clockgen-ddr-pll { - #clock-cells = <1>; - compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-ddr0", - "clockgen-ddr1"; - }; - }; - - /* - * GPU PLL - */ - clockgen-gpu@fd68ff00 { - reg = <0xfd68ff00 0x910>; - - clockgen_gpu_pll: clockgen-gpu-pll { - #clock-cells = <1>; - compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"; - - clocks = <&clk_sysin>; - clock-output-names = "clockgen-gpu-pll"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih416-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih416-pinctrl.dtsi deleted file mode 100644 index 9c97f7e65..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ /dev/null @@ -1,692 +0,0 @@ - -/* - * Copyright (C) 2013 STMicroelectronics Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "st-pincfg.h" -#include -/ { - - aliases { - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio40; - gpio6 = &pio5; - gpio7 = &pio6; - gpio8 = &pio7; - gpio9 = &pio8; - gpio10 = &pio9; - gpio11 = &pio10; - gpio12 = &pio11; - gpio13 = &pio12; - gpio14 = &pio30; - gpio15 = &pio31; - gpio16 = &pio13; - gpio17 = &pio14; - gpio18 = &pio15; - gpio19 = &pio16; - gpio20 = &pio17; - gpio21 = &pio18; - gpio22 = &pio100; - gpio23 = &pio101; - gpio24 = &pio102; - gpio25 = &pio103; - gpio26 = &pio104; - gpio27 = &pio105; - gpio28 = &pio106; - gpio29 = &pio107; - }; - - soc { - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0xfe61f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe610000 0x6000>; - - pio0: gpio@fe610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@fe611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@fe612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@fe613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@fe614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - pio40: gpio@fe615000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO40"; - st,retime-pin-mask = <0x7f>; - }; - - rc{ - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - }; - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio0 2 ALT2 IN>; - keyin1 = <&pio0 3 ALT2 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio1 6 ALT2 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - sbc_i2c0 { - pinctrl_sbc_i2c0_default: sbc_i2c0-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb3: usb3 { - st,pins { - oc-detect = <&pio40 0 ALT1 IN>; - pwr-enable = <&pio40 1 ALT1 OUT>; - }; - }; - }; - - sbc_i2c1 { - pinctrl_sbc_i2c1_default: sbc_i2c1-default { - st,pins { - sda = <&pio3 2 ALT2 BIDIR>; - scl = <&pio3 1 ALT2 BIDIR>; - }; - }; - }; - - gmac1 { - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - pinctrl_rgmii1: rgmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - pwm-capturein = <&pio3 2 ALT1 IN>; - - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-out = <&pio4 4 ALT1 OUT>; - pwm-capturein = <&pio4 3 ALT1 IN>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - }; - - pin-controller-front { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0xfee0f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfee00000 0x10000>; - - pio5: gpio@fee00000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO5"; - }; - pio6: gpio@fee01000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO6"; - }; - pio7: gpio@fee02000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO7"; - }; - pio8: gpio@fee03000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO8"; - }; - pio9: gpio@fee04000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO9"; - }; - pio10: gpio@fee05000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO10"; - }; - pio11: gpio@fee06000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: gpio@fee07000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO12"; - }; - pio30: gpio@fee08000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@fee09000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO31"; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-out = <&pio9 7 ALT2 OUT>; - pwm-capturein = <&pio9 6 ALT2 IN>; - }; - }; - }; - - serial2-oe { - pinctrl_serial2_oe: serial2-1 { - st,pins { - output-enable = <&pio11 3 ALT2 OUT>; - }; - }; - }; - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio9 3 ALT1 BIDIR>; - scl = <&pio9 2 ALT1 BIDIR>; - }; - }; - }; - - usb { - pinctrl_usb0: usb0 { - st,pins { - oc-detect = <&pio9 4 ALT1 IN>; - pwr-enable = <&pio9 5 ALT1 OUT>; - }; - }; - }; - - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio12 1 ALT1 BIDIR>; - scl = <&pio12 0 ALT1 BIDIR>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio12 2 ALT1 OUT>; - spi-fsm-cs = <&pio12 3 ALT1 OUT>; - spi-fsm-mosi = <&pio12 4 ALT1 OUT>; - spi-fsm-miso = <&pio12 5 ALT1 IN>; - spi-fsm-hol = <&pio12 6 ALT1 OUT>; - spi-fsm-wp = <&pio12 7 ALT1 OUT>; - }; - }; - }; - }; - - pin-controller-rear { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0xfe82f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfe820000 0x6000>; - - pio13: gpio@fe820000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO13"; - }; - pio14: gpio@fe821000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: gpio@fe822000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: gpio@fe823000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: gpio@fe824000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: gpio@fe825000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO18"; - st,retime-pin-mask = <0xf>; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio17 4 ALT2 OUT>; - rx = <&pio17 5 ALT2 IN>; - }; - }; - }; - - gmac0 { - pinctrl_mii0: mii0 { - st,pins { - mdint = <&pio13 6 ALT2 IN BYPASS 0>; - txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&pio15 2 ALT2 IN BYPASS 1000>; - col = <&pio15 3 ALT2 IN BYPASS 1000>; - mdio= <&pio15 4 ALT2 OUT BYPASS 1500>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>; - }; - }; - - pinctrl_gmii0: gmii0 { - st,pins { - }; - }; - pinctrl_rgmii0: rgmii0 { - st,pins { - phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; - txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>; - txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>; - txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>; - txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>; - txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>; - txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; - - mdio = <&pio15 4 ALT2 OUT BYPASS 0>; - mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>; - rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>; - rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>; - rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>; - rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>; - rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>; - - clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>; - }; - }; - }; - - mmc0 { - pinctrl_mmc0: mmc0 { - st,pins { - mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; - data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; - data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; - data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; - cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; - wp = <&pio15 3 ALT4 IN>; - data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; - data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; - data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; - data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; - pwr = <&pio17 1 ALT4 OUT>; - cd = <&pio17 2 ALT4 IN>; - led = <&pio17 3 ALT4 OUT>; - }; - }; - }; - mmc1 { - pinctrl_mmc1: mmc1 { - st,pins { - mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; - data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>; - data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>; - data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>; - data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>; - cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>; - data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>; - data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>; - data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>; - data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>; - pwr = <&pio16 2 ALT3 OUT>; - nreset = <&pio13 6 ALT3 OUT>; - }; - }; - }; - - usb { - pinctrl_usb1: usb1 { - st,pins { - oc-detect = <&pio18 0 ALT1 IN>; - pwr-enable = <&pio18 1 ALT1 OUT>; - }; - }; - pinctrl_usb2: usb2 { - st,pins { - oc-detect = <&pio18 2 ALT1 IN>; - pwr-enable = <&pio18 3 ALT1 OUT>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan1_default: pwm0-1-default { - st,pins { - pwm-out = <&pio13 2 ALT2 OUT>; - pwm-capturein = <&pio13 1 ALT2 IN>; - }; - }; - pinctrl_pwm0_chan2_default: pwm0-2-default { - st,pins { - pwm-out = <&pio15 2 ALT4 OUT>; - }; - }; - pinctrl_pwm0_chan3_default: pwm0-3-default { - st,pins { - pwm-out = <&pio17 4 ALT1 OUT>; - }; - }; - }; - - }; - - pin-controller-fvdp-fe { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-fe-pinctrl"; - st,syscfg = <&syscfg_fvdp_fe>; - reg = <0xfd6bf080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd6b0000 0x3000>; - - pio100: gpio@fd6b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO100"; - }; - pio101: gpio@fd6b1000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO101"; - }; - pio102: gpio@fd6b2000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO102"; - }; - }; - - pin-controller-fvdp-lite { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih416-fvdp-lite-pinctrl"; - st,syscfg = <&syscfg_fvdp_lite>; - reg = <0xfd33f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0xfd330000 0x5000>; - - pio103: gpio@fd330000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO103"; - }; - pio104: gpio@fd331000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO104"; - }; - pio105: gpio@fd332000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO105"; - }; - pio106: gpio@fd333000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO106"; - }; - - pio107: gpio@fd334000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO107"; - st,retime-pin-mask = <0xf>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih416.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih416.dtsi deleted file mode 100644 index fe1f9cf77..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih416.dtsi +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright (C) 2012 STMicroelectronics Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x.dtsi" -#include "stih416-clock.dtsi" -#include "stih416-pinctrl.dtsi" - -#include -#include -#include -#include -/ { - L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfffe2000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&intc>; - interrupts = ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - restart { - compatible = "st,stih416-restart"; - st,syscfg = <&syscfg_sbc>; - status = "okay"; - }; - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih416-powerdown"; - }; - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih416-softreset"; - }; - - syscfg_sbc:sbc-syscfg@fe600000{ - compatible = "st,stih416-sbc-syscfg", "syscon"; - reg = <0xfe600000 0x1000>; - }; - - syscfg_front:front-syscfg@fee10000{ - compatible = "st,stih416-front-syscfg", "syscon"; - reg = <0xfee10000 0x1000>; - }; - - syscfg_rear:rear-syscfg@fe830000{ - compatible = "st,stih416-rear-syscfg", "syscon"; - reg = <0xfe830000 0x1000>; - }; - - /* MPE */ - syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{ - compatible = "st,stih416-fvdp-fe-syscfg", "syscon"; - reg = <0xfddf0000 0x1000>; - }; - - syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{ - compatible = "st,stih416-fvdp-lite-syscfg", "syscon"; - reg = <0xfd6a0000 0x1000>; - }; - - syscfg_cpu:cpu-syscfg@fdde0000{ - compatible = "st,stih416-cpu-syscfg", "syscon"; - reg = <0xfdde0000 0x1000>; - }; - - syscfg_compo:compo-syscfg@fd320000{ - compatible = "st,stih416-compo-syscfg", "syscon"; - reg = <0xfd320000 0x1000>; - }; - - syscfg_transport:transport-syscfg@fd690000{ - compatible = "st,stih416-transport-syscfg", "syscon"; - reg = <0xfd690000 0x1000>; - }; - - syscfg_lpm:lpm-syscfg@fe4b5100{ - compatible = "st,stih416-lpm-syscfg", "syscon"; - reg = <0xfe4b5100 0x8>; - }; - - irq-syscfg { - compatible = "st,stih416-irq-syscfg"; - st,syscfg = <&syscfg_cpu>; - st,irq-device = , - ; - st,fiq-device = , - ; - }; - - serial2: serial@fed32000{ - compatible = "st,asc"; - status = "disabled"; - reg = <0xfed32000 0x2c>; - interrupts = <0 197 0>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; - }; - - /* SBC_UART1 */ - sbc_serial1: serial@fe531000 { - compatible = "st,asc"; - status = "disabled"; - reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - }; - - i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - status = "disabled"; - }; - - i2c@fed41000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed41000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - - status = "disabled"; - }; - - i2c@fe540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe540000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c0_default>; - - status = "disabled"; - }; - - i2c@fe541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfe541000 0x110>; - interrupts = ; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_i2c1_default>; - - status = "disabled"; - }; - - ethernet0: dwmac@fe810000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfe810000 0x8000>; - reg-names = "stmmaceth"; - - interrupts = <0 133 0>, <0 134 0>, <0 135 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_rear 0x8bc>; - resets = <&softreset STIH416_ETH0_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii0>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>; - }; - - ethernet1: dwmac@fef08000 { - device_type = "network"; - compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - status = "disabled"; - reg = <0xfef08000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 136 0>, <0 137 0>, <0 138 0>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - st,syscon = <&syscfg_sbc 0x7f0>; - - resets = <&softreset STIH416_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mii1>; - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>; - }; - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - rx-mode = "infrared"; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - resets = <&softreset STIH416_IRB_SOFTRESET>; - }; - - /* FSM */ - spifsm: spifsm@fe902000 { - compatible = "st,spi-fsm"; - reg = <0xfe902000 0x1000>; - pinctrl-0 = <&pinctrl_fsm>; - - st,syscfg = <&syscfg_rear>; - st,boot-device-reg = <0x958>; - st,boot-device-spi = <0x1a>; - - status = "disabled"; - }; - - keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - status = "disabled"; - reg = <0xfe4b0000 0x2000>; - interrupts = ; - clocks = <&clk_sysin>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, - <&softreset STIH416_KEYSCAN_SOFTRESET>; - }; - - temp0 { - compatible = "st,stih416-sas-thermal"; - clock-names = "thermal"; - clocks = <&clockgen_c_vcc 14>; - - status = "okay"; - }; - - temp1@fdfe8000 { - compatible = "st,stih416-mpe-thermal"; - reg = <0xfdfe8000 0x10>; - clocks = <&clockgen_e 3>; - clock-names = "thermal"; - interrupts = ; - - status = "okay"; - }; - - mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81e000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - }; - - mmc1: sdhci@fe81f000 { - compatible = "st,sdhci"; - status = "disabled"; - reg = <0xfe81f000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 8>; - }; - - miphy365x_phy: phy@fe382000 { - compatible = "st,miphy365x-phy"; - st,syscfg = <&syscfg_rear 0x824 0x828>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@fe382000 { - #phy-cells = <1>; - reg = <0xfe382000 0x100>, <0xfe394000 0x100>; - reg-names = "sata", "pcie"; - }; - - phy_port1: port@fe38a000 { - #phy-cells = <1>; - reg = <0xfe38a000 0x100>, <0xfe804000 0x100>; - reg-names = "sata", "pcie"; - }; - }; - - sata0: sata@fe380000 { - compatible = "st,sti-ahci"; - reg = <0xfe380000 0x1000>; - interrupts = ; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - resets = <&powerdown STIH416_SATA0_POWERDOWN>, - <&softreset STIH416_SATA0_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst"; - clock-names = "ahci_clk"; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - - status = "disabled"; - }; - - usb2_phy: phy@0 { - compatible = "st,stih416-usb-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_rear>; - clocks = <&clk_sysin>; - clock-names = "osc_phy"; - }; - - ehci0: usb@fe1ffe00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe1ffe00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci0: usb@fe1ffc00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe1ffc00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - status = "okay"; - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci1: usb@fe203e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe203e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci1: usb@fe203c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe203c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci2: usb@fe303e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe303e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci2: usb@fe303c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe303c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB2_POWERDOWN>, - <&softreset STIH416_USB2_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ehci3: usb@fe343e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe343e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - ohci3: usb@fe343c00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe343c00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - resets = <&powerdown STIH416_USB3_POWERDOWN>, - <&softreset STIH416_USB3_SOFTRESET>; - reset-names = "power", "softreset"; - }; - - /* SAS PWM Module */ - pwm0: pwm@fed10000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfed10000 0x68>; - interrupts = ; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default - &pinctrl_pwm0_chan1_default - &pinctrl_pwm0_chan2_default - &pinctrl_pwm0_chan3_default>; - - clock-names = "pwm", "capture"; - clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>; - - st,pwm-num-chan = <4>; - st,capture-num-chan = <2>; - }; - - /* SBC PWM Module */ - pwm1: pwm@fe510000 { - compatible = "st,sti-pwm"; - status = "disabled"; - #pwm-cells = <2>; - reg = <0xfe510000 0x68>; - interrupts = ; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - /* - * Shared with SBC_OBS_NOTRST. Don't - * enable unless you really know what - * you're doing. - * - * &pinctrl_pwm1_chan1_default - */ - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <3>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih418-b2199.dts b/software/linux/kernel/arch/arm/boot/dts/stih418-b2199.dts deleted file mode 100644 index 438e54c58..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih418-b2199.dts +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (C) 2015 STMicroelectronics (R&D) Limited. - * Author: Maxime Coquelin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; -#include "stih418.dtsi" -#include -/ { - model = "STiH418 B2199"; - compatible = "st,stih418-b2199", "st,stih418"; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial0; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0xc0000000>; - }; - - aliases { - ttyAS0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - i2c@9842000 { - status = "okay"; - }; - - i2c@9843000 { - status = "okay"; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - mmc1: sdhci@09080000 { - status = "okay"; - }; - - mmc0: sdhci@09060000 { - status = "okay"; - max-frequency = <200000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - non-removable; - }; - - miphy28lp_phy: miphy28lp@9b22000 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - st,tx-retime-src = "clkgen"; - status = "okay"; - phy-mode = "rgmii"; - fixed-link = <0 1 1000 0 0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih418-clock.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih418-clock.dtsi deleted file mode 100644 index ee6614b79..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih418-clock.dtsi +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (C) 2015 STMicroelectronics R&D Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - compatible = "st,stih418-clk", "simple-bus"; - - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih418-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - }; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; - }; - - clockgen-a@090ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0", - "clk-ic-lmi1"; - }; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - }; - - clk_s_c0: clockgen-c@09103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-icn-reg", - "clk-proc-bdisp-0", - "clk-proc-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phyref", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp", - "clk-tx-icn-hades", - "clk-rx-icn-hades", - "clk-icn-reg-16", - "clk-pp-hevc", - "clk-clust-hevc", - "clk-hwpe-hevc", - "clk-fc-hevc", - "clk-proc-mixer", - "clk-proc-sc", - "clk-avsp-hevc"; - }; - }; - - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; - }; - - clockgen-d0@09104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-audio", "st,flexgen"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-pcm-0", - "clk-pcm-1", - "clk-pcm-2", - "clk-spdiff", - "clk-pcmr10-master", - "clk-usb2-phy"; - }; - }; - - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-video", "st,flexgen"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - - clock-output-names = "clk-pix-main-disp", - "", - "", - "", - "", - "clk-tmds-hdmi-div2", - "clk-pix-aux-disp", - "clk-denc", - "clk-pix-hddac", - "clk-hddac", - "clk-sddac", - "clk-pix-dvo", - "clk-dvo", - "clk-pix-hdmi", - "clk-tmds-hdmi", - "clk-ref-hdmiphy", - "", "", "", "", "", - "", "", "", "", "", - "", "", "", "", "", - "", "", "", "", "", - "", "", "", "", "", - "", "", "", "", "", - "", "clk-vp9"; - }; - }; - - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-stfe-frc1", - "clk-tsout-0", - "clk-tsout-1", - "clk-mchi", - "clk-vsens-compo", - "clk-frc1-remote", - "clk-lpc-0", - "clk-lpc-1"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih418.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih418.dtsi deleted file mode 100644 index 965f88160..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih418.dtsi +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih418-clock.dtsi" -#include "stih407-family.dtsi" -#include "stih410-pinctrl.dtsi" -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - }; - }; - - soc { - usb2_picophy1: phy2 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - }; - - usb2_picophy2: phy3 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - }; - - ohci0: usb@9a03c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a03c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - }; - - ehci0: usb@9a03e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a03e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - }; - - ohci1: usb@9a83c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a83c00 0x100>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - }; - - ehci1: usb@9a83e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a83e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - }; - - mmc0: sdhci@09060000 { - assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; - assigned-clock-parents = <&clk_s_c0_pll1 0>; - assigned-clock-rates = <200000000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih41x-b2000.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih41x-b2000.dtsi deleted file mode 100644 index 9bfa0674b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih41x-b2000.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include -#include - -/ { - - memory{ - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &serial2; - }; - - aliases { - ttyAS0 = &serial2; - ethernet0 = ðernet0; - ethernet1 = ðernet1; - }; - - soc { - serial2: serial@fed32000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - fp_led { - label = "Front Panel LED"; - gpios = <&pio105 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - ethernet0: dwmac@fe810000 { - status = "okay"; - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_mii0>; - - snps,reset-gpio = <&pio106 2>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - ethernet1: dwmac@fef08000 { - status = "disabled"; - phy-mode = "mii"; - st,tx-retime-src = "txclk"; - - snps,reset-gpio = <&pio4 7>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - }; - - keyscan: keyscan@fe4b0000 { - keypad,num-rows = <4>; - keypad,num-columns = <4>; - st,debounce-us = <5000>; - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13) - MATRIX_KEY(0x00, 0x01, KEY_F9) - MATRIX_KEY(0x00, 0x02, KEY_F5) - MATRIX_KEY(0x00, 0x03, KEY_F1) - MATRIX_KEY(0x01, 0x00, KEY_F14) - MATRIX_KEY(0x01, 0x01, KEY_F10) - MATRIX_KEY(0x01, 0x02, KEY_F6) - MATRIX_KEY(0x01, 0x03, KEY_F2) - MATRIX_KEY(0x02, 0x00, KEY_F15) - MATRIX_KEY(0x02, 0x01, KEY_F11) - MATRIX_KEY(0x02, 0x02, KEY_F7) - MATRIX_KEY(0x02, 0x03, KEY_F3) - MATRIX_KEY(0x03, 0x00, KEY_F16) - MATRIX_KEY(0x03, 0x01, KEY_F12) - MATRIX_KEY(0x03, 0x02, KEY_F8) - MATRIX_KEY(0x03, 0x03, KEY_F4) >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih41x-b2020.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih41x-b2020.dtsi deleted file mode 100644 index 322e0e951..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih41x-b2020.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Srinivas Kandagatla - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -#include "stih41x-b2020x.dtsi" -#include -/ { - memory{ - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttyAS0,115200 clk_ignore_unused"; - linux,stdout-path = &sbc_serial1; - }; - - aliases { - ttyAS0 = &sbc_serial1; - ethernet1 = ðernet1; - }; - soc { - sbc_serial1: serial@fe531000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio4 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - i2c@fed40000 { - status = "okay"; - }; - - /* HDMI Tx I2C */ - i2c@fed41000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - i2c-min-scl-pulse-width-us = <0>; - i2c-min-sda-pulse-width-us = <5>; - - status = "okay"; - }; - - i2c@fe540000 { - status = "okay"; - }; - - i2c@fe541000 { - status = "okay"; - }; - - ethernet1: dwmac@fef08000 { - status = "okay"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - st,tx-retime-src = "clk_125"; - snps,reset-gpio = <&pio3 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-0 = <&pinctrl_rgmii1>; - }; - - mmc0: sdhci@fe81e000 { - bus-width = <8>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih41x-b2020x.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih41x-b2020x.dtsi deleted file mode 100644 index f797a0607..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih41x-b2020x.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * Author: Lee Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - soc { - mmc0: sdhci@fe81e000 { - status = "okay"; - }; - - spifsm: spifsm@fe902000 { - #address-cells = <1>; - #size-cells = <1>; - - status = "okay"; - - partition@0 { - label = "SerialFlash1"; - reg = <0x00000000 0x00500000>; - }; - - partition@500000 { - label = "SerialFlash2"; - reg = <0x00500000 0x00b00000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stih41x.dtsi b/software/linux/kernel/arch/arm/boot/dts/stih41x.dtsi deleted file mode 100644 index 5cb0e6337..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stih41x.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - intc: interrupt-controller@fffe1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffe1000 0x1000>, - <0xfffe0100 0x100>; - }; - - scu@fffe0000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xfffe0000 0x1000>; - }; - - timer@fffe0200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfffe0200 0x100>; - interrupts = <1 11 0x04>; - clocks = <&arm_periph_clk>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stihxxx-b2120.dtsi b/software/linux/kernel/arch/arm/boot/dts/stihxxx-b2120.dtsi deleted file mode 100644 index ed2b7a99e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Giuseppe Cavallaro - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -/ { - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pwm0: pwm@9810000 { - status = "okay"; - }; - - pwm1: pwm@9510000 { - status = "okay"; - }; - - ssc2: i2c@9842000 { - status = "okay"; - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - ssc3: i2c@9843000 { - status = "okay"; - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - mmc0: sdhci@09060000 { - non-removable; - status = "okay"; - }; - - mmc1: sdhci@09080000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - hdmiddc: i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - miphy28lp_phy: miphy28lp@9b22000 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - st,tx-retime-src = "clkgen"; - status = "okay"; - phy-mode = "rgmii"; - fixed-link = <0 1 1000 0 0>; - }; - - demux@08a20000 { - compatible = "st,stih407-c8sectpfe"; - status = "okay"; - reg = <0x08a20000 0x10000>, - <0x08a00000 0x4000>; - reg-names = "c8sectpfe", "c8sectpfe-ram"; - interrupts = , - ; - interrupt-names = "c8sectpfe-error-irq", - "c8sectpfe-idle-irq"; - pinctrl-0 = <&pinctrl_tsin0_serial>; - pinctrl-1 = <&pinctrl_tsin0_parallel>; - pinctrl-2 = <&pinctrl_tsin3_serial>; - pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; - pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; - pinctrl-names = "tsin0-serial", - "tsin0-parallel", - "tsin3-serial", - "tsin4-serial", - "tsin5-serial"; - clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; - clock-names = "c8sectpfe"; - - /* tsin0 is TSA on NIMA */ - tsin0: port@0 { - tsin-num = <0>; - serial-not-parallel; - i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; - dvb-card = ; - }; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - status = "okay"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - status = "okay"; - }; - - sti_sasg_codec: sti-sasg-codec { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif_out>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sti audio card"; - status = "okay"; - - simple-audio-card,dai-link@0 { - /* DAC */ - format = "i2s"; - mclk-fs = <256>; - cpu { - sound-dai = <&sti_uni_player2>; - }; - - codec { - sound-dai = <&sti_sasg_codec 1>; - }; - }; - simple-audio-card,dai-link@1 { - /* SPDIF */ - format = "left_j"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player3>; - }; - - codec { - sound-dai = <&sti_sasg_codec 0>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stm32429i-eval.dts b/software/linux/kernel/arch/arm/boot/dts/stm32429i-eval.dts deleted file mode 100644 index 6bfc5959d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stm32429i-eval.dts +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f429.dtsi" - -/ { - model = "STMicroelectronics STM32429i-EVAL board"; - compatible = "st,stm32429i-eval", "st,stm32f429"; - - chosen { - bootargs = "root=/dev/ram rdinit=/linuxrc"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - green { - gpios = <&gpiog 6 1>; - linux,default-trigger = "heartbeat"; - }; - orange { - gpios = <&gpiog 7 1>; - }; - red { - gpios = <&gpiog 10 1>; - }; - blue { - gpios = <&gpiog 12 1>; - }; - }; - - usbotg_hs_phy: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 30>; - clock-names = "main_clk"; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_mii>; - pinctrl-names = "default"; - phy-mode = "mii-id"; - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "host"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stm32f429-disco.dts b/software/linux/kernel/arch/arm/boot/dts/stm32f429-disco.dts deleted file mode 100644 index 01408073d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stm32f429-disco.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f429.dtsi" - -/ { - model = "STMicroelectronics STM32F429i-DISCO board"; - compatible = "st,stm32f429i-disco", "st,stm32f429"; - - chosen { - bootargs = "root=/dev/ram rdinit=/linuxrc"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x90000000 0x800000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - red { - gpios = <&gpiog 14 0>; - }; - green { - gpios = <&gpiog 13 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&clk_hse { - clock-frequency = <8000000>; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stm32f429.dtsi b/software/linux/kernel/arch/arm/boot/dts/stm32f429.dtsi deleted file mode 100644 index 336ee4fb5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stm32f429.dtsi +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Copyright 2015 - Maxime Coquelin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include "armv7-m.dtsi" -#include - -/ { - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - - soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 128>; - status = "disabled"; - }; - - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 129>; - status = "disabled"; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 130>; - status = "disabled"; - }; - - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 131>; - }; - - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 132>; - status = "disabled"; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 133>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&rcc 0 145>; - status = "disabled"; - }; - - usart3: serial@40004800 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - clocks = <&rcc 0 146>; - status = "disabled"; - }; - - usart4: serial@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&rcc 0 147>; - status = "disabled"; - }; - - usart5: serial@40005000 { - compatible = "st,stm32-uart"; - reg = <0x40005000 0x400>; - interrupts = <53>; - clocks = <&rcc 0 148>; - status = "disabled"; - }; - - usart7: serial@40007800 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40007800 0x400>; - interrupts = <82>; - clocks = <&rcc 0 158>; - status = "disabled"; - }; - - usart8: serial@40007c00 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40007c00 0x400>; - interrupts = <83>; - clocks = <&rcc 0 159>; - status = "disabled"; - }; - - usart1: serial@40011000 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 164>; - status = "disabled"; - }; - - usart6: serial@40011400 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40011400 0x400>; - interrupts = <71>; - clocks = <&rcc 0 165>; - status = "disabled"; - }; - - syscfg: system-config@40013800 { - compatible = "syscon"; - reg = <0x40013800 0x400>; - }; - - exti: interrupt-controller@40013c00 { - compatible = "st,stm32-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40013C00 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; - }; - - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f429-pinctrl"; - ranges = <0 0x40020000 0x3000>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 0>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 1>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 2>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 3>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 4>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 5>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 6>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 7>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 8>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 9>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 10>; - st,bank-name = "GPIOK"; - }; - - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg_hs@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - ; - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - ethernet0_mii: mii@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - }; - - rcc: rcc@40023810 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>; - }; - - dma1: dma-controller@40026000 { - compatible = "st,stm32-dma"; - reg = <0x40026000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc 0 21>; - #dma-cells = <4>; - }; - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc 0 22>; - #dma-cells = <4>; - st,mem2mem; - }; - - ethernet0: dwmac@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <61>, <62>; - interrupt-names = "macirq", "eth_wake_irq"; - clock-names = "stmmaceth", "tx-clk", "rx-clk"; - clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - snps,mixed-burst; - dma-ranges; - status = "disabled"; - }; - - usbotg_hs: usb@40040000 { - compatible = "snps,dwc2"; - dma-ranges; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc 0 29>; - clock-names = "otg"; - status = "disabled"; - }; - - rng: rng@50060800 { - compatible = "st,stm32-rng"; - reg = <0x50060800 0x400>; - interrupts = <80>; - clocks = <&rcc 0 38>; - }; - }; -}; - -&systick { - clocks = <&rcc 1 0>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/stm32f469-disco.dts b/software/linux/kernel/arch/arm/boot/dts/stm32f469-disco.dts deleted file mode 100644 index e911af836..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/stm32f469-disco.dts +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2016 - Lee Jones - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32f429.dtsi" - -/ { - model = "STMicroelectronics STM32F469i-DISCO board"; - compatible = "st,stm32f469i-disco", "st,stm32f469"; - - chosen { - bootargs = "root=/dev/ram rdinit=/linuxrc"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x800000>; - }; - - aliases { - serial0 = &usart3; - }; -}; - -&clk_hse { - clock-frequency = <8000000>; -}; - -&usart3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-a1000.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-a1000.dts deleted file mode 100644 index 39e368ec3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2013 Emilio López - * - * Emilio López - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Mele A1000"; - compatible = "mele,a1000", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a1000>; - - red { - label = "a1000:red:usr"; - gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; - }; - - blue { - label = "a1000:blue:pwr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_a1000>; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - emac_power_pin_a1000: emac_power_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_a1000: led_pins@0 { - allwinner,pins = "PH10", "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts deleted file mode 100644 index 5f9858223..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include - -/ { - model = "BA10 tvbox"; - compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb2_vbus_pin_a: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - }; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts deleted file mode 100644 index 023b03efa..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include - -/ { - model = "Chuwi V7 CW0825"; - compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - ft5306de4: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@800 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button@1000 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button@1200 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-cubieboard.dts deleted file mode 100644 index 710e2ef51..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Cubietech Cubieboard"; - compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard>; - - blue { - label = "cubieboard:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */ - }; - - green { - label = "cubieboard:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_cubieboard: led_pins@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts deleted file mode 100644 index 893497e39..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Dserve DSRV9703C"; - compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_dsrv9703c>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <®_motor>; - min-microvolt = <3000000>; - max-microvolt = <3000000>; - }; - - reg_motor: reg_motor { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&motor_pins>; - regulator-name = "vcc-motor"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - }; -}; - -&codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; - reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - - button@800 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - bl_en_pin_dsrv9703c: bl_en_pin@0 { - allwinner,pins = "PH7"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - motor_pins: motor_pins@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - touchscreen_pins: touchscreen_pins@0 { - allwinner,pins = "PB13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts deleted file mode 100644 index ac64781a0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright 2015 Priit Laes - * - * Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include - -/ { - model = "Gemei G9 Tablet"; - compatible = "gemei,g9", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* - * TODO: - * 2x cameras via CSI - * AXP battery management - * NAND - * OTG - * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 - */ -&codec { - /* PH15 controls power to external amplifier (ft2012q) */ - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH00 / EINT0 */ - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - - status = "okay"; - - button@158 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button@349 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; - - button@1142 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1142856>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */ - cd-inverted; - status = "okay"; -}; - -&pio { - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-hackberry.dts deleted file mode 100644 index 6de83a618..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Miniand Hackberry"; - compatible = "miniand,hackberry", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy0>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&hackberry_hogs>; - - hackberry_hogs: hogs@0 { - allwinner,pins = "PH19"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_hackberry>; - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts deleted file mode 100644 index 9103864fe..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "Hyundai A7HD"; - compatible = "hyundai,a7hd", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb2_vbus_pin_a { - allwinner,pins = "PH6"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet1.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet1.dts deleted file mode 100644 index e09053bf5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "iNet-1"; - compatible = "inet-tek,inet1", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_inet>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - ft5x: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_wake_pin>; - wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ - touchscreen-size-x = <600>; - touchscreen-size-y = <1024>; - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@1000 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button@1200 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - bl_en_pin_inet: bl_en_pin@0 { - allwinner,pins = "PH7"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - touchscreen_wake_pin: touchscreen_wake_pin@0 { - allwinner,pins = "PB13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts deleted file mode 100644 index 04b0d2d1a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright 2014 Open Source Support GmbH - * - * David Lanzendörfer - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "INet-97F Rev 02"; - compatible = "primux,inet97fv2", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@600 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button@800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button@1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button@1200 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts deleted file mode 100644 index bba4f9cf9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include - -/ { - model = "iNet-9F Rev 03"; - compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys-polled"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_inet9f>; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - button@0 { - label = "Left Joystick Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ - }; - - button@1 { - label = "Left Joystick Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ - }; - - button@2 { - label = "Left Joystick Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - }; - - button@3 { - label = "Left Joystick Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - }; - - button@4 { - label = "Right Joystick Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ - }; - - button@5 { - label = "Right Joystick Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ - }; - - button@6 { - label = "Right Joystick Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ - }; - - button@7 { - label = "Right Joystick Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ - }; - - button@8 { - label = "DPad Left"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */ - }; - - button@9 { - label = "DPad Right"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ - }; - - button@10 { - label = "DPad Up"; - linux,code = ; - linux,input-type = ; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ - }; - - button@11 { - label = "DPad Down"; - linux,code = ; - linux,input-type = ; - linux,input-value = <1>; - gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ - }; - - button@12 { - label = "Button X"; - linux,code = ; - gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */ - }; - - button@13 { - label = "Button Y"; - linux,code = ; - gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */ - }; - - button@14 { - label = "Button A"; - linux,code = ; - gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ - }; - - button@15 { - label = "Button B"; - linux,code = ; - gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */ - }; - - button@16 { - label = "Select Button"; - linux,code = ; - gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ - }; - - button@17 { - label = "Start Button"; - linux,code = ; - gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ - }; - - button@18 { - label = "Top Left Button"; - linux,code = ; - gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ - }; - - button@19 { - label = "Top Right Button"; - linux,code = ; - gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */ - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@600 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button@800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button@1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; - - button@1200 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - key_pins_inet9f: key_pins@0 { - allwinner,pins = "PA0", "PA1", "PA3", "PA4", - "PA5", "PA6", "PA8", "PA9", - "PA11", "PA12", "PA13", - "PA14", "PA15", "PA16", "PA17", - "PH22", "PH23", "PH24", "PH25", "PH26"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts deleted file mode 100644 index 4e798f014..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2015 Josef Gajdusek - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-itead-core-common.dtsi" - -/ { - model = "Iteaduino Plus A10"; - compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10"; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - axp209: pmic@34 { - interrupts = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -®_ahci_5v { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts deleted file mode 100644 index e28f080b1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2015 Gábor Nyers - * - * Gábor Nyers - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Jesurun Q5"; - compatible = "jesurun,q5", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_q5>; - - green { - label = "q5:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ - }; - - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_q5>; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - emac_power_pin_q5: emac_power_pin@0 { - allwinner,pins = "PH19"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_q5: led_pins@0 { - allwinner,pins = "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-marsboard.dts deleted file mode 100644 index 8e50723db..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2015 Aleksei Mamlin - * Aleksei Mamlin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "HAOYU Electronics Marsboard A10"; - compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_marsboard>; - - red1 { - label = "marsboard:red1:usr"; - gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>; - }; - - red2 { - label = "marsboard:red2:usr"; - gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>; - }; - - red3 { - label = "marsboard:red3:usr"; - gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; - }; - - red4 { - label = "marsboard:red4:usr"; - gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_marsboard: led_pins@0 { - allwinner,pins = "PB5", "PB6", "PB7", "PB8"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts deleted file mode 100644 index a7dd86d30..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "PineRiver Mini X-Plus"; - compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&ir0_rx_pins_a { - /* The ir receiver is not always populated */ - allwinner,pull = ; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mk802.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mk802.dts deleted file mode 100644 index ee46ea854..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mk802.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "MK802"; - compatible = "allwinner,mk802", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_mk802: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_mk802>; - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mk802ii.dts deleted file mode 100644 index c861fa7e3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-mk802ii.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "MK802ii"; - compatible = "allwinner,mk802ii", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts deleted file mode 100644 index b350448c7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright 2014 - Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A10-OLinuXino-LIME"; - compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - green { - label = "a10-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&cpu0 { - /* - * The A10-Lime is known to be unstable when running at 1008 MHz - */ - operating-points = < - /* kHz uV */ - 912000 1350000 - 864000 1300000 - 624000 1250000 - >; - cooling-max-level = <2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pcduino.dts deleted file mode 100644 index 39034aa8e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright 2014 Zoltan HERPAI - * Zoltan HERPAI - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "LinkSprite pcDuino"; - compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_pcduino>; - - tx { - label = "pcduino:green:tx"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; - }; - - rx { - label = "pcduino:green:rx"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_pcduino>; - #address-cells = <1>; - #size-cells = <0>; - - button@0 { - label = "Key Back"; - linux,code = ; - gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; - }; - - button@1 { - label = "Key Home"; - linux,code = ; - gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; - }; - - button@2 { - label = "Key Menu"; - linux,code = ; - gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_pcduino: led_pins@0 { - allwinner,pins = "PH15", "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - key_pins_pcduino: key_pins@0 { - allwinner,pins = "PH17", "PH18", "PH19"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ - usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pcduino2.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pcduino2.dts deleted file mode 100644 index de483a1bf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pcduino2.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2015 Siarhei Siamashka - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The LinkSprite pcDuino2 board is almost identical to the older - * LinkSprite pcDuino1 board. The only software visible difference - * is that the pcDuino2 board got a USB VBUS voltage regulator, which - * is controlled by the PD2 pin (pulled-up by default). Also one of - * the USB host ports has been replaced with a USB WIFI chip. - */ - -#include "sun4i-a10-pcduino.dts" - -/ { - model = "LinkSprite pcDuino2"; - compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; -}; - -&pio { - usb2_vbus_pin_pcduino2: usb2_vbus_pin@0 { - allwinner,pins = "PD2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb2_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_pcduino2>; - gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc3v3>; /* USB WIFI is always on */ - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts deleted file mode 100644 index 918f97294..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Point of View Protab2-IPS9"; - compatible = "pov,protab2-ips9", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_protab>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - pixcir_ts@5c { - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; - compatible = "pixcir,pixcir_tangoc"; - reg = <0x5c>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ - attb-gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ - enable-gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; - wake-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@400 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - - button@800 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - bl_en_pin_protab: bl_en_pin@0 { - allwinner,pins = "PH7"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - touchscreen_pins: touchscreen_pins@0 { - allwinner,pins = "PA5", "PB13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun4i-a10.dtsi deleted file mode 100644 index 7e7dfc2b4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun4i-a10.dtsi +++ /dev/null @@ -1,1379 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -#include - -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - aliases { - ethernet0 = &emac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; - status = "disabled"; - }; - - framebuffer@1 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 25>, <&dram_gates 26>; - status = "disabled"; - }; - - framebuffer@2 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 25>, <&dram_gates 26>; - status = "disabled"; - }; - - framebuffer@3 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 5>, - <&dram_gates 25>, <&dram_gates 26>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&cpu>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1400000 - 912000 1350000 - 864000 1300000 - 624000 1250000 - >; - #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <3>; - }; - }; - - thermal-zones { - cpu_thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <850000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc3M: osc3M_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - - osc32k: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll3>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll7>; - clock-output-names = "pll7-2x"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-axi-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-indices = <0>; - clock-output-names = "axi_dram"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>; - clock-output-names = "ahb"; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <5>, <6>, - <7>, <8>, <9>, - <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, - <21>, <22>, <23>, - <24>, <25>, <26>, - <32>, <33>, <34>, - <35>, <36>, <37>, - <40>, <41>, <43>, - <44>, <45>, - <46>, <47>, - <50>, <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", - "ahb_ohci1", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", - "ahb_spi1", "ahb_spi2", "ahb_spi3", - "ahb_pata", "ahb_sata", "ahb_gps", - "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", - "ahb_csi0", "ahb_csi1", "ahb_hdmi", - "ahb_de_be0", "ahb_de_be1", - "ahb_de_fe0", "ahb_de_fe1", - "ahb_mp", "ahb_mali400"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, - <5>, <6>, - <7>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis", - "apb0_pio", "apb0_ir0", - "apb0_ir1", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <4>, - <5>, <6>, - <7>, <16>, - <17>, <18>, - <19>, <20>, - <21>, <22>, - <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_can", - "apb1_scr", "apb1_ps20", - "apb1_ps21", "apb1_uart0", - "apb1_uart1", "apb1_uart2", - "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", - "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - }; - - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram-controller@01c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@00000000 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@00010000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0000 { - compatible = "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - }; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ahb_gates 6>; - #dma-cells = <2>; - }; - - nfc: nand@01c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ahb_gates 13>, <&nand_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@01c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@01c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@01c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ahb_gates 17>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; - - mdio: mdio@01c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <32>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@01c12000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <35>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@01c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - status = "disabled"; - }; - - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - status = "disabled"; - }; - - ehci0: usb@01c14000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ahb_gates 1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c14400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <64>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <86>; - clocks = <&ahb_gates 5>, <&ss_clk>; - clock-names = "ahb", "mod"; - }; - - spi2: spi@01c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@01c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <56>; - clocks = <&pll6 0>, <&ahb_gates 25>; - status = "disabled"; - }; - - ehci1: usb@01c1c000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = <40>; - clocks = <&ahb_gates 3>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@01c1c400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = <65>; - clocks = <&usb_clk 7>, <&ahb_gates 4>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - spi3: spi@01c1f000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = <50>; - clocks = <&ahb_gates 23>, <&spi3_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 31>, - <&dma SUN4I_DMA_DEDICATED 30>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun4i-a10-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&apb0_gates 5>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB18", "PB19"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB20", "PB21"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir0_rx_pins_a: ir0@0 { - allwinner,pins = "PB4"; - allwinner,function = "ir0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir0_tx_pins_a: ir0@1 { - allwinner,pins = "PB3"; - allwinner,function = "ir0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir1_rx_pins_a: ir1@0 { - allwinner,pins = "PB23"; - allwinner,function = "ir1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir1_tx_pins_a: ir1@1 { - allwinner,pins = "PB22"; - allwinner,function = "ir1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ps20_pins_a: ps20@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "ps2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ps21_pins_a: ps21@0 { - allwinner,pins = "PH12", "PH13"; - allwinner,function = "ps2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - pwm0_pins_a: pwm0@0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm"; - allwinner,drive = ; - allwinner,pull = ; - }; - - pwm1_pins_a: pwm1@0 { - allwinner,pins = "PI3"; - allwinner,function = "pwm"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spdif_tx_pins_a: spdif@0 { - allwinner,pins = "PB13"; - allwinner,function = "spdif"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi0_pins_a: spi0@0 { - allwinner,pins = "PI11", "PI12", "PI13"; - allwinner,function = "spi0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi0_cs0_pins_a: spi0_cs0@0 { - allwinner,pins = "PI10"; - allwinner,function = "spi0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi1_pins_a: spi1@0 { - allwinner,pins = "PI17", "PI18", "PI19"; - allwinner,function = "spi1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi1_cs0_pins_a: spi1_cs0@0 { - allwinner,pins = "PI16"; - allwinner,function = "spi1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_pins_a: spi2@0 { - allwinner,pins = "PC20", "PC21", "PC22"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_pins_b: spi2@1 { - allwinner,pins = "PB15", "PB16", "PB17"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_cs0_pins_a: spi2_cs0@0 { - allwinner,pins = "PC19"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_cs0_pins_b: spi2_cs0@1 { - allwinner,pins = "PB14"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PB22", "PB23"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_b: uart0@1 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_pins_a: uart1@0 { - allwinner,pins = "PA10", "PA11"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>; - clocks = <&osc24M>; - }; - - wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - }; - - rtc: rtc@01c20d00 { - compatible = "allwinner,sun4i-a10-rtc"; - reg = <0x01c20d00 0x20>; - interrupts = <24>; - }; - - pwm: pwm@01c20e00 { - compatible = "allwinner,sun4i-a10-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@01c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = <13>; - clocks = <&apb0_gates 1>, <&spdif_clk>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ir0: ir@01c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - ir1: ir@01c21c00 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; - clock-names = "apb", "ir"; - interrupts = <6>; - reg = <0x01c21c00 0x40>; - status = "disabled"; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@01c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&apb0_gates 0>, <&codec_clk>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@01c25000 { - compatible = "allwinner,sun4i-a10-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 16>; - status = "disabled"; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 17>; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 18>; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 19>; - status = "disabled"; - }; - - uart4: serial@01c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = <17>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 20>; - status = "disabled"; - }; - - uart5: serial@01c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = <18>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 21>; - status = "disabled"; - }; - - uart6: serial@01c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = <19>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 22>; - status = "disabled"; - }; - - uart7: serial@01c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = <20>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 23>; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&apb1_gates 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&apb1_gates 1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&apb1_gates 2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ps20: ps2@01c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = <62>; - clocks = <&apb1_gates 6>; - status = "disabled"; - }; - - ps21: ps2@01c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = <63>; - clocks = <&apb1_gates 7>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts deleted file mode 100644 index d4ad02182..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "Auxtek t003 A10s hdmi tv-stick"; - compatible = "allwinner,auxtek-t003", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_t003>; - - red { - label = "t003-tv-dongle:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_t003: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_t003: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG13"; -}; - -&usb1_vbus_pin_a { - allwinner,pins = "PB10"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts deleted file mode 100644 index 2150e15e1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "Auxtek t004 A10s hdmi tv-stick"; - compatible = "allwinner,auxtek-t004", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_t004>; - - red { - label = "t004-tv-dongle:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - default-state = "on"; - }; - }; - - reg_vmmc1: vmmc1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_vcc_en_pin_t004>; - regulator-name = "vmmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 1 18 GPIO_ACTIVE_HIGH>; /* PB18 */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vmmc1>; - bus-width = <4>; - non-removable; - cap-sdio-irq; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_t004: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 { - allwinner,pins = "PB18"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_t004: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb1_vbus_pin_a { - allwinner,pins = "PG13"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-mk802.dts deleted file mode 100644 index c84ac0053..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "MK802-A10s"; - compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_mk802>; - - red { - label = "mk802:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_mk802: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_mk802: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_mk802: usb1_vbus_pin@0 { - allwinner,pins = "PB10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_mk802>; - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts deleted file mode 100644 index aef91476f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A10s-Olinuxino Micro"; - compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - green { - label = "a10s-olinuxino-micro:green:usr"; - gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp152: pmic@30 { - reg = <0x30>; - interrupts = <0>; - }; -}; - -#include "axp152.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - at24@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - read-only; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button@392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button@601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button@795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button@987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { - allwinner,pins = "PG13"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PE3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 { - allwinner,pins = "PB10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - status = "okay"; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>; - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>, - <&spi2_cs0_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG11"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts deleted file mode 100644 index 3b057983c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "R7 A10s hdmi tv-stick"; - compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_r7>; - - green { - label = "r7-tv-dongle:green:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_r7: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_r7: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_r7: usb1_vbus_pin@0 { - allwinner,pins = "PG13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_r7>; - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts deleted file mode 100644 index b5de75f4c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright 2015 Jelle van der Waa - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "A10s-Wobo i5"; - compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_wobo_i5>; - - blue { - label = "a10s-wobo-i5:blue:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_wobo>; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_b>; - phy = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_wobo_i5: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - emac_power_pin_wobo: emac_power_pin@0 { - allwinner,pins = "PA02"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_ldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi2"; -}; - -®_usb1_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb1_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s.dtsi deleted file mode 100644 index c41a2ba34..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a10s.dtsi +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -#include "sun5i.dtsi" - -#include -#include - -/ { - interrupt-parent = <&intc>; - - aliases { - ethernet0 = &emac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 43>, <&ahb_gates 44>; - status = "disabled"; - }; - - framebuffer@1 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 44>; - status = "disabled"; - }; - - framebuffer@2 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>, - <&ahb_gates 36>, <&ahb_gates 44>; - status = "disabled"; - }; - }; - - clocks { - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <5>, <6>, - <7>, <8>, <9>, - <10>, <13>, - <14>, <17>, <18>, - <20>, <21>, <22>, - <26>, <28>, <32>, - <34>, <36>, <40>, - <43>, <44>, - <46>, <51>, - <52>; - clock-output-names = "ahb_usbotg", "ahb_ehci", - "ahb_ohci", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_nand", - "ahb_sdram", "ahb_emac", "ahb_ts", - "ahb_spi0", "ahb_spi1", "ahb_spi2", - "ahb_gps", "ahb_stimer", "ahb_ve", - "ahb_tve", "ahb_lcd", "ahb_csi", - "ahb_hdmi", "ahb_de_be", - "ahb_de_fe", "ahb_iep", - "ahb_mali400"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <3>, - <5>, <6>, - <10>; - clock-output-names = "apb0_codec", "apb0_iis", - "apb0_pio", "apb0_ir", - "apb0_keypad"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <16>, - <17>, <18>, - <19>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart0", - "apb1_uart1", "apb1_uart2", - "apb1_uart3"; - }; - }; - - soc@01c00000 { - emac: ethernet@01c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ahb_gates 17>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; - - mdio: mdio@01c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - pwm: pwm@01c20e00 { - compatible = "allwinner,sun5i-a10s-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 16>; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 18>; - status = "disabled"; - }; - }; -}; - -&pio { - compatible = "allwinner,sun5i-a10s-pinctrl"; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PB19", "PB20"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart2_pins_a: uart2@0 { - allwinner,pins = "PC18", "PC19"; - allwinner,function = "uart2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - emac_pins_b: emac0@1 { - allwinner,pins = "PD6", "PD7", "PD10", - "PD11", "PD12", "PD13", "PD14", - "PD15", "PD18", "PD19", "PD20", - "PD21", "PD22", "PD23", "PD24", - "PD25", "PD26", "PD27"; - allwinner,function = "emac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8"; - allwinner,function = "mmc1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_pins_a: spi2@0 { - allwinner,pins = "PB12", "PB13", "PB14"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_cs0_pins_a: spi2_cs0@0 { - allwinner,pins = "PB11"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&sram_a { - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts deleted file mode 100644 index 894c4c4f9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "Difrnce DIT4350"; - compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts deleted file mode 100644 index 6efbba6d4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include -#include - -/ { - model = "Empire Electronix D709 tablet"; - compatible = "empire-electronix,d709", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_d709: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts deleted file mode 100644 index b1e2afd9d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" -#include - -/ { - model = "Empire Electronix M712 tablet"; - compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts deleted file mode 100644 index 3724b9880..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "HSG H702"; - compatible = "hsg,h702", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_h702: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_a>; - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts deleted file mode 100644 index 439ae3b53..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "INet-98V Rev 02"; - compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts deleted file mode 100644 index 081329e2b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * Copyright 2013 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A13-Olinuxino Micro"; - compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinom>; - - power { - label = "a13-olinuxino-micro:green:power"; - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxinom: led_pins@0 { - allwinner,pins = "PG9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { - allwinner,pins = "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_olinuxinom>; - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxinom>; - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-olinuxino.dts deleted file mode 100644 index b3c234c65..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A13-Olinuxino"; - compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - power { - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button@392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button@601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button@795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button@987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PG9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { - allwinner,pins = "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - status = "okay"; - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxino>; - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts deleted file mode 100644 index a89f29fa3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "Q8 A13 Tablet"; - compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; - - panel: panel { - compatible = "urt,umsh-8596md-t", "simple-panel"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - /* TODO: lcd panel uses axp gpio0 as enable pin */ - backlight = <&backlight>; - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts deleted file mode 100644 index a8b0bcc04..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" -#include - -/ { - model = "Utoo P66"; - compatible = "utoo,p66", "allwinner,sun5i-a13"; - - /* The P66 uses the uart pins as gpios */ - aliases { - /delete-property/serial0; - }; - - chosen { - /delete-property/stdout-path; - }; - - i2c_lcd: i2c@0 { - /* The lcd panel i2c interface is hooked up via gpios */ - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_lcd_pins>; - gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>, /* PG12, sda */ - <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10, scl */ - i2c-gpio,delay-us = <5>; - }; -}; - -&backlight { - /* Note levels of 10 / 20% result in backlight off */ - brightness-levels = <0 30 40 50 60 70 80 90 100>; - default-brightness-level = <6>; -}; - -&codec { - allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ -}; - -&codec_pa_pin { - allwinner,pins = "PG3"; -}; - -&i2c1 { - icn8318: touchscreen@40 { - compatible = "chipone,icn8318"; - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_wake_pin_p66>; - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; - -&pio { - i2c_lcd_pins: i2c_lcd_pin@0 { - allwinner,pins = "PG10", "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ts_wake_pin_p66: ts_wake_pin@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - -}; - -®_usb0_vbus { - gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ -}; - -&uart1 { - /* The P66 uses the uart pins as gpios */ - status = "disabled"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PB4"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun5i-a13.dtsi deleted file mode 100644 index a17ba0243..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-a13.dtsi +++ /dev/null @@ -1,375 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -#include "sun5i.dtsi" - -#include -#include - -/ { - interrupt-parent = <&intc>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>, - <&tcon_ch0_clk>, <&dram_gates 26>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - clocks { - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <5>, <6>, - <7>, <8>, <9>, - <10>, <13>, - <14>, <20>, - <21>, <22>, - <28>, <32>, <34>, - <36>, <40>, <44>, - <46>, <51>, - <52>; - clock-output-names = "ahb_usbotg", "ahb_ehci", - "ahb_ohci", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_nand", - "ahb_sdram", "ahb_spi0", - "ahb_spi1", "ahb_spi2", - "ahb_stimer", "ahb_ve", "ahb_tve", - "ahb_lcd", "ahb_csi", "ahb_de_be", - "ahb_de_fe", "ahb_iep", - "ahb_mali400"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <5>, - <6>; - clock-output-names = "apb0_codec", "apb0_pio", - "apb0_ir"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <17>, - <19>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart1", - "apb1_uart3"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-dram-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, - <25>, - <26>, - <29>, - <31>; - clock-output-names = "dram_ve", - "dram_csi", - "dram_de_fe", - "dram_de_be", - "dram_ace", - "dram_iep"; - }; - - de_be_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be"; - }; - - de_fe_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe"; - }; - - tcon_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon-ch0-sclk"; - }; - - tcon_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon-ch1-sclk"; - }; - }; - - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc@01c00000 { - tcon0: lcd-controller@01c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&tcon_ch0_clk 1>; - reset-names = "lcd"; - clocks = <&ahb_gates 36>, - <&tcon_ch0_clk>, - <&tcon_ch1_clk>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - pwm: pwm@01c20e00 { - compatible = "allwinner,sun5i-a13-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - fe0: display-frontend@01e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ahb_gates 46>, <&de_fe_clk>, - <&dram_gates 25>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_fe_clk>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@01e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - clocks = <&ahb_gates 44>, <&de_be_clk>, - <&dram_gates 26>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_be_clk>; - status = "disabled"; - - assigned-clocks = <&de_be_clk>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; - }; - }; -}; - -&cpu0 { - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1400000 - 912000 1350000 - 864000 1300000 - 624000 1200000 - 576000 1200000 - 432000 1200000 - >; - #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <5>; -}; - -&pio { - compatible = "allwinner,sun5i-a13-pinctrl"; - - lcd_rgb666_pins: lcd_rgb666@0 { - allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - allwinner,function = "lcd0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_pins_a: uart1@0 { - allwinner,pins = "PE10", "PE11"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_pins_b: uart1@1 { - allwinner,pins = "PG3", "PG4"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-gr8-evb.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-gr8-evb.dts deleted file mode 100644 index 714381fd6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * Copyright 2016 NextThing Co - * - * Mylène Josserand - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-gr8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "NextThing GR8-EVB"; - compatible = "nextthing,gr8-evb", "nextthing,gr8"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 10000 0>; - enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; - - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - wm8978: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; - - pcf8563: rtc@51 { - compatible = "phg,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button@390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button@600 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button@800 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button@980 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <980000>; - }; - - button@1180 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1180000>; - }; - - button@1400 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; - - /* MLC Support sucks for now */ - status = "disabled"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_gr8_evb: mmc0-cd-pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_pin_gr8_evb: usb0-id-pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_det_pin_gr8_evb: usb0-vbus-det-pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_gr8_evb: usb1-vbus-pin@0 { - allwinner,pins = "PG13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_gr8_evb>; - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&rtp { - allwinner,ts-attached; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; - status = "okay"; -}; - -&tve0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>; - status = "okay"; -}; - -&usb_otg { - /* - * The GR8-EVB has a somewhat interesting design. There's a - * pin supposed to control VBUS, an ID pin, a VBUS detect pin, - * so everything should work just fine. - * - * Except that the pin supposed to control VBUS is not - * connected to any controllable output, neither to the SoC - * through a GPIO or to the PMIC, and it is pulled down, - * meaning that we will never be able to enable VBUS on this - * board. - */ - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pin_gr8_evb>, <&usb0_vbus_det_pin_gr8_evb>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-gr8.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun5i-gr8.dtsi deleted file mode 100644 index ca54e03ef..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-gr8.dtsi +++ /dev/null @@ -1,1087 +0,0 @@ -/* - * Copyright 2016 Mylène Josserand - * - * Mylène Josserand - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&cpu>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc3M: osc3M-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - - osc32k: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2-clk { - compatible = "allwinner,sun4i-a10-pll3-2x-clk"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll3>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2-clk { - compatible = "allwinner,sun4i-a10-pll3-2x-clk"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll7>; - clock-output-names = "pll7-2x"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&cpu>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 1>; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-indices = <0>; - clock-output-names = "axi_dram"; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <5>, <6>, - <7>, <8>, <9>, - <10>, <13>, - <14>, <17>, <20>, - <21>, <22>, - <28>, <32>, <34>, - <36>, <40>, <44>, - <46>, <51>, - <52>; - clock-output-names = "ahb_usbotg", "ahb_ehci", - "ahb_ohci", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_nand", - "ahb_sdram", "ahb_emac", "ahb_spi0", - "ahb_spi1", "ahb_spi2", - "ahb_hstimer", "ahb_ve", "ahb_tve", - "ahb_lcd", "ahb_csi", "ahb_de_be", - "ahb_de_fe", "ahb_iep", - "ahb_mali400"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <3>, - <5>, <6>; - clock-output-names = "apb0_codec", "apb0_i2s0", - "apb0_pio", "apb0_ir"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <17>, - <18>, <19>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart1", - "apb1_uart2", "apb1_uart3"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - i2s0_clk: clk@01c200b8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200b8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s0"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_phy"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "nextthing,gr8-dram-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, - <25>, - <26>, - <29>, - <31>; - clock-output-names = "dram_ve", - "dram_csi", - "dram_de_fe", - "dram_de_be", - "dram_ace", - "dram_iep"; - }; - - de_be_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be"; - }; - - de_fe_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe"; - }; - - tcon_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon-ch0-sclk"; - }; - - tcon_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon-ch1-sclk"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mbus"; - }; - }; - - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram-controller@01c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@00000000 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - }; - - sram_d: sram@00010000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0000 { - compatible = "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - }; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ahb_gates 6>; - #dma-cells = <2>; - }; - - nfc: nand@01c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ahb_gates 13>, <&nand_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@01c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@01c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tve0: tv-encoder@01c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ahb_gates 34>; - resets = <&tcon_ch0_clk 0>; - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tve0_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_tve0>; - }; - }; - }; - - tcon0: lcd-controller@01c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&tcon_ch0_clk 1>; - reset-names = "lcd"; - clocks = <&ahb_gates 36>, - <&tcon_ch0_clk>, - <&tcon_ch1_clk>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - }; - }; - }; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <32>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@01c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - status = "disabled"; - - dr_mode = "otg"; - }; - - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4>; - reg-names = "phy_ctrl", "pmu1"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>; - reset-names = "usb0_reset", "usb1_reset"; - status = "disabled"; - }; - - ehci0: usb@01c14000 { - compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ahb_gates 1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c14400 { - compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <40>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - spi2: spi@01c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@01c20800 { - compatible = "nextthing,gr8-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&apb0_gates 5>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB15", "PB16"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB17", "PB18"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2s0_data_pins_a: i2s0-data@0 { - allwinner,pins = "PB6", "PB7", "PB8", "PB9"; - allwinner,function = "i2s0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2s0_mclk_pins_a: i2s0-mclk@0 { - allwinner,pins = "PB6", "PB7", "PB8", "PB9"; - allwinner,function = "i2s0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir0_rx_pins_a: ir0@0 { - allwinner,pins = "PB4"; - allwinner,function = "ir0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - lcd_rgb666_pins: lcd-rgb666@0 { - allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - allwinner,function = "lcd0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - nand_pins_a: nand-base0@0 { - allwinner,pins = "PC0", "PC1", "PC2", - "PC5", "PC8", "PC9", "PC10", - "PC11", "PC12", "PC13", "PC14", - "PC15"; - allwinner,function = "nand0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - nand_cs0_pins_a: nand-cs@0 { - allwinner,pins = "PC4"; - allwinner,function = "nand0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - nand_rb0_pins_a: nand-rb@0 { - allwinner,pins = "PC6"; - allwinner,function = "nand0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - pwm0_pins_a: pwm0@0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spdif_tx_pins_a: spdif@0 { - allwinner,pins = "PB10"; - allwinner,function = "spdif"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_pins_a: uart1@1 { - allwinner,pins = "PG3", "PG4"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_cts_rts_pins_a: uart1-cts-rts@0 { - allwinner,pins = "PG5", "PG6"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - pwm: pwm@01c20e00 { - compatible = "allwinner,sun5i-a10s-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>; - clocks = <&osc24M>; - }; - - wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - }; - - spdif: spdif@01c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = <13>; - clocks = <&apb0_gates 1>, <&spdif_clk>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ir0: ir@01c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - i2s0: i2s@01c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = <16>; - clocks = <&apb0_gates 3>, <&i2s0_clk>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@01c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&apb0_gates 0>, <&codec_clk>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtp: rtp@01c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 17>; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 18>; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&apb1_gates 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&apb1_gates 1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&apb1_gates 2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - timer@01c60000 { - compatible = "allwinner,sun5i-a13-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <82>, <83>; - clocks = <&ahb_gates 28>; - }; - - fe0: display-frontend@01e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ahb_gates 46>, <&de_fe_clk>, - <&dram_gates 25>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_fe_clk>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@01e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - clocks = <&ahb_gates 44>, <&de_be_clk>, - <&dram_gates 26>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_be_clk>; - status = "disabled"; - - assigned-clocks = <&de_be_clk>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-r8-chip.dts b/software/linux/kernel/arch/arm/boot/dts/sun5i-r8-chip.dts deleted file mode 100644 index b68a12374..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-r8-chip.dts +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright 2015 Free Electrons - * Copyright 2015 NextThing Co - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-r8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "NextThing C.H.I.P."; - compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13"; - - aliases { - i2c0 = &i2c0; - i2c2 = &i2c2; - serial0 = &uart1; - serial1 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "chip:white:status"; - gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - xio: gpio@38 { - compatible = "nxp,pcf8574a"; - reg = <0x38>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&pio>; - interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - chip_vbus_pin: chip_vbus_pin@0 { - allwinner,pins = "PB10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - chip_id_det_pin: chip_id_det_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "cpuvdd"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "corevdd"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "rtcvdd"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -®_ldo5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_usb0_vbus { - pinctrl-0 = <&chip_vbus_pin>; - vin-supply = <®_vcc5v0>; - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&tcon0 { - status = "okay"; -}; - -&tve0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>, - <&uart3_pins_cts_rts_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&chip_id_det_pin>; - status = "okay"; - - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_vcc5v0>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-r8.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun5i-r8.dtsi deleted file mode 100644 index 8b058f53b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-r8.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright 2015 Free Electrons - * Copyright 2015 NextThing Co - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i-a13.dtsi" - -/ { - chosen { - framebuffer@1 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, <&de_be_clk>, - <&tcon_ch1_clk>, <&dram_gates 26>; - status = "disabled"; - }; - }; - - soc@01c00000 { - tve0: tv-encoder@01c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ahb_gates 34>; - resets = <&tcon_ch0_clk 0>; - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tve0_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_tve0>; - }; - }; - }; - }; -}; - -&tcon0_out { - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi deleted file mode 100644 index 20cc940f5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" - -#include - -/ { - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; - allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&lradc { - vref-supply = <®_ldo2>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PG10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun5i.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun5i.dtsi deleted file mode 100644 index e374f4fc8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun5i.dtsi +++ /dev/null @@ -1,717 +0,0 @@ -/* - * Copyright 2012-2015 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&cpu>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc3M: osc3M_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - - osc32k: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll3>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll7>; - clock-output-names = "pll7-2x"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&cpu>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 1>; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-axi-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-indices = <0>; - clock-output-names = "axi_dram"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_phy"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mbus"; - }; - }; - - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram-controller@01c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@00000000 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - }; - - sram_d: sram@00010000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0000 { - compatible = "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - }; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ahb_gates 6>; - #dma-cells = <2>; - }; - - spi0: spi@01c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@01c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <32>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@01c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - status = "disabled"; - }; - - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4>; - reg-names = "phy_ctrl", "pmu1"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>; - reset-names = "usb0_reset", "usb1_reset"; - status = "disabled"; - }; - - ehci0: usb@01c14000 { - compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ahb_gates 1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c14400 { - compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <40>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - spi2: spi@01c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@01c20800 { - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&apb0_gates 5>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB15", "PB16"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB17", "PB18"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart3_pins_a: uart3@0 { - allwinner,pins = "PG9", "PG10"; - allwinner,function = "uart3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart3_pins_cts_rts_a: uart3-cts-rts@0 { - allwinner,pins = "PG11", "PG12"; - allwinner,function = "uart3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - pwm0_pins: pwm0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>; - clocks = <&osc24M>; - }; - - wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@01c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&apb0_gates 0>, <&codec_clk>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@01c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 17>; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 19>; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&apb1_gates 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&apb1_gates 1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&apb1_gates 2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - timer@01c60000 { - compatible = "allwinner,sun5i-a13-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <82>, <83>; - clocks = <&ahb_gates 28>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts deleted file mode 100644 index 2f8cfab77..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2014 Boris Brezillon - * - * Boris Brezillon - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Allwinner A31 APP4 EVB1 Evaluation Board"; - compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&pio { - usb1_vbus_pin_a: usb1_vbus_pin@0 { - allwinner,pins = "PH27"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_a>; - gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-colombus.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-colombus.dts deleted file mode 100644 index f9cf36888..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "WITS A31 Colombus Evaluation Board"; - compatible = "wits,colombus", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - i2c_lcd: i2c@0 { - /* The lcd panel i2c interface is hooked up via gpios */ - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_lcd_pins>; - gpios = <&pio 0 23 GPIO_ACTIVE_HIGH>, /* PA23, sda */ - <&pio 0 24 GPIO_ACTIVE_HIGH>; /* PA24, scl */ - i2c-gpio,delay-us = <5>; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "fail"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PA9 */ - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; -}; - -&mmc0_pins_a { - allwinner,pull = ; -}; - -&pio { - mmc0_cd_pin_colombus: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_colombus: usb2_vbus_pin@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c_lcd_pins: i2c_lcd_pin@0 { - allwinner,pins = "PA23", "PA24"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb2_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_colombus>; - gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-hummingbird.dts deleted file mode 100644 index 9a74637f6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright 2014 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Merrii A31 Hummingbird"; - compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31"; - - aliases { - rtc0 = &pcf8563; - rtc1 = &rtc; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_hummingbird>; - phy = <&phy1>; - phy-mode = "rgmii"; - snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - /* pull-ups and devices require AXP221 DLDO3 */ - status = "failed"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; -}; - -&mmc0_pins_a { - /* external pull-ups missing for some pins */ - allwinner,pull = ; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_hummingbird>; - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin@0 { - allwinner,pins = "PA21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - wifi_reset_pin_hummingbird: wifi_reset_pin@0 { - allwinner,pins = "PG10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_usb1_vbus { - gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb1_vbus_pin_a { - /* different pin from sunxi-common-regulators */ - allwinner,pins = "PH24"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-i7.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-i7.dts deleted file mode 100644 index e9185dad6..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-i7.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2015 Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Mele I7 Quad top set box"; - compatible = "mele,i7", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_i7>; - - blue { - label = "i7:blue:usr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; - status = "okay"; -}; - -&pio { - led_pins_i7: led_pins@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_i7: mmc0_cd_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_i7: usb1_vbus_pin@0 { - allwinner,pins = "PC27"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_i7>; - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-m9.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-m9.dts deleted file mode 100644 index 29016a13a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-m9.dts +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Mele M9 top set box"; - compatible = "mele,m9", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_m9>; - - blue { - label = "m9:blue:pwr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&pio { - led_pins_m9: led_pins@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_m9: mmc0_cd_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_m9: usb1_vbus_pin@0 { - allwinner,pins = "PC27"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ethernet-phy"; -}; - -/* - * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached - * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is - * marked as regulator-always-on. - */ -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-hub"; -}; - -®_usb1_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_m9>; - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_aldo1>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts deleted file mode 100644 index 5faeae429..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Mele A1000G Quad top set box"; - compatible = "mele,a1000g-quad", "allwinner,sun6i-a31"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_m9>; - - blue { - label = "a1000g:blue:pwr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; - status = "okay"; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -&pio { - led_pins_m9: led_pins@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_m9: mmc0_cd_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_m9: usb1_vbus_pin@0 { - allwinner,pins = "PC27"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_aldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ethernet-phy"; -}; - -/* - * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached - * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is - * marked as regulator-always-on. - */ -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-hub"; -}; - -®_usb1_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_m9>; - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_aldo1>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31.dtsi deleted file mode 100644 index ce1960453..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31.dtsi +++ /dev/null @@ -1,926 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -#include -#include - -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - simplefb_hdmi: framebuffer@0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, - <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, - <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, - <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - - simplefb_lcd: framebuffer@1 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, - <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, - <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - cpus { - enable-method = "allwinner,sun6i-a31"; - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1200000 - 864000 1200000 - 720000 1100000 - 480000 1000000 - >; - #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <3>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - }; - }; - - thermal-zones { - cpu_thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - osc32k: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk@1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk@2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@01c200d0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c200d0 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - }; - - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun6i-a31-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_DMA>; - resets = <&ccu RST_AHB1_DMA>; - #dma-cells = <1>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@01c12000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_AHB1_MMC3>, - <&ccu CLK_MMC3>, - <&ccu CLK_MMC3_OUTPUT>, - <&ccu CLK_MMC3_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_AHB1_MMC3>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@01c19000 { - compatible = "allwinner,sun6i-a31-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_AHB1_OTG>; - resets = <&ccu RST_AHB1_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@01c19400 { - compatible = "allwinner,sun6i-a31-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>; - reg-names = "phy_ctrl", - "pmu1", - "pmu2"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@01c1a000 { - compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_EHCI0>; - resets = <&ccu RST_AHB1_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c1a400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_AHB1_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@01c1b000 { - compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_EHCI1>; - resets = <&ccu RST_AHB1_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@01c1b400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_AHB1_OHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@01c1c400 { - compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_AHB1_OHCI2>; - status = "disabled"; - }; - - ccu: clock@01c20000 { - compatible = "allwinner,sun6i-a31-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun6i-a31-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_APB1_PIO>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PH14", "PH15"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PH16", "PH17"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PH18", "PH19"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - allwinner,function = "mmc1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc2_8bit_emmc_pins: mmc2@1 { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC24"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_8bit_emmc_pins: mmc3@1 { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC24"; - allwinner,function = "mmc3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_pins_mii_a: gmac_mii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA8", "PA9", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA26", "PA27"; - allwinner,function = "gmac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_pins_gmii_a: gmac_gmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA6", "PA7", - "PA8", "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA15", - "PA16", "PA17", "PA18", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA25", "PA26", "PA27"; - allwinner,function = "gmac"; - /* - * data lines in GMII mode run at 125MHz and - * might need a higher signal drive strength - */ - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_pins_rgmii_a: gmac_rgmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA25", "PA26", "PA27"; - allwinner,function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - , - , - , - ; - clocks = <&osc24M>; - }; - - wdt1: watchdog@01c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = ; - status = "disabled"; - }; - - rtp: rtp@01c25000 { - compatible = "allwinner,sun6i-a31-ts"; - reg = <0x01c25000 0x100>; - interrupts = ; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART0>; - resets = <&ccu RST_APB2_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART1>; - resets = <&ccu RST_APB2_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART2>; - resets = <&ccu RST_APB2_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART3>; - resets = <&ccu RST_APB2_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@01c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART4>; - resets = <&ccu RST_APB2_UART4>; - dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@01c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB2_UART5>; - resets = <&ccu RST_APB2_UART5>; - dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C0>; - resets = <&ccu RST_APB2_I2C0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C1>; - resets = <&ccu RST_APB2_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C2>; - resets = <&ccu RST_APB2_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@01c2b800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = ; - clocks = <&ccu CLK_APB2_I2C3>; - resets = <&ccu RST_APB2_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gmac: ethernet@01c30000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x01c30000 0x1054>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ccu RST_AHB1_EMAC>; - reset-names = "stmmaceth"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_AHB1_SS>; - reset-names = "ahb"; - }; - - timer@01c60000 { - compatible = "allwinner,sun6i-a31-hstimer", - "allwinner,sun7i-a20-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_AHB1_HSTIMER>; - resets = <&ccu RST_AHB1_HSTIMER>; - }; - - spi0: spi@01c68000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI0>; - status = "disabled"; - }; - - spi1: spi@01c69000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c69000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 24>, <&dma 24>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI1>; - status = "disabled"; - }; - - spi2: spi@01c6a000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c6a000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma 25>, <&dma 25>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI2>; - status = "disabled"; - }; - - spi3: spi@01c6b000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c6b000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - dmas = <&dma 26>, <&dma 26>; - dma-names = "rx", "tx"; - resets = <&ccu RST_AHB1_SPI3>; - status = "disabled"; - }; - - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - rtc: rtc@01f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupts = , - ; - }; - - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; - interrupts = ; - }; - - prcm@01f01400 { - compatible = "allwinner,sun6i-a31-prcm"; - reg = <0x01f01400 0x200>; - - ar100: ar100_clk { - compatible = "allwinner,sun6i-a31-ar100-clk"; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, - <&ccu CLK_PLL_PERIPH>, - <&ccu CLK_PLL_PERIPH>; - clock-output-names = "ar100"; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun6i-a31-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun6i-a31-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_ir", - "apb0_timer", "apb0_p2wi", - "apb0_uart", "apb0_1wire", - "apb0_i2c"; - }; - - ir_clk: ir_clk { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "ir"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - }; - - cpucfg@01f01c00 { - compatible = "allwinner,sun6i-a31-cpuconfig"; - reg = <0x01f01c00 0x300>; - }; - - ir: ir@01f02000 { - compatible = "allwinner,sun5i-a13-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; - clock-names = "apb", "ir"; - resets = <&apb0_rst 1>; - interrupts = ; - reg = <0x01f02000 0x40>; - status = "disabled"; - }; - - r_pio: pinctrl@01f02c00 { - compatible = "allwinner,sun6i-a31-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = , - ; - clocks = <&apb0_gates 0>; - resets = <&apb0_rst 0>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #size-cells = <0>; - #gpio-cells = <3>; - - ir_pins_a: ir@0 { - allwinner,pins = "PL4"; - allwinner,function = "s_ir"; - allwinner,drive = ; - allwinner,pull = ; - }; - - p2wi_pins: p2wi { - allwinner,pins = "PL0", "PL1"; - allwinner,function = "s_p2wi"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - p2wi: i2c@01f03400 { - compatible = "allwinner,sun6i-a31-p2wi"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>; - clock-frequency = <100000>; - resets = <&apb0_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&p2wi_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts deleted file mode 100644 index 882a4d89f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sun6i-reference-design-tablet.dtsi" - -/ { - model = "Colorfly E708 Q1 tablet"; - compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button@1000 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <1000000>; - }; -}; - -®_dldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pg"; -}; - -&simplefb_lcd { - vcc-pg-supply = <®_dldo2>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-cs908.dts deleted file mode 100644 index 5e8f8c4f2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-cs908.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" - -#include - -/ { - model = "CSQ CS908 top set box"; - compatible = "csq,cs908", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts deleted file mode 100644 index e584e6b18..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sun6i-reference-design-tablet.dtsi" - -/ { - model = "iNet Q972 tablet"; - compatible = "inet-tek,inet-q972", "allwinner,sun6i-a31s"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ - touchscreen-size-x = <768>; - touchscreen-size-y = <1024>; - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button@200 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@900 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <900000>; - }; - - button@1200 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <1200000>; - }; -}; - -&ohci1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-primo81.dts deleted file mode 100644 index 73c133f5e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright 2014 Siarhei Siamashka - * Copyright 2015 Karsten Merker - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "MSI Primo81 tablet"; - compatible = "msi,primo81", "allwinner,sun6i-a31s"; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - /* rtl8188etv wifi is connected here */ - status = "okay"; -}; - -&i2c0 { - /* pull-ups and device VDDIO use AXP221 DLDO3 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "failed"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - ctp@5d { - pinctrl-names = "default"; - pinctrl-0 = <>911_int_primo81>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ - touchscreen-swapped-x-y; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - accelerometer@1c { - pinctrl-names = "default"; - pinctrl-0 = <&mma8452_int_primo81>; - compatible = "fsl,mma8452"; - reg = <0x1c>; - interrupt-parent = <&pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; /* PA9 */ - #io-channel-cells = <1>; - }; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button@158 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button@349 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; -}; - -&pio { - gt911_int_primo81: gt911_int_pin@0 { - allwinner,pins = "PA3"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mma8452_int_primo81: mma8452_int_pin@0 { - allwinner,pins = "PA9"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_primo81: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi"; -}; - -®_eldo3 { - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-mipi-bridge"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; - vdd-mipi-bridge-supply = <®_eldo3>; -}; - -&usb_otg { - /* otg support requires support for AXP221 usb-power-supply and GPIO */ - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi deleted file mode 100644 index 4ec0c8679..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Sinlinx SinA31s Core Board"; - compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -/* eMMC on core board */ -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_8bit_emmc_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -/* AXP221s PMIC on core board */ -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -/* UART0 pads available on core board */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sina31s.dts deleted file mode 100644 index 6ead2f5c8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The SinA31s development board has the SinA31s core board soldered on */ -#include "sun6i-a31s-sina31s-core.dtsi" - -#include - -/ { - model = "Sinlinx SinA31s Development Board"; - compatible = "sinlinx,sina31s-sdk", "allwinner,sun6i-a31s"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_sina31s>; - - status { - label = "sina31s:status:usr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ - }; - }; -}; - -&ehci0 { - /* USB 2.0 4 port hub IC */ - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_dldo1>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button@158 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <158730>; - }; - - button@349 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <349206>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */ - cd-inverted; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - led_pin_sina31s: led_pin@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_sina31s: mmc0_cd_pin@0 { - allwinner,pins = "PA4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-gmac-phy"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts deleted file mode 100644 index db7fa13f5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include - -/ { - model = "Sinovoip BPI-M2"; - compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bpi_m2>; - - blue { - label = "bpi-m2:blue:usr"; - gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - }; - - green { - label = "bpi-m2:green:usr"; - gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ - }; - - red { - label = "bpi-m2:red:usr"; - gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */ - }; - }; - - mmc2_pwrseq: mmc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pwrseq_pin_bpi_m2>; - reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>; - phy = <&phy1>; - phy-mode = "rgmii"; - snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */ - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */ - cd-inverted; - status = "okay"; -}; - -&mmc0_pins_a { - allwinner,pull = ; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v0>; - mmc-pwrseq = <&mmc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2_pins_a { - allwinner,pull = ; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 { - allwinner,pins = "PA21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_bpi_m2: led_pins@0 { - allwinner,pins = "PG5", "PG10", "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 { - allwinner,pins = "PA4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_pio { - mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 { - allwinner,pins = "PL8"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts deleted file mode 100644 index d6ad6196a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2015 Lawrence Yu - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Yones TopTech BS1078 v2 Tablet"; - compatible = "yones-toptech,bs1078-v2", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_bs1078v2: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; -}; - -&mmc0_pins_a { - allwinner,pull = ; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd-usb2"; -}; - -®_dc5ldo { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -/* Voltage source for I2C pullup resistors for I2C Bus 0 */ -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vddio-csi"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; - usb2_vbus-supply = <®_dc1sw>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s.dtsi deleted file mode 100644 index c17a32771..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-a31s.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The A31s is the same die as the A31 in a different package, this is - * reflected by it having different pinctrl compatible everything else is - * identical. - */ - -#include "sun6i-a31.dtsi" - -&pio { - compatible = "allwinner,sun6i-a31s-pinctrl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi deleted file mode 100644 index 0c434304e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - /* Wifi is connected here */ - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; -}; - -&pio { - mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts deleted file mode 100644 index 44377a98c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright 2016 Luo Yi - * - * Thanks to the original work by Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "Banana Pi BPI-M1-Plus"; - compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bpi_m1p>; - - green { - label = "bananapi-m1-plus:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - - pwr { - label = "bananapi-m1-plus:pwr:usr"; - gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pwrseq_pin_bpi_m1p>; - reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bpi_m1p>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - enable-sdio-wakeup; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&mmc3_pins_a { - /* AP6210 requires pull-up */ - allwinner,pull = ; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - gmac_power_pin_bpi_m1p: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_bpi_m1p: led_pins@0 { - allwinner,pins = "PH24", "PH25"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_bpi_m1p: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_pwrseq_pin_bpi_m1p: mmc3_pwrseq_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - /* VBUS on usb host ports are tied to DC5V and therefore always on */ - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapi.dts deleted file mode 100644 index 67c8a7644..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "LeMaker Banana Pi"; - compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart3; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bananapi>; - - green { - label = "bananapi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bananapi>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; - operating-points = < - /* kHz uV */ - 960000 1400000 - 912000 1400000 - 864000 1350000 - 720000 1250000 - 528000 1150000 - 312000 1100000 - 144000 1050000 - >; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_power_pin_bananapi: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_bananapi: led_pins@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>, - <&spi0_cs1_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_b>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapro.dts deleted file mode 100644 index 18fcc87f4..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-bananapro.dts +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "LeMaker Banana Pro"; - compatible = "lemaker,bananapro", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bananapro>; - - blue { - label = "bananapro:blue:usr"; - gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "bananapro:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bananapro>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; - - reg_vmmc3: vmmc3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_bananapro>; - regulator-name = "vmmc3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; - }; -}; - -&ahci { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - gmac_power_pin_bananapro: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_bananapro: led_pins@0 { - allwinner,pins = "PH24", "PG2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_bananapro: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - allwinner,pins = "PH0"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - vmmc3_pin_bananapro: vmmc3_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_bananapro>; - gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ - status = "okay"; -}; - -®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_bananapro>; - gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>, - <&spi0_cs1_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts deleted file mode 100644 index 1fa832d7b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Cubietech Cubieboard2"; - compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard2>; - - blue { - label = "cubieboard2:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "cubieboard2:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_cubieboard2: led_pins@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-cubietruck.dts deleted file mode 100644 index 83f39b036..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright 2013 Oliver Schinagl - * - * Oliver Schinagl - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Cubietech Cubietruck"; - compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubietruck>; - - blue { - label = "cubietruck:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; - - orange { - label = "cubietruck:orange:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - - white { - label = "cubietruck:white:usr"; - gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; - }; - - green { - label = "cubietruck:green:usr"; - gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; - }; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pwrseq_pin_cubietruck>; - reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc3_pins_a { - /* AP6210 requires pull-up */ - allwinner,pull = ; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_cubietruck: led_pins@0 { - allwinner,pins = "PH7", "PH11", "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PH17"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH19"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; - status = "okay"; -}; - -®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_cubietruck>; - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_a>; - gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-hummingbird.dts deleted file mode 100644 index 37f4a5497..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright 2013 Wills Wang - * - * Wills Wang - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Merrii A20 Hummingbird"; - compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_mmc3_vdd: mmc3_vdd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>; - regulator-name = "mmc3_vdd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - }; - - reg_gmac_vdd: gmac_vdd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>; - regulator-name = "gmac_vdd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */ - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_vdd>; - /* phy reset config */ - snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ - snps,reset-active-low; - /* wait 1s after reset, otherwise fail to read phy id */ - snps,reset-delays-us = <0 10000 1000000>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_mmc3_vdd>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 { - allwinner,pins = "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>; - gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>; - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_b>, - <&spi2_cs0_pins_b>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts deleted file mode 100644 index 1e6bd360d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "I12 / Q5 / QT840A A20 tvbox"; - compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_i12_tvbox>; - - red { - label = "i12_tvbox:red:usr"; - gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; - }; - - blue { - label = "i12_tvbox:blue:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vmmc3: vmmc3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_i12_tvbox>; - regulator-name = "vmmc3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; - }; - - reg_vmmc3_io: vmmc3-io { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_io_pin_i12_tvbox>; - regulator-name = "vmmc3-io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* This controls VCC-PI, must be always on! */ - regulator-always-on; - enable-active-high; - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_i12_tvbox>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - enable-active-high; - gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc3_pins_a { - /* AP6210 / AP6330 requires pull-up */ - allwinner,pull = ; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vmmc3_pin_i12_tvbox: vmmc3_pin@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_power_pin_i12_tvbox: gmac_power_pin@0 { - allwinner,pins = "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_i12_tvbox: led_pins@0 { - allwinner,pins = "PH9", "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts deleted file mode 100644 index f5b5325a7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright 2015 Stefan Roese - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "ICnova-A20 SWAC"; - compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts deleted file mode 100644 index 10d48cbf8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-itead-core-common.dtsi" - -/ { - model = "Itead Ibox A20"; - compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20"; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_itead_core>; - - green { - label = "itead_core:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - blue { - label = "itead_core:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - axp209: pmic@34 { - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&pio { - led_pins_itead_core: led_pins@0 { - allwinner,pins = "PH20","PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts deleted file mode 100644 index e00539ae1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright 2015 Jelle de Jong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Lamobo R1"; - compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart3; - serial2 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_lamobo_r1>; - - green { - label = "lamobo_r1:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_lamobo_r1>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci_pwr_pin_a { - allwinner,pins = "PB3"; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - switch: ethernet-switch@1e { - compatible = "brcm,bcm53125"; - reg = <30>; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port0: port@0 { - reg = <0>; - label = "lan2"; - }; - - port1: port@1 { - reg = <1>; - label = "lan3"; - }; - - port2: port@2 { - reg = <2>; - label = "lan4"; - }; - - port3: port@3 { - reg = <3>; - label = "wan"; - }; - - port4: port@4 { - reg = <4>; - label = "lan1"; - }; - - port8: port@8 { - reg = <8>; - label = "cpu"; - ethernet = <&gmac>; - phy-mode = "rgmii-txid"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_power_pin_lamobo_r1: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_lamobo_r1: led_pins@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -#include "axp209.dtsi" - -®_ahci_5v { - gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>, - <&spi0_cs1_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_b>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usb2_vbus_pin_a { - allwinner,pins = "PH12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-m3.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-m3.dts deleted file mode 100644 index 8d9ea48dd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-m3.dts +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright 2014 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Mele M3"; - compatible = "mele,m3", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_m3>; - - blue { - label = "m3:blue:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - led_pins_m3: led_pins@0 { - allwinner,pins = "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-mk808c.dts deleted file mode 100644 index 90ff4a267..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright 2015 Marcus Cooper - * - * Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "mk808c"; - compatible = "allwinner,mk808c", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts deleted file mode 100644 index 23aacce4d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * Copyright 2015 - Karsten Merker - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include - -/ { - model = "Olimex A20-Olimex-SOM-EVB"; - compatible = "olimex,a20-olimex-som-evb", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olimex_som_evb>; - - green { - label = "a20-olimex-som-evb:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button@390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button@600 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; - - button@800 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <800000>; - }; - - button@980 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <980000>; - }; - - button@1180 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1180000>; - }; - - button@1400 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olimex_som_evb: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin@0 { - allwinner,pins = "PH0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olimex_som_evb>; - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts deleted file mode 100644 index 35ad7006c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ /dev/null @@ -1,222 +0,0 @@ -/* - * This is based on sun4i-a10-olinuxino-lime.dts - * - * Copyright 2014 - Hans de Goede - * Copyright (c) 2014 FUKAUMI Naoki - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A20-OLinuXino-LIME"; - compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - green { - label = "a20-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts deleted file mode 100644 index 10d307408..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts +++ /dev/null @@ -1,82 +0,0 @@ - /* - * Copyright 2015 - Ultimaker B.V. - * Author Olliver Schinagl - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun7i-a20-olinuxino-lime2.dts" - -/ { - model = "Olimex A20-OLinuXino-LIME2-eMMC"; - compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20"; - - mmc2_pwrseq: pwrseq { - pinctrl-0 = <&mmc2_pins_nrst>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; - }; -}; - -&pio { - mmc2_pins_nrst: mmc2-rst-pin { - allwinner,pins = "PC16"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&mmc2_pwrseq>; - status = "okay"; - - emmc: emmc@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts deleted file mode 100644 index d5c796c8d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright 2014 - Iain Paton - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A20-OLinuXino-LIME2"; - compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - green { - label = "a20-olinuxino-lime2:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_axp_ipsout: axp_ipsout { - compatible = "regulator-fixed"; - regulator-name = "axp-ipsout"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - - acin-supply = <®_axp_ipsout>; - vin2-supply = <®_axp_ipsout>; - vin3-supply = <®_axp_ipsout>; - ldo24in-supply = <®_axp_ipsout>; - ldo3in-supply = <®_axp_ipsout>; - - regulators { - vdd_rtc: ldo1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - avcc: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_csi0: ldo3 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - vcc_csi1: ldo4 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_cpu: dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <2275000>; - regulator-always-on; - }; - - vdd_int: dcdc3 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_pin_lime2: usb0_vbus_pin@0 { - allwinner,pins = "PC17"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_lime2>; - gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts deleted file mode 100644 index 7e3006f6a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include - -/ { - model = "Olimex A20-Olinuxino Micro"; - compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - serial1 = &uart6; - serial2 = &uart7; - spi0 = &spi1; - spi1 = &spi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - green { - label = "a20-olinuxino-micro:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button@392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button@601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button@795 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button@987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; - - button@1184 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1184678>; - }; - - button@1398 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1398804>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { - allwinner,pins = "PH11"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>, - <&spi1_cs0_pins_a>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>, - <&spi2_cs0_pins_a>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pins_a>; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts deleted file mode 100644 index 2be04c438..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Orange Pi Mini"; - compatible = "xunlong,orangepi-mini", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_orangepi>; - - green { - label = "orangepi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - }; - - blue { - label = "orangepi:blue:usr"; - gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_orangepi>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_orangepi: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_cd_pin_orangepi: mmc3_cd_pin@0 { - allwinner,pins = "PH11"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_power_pin_orangepi: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_orangepi: led_pins@0 { - allwinner,pins = "PH24", "PH25"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - allwinner,pins = "PH26"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_bananapro>; - gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ - status = "okay"; -}; - -®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_bananapro>; - gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-orangepi.dts deleted file mode 100644 index 71125bf64..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Orange Pi"; - compatible = "xunlong,orangepi", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_orangepi>; - - green { - label = "orangepi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_orangepi>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_orangepi: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_power_pin_orangepi: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_orangepi: led_pins@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - allwinner,pins = "PH26"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_bananapro>; - gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ - status = "okay"; -}; - -®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_bananapro>; - gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts deleted file mode 100644 index ddac7328b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright 2015 Adam Sampson - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include - -/ { - model = "LinkSprite pcDuino3 Nano"; - compatible = "linksprite,pcduino3-nano", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_pcduino3_nano>; - - /* Marked "LED3" on the PCB. */ - usr1 { - label = "pcduino3-nano:green:usr1"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */ - }; - - /* Marked "LED4" on the PCB. */ - usr2 { - label = "pcduino3-nano:green:usr2"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_pcduino3_nano: led_pins@0 { - allwinner,pins = "PH16", "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 { - allwinner,pins = "PD2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_pcduino3_nano>; - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -/* A single regulator (U24) powers both USB host ports. */ -®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_pcduino3_nano>; - gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-pcduino3.dts deleted file mode 100644 index 1a8b39be1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright 2014 Zoltan HERPAI - * Zoltan HERPAI - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include - -/ { - model = "LinkSprite pcDuino3"; - compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_pcduino3>; - - tx { - label = "pcduino3:green:tx"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; - }; - - rx { - label = "pcduino3:green:rx"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_pcduino3>; - #address-cells = <1>; - #size-cells = <0>; - button@0 { - label = "Key Back"; - linux,code = ; - gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; - }; - button@1 { - label = "Key Home"; - linux,code = ; - gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; - }; - button@2 { - label = "Key Menu"; - linux,code = ; - gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&ahci_pwr_pin_a { - allwinner,pins = "PH2"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_pcduino3: led_pins@0 { - allwinner,pins = "PH15", "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - key_pins_pcduino3: key_pins@0 { - allwinner,pins = "PH17", "PH18", "PH19"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ahci_5v { - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts deleted file mode 100644 index 2f6b21add..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright 2015 Aleksei Mamlin - * Aleksei Mamlin - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include - -/ { - model = "Wexler TAB7200"; - compatible = "wexler,tab7200", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_enable_pin>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - - gt911: touchscreen@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_reset_pin>; - irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */ - reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */ - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@571 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <571428>; - }; - - button@761 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <761904>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - bl_enable_pin: bl_enable_pin@0 { - allwinner,pins = "PH7"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ts_reset_pin: ts_reset_pin@0 { - allwinner,pins = "PB13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts deleted file mode 100644 index dc31d476e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 2015 Jelle de Jong - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun7i-a20.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Wits Pro A20 DKT"; - compatible = "wits,pro-a20-dkt", "allwinner,sun7i-a20"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - mmc3_pwrseq: mmc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_ap6xxx_wl_regon>; - reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -#include "axp209.dtsi" - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; -}; - -&mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - vmmc3_pin_ap6xxx_wl_regon: vmmc3_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun7i-a20.dtsi deleted file mode 100644 index 94cf5a1c7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun7i-a20.dtsi +++ /dev/null @@ -1,1714 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -#include -#include - -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; - status = "disabled"; - }; - - framebuffer@1 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 26>; - status = "disabled"; - }; - - framebuffer@2 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 5>, <&dram_gates 26>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&cpu>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 960000 1400000 - 912000 1400000 - 864000 1300000 - 720000 1200000 - 528000 1100000 - 312000 1000000 - 144000 1000000 - >; - #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <6>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - }; - - thermal-zones { - cpu_thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; - interrupts = , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc3M: osc3M_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - - osc32k: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll3>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6", - "pll6_div_4"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll7>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll7-2x"; - }; - - pll8: clk@01c20040 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20040 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll8"; - }; - - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&pll6 3>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 3>; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, <8>, - <9>, <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, <21>, - <22>, <23>, <25>, - <28>, <32>, <33>, <34>, - <35>, <36>, <37>, <40>, - <41>, <42>, <43>, - <44>, <45>, <46>, - <47>, <49>, <50>, - <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", - "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", - "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", - "ahb_spi2", "ahb_spi3", "ahb_sata", - "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", - "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", - "ahb_de_fe1", "ahb_gmac", "ahb_mp", - "ahb_mali"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <8>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_i2s0", "apb0_i2s1", - "apb0_pio", "apb0_ir0", "apb0_ir1", - "apb0_i2s2", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <15>, <16>, <17>, - <18>, <19>, <20>, - <21>, <22>, <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_i2c3", "apb1_can", - "apb1_scr", "apb1_ps20", "apb1_ps21", - "apb1_i2c4", "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - i2s0_clk: clk@01c200b8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200b8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s0"; - }; - - ac97_clk: clk@01c200bc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200bc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "ac97"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - keypad_clk: clk@01c200c4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200c4 0x4>; - clocks = <&osc24M>; - clock-output-names = "keypad"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - i2s1_clk: clk@01c200d8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200d8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s1"; - }; - - i2s2_clk: clk@01c200dc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200dc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s2"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; - clock-output-names = "mbus"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk@2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk@3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@01c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - - /* - * Dummy clock used by output clocks - */ - osc24M_32k: clk@1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <750>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc24M_32k"; - }; - - clk_out_a: clk@01c201f0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f0 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_a"; - }; - - clk_out_b: clk@01c201f4 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f4 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_b"; - }; - }; - - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram-controller@01c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@00000000 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@00010000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0000 { - compatible = "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - }; - - nmi_intc: interrupt-controller@01c00030 { - compatible = "allwinner,sun7i-a20-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c00030 0x0c>; - interrupts = ; - }; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 6>; - #dma-cells = <2>; - }; - - nfc: nand@01c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 13>, <&nand_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@01c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 20>, <&spi0_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@01c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@01c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 17>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; - - mdio: mdio@01c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@01c12000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@01c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - status = "disabled"; - }; - - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun7i-a20-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - status = "disabled"; - }; - - ehci0: usb@01c14000 { - compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = ; - clocks = <&ahb_gates 1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c14400 { - compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = ; - clocks = <&usb_clk 6>, <&ahb_gates 2>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 5>, <&ss_clk>; - clock-names = "ahb", "mod"; - }; - - spi2: spi@01c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@01c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = ; - clocks = <&pll6 0>, <&ahb_gates 25>; - status = "disabled"; - }; - - ehci1: usb@01c1c000 { - compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = ; - clocks = <&ahb_gates 3>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@01c1c400 { - compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&usb_clk 7>, <&ahb_gates 4>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - spi3: spi@01c1f000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 23>, <&spi3_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 31>, - <&dma SUN4I_DMA_DEDICATED 30>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun7i-a20-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = ; - clocks = <&apb0_gates 5>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - clk_out_a_pins_a: clk_out_a@0 { - allwinner,pins = "PI12"; - allwinner,function = "clk_out_a"; - allwinner,drive = ; - allwinner,pull = ; - }; - - clk_out_b_pins_a: clk_out_b@0 { - allwinner,pins = "PI13"; - allwinner,function = "clk_out_b"; - allwinner,drive = ; - allwinner,pull = ; - }; - - emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_pins_mii_a: gmac_mii@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "gmac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_pins_rgmii_a: gmac_rgmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA10", - "PA11", "PA12", "PA13", - "PA15", "PA16"; - allwinner,function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB18", "PB19"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB20", "PB21"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c3_pins_a: i2c3@0 { - allwinner,pins = "PI0", "PI1"; - allwinner,function = "i2c3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir0_rx_pins_a: ir0@0 { - allwinner,pins = "PB4"; - allwinner,function = "ir0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir0_tx_pins_a: ir0@1 { - allwinner,pins = "PB3"; - allwinner,function = "ir0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir1_rx_pins_a: ir1@0 { - allwinner,pins = "PB23"; - allwinner,function = "ir1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ir1_tx_pins_a: ir1@1 { - allwinner,pins = "PB22"; - allwinner,function = "ir1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6", "PC7", "PC8", - "PC9", "PC10", "PC11"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_pins_a: mmc3@0 { - allwinner,pins = "PI4", "PI5", "PI6", - "PI7", "PI8", "PI9"; - allwinner,function = "mmc3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ps20_pins_a: ps20@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "ps2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ps21_pins_a: ps21@0 { - allwinner,pins = "PH12", "PH13"; - allwinner,function = "ps2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - pwm0_pins_a: pwm0@0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm"; - allwinner,drive = ; - allwinner,pull = ; - }; - - pwm1_pins_a: pwm1@0 { - allwinner,pins = "PI3"; - allwinner,function = "pwm"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spdif_tx_pins_a: spdif@0 { - allwinner,pins = "PB13"; - allwinner,function = "spdif"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi0_pins_a: spi0@0 { - allwinner,pins = "PI11", "PI12", "PI13"; - allwinner,function = "spi0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi0_cs0_pins_a: spi0_cs0@0 { - allwinner,pins = "PI10"; - allwinner,function = "spi0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi0_cs1_pins_a: spi0_cs1@0 { - allwinner,pins = "PI14"; - allwinner,function = "spi0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi1_pins_a: spi1@0 { - allwinner,pins = "PI17", "PI18", "PI19"; - allwinner,function = "spi1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi1_cs0_pins_a: spi1_cs0@0 { - allwinner,pins = "PI16"; - allwinner,function = "spi1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_pins_a: spi2@0 { - allwinner,pins = "PC20", "PC21", "PC22"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_pins_b: spi2@1 { - allwinner,pins = "PB15", "PB16", "PB17"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_cs0_pins_a: spi2_cs0@0 { - allwinner,pins = "PC19"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - spi2_cs0_pins_b: spi2_cs0@1 { - allwinner,pins = "PB14"; - allwinner,function = "spi2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PB22", "PB23"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart2_pins_a: uart2@0 { - allwinner,pins = "PI16", "PI17", "PI18", "PI19"; - allwinner,function = "uart2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart3_pins_a: uart3@0 { - allwinner,pins = "PG6", "PG7", "PG8", "PG9"; - allwinner,function = "uart3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart3_pins_b: uart3@1 { - allwinner,pins = "PH0", "PH1"; - allwinner,function = "uart3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart4_pins_a: uart4@0 { - allwinner,pins = "PG10", "PG11"; - allwinner,function = "uart4"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart4_pins_b: uart4@1 { - allwinner,pins = "PH4", "PH5"; - allwinner,function = "uart4"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart5_pins_a: uart5@0 { - allwinner,pins = "PI10", "PI11"; - allwinner,function = "uart5"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart6_pins_a: uart6@0 { - allwinner,pins = "PI12", "PI13"; - allwinner,function = "uart6"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart7_pins_a: uart7@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "uart7"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = , - , - , - , - , - ; - clocks = <&osc24M>; - }; - - wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - }; - - rtc: rtc@01c20d00 { - compatible = "allwinner,sun7i-a20-rtc"; - reg = <0x01c20d00 0x20>; - interrupts = ; - }; - - pwm: pwm@01c20e00 { - compatible = "allwinner,sun7i-a20-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@01c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&apb0_gates 1>, <&spdif_clk>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ir0: ir@01c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; - clock-names = "apb", "ir"; - interrupts = ; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - ir1: ir@01c21c00 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; - clock-names = "apb", "ir"; - interrupts = ; - reg = <0x01c21c00 0x40>; - status = "disabled"; - }; - - i2s1: i2s@01c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&apb0_gates 4>, <&i2s1_clk>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 4>, - <&dma SUN4I_DMA_NORMAL 4>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s0: i2s@01c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>, <&i2s0_clk>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = ; - status = "disabled"; - }; - - codec: codec@01c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun7i-a20-codec"; - reg = <0x01c22c00 0x40>; - interrupts = ; - clocks = <&apb0_gates 0>, <&codec_clk>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@01c23800 { - compatible = "allwinner,sun7i-a20-sid"; - reg = <0x01c23800 0x200>; - }; - - i2s2: i2s@01c24400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c24400 0x400>; - interrupts = ; - clocks = <&apb0_gates 8>, <&i2s2_clk>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 6>, - <&dma SUN4I_DMA_NORMAL 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtp: rtp@01c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = ; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 16>; - status = "disabled"; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 17>; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 18>; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 19>; - status = "disabled"; - }; - - uart4: serial@01c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 20>; - status = "disabled"; - }; - - uart5: serial@01c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 21>; - status = "disabled"; - }; - - uart6: serial@01c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 22>; - status = "disabled"; - }; - - uart7: serial@01c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 23>; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&apb1_gates 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&apb1_gates 1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&apb1_gates 2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@01c2b800 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = ; - clocks = <&apb1_gates 3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@01c2c000 { - compatible = "allwinner,sun7i-a20-i2c", - "allwinner,sun4i-a10-i2c"; - reg = <0x01c2c000 0x400>; - interrupts = ; - clocks = <&apb1_gates 15>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gmac: ethernet@01c50000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x01c50000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&ahb_gates 49>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - hstimer@01c60000 { - compatible = "allwinner,sun7i-a20-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = , - , - , - ; - clocks = <&ahb_gates 28>; - }; - - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - ps20: ps2@01c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = ; - clocks = <&apb1_gates 6>; - status = "disabled"; - }; - - ps21: ps2@01c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = ; - clocks = <&apb1_gates 7>; - status = "disabled"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-a33.dtsi deleted file mode 100644 index 300a1bd5a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ /dev/null @@ -1,616 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -#include - -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - simplefb_lcd: framebuffer@0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, - <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - cpus { - enable-method = "allwinner,sun8i-a23"; - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun8i-a23-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - nfc: nand@01c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_NAND>; - reset-names = "ahb"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@01c19000 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@01c19400 { - /* - * compatible and address regions get set in - * SoC specific dtsi file - */ - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@01c1a000 { - compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI>; - resets = <&ccu RST_BUS_EHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c1a400 { - compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; - resets = <&ccu RST_BUS_OHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@01c20000 { - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@01c20800 { - /* compatible gets set in SoC specific dtsi file */ - reg = <0x01c20800 0x400>; - /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_pins_a: uart1@0 { - allwinner,pins = "PG6", "PG7"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_pins_cts_rts_a: uart1-cts-rts@0 { - allwinner,pins = "PG8", "PG9"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - allwinner,function = "mmc1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc2_8bit_pins: mmc2_8bit { - allwinner,pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - pwm0_pins: pwm0 { - allwinner,pins = "PH0"; - allwinner,function = "pwm0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PH2", "PH3"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PH4", "PH5"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PE12", "PE13"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - lcd_rgb666_pins: lcd-rgb666@0 { - allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - allwinner,function = "lcd0"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - wdt0: watchdog@01c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - }; - - pwm: pwm@01c21400 { - compatible = "allwinner,sun7i-a20-pwm"; - reg = <0x01c21400 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = ; - status = "disabled"; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@01c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - rtc: rtc@01f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupts = , - ; - }; - - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; - interrupts = ; - }; - - prcm@01f01400 { - compatible = "allwinner,sun8i-a23-prcm"; - reg = <0x01f01400 0x200>; - - ar100: ar100_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "ar100"; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun8i-a23-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun8i-a23-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_timer", - "apb0_rsb", "apb0_uart", - "apb0_i2c"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - }; - - cpucfg@01f01c00 { - compatible = "allwinner,sun8i-a23-cpuconfig"; - reg = <0x01f01c00 0x300>; - }; - - r_uart: serial@01f02800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01f02800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb0_gates 4>; - resets = <&apb0_rst 4>; - status = "disabled"; - }; - - r_pio: pinctrl@01f02c00 { - compatible = "allwinner,sun8i-a23-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&apb0_gates 0>; - resets = <&apb0_rst 0>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <0>; - #gpio-cells = <3>; - - r_rsb_pins: r_rsb { - allwinner,pins = "PL0", "PL1"; - allwinner,function = "s_rsb"; - allwinner,drive = ; - allwinner,pull = ; - }; - - r_uart_pins_a: r_uart@0 { - allwinner,pins = "PL2", "PL3"; - allwinner,function = "s_uart"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - r_rsb: rsb@01f03400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>; - clock-frequency = <3000000>; - resets = <&apb0_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-evb.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-evb.dts deleted file mode 100644 index 610786e63..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-evb.dts +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright 2015 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Allwinner A23 Evaluation Board"; - compatible = "allwinner,sun8i-a23-evb", "allwinner,sun8i-a23"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &r_uart; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@190 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button@390 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - - button@600 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&pio { - mmc0_cd_pin_evb: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -/* - * The RX line has a non-populated resistance. In order to use it, you - * need to solder R207 on the back of the board in order to close the - * line and get a working UART. - */ -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts deleted file mode 100644 index e3c7a25ca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Allwinner GT90H Dual Core Tablet (v4)"; - compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3675"; - firmware-name = "gsl3675-gt90h.fw"; - touchscreen-size-x = <1792>; - touchscreen-size-y = <1024>; - status = "okay"; -}; - -&lradc { - button@600 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-inet86dz.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-inet86dz.dts deleted file mode 100644 index d4405752a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-inet86dz.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "INet-86DZ Rev 01"; - compatible = "primux,inet86dz", "allwinner,sun8i-a23"; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl1680"; - firmware-name = "gsl1680-inet86dz.fw"; - touchscreen-size-x = <960>; - touchscreen-size-y = <640>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts deleted file mode 120000 index c2f22fc33..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a23-q8-tablet.dts \ No newline at end of file diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts deleted file mode 120000 index c2f22fc33..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a23-q8-tablet.dts \ No newline at end of file diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts deleted file mode 100644 index a86cbedda..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Polaroid MID2407PXE03 tablet"; - compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; - - aliases { - ethernet0 = &esp8089; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_mid2407>; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&i2c1 { - mma7660: accelerometer@4c { - reg = <0x4c>; - compatible = "fsl,mma7660"; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; - -&mmc1_pins_a { - allwinner,pull = ; -}; - -&r_pio { - wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 { - allwinner,pins = "PL6"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_ldo_io1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-touchscreen"; - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl1680"; - firmware-name = "gsl1680-polaroid-mid2407pxe03.fw"; - touchscreen-size-x = <960>; - touchscreen-size-y = <640>; - touchscreen-inverted-x; - touchscreen-inverted-y; - vddio-supply = <®_ldo_io1>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts deleted file mode 100644 index 9955f85f9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Polaroid MID2809PXE04 tablet"; - compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; - - aliases { - ethernet0 = &esp8089; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_mid2809>; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; - -&mmc1_pins_a { - allwinner,pull = ; -}; - -&r_pio { - wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 { - allwinner,pins = "PL6"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3670"; - firmware-name = "gsl3670-polaroid-mid2809pxe04.fw"; - touchscreen-size-x = <1660>; - touchscreen-size-y = <890>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts deleted file mode 100644 index 956320a6c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun8i-a23.dtsi deleted file mode 100644 index 54d045dab..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a23.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-a23-a33.dtsi" - -/ { - memory { - reg = <0x40000000 0x40000000>; - }; -}; - -&ccu { - compatible = "allwinner,sun8i-a23-ccu"; -}; - -&pio { - compatible = "allwinner,sun8i-a23-pinctrl"; - interrupts = , - , - ; -}; - -&usb_otg { - compatible = "allwinner,sun6i-a31-musb"; -}; - -&usbphy { - compatible = "allwinner,sun8i-a23-usb-phy"; - reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; - reg-names = "phy_ctrl", "pmu1"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts deleted file mode 120000 index 4519fd791..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a33-q8-tablet.dts \ No newline at end of file diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts deleted file mode 100644 index f71159987..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "Allwinner GA10H Quad Core Tablet (v1.1)"; - compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; - - aliases { - /* Make u-boot set mac-address for rtl8703as (no eeprom) */ - ethernet0 = &rtl8703as; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&touchscreen { - reg = <0x40>; - compatible = "silead,gsl3675"; - firmware-name = "gsl3675-ga10h.fw"; - touchscreen-size-x = <1630>; - touchscreen-size-y = <990>; - touchscreen-inverted-y; - status = "okay"; -}; - -&lradc { - button@600 { - label = "Back"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_dldo1>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8703as: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts deleted file mode 100644 index fb4665576..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * Copyright 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - model = "INet-D978 Rev 02"; - compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart1; - }; - - chosen { - /* Delete debug UART as serial0 is the UART for bluetooth */ - /delete-property/stdout-path; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_d978>; - - home { - label = "d978:blue:home"; - gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - }; - }; -}; - -&mmc1_pins_a { - allwinner,pull = ; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_dldo1>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: sdio_wifi@1 { - reg = <1>; - }; -}; - -&r_pio { - led_pin_d978: led_pin_d978@0 { - allwinner,pins = "PL5"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_uart { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>, - <&uart1_pins_cts_rts_a>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts deleted file mode 120000 index 4519fd791..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a33-q8-tablet.dts \ No newline at end of file diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-olinuxino.dts deleted file mode 100644 index 9ea637e82..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright 2016 - Stefan Mavrodiev - * Olimex LTD. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Olimex A33-OLinuXino"; - compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_olinuxino>; - - green { - label = "a33-olinuxino:green:usr"; - gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - led_pin_olinuxino: led_pins@0 { - allwinner,pins = "PB7"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts deleted file mode 100644 index b0bc2360f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts deleted file mode 100644 index fef6abc0a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Sinlinx SinA33"; - compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_dcdc1>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191011>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <391304>; - }; - - button@600 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <600000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - allwinner,drive = ; - /* eMMC is missing pull-ups */ - allwinner,pull = ; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_sina33: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; - status = "okay"; -}; - -&usbphy { - status = "okay"; - usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun8i-a33.dtsi deleted file mode 100644 index fd1e1cddd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a33.dtsi +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-a23-a33.dtsi" - -/ { - cpus { - cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-a33-display-engine"; - allwinner,pipelines = <&fe0>; - status = "disabled"; - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - soc@01c00000 { - tcon0: lcd-controller@01c0c000 { - compatible = "allwinner,sun8i-a33-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_LCD>, - <&ccu CLK_LCD_CH0>; - clock-names = "ahb", - "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; - resets = <&ccu RST_BUS_LCD>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SS>; - reset-names = "ahb"; - }; - - fe0: display-frontend@01e00000 { - compatible = "allwinner,sun8i-a33-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, - <&ccu CLK_DRAM_DE_FE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_BUS_DE_FE>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@01e60000 { - compatible = "allwinner,sun8i-a33-display-backend"; - reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; - reg-names = "be", "sat"; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; - clock-names = "ahb", "mod", - "ram", "sat"; - resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; - reset-names = "be", "sat"; - assigned-clocks = <&ccu CLK_DE_BE>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - drc0: drc@01e70000 { - compatible = "allwinner,sun8i-a33-drc"; - reg = <0x01e70000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, - <&ccu CLK_DRAM_DRC>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_DRC>; - - assigned-clocks = <&ccu CLK_DRC>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - drc0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - drc0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_drc0>; - }; - }; - }; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun8i-a33-ccu"; -}; - -&pio { - compatible = "allwinner,sun8i-a33-pinctrl"; - interrupts = , - ; - - uart0_pins_b: uart0@1 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - -}; - -&usb_otg { - compatible = "allwinner,sun8i-a33-musb"; -}; - -&usbphy { - compatible = "allwinner,sun8i-a33-usb-phy"; - reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; - reg-names = "phy_ctrl", "pmu1"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts deleted file mode 100644 index 342e1d33f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2015 Vishnu Patekar - * Vishnu Patekar - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -/ { - model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; - compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts deleted file mode 100644 index 88b1e0970..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright 2015 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a83t.dtsi" - -/ { - model = "Cubietech Cubietruck Plus"; - compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t.dtsi deleted file mode 100644 index d3473f81b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-a83t.dtsi +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright 2015 Vishnu Patekar - * - * Vishnu Patekar - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - - */ - -#include "skeleton.dtsi" - -#include - -#include - -/ { - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - }; - - cpu@100 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x100>; - }; - - cpu@101 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x101>; - }; - - cpu@102 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x102>; - }; - - cpu@103 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x103>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* TODO: PRCM block has a mux for this. */ - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - /* - * This is called "internal OSC" in some places. - * It is an internal RC-based oscillator. - * TODO: Its controls are in the PRCM block. - */ - osc16M: osc16M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-output-names = "osc16M"; - }; - - osc16Md512: osc16Md512_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <512>; - clock-mult = <1>; - clocks = <&osc16M>; - clock-output-names = "osc16M-d512"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun8i-a83t-pinctrl"; - interrupts = , - , - ; - reg = <0x01c20800 0x400>; - clocks = <&osc24M>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_b: uart0@1 { - allwinner,pins = "PB9", "PB10"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - watchdog@01c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&osc24M>; - status = "disabled"; - }; - - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts deleted file mode 100644 index 06fddaae8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Banana Pi BPI-M2-Plus"; - compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_led_bpi_m2p>; - - pwr_led { - label = "bananapi-m2-plus:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_bpi_m2p>; - - sw4 { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_en_bpi_m2p>; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&r_pio { - pwr_led_bpi_m2p: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - sw_r_bpi_m2p: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - wifi_en_bpi_m2p: wifi_en_pin { - allwinner,pins = "PL7"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is on as long as VCC-IO is on */ - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts deleted file mode 100644 index 3d64cafc1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (C) 2016 James Pettigrew - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "FriendlyARM NanoPi NEO"; - compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - status { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - }; - }; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - leds_opc: led-pins { - allwinner,pins = "PA10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_pio { - leds_r_opc: led-pins { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts deleted file mode 100644 index e5bcaba3e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Xunlong Orange Pi 2"; - compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet1 = &rtl8189; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; - - sw2 { - label = "sw2"; - linux,code = ; - gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; - }; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_orangepi>; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189: sdio_wifi@1 { - reg = <1>; - }; -}; - -&pio { - leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_pio { - leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - sw_r_opc: key_pins@0 { - allwinner,pins = "PL3", "PL4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 { - allwinner,pins = "PL7"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usb1_vbus_pin_a { - allwinner,pins = "PG13"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts deleted file mode 100644 index 1550fee1e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Xunlong Orange Pi Lite"; - compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; - - aliases { - /* The H3 emac is not used so the wifi is ethernet0 */ - ethernet0 = &rtl8189ftv; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189ftv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&pio { - leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_pio { - leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - sw_r_opc: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts deleted file mode 100644 index 5c9b5bfa5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Xunlong Orange Pi One"; - compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_pio { - leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - sw_r_opc: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts deleted file mode 100644 index 851fd2c2c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The Orange Pi PC Plus is an extended version of the regular PC */ -#include "sun8i-h3-orangepi-pc.dts" - -/ { - model = "Xunlong Orange Pi PC Plus"; - compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; - - aliases { - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet1 = &rtl8189ftv; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189ftv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - allwinner,drive = ; - /* eMMC is missing pull-ups */ - allwinner,pull = ; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts deleted file mode 100644 index 3ec971285..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (C) 2015 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include - -/ { - model = "Xunlong Orange Pi PC"; - compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; - - pwr_led { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status_led { - label = "orangepi:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_pio { - leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - sw_r_opc: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -&usbphy { - /* USB VBUS is always on */ - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts deleted file mode 100644 index bb585918c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2015 Jens Kuske - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* The Orange Pi Plus is an extended version of the Orange Pi 2 */ -#include "sun8i-h3-orangepi-2.dts" - -/ { - model = "Xunlong Orange Pi Plus / Plus 2"; - compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_pin_a>; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - }; -}; - -&ehci3 { - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - allwinner,drive = ; - /* eMMC is missing pull-ups */ - allwinner,pull = ; -}; - -&pio { - usb3_vbus_pin_a: usb3_vbus_pin@0 { - allwinner,pins = "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&usbphy { - usb3_vbus-supply = <®_usb3_vbus>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts deleted file mode 100644 index 5851a47a3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2016 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The Orange Pi Plus 2E is an extended version of the Orange Pi PC Plus, - * with 2G RAM and an external gbit ethernet phy. - */ - -#include "sun8i-h3-orangepi-pc-plus.dts" - -/ { - model = "Xunlong Orange Pi Plus 2E"; - compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun8i-h3.dtsi deleted file mode 100644 index f4ba088b2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-h3.dtsi +++ /dev/null @@ -1,586 +0,0 @@ -/* - * Copyright (C) 2015 Jens Kuske - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" - -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - apb0: apb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01f01428 { - compatible = "allwinner,sun8i-h3-apb0-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01f01428 0x4>; - #clock-cells = <1>; - clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; - }; - - ir_clk: ir_clk@01f01454 { - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01f01454 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "ir"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun8i-h3-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-h3-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>, - <0x01c1c800 0x4>, - <0x01c1d800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci1: usb@01c1b000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@01c1b400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@01c1c000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@01c1c400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@01c1d000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1d000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@01c1d400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1d400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@01c20000 { - compatible = "allwinner,sun8i-h3-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun8i-h3-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = , - ; - clocks = <&ccu CLK_BUS_PIO>; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - i2c0_pins: i2c0 { - allwinner,pins = "PA11", "PA12"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins: i2c1 { - allwinner,pins = "PA18", "PA19"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins: i2c2 { - allwinner,pins = "PE12", "PE13"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin: mmc0_cd_pin@0 { - allwinner,pins = "PF6"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - allwinner,function = "mmc1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc2_8bit_pins: mmc2_8bit { - allwinner,pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PA4", "PA5"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_pins: uart1 { - allwinner,pins = "PG6", "PG7"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_rts_cts_pins: uart1_rts_cts { - allwinner,pins = "PG8", "PG9"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart2_pins: uart2 { - allwinner,pins = "PA0", "PA1"; - allwinner,function = "uart2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart3_pins: uart3 { - allwinner,pins = "PA13", "PA14"; - allwinner,function = "uart3"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - wdt0: watchdog@01c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - }; - - pwm: pwm@01c21400 { - compatible = "allwinner,sun8i-h3-pwm"; - reg = <0x01c21400 0x8>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - rtc: rtc@01f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupts = , - ; - }; - - apb0_reset: reset@01f014b0 { - reg = <0x01f014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - ir: ir@01f02000 { - compatible = "allwinner,sun5i-a13-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; - clock-names = "apb", "ir"; - resets = <&apb0_reset 1>; - interrupts = ; - reg = <0x01f02000 0x40>; - status = "disabled"; - }; - - r_pio: pinctrl@01f02c00 { - compatible = "allwinner,sun8i-h3-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&apb0_gates 0>; - resets = <&apb0_reset 0>; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - ir_pins_a: ir@0 { - allwinner,pins = "PL11"; - allwinner,function = "s_cir_rx"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-q8-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun8i-q8-common.dtsi deleted file mode 100644 index 29f837a47..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" -#include "sun8i-reference-design-tablet.dtsi" - -/ { - aliases { - serial0 = &r_uart; - /* Make u-boot set mac-address for wifi without an eeprom */ - ethernet0 = &sdio_wifi; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - /* - * Q8 boards use various PL# pins as wifi-en. On other boards - * these may be connected to a wifi module output pin. To avoid - * short-circuits we configure these as inputs with pull-ups via - * pinctrl, instead of listing them as active-low reset-gpios. - */ - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_q8>; - /* The esp8089 needs 200 ms after driving wifi-en high */ - post-power-on-delay-ms = <200>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: sdio_wifi@1 { - reg = <1>; - }; -}; - -&mmc1_pins_a { - allwinner,pull = ; -}; - -&r_pio { - wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 { - allwinner,pins = "PL6", "PL7", "PL11"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-r16-parrot.dts b/software/linux/kernel/arch/arm/boot/dts/sun8i-r16-parrot.dts deleted file mode 100644 index 47553e522..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright 2016 Quentin Schulz - * - * Quentin Schulz - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include - -/ { - model = "Allwinner R16 EVB (Parrot)"; - compatible = "allwinner,parrot", "allwinner,sun8i-a33"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_parrot>; - - led1 { - label = "parrot:led1:usr"; - gpio = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - }; - - led2 { - label = "parrot:led2:usr"; - gpio = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - }; - -}; - -&ehci0 { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - /* - * FIXME: An as-yet-unknown accelerometer is connected to this - * i2c bus. - */ -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button@0 { - label = "V+"; - linux,code = ; - channel = <0>; - voltage = <190000>; - }; - - button@1 { - label = "V-"; - linux,code = ; - channel = <0>; - voltage = <390000>; - }; - -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_parrot>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_parrot>; - vmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - allwinner,drive = ; - allwinner,pull = ; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_parrot: mmc0_cd_pin@0 { - allwinner,pins = "PD14"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_parrot: led_pins@0 { - allwinner,pins = "PE16", "PE17"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_det: usb0_id_detect_pin@0 { - allwinner,pins = "PD10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_parrot: usb1_vbus_pin@0 { - allwinner,pins = "PD12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_pio { - wifi_reset_pin_parrot: wifi_reset_pin@0 { - allwinner,pins = "PL6"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - /* - * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. - * Remove next line once it is possible to sync two regulators. - */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi0"; -}; - -®_dldo2 { - /* - * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered. - * Remove next line once it is possible to sync two regulators. - */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_dldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0-csi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -®_eldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-dsp"; -}; - -®_eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "eldo3"; -}; - -®_usb1_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_parrot>; - gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_det>; - usb0_vbus-supply = <®_drivevbus>; - usb0_id_det-gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_usb1_vbus>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi deleted file mode 100644 index 08cd00143..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" - -#include - -/ { - aliases { - serial0 = &r_uart; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - /* - * The gsl1680 is rated at 400KHz and it will not work reliable at - * 100KHz, this has been confirmed on multiple different q8 tablets. - * The gsl1680 is the only device on this bus. - */ - clock-frequency = <400000>; - - touchscreen: touchscreen@0 { - interrupt-parent = <&pio>; - interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_power_pin>; - power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - /* Tablet dts must provide reg and compatible */ - status = "disabled"; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&pio { - bl_en_pin: bl_en_pin@0 { - allwinner,pins = "PH6"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ts_power_pin: ts_power_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/software/linux/kernel/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts deleted file mode 100644 index 439847acd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ /dev/null @@ -1,406 +0,0 @@ -/* - * Copyright 2015 Tyler Baker - * - * Tyler Baker - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun9i-a80.dtsi" - -#include -#include - -/ { - model = "Cubietech Cubieboard4"; - compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard4>; - - green { - label = "cubieboard4:green:usr"; - gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */ - }; - - red { - label = "cubieboard4:red:usr"; - gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_cubieboard4>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ - cd-inverted; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - allwinner,drive = ; -}; - -&osc32k { - /* osc32k input is from AC100 */ - clocks = <&ac100_rtc 0>; -}; - -&pio { - led_pins_cubieboard4: led-pins@0 { - allwinner,pins = "PH6", "PH17"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 { - allwinner,pins = "PH18"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_ir { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp809: pmic@3a3 { - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_aldo1: aldo1 { - /* - * TODO: This should be handled by the - * USB PHY driver. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc33-usbh"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pb-io-cam"; - }; - - aldo3 { - /* unused */ - }; - - reg_dc5ldo: dc5ldo { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus-09-usbh"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; - }; - - reg_dcdc2: dcdc2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; - }; - - reg_dcdc4: dcdc4 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys-usb0-hdmi"; - }; - - reg_dcdc5: dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1425000>; - regulator-max-microvolt = <1575000>; - regulator-name = "vcc-dram"; - }; - - reg_dldo1: dldo1 { - /* - * The WiFi chip supports a wide range - * (3.0 ~ 4.8V) of voltages, and so does - * this regulator (3.0 ~ 4.2V), but - * Allwinner SDK always sets it to 3.3V. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_dldo2: dldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pl"; - }; - - reg_eldo1: eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dvdd-cam"; - }; - - reg_eldo2: eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pe"; - }; - - reg_eldo3: eldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pm-codec-io1"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa-gmac-2v5"; - }; - - reg_rtc_ldo: rtc_ldo { - regulator-name = "vcc-rtc-vdd1v8-io"; - }; - - sw { - /* unused */ - }; - }; - }; - - axp806: pmic@745 { - compatible = "x-powers,axp806"; - reg = <0x745>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - bldoin-supply = <®_dcdce>; - - regulators { - reg_s_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - aldo2 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo2"; - }; - - aldo3 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo3"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = "vcc18-efuse-adc-display-csi"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = - "vdd18-drampll-vcc18-pll-cpvdd"; - }; - - bldo3 { - /* unused */ - }; - - reg_bldo4: bldo4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vcc12-hsic"; - }; - - reg_cldo1: cldo1 { - /* - * This was 3V in the original design, but - * 3.3V is the recommended supply voltage - * for the Ethernet PHY. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-gmac-phy"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-cam"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io-wifi-codec-io2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-vpu"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - regulator-name = "vcc-bldo-codec-ldoin"; - }; - - sw { - /* - * unused, but use a different name to - * avoid name clash with axp809's sw - */ - regulator-name = "s_sw"; - }; - }; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp809.dtsi" - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun9i-a80-optimus.dts b/software/linux/kernel/arch/arm/boot/dts/sun9i-a80-optimus.dts deleted file mode 100644 index ceb6ef15d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ /dev/null @@ -1,495 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun9i-a80.dtsi" - -#include -#include - -/ { - model = "Merrii A80 Optimus Board"; - compatible = "merrii,a80-optimus", "allwinner,sun9i-a80"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_optimus>, <&led_r_pins_optimus>; - - /* The LED names match those found on the board */ - - led2 { - label = "optimus:led2:usr"; - gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; - }; - - led3 { - label = "optimus:led3:usr"; - gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */ - }; - - led4 { - label = "optimus:led4:usr"; - gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_optimus>; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_pin_optimus>; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - /* Enable if HSIC peripheral is connected */ - status = "disabled"; -}; - -&ehci2 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */ - cd-inverted; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - allwinner,drive = ; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&osc32k { - /* osc32k input is from AC100 */ - clocks = <&ac100_rtc 0>; -}; - -&pio { - led_pins_optimus: led-pins@0 { - allwinner,pins = "PH0", "PH1"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_optimus: mmc0_cd_pin@0 { - allwinner,pins = "PH18"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_optimus: usb1_vbus_pin@1 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb3_vbus_pin_optimus: usb3_vbus_pin@1 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - led_r_pins_optimus: led-pins@1 { - allwinner,pins = "PM15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&r_rsb { - status = "okay"; - - axp809: pmic@3a3 { - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_aldo1: aldo1 { - /* - * TODO: This should be handled by the - * USB PHY driver. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc33-usbh"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pb-io-cam"; - }; - - aldo3 { - /* unused */ - }; - - reg_dc5ldo: dc5ldo { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus-09-usbh"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; - }; - - reg_dcdc2: dcdc2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; - }; - - reg_dcdc4: dcdc4 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys-usb0-hdmi"; - }; - - reg_dcdc5: dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1425000>; - regulator-max-microvolt = <1575000>; - regulator-name = "vcc-dram"; - }; - - reg_dldo1: dldo1 { - /* - * The WiFi chip supports a wide range - * (3.0 ~ 4.8V) of voltages, and so does - * this regulator (3.0 ~ 4.2V), but - * Allwinner SDK always sets it to 3.3V. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_dldo2: dldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pl"; - }; - - reg_eldo1: eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dvdd-cam"; - }; - - reg_eldo2: eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pe"; - }; - - reg_eldo3: eldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pm-codec-io1"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa-gmac-2v5"; - }; - - reg_rtc_ldo: rtc_ldo { - regulator-name = "vcc-rtc-vdd1v8-io"; - }; - - sw { - /* unused */ - }; - }; - }; - - axp806: pmic@745 { - compatible = "x-powers,axp806"; - reg = <0x745>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - bldoin-supply = <®_dcdce>; - - regulators { - reg_s_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - aldo2 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo2"; - }; - - aldo3 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo3"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = "vcc18-efuse-adc-display-csi"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = - "vdd18-drampll-vcc18-pll-cpvdd"; - }; - - bldo3 { - /* unused */ - }; - - reg_bldo4: bldo4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vcc12-hsic"; - }; - - reg_cldo1: cldo1 { - /* - * This was 3V in the original design, but - * 3.3V is the recommended supply voltage - * for the Ethernet PHY. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-gmac-phy"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-cam"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io-wifi-codec-io2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-vpu"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - regulator-name = "vcc-bldo-codec-ldoin"; - }; - - sw { - /* - * unused, but use a different name to - * avoid name clash with axp809's sw - */ - regulator-name = "s_sw"; - }; - }; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp809.dtsi" - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy1 { - phy-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbphy2 { - phy-supply = <®_bldo4>; - /* Enable if HSIC peripheral is connected */ - status = "disabled"; -}; - -&usbphy3 { - phy-supply = <®_usb3_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sun9i-a80.dtsi b/software/linux/kernel/arch/arm/boot/dts/sun9i-a80.dtsi deleted file mode 100644 index 3c5214cbe..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sun9i-a80.dtsi +++ /dev/null @@ -1,933 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton64.dtsi" - -#include - -#include - -/ { - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x3>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0x103>; - }; - }; - - memory { - /* 8GB max. with LPAE */ - reg = <0 0x20000000 0x02 0>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - /* - * map 64 bit address range down to 32 bits, - * as the peripherals are all under 512MB. - */ - ranges = <0 0 0 0x20000000>; - - /* - * This clock is actually configurable from the PRCM address - * space. The external 24M oscillator can be turned off, and - * the clock switched to an internal 16M RC oscillator. Under - * normal operation there's no reason to do this, and the - * default is to use the external good one, so just model this - * as a fixed clock. Also it is not entirely clear if the - * osc24M mux in the PRCM affects the entire clock tree, which - * would also throw all the PLL clock rates off, or just the - * downstream clocks in the PRCM. - */ - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - /* - * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This serves as a placeholder for - * board dts files to specify the source. - */ - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "osc32k"; - }; - - usb_mod_clk: clk@00a08000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun9i-a80-usb-mod-clk"; - reg = <0x00a08000 0x4>; - clocks = <&ahb1_gates 1>; - clock-output-names = "usb0_ahb", "usb_ohci0", - "usb1_ahb", "usb_ohci1", - "usb2_ahb", "usb_ohci2"; - }; - - usb_phy_clk: clk@00a08004 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun9i-a80-usb-phy-clk"; - reg = <0x00a08004 0x4>; - clocks = <&ahb1_gates 1>; - clock-output-names = "usb_phy0", "usb_hsic1_480M", - "usb_phy1", "usb_hsic2_480M", - "usb_phy2", "usb_hsic_12M"; - }; - - pll3: clk@06000008 { - /* placeholder until implemented */ - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-rate = <0>; - clock-output-names = "pll3"; - }; - - pll4: clk@0600000c { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-pll4-clk"; - reg = <0x0600000c 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll12: clk@0600002c { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-pll4-clk"; - reg = <0x0600002c 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll12"; - }; - - gt_clk: clk@0600005c { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-gt-clk"; - reg = <0x0600005c 0x4>; - clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "gt"; - }; - - ahb0: clk@06000060 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-ahb-clk"; - reg = <0x06000060 0x4>; - clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "ahb0"; - }; - - ahb1: clk@06000064 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-ahb-clk"; - reg = <0x06000064 0x4>; - clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "ahb1"; - }; - - ahb2: clk@06000068 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-ahb-clk"; - reg = <0x06000068 0x4>; - clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "ahb2"; - }; - - apb0: clk@06000070 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-apb0-clk"; - reg = <0x06000070 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "apb0"; - }; - - apb1: clk@06000074 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-apb1-clk"; - reg = <0x06000074 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "apb1"; - }; - - cci400_clk: clk@06000078 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-gt-clk"; - reg = <0x06000078 0x4>; - clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "cci400"; - }; - - mmc0_clk: clk@06000410 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-mmc-clk"; - reg = <0x06000410 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "mmc0", "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@06000414 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-mmc-clk"; - reg = <0x06000414 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "mmc1", "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@06000418 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-mmc-clk"; - reg = <0x06000418 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "mmc2", "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@0600041c { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-mmc-clk"; - reg = <0x0600041c 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "mmc3", "mmc3_output", - "mmc3_sample"; - }; - - ahb0_gates: clk@06000580 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; - reg = <0x06000580 0x4>; - clocks = <&ahb0>; - clock-indices = <0>, <1>, <3>, - <5>, <8>, <12>, - <13>, <14>, - <15>, <16>, <18>, - <20>, <21>, <22>, - <23>; - clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu", - "ahb0_ss", "ahb0_sd", "ahb0_nand1", - "ahb0_nand0", "ahb0_sdram", - "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts", - "ahb0_spi0", "ahb0_spi1", "ahb0_spi2", - "ahb0_spi3"; - }; - - ahb1_gates: clk@06000584 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-ahb1-gates-clk"; - reg = <0x06000584 0x4>; - clocks = <&ahb1>; - clock-indices = <0>, <1>, - <17>, <21>, - <22>, <23>, - <24>; - clock-output-names = "ahb1_usbotg", "ahb1_usbhci", - "ahb1_gmac", "ahb1_msgbox", - "ahb1_spinlock", "ahb1_hstimer", - "ahb1_dma"; - }; - - ahb2_gates: clk@06000588 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-ahb2-gates-clk"; - reg = <0x06000588 0x4>; - clocks = <&ahb2>; - clock-indices = <0>, <1>, - <2>, <4>, <5>, - <7>, <8>, <11>; - clock-output-names = "ahb2_lcd0", "ahb2_lcd1", - "ahb2_edp", "ahb2_csi", "ahb2_hdmi", - "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi"; - }; - - apb0_gates: clk@06000590 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-apb0-gates-clk"; - reg = <0x06000590 0x4>; - clocks = <&apb0>; - clock-indices = <1>, <5>, - <11>, <12>, <13>, - <15>, <17>, <18>, - <19>; - clock-output-names = "apb0_spdif", "apb0_pio", - "apb0_ac97", "apb0_i2s0", "apb0_i2s1", - "apb0_lradc", "apb0_gpadc", "apb0_twd", - "apb0_cirtx"; - }; - - apb1_gates: clk@06000594 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-apb1-gates-clk"; - reg = <0x06000594 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <16>, <17>, - <18>, <19>, - <20>, <21>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_i2c3", "apb1_i2c4", - "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3", - "apb1_uart4", "apb1_uart5"; - }; - - cpus_clk: clk@08001410 { - compatible = "allwinner,sun9i-a80-cpus-clk"; - reg = <0x08001410 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>; - clock-output-names = "cpus"; - }; - - ahbs: ahbs_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&cpus_clk>; - clock-output-names = "ahbs"; - }; - - apbs: clk@0800141c { - compatible = "allwinner,sun8i-a23-apb0-clk"; - reg = <0x0800141c 0x4>; - #clock-cells = <0>; - clocks = <&ahbs>; - clock-output-names = "apbs"; - }; - - apbs_gates: clk@08001428 { - compatible = "allwinner,sun9i-a80-apbs-gates-clk"; - reg = <0x08001428 0x4>; - #clock-cells = <1>; - clocks = <&apbs>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <5>, - <6>, <7>, - <12>, <13>, - <16>, <17>, - <18>, <20>; - clock-output-names = "apbs_pio", "apbs_ir", - "apbs_timer", "apbs_rsb", - "apbs_uart", "apbs_1wire", - "apbs_i2c0", "apbs_i2c1", - "apbs_ps2_0", "apbs_ps2_1", - "apbs_dma", "apbs_i2s0", - "apbs_i2s1", "apbs_twd"; - }; - - r_1wire_clk: clk@08001450 { - reg = <0x08001450 0x4>; - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "r_1wire"; - }; - - r_ir_clk: clk@08001454 { - reg = <0x08001454 0x4>; - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "r_ir"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - /* - * map 64 bit address range down to 32 bits, - * as the peripherals are all under 512MB. - */ - ranges = <0 0 0 0x20000000>; - - ehci0: usb@00a00000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a00000 0x100>; - interrupts = ; - clocks = <&usb_mod_clk 1>; - resets = <&usb_mod_clk 17>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@00a00400 { - compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; - reg = <0x00a00400 0x100>; - interrupts = ; - clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>; - resets = <&usb_mod_clk 17>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy1: phy@00a00800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a00800 0x4>; - clocks = <&usb_phy_clk 1>; - clock-names = "phy"; - resets = <&usb_phy_clk 17>; - reset-names = "phy"; - status = "disabled"; - #phy-cells = <0>; - }; - - ehci1: usb@00a01000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a01000 0x100>; - interrupts = ; - clocks = <&usb_mod_clk 3>; - resets = <&usb_mod_clk 18>; - phys = <&usbphy2>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy2: phy@00a01800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a01800 0x4>; - clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, - <&usb_phy_clk 3>; - clock-names = "hsic_480M", "hsic_12M", "phy"; - resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; - reset-names = "hsic", "phy"; - status = "disabled"; - #phy-cells = <0>; - /* usb1 is always used with HSIC */ - phy_type = "hsic"; - }; - - ehci2: usb@00a02000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a02000 0x100>; - interrupts = ; - clocks = <&usb_mod_clk 5>; - resets = <&usb_mod_clk 19>; - phys = <&usbphy3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@00a02400 { - compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; - reg = <0x00a02400 0x100>; - interrupts = ; - clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>; - resets = <&usb_mod_clk 19>; - phys = <&usbphy3>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy3: phy@00a02800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a02800 0x4>; - clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>, - <&usb_phy_clk 5>; - clock-names = "hsic_480M", "hsic_12M", "phy"; - resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>; - reset-names = "hsic", "phy"; - status = "disabled"; - #phy-cells = <0>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>, - <&mmc0_clk 1>, <&mmc0_clk 2>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 0>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>, - <&mmc1_clk 1>, <&mmc1_clk 2>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 1>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>, - <&mmc2_clk 1>, <&mmc2_clk 2>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 2>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@01c12000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>, - <&mmc3_clk 1>, <&mmc3_clk 2>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 3>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc_config_clk: clk@01c13000 { - compatible = "allwinner,sun9i-a80-mmc-config-clk"; - reg = <0x01c13000 0x10>; - clocks = <&ahb0_gates 8>; - clock-names = "ahb"; - resets = <&ahb0_resets 8>; - reset-names = "ahb"; - #clock-cells = <1>; - #reset-cells = <1>; - clock-output-names = "mmc0_config", "mmc1_config", - "mmc2_config", "mmc3_config"; - }; - - gic: interrupt-controller@01c41000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c41000 0x1000>, - <0x01c42000 0x1000>, - <0x01c44000 0x2000>, - <0x01c46000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - ahb0_resets: reset@060005a0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005a0 0x4>; - }; - - ahb1_resets: reset@060005a4 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005a4 0x4>; - }; - - ahb2_resets: reset@060005a8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005a8 0x4>; - }; - - apb0_resets: reset@060005b0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005b0 0x4>; - }; - - apb1_resets: reset@060005b4 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005b4 0x4>; - }; - - timer@06000c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x06000c00 0xa0>; - interrupts = , - , - , - , - , - ; - - clocks = <&osc24M>; - }; - - wdt: watchdog@06000ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x06000ca0 0x20>; - interrupts = ; - }; - - pio: pinctrl@06000800 { - compatible = "allwinner,sun9i-a80-pinctrl"; - reg = <0x06000800 0x400>; - interrupts = , - , - , - , - ; - clocks = <&apb0_gates 5>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #size-cells = <0>; - #gpio-cells = <3>; - - i2c3_pins_a: i2c3@0 { - allwinner,pins = "PG10", "PG11"; - allwinner,function = "i2c3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins: mmc0 { - allwinner,pins = "PF0", "PF1" ,"PF2", "PF3", - "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc2_8bit_pins: mmc2_8bit { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC16"; - allwinner,function = "mmc2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PH12", "PH13"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart4_pins_a: uart4@0 { - allwinner,pins = "PG12", "PG13", "PG14", "PG15"; - allwinner,function = "uart4"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - uart0: serial@07000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 16>; - resets = <&apb1_resets 16>; - status = "disabled"; - }; - - uart1: serial@07000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 17>; - resets = <&apb1_resets 17>; - status = "disabled"; - }; - - uart2: serial@07000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 18>; - resets = <&apb1_resets 18>; - status = "disabled"; - }; - - uart3: serial@07000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 19>; - resets = <&apb1_resets 19>; - status = "disabled"; - }; - - uart4: serial@07001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07001000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 20>; - resets = <&apb1_resets 20>; - status = "disabled"; - }; - - uart5: serial@07001400 { - compatible = "snps,dw-apb-uart"; - reg = <0x07001400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 21>; - resets = <&apb1_resets 21>; - status = "disabled"; - }; - - i2c0: i2c@07002800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07002800 0x400>; - interrupts = ; - clocks = <&apb1_gates 0>; - resets = <&apb1_resets 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@07002c00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07002c00 0x400>; - interrupts = ; - clocks = <&apb1_gates 1>; - resets = <&apb1_resets 1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@07003000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003000 0x400>; - interrupts = ; - clocks = <&apb1_gates 2>; - resets = <&apb1_resets 2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@07003400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003400 0x400>; - interrupts = ; - clocks = <&apb1_gates 3>; - resets = <&apb1_resets 3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@07003800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003800 0x400>; - interrupts = ; - clocks = <&apb1_gates 4>; - resets = <&apb1_resets 4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_wdt: watchdog@08001000 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x08001000 0x20>; - interrupts = ; - }; - - apbs_rst: reset@080014b0 { - reg = <0x080014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - nmi_intc: interrupt-controller@080015a0 { - compatible = "allwinner,sun9i-a80-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x080015a0 0xc>; - interrupts = ; - }; - - r_ir: ir@08002000 { - compatible = "allwinner,sun5i-a13-ir"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_pins>; - clocks = <&apbs_gates 1>, <&r_ir_clk>; - clock-names = "apb", "ir"; - resets = <&apbs_rst 1>; - reg = <0x08002000 0x40>; - status = "disabled"; - }; - - r_uart: serial@08002800 { - compatible = "snps,dw-apb-uart"; - reg = <0x08002800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apbs_gates 4>; - resets = <&apbs_rst 4>; - status = "disabled"; - }; - - r_pio: pinctrl@08002c00 { - compatible = "allwinner,sun9i-a80-r-pinctrl"; - reg = <0x08002c00 0x400>; - interrupts = , - ; - clocks = <&apbs_gates 0>; - resets = <&apbs_rst 0>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - r_ir_pins: r_ir { - allwinner,pins = "PL6"; - allwinner,function = "s_cir_rx"; - allwinner,drive = ; - allwinner,pull = ; - }; - - r_rsb_pins: r_rsb { - allwinner,pins = "PN0", "PN1"; - allwinner,function = "s_rsb"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - r_rsb: i2c@08003400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x08003400 0x400>; - interrupts = ; - clocks = <&apbs_gates 3>; - clock-frequency = <3000000>; - resets = <&apbs_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/software/linux/kernel/arch/arm/boot/dts/sunxi-common-regulators.dtsi deleted file mode 100644 index f1953b0c5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ /dev/null @@ -1,150 +0,0 @@ -/* - * sunxi boards common regulator (ahci target power supply, usb-vbus) code - * - * Copyright 2014 - Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -&pio { - ahci_pwr_pin_a: ahci_pwr_pin@0 { - allwinner,pins = "PB8"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PB9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_a: usb1_vbus_pin@0 { - allwinner,pins = "PH6"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_a: usb2_vbus_pin@0 { - allwinner,pins = "PH3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -/ { - reg_ahci_5v: ahci-5v { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&ahci_pwr_pin_a>; - regulator-name = "ahci-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 1 8 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_vbus_pin_a>; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 1 9 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_a>; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_usb2_vbus: usb2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_a>; - regulator-name = "usb2-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_vcc3v0: vcc3v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sunxi-itead-core-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/sunxi-itead-core-common.dtsi deleted file mode 100644 index 2565d5137..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sunxi-itead-core-common.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright 2015 - Marcus Cooper - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sunxi-common-regulators.dtsi" - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/software/linux/kernel/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi deleted file mode 100644 index b8241462f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2015 Hans de Goede - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include "sunxi-common-regulators.dtsi" - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tango4-common.dtsi b/software/linux/kernel/arch/arm/boot/dts/tango4-common.dtsi deleted file mode 100644 index dd7eb5f62..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tango4-common.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Based on Mans Rullgard's Tango3 DT - * https://github.com/mansr/linux-tangox - */ - -#include - -#define CPU_CLK 0 -#define SYS_CLK 1 -#define USB_CLK 2 -#define SDIO_CLK 3 - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - periph_clk: periph_clk { - compatible = "fixed-factor-clock"; - clocks = <&clkgen CPU_CLK>; - clock-mult = <1>; - clock-div = <2>; - #clock-cells = <0>; - }; - - mpcore { - compatible = "simple-bus"; - ranges = <0x00000000 0x20000000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - - scu@0 { - compatible = "arm,cortex-a9-scu"; - reg = <0x0 0x100>; - }; - - twd@600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x600 0x10>; - interrupts = ; - clocks = <&periph_clk>; - always-on; - }; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, <0x100 0x100>; - }; - }; - - l2cc: l2-cache-controller@20100000 { - compatible = "arm,pl310-cache"; - reg = <0x20100000 0x1000>; - cache-level = <2>; - cache-unified; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&irq0>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - xtal: xtal { - compatible = "fixed-clock"; - clock-frequency = <27000000>; - #clock-cells = <0>; - }; - - clkgen: clkgen@10000 { - compatible = "sigma,tango4-clkgen"; - reg = <0x10000 0x100>; - clocks = <&xtal>; - #clock-cells = <1>; - }; - - tick-counter@10048 { - compatible = "sigma,tick-counter"; - reg = <0x10048 0x4>; - clocks = <&xtal>; - }; - - uart: serial@10700 { - compatible = "ralink,rt2880-uart"; - reg = <0x10700 0x30>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <7372800>; - reg-shift = <2>; - }; - - watchdog@1fd00 { - compatible = "sigma,smp8759-wdt"; - reg = <0x1fd00 8>; - clocks = <&xtal>; - }; - - eth0: ethernet@26000 { - compatible = "sigma,smp8734-ethernet"; - reg = <0x26000 0x800>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkgen SYS_CLK>; - }; - - intc: interrupt-controller@6e000 { - compatible = "sigma,smp8642-intc"; - reg = <0x6e000 0x400>; - ranges = <0 0x6e000 0x400>; - interrupt-parent = <&gic>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <1>; - - irq0: irq0@000 { - reg = <0x000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - irq1: irq1@100 { - reg = <0x100 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - irq2: irq2@300 { - reg = <0x300 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tango4-smp8758.dtsi b/software/linux/kernel/arch/arm/boot/dts/tango4-smp8758.dtsi deleted file mode 100644 index d2e65c46b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tango4-smp8758.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -#include "tango4-common.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "sigma,tango4-smp"; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - next-level-cache = <&l2cc>; - device_type = "cpu"; - reg = <0>; - clocks = <&clkgen CPU_CLK>; - clock-latency = <1>; - operating-points = <1215000 0 607500 0 405000 0 243000 0 135000 0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - next-level-cache = <&l2cc>; - device_type = "cpu"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-affinity = <&cpu0>, <&cpu1>; - interrupts = - , - ; - }; - - soc { - cpu_temp: thermal@920100 { - #thermal-sensor-cells = <0>; - compatible = "sigma,smp8758-thermal"; - reg = <0x920100 12>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <997>; /* milliseconds */ - polling-delay-passive = <499>; /* milliseconds */ - thermal-sensors = <&cpu_temp>; - trips { - cpu_critical { - temperature = <120000>; - hysteresis = <2500>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tango4-vantage-1172.dts b/software/linux/kernel/arch/arm/boot/dts/tango4-vantage-1172.dts deleted file mode 100644 index e3a51e353..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tango4-vantage-1172.dts +++ /dev/null @@ -1,36 +0,0 @@ -/dts-v1/; - -#include "tango4-smp8758.dtsi" - -/ { - model = "Sigma Designs SMP8758 Vantage-1172 Rev E1"; - compatible = "sigma,vantage-1172", "sigma,smp8758", "sigma,tango4"; - - aliases { - serial = &uart; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; /* 2 GB */ - }; - - chosen { - stdout-path = "serial:115200n8"; - }; -}; - -ð0 { - phy-connection-type = "rgmii-id"; - phy-handle = <ð0_phy>; - #address-cells = <1>; - #size-cells = <0>; - - /* Atheros AR8035 */ - eth0_phy: ethernet-phy@4 { - compatible = "ethernet-phy-id004d.d072", - "ethernet-phy-ieee802.3-c22"; - interrupts = <37 IRQ_TYPE_EDGE_RISING>; - reg = <4>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra114-dalmore.dts b/software/linux/kernel/arch/arm/boot/dts/tegra114-dalmore.dts deleted file mode 100644 index 1444fbd54..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra114-dalmore.dts +++ /dev/null @@ -1,1291 +0,0 @@ -/* - * This dts file supports Dalmore A04. - * Other board revisions are not supported - */ - -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "NVIDIA Tegra114 Dalmore evaluation board"; - compatible = "nvidia,dalmore", "nvidia,tegra114"; - - aliases { - rtc0 = "/i2c@7000d000/tps65913@58"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x80000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&vdd_hdmi_reg>; - pll-supply = <&palmas_smps3_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - dsi@54300000 { - status = "okay"; - - avdd-dsi-csi-supply = <&avdd_1v2_reg>; - - panel@0 { - compatible = "panasonic,vvx10f004b00", - "simple-panel"; - reg = <0>; - - power-supply = <&avdd_lcd_reg>; - backlight = <&backlight>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1", - "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0", - "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5", - "gmi_cs6_n_pi3", - "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6", - "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2", - "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1", - "dap3_sclk_pp3"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4", - "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb5", - "pbb6", - "pbb7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1", - "pcc2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad13_ph5", - "gmi_ad8_ph0", - "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2", - "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0", - "gmi_cs0_n_pj0", - "gmi_cs2_n_pk3", - "gmi_cs4_n_pk2", - "gmi_cs7_n_pi6", - "gmi_dqs_p_pj3", - "gmi_iordy_pi5", - "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3", - "kb_col6_pq6", - "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3", - "kb_row4_pr4", - "kb_row6_pr6", - "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5", - "pu6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2", - "usb_vbus_en1_pn5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - battery: smart-battery@b { - compatible = "ti,bq20z45", "sbs,sbs-battery"; - reg = <0xb>; - battery-name = "battery"; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <100>; - power-supplies = <&charger>; - }; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&palmas_ldo6_reg>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - tps51632@43 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1520000>; - regulator-boot-on; - regulator-always-on; - }; - - tps65090@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - interrupt-parent = <&gpio>; - interrupts = ; - - vsys1-supply = <&vdd_ac_bat_reg>; - vsys2-supply = <&vdd_ac_bat_reg>; - vsys3-supply = <&vdd_ac_bat_reg>; - infet1-supply = <&vdd_ac_bat_reg>; - infet2-supply = <&vdd_ac_bat_reg>; - infet3-supply = <&tps65090_dcdc2_reg>; - infet4-supply = <&tps65090_dcdc2_reg>; - infet5-supply = <&tps65090_dcdc2_reg>; - infet6-supply = <&tps65090_dcdc2_reg>; - infet7-supply = <&tps65090_dcdc2_reg>; - vsys-l1-supply = <&vdd_ac_bat_reg>; - vsys-l2-supply = <&vdd_ac_bat_reg>; - - charger: charger { - compatible = "ti,tps65090-charger"; - ti,enable-low-current-chrg; - }; - - regulators { - tps65090_dcdc1_reg: dcdc1 { - regulator-name = "vdd-sys-5v0"; - regulator-always-on; - regulator-boot-on; - }; - - tps65090_dcdc2_reg: dcdc2 { - regulator-name = "vdd-sys-3v3"; - regulator-always-on; - regulator-boot-on; - }; - - tps65090_dcdc3_reg: dcdc3 { - regulator-name = "vdd-ao"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_bl_reg: fet1 { - regulator-name = "vdd-lcd-bl"; - }; - - fet3 { - regulator-name = "vdd-modem-3v3"; - }; - - avdd_lcd_reg: fet4 { - regulator-name = "avdd-lcd"; - }; - - fet5 { - regulator-name = "vdd-lvds"; - }; - - fet6 { - regulator-name = "vdd-sd-slot"; - regulator-always-on; - regulator-boot-on; - }; - - fet7 { - regulator-name = "vdd-com-3v3"; - }; - - ldo1 { - regulator-name = "vdd-sby-5v0"; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "vdd-sby-3v3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - palmas: tps65913@58 { - compatible = "ti,palmas"; - reg = <0x58>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - smps1-in-supply = <&tps65090_dcdc3_reg>; - smps3-in-supply = <&tps65090_dcdc3_reg>; - smps4-in-supply = <&tps65090_dcdc2_reg>; - smps7-in-supply = <&tps65090_dcdc2_reg>; - smps8-in-supply = <&tps65090_dcdc2_reg>; - smps9-in-supply = <&tps65090_dcdc2_reg>; - ldo1-in-supply = <&tps65090_dcdc2_reg>; - ldo2-in-supply = <&tps65090_dcdc2_reg>; - ldo3-in-supply = <&palmas_smps3_reg>; - ldo4-in-supply = <&tps65090_dcdc2_reg>; - ldo5-in-supply = <&vdd_ac_bat_reg>; - ldo6-in-supply = <&tps65090_dcdc2_reg>; - ldo7-in-supply = <&tps65090_dcdc2_reg>; - ldo8-in-supply = <&tps65090_dcdc3_reg>; - ldo9-in-supply = <&palmas_smps9_reg>; - ldoln-in-supply = <&tps65090_dcdc1_reg>; - ldousb-in-supply = <&tps65090_dcdc1_reg>; - - regulators { - smps12 { - regulator-name = "vddio-ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas_smps3_reg: smps3 { - regulator-name = "vddio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45 { - regulator-name = "vdd-core"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps457 { - regulator-name = "vdd-core"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8 { - regulator-name = "avdd-pll"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas_smps9_reg: smps9 { - regulator-name = "sdhci-vdd-sd-slot"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo1 { - regulator-name = "avdd-cam1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo2 { - regulator-name = "avdd-cam2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - avdd_1v2_reg: ldo3 { - regulator-name = "avdd-dsi-csi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo4 { - regulator-name = "vpp-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - palmas_ldo6_reg: ldo6 { - regulator-name = "vdd-sensor-2v85"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo7 { - regulator-name = "vdd-af-cam1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo8 { - regulator-name = "vdd-rtc"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - ti,enable-ldo8-tracking; - }; - - ldo9 { - regulator-name = "vddio-sdmmc-2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln { - regulator-name = "hvdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldousb { - regulator-name = "avdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen1 { - regulator-name = "rail-3v3"; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen2 { - regulator-name = "rail-5v0"; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@0 { - compatible = "winbond,w25q32dw"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - sdhci@78000400 { - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - status = "okay"; - }; - - sdhci@78000600 { - bus-width = <8>; - status = "okay"; - non-removable; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&usb3_vbus_reg>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - home { - label = "Home"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume_down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - dvdd_ts_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "dvdd_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - usb3_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - vdd_hdmi_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_hdmi_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - vdd_cam_1v8_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd_cam_1v8_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&palmas_gpio 6 0>; - }; - - vdd_5v0_hdmi: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&tps65090_dcdc1_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-dalmore", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Dalmore"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Speakers", "SPORP", - "Speakers", "SPORN", - "Speakers", "SPOLP", - "Speakers", "SPOLN", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA114_CLK_PLL_A>, - <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA114_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra114-roth.dts b/software/linux/kernel/arch/arm/boot/dts/tegra114-roth.dts deleted file mode 100644 index 966a7fc04..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra114-roth.dts +++ /dev/null @@ -1,1126 +0,0 @@ -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "NVIDIA SHIELD"; - compatible = "nvidia,roth", "nvidia,tegra114"; - - chosen { - /* SHIELD's bootloader's arguments need to be overridden */ - bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; - /* SHIELD's bootloader will place initrd at this address */ - linux,initrd-start = <0x82000000>; - linux,initrd-end = <0x82800000>; - }; - - aliases { - serial0 = &uartd; - }; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory { - /* memory >= 0x79600000 is reserved for firmware usage */ - reg = <0x80000000 0x79600000>; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - vdd-supply = <&vdd_1v2_ap>; - - panel@0 { - compatible = "lg,lh500wx1-sd03"; - reg = <0>; - - power-supply = <&vdd_lcd>; - backlight = <&backlight>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1", - "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0", - "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5", - "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6", - "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs6_n_pi13 { - nvidia,pins = "gmi_cs6_n_pi3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2", - "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_cd_n_pv2", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2", - "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs0_n_pj0 { - nvidia,pins = "gmi_cs0_n_pj0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4", - "gpio_x5_aud_px5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_din_pp1", - "dap3_dout_pp2", - "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb5", - "pbb6", - "pbb7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1", - "pcc2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad12_ph4", - "gmi_ad15_ph7", - "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3", - "gmi_ad13_ph5", - "gmi_ad8_ph0", - "gmi_clk_pk1", - "gmi_cs2_n_pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6", - "gmi_cs0_n_pj0", - "gmi_cs4_n_pk2", - "gmi_cs7_n_pi6", - "gmi_dqs_p_pj3", - "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2", - "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6", - "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3", - "kb_row4_pr4", - "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - /* Usable on reworked devices only */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - regulator@43 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1520000>; - regulator-always-on; - regulator-boot-on; - }; - - palmas: pmic@58 { - compatible = "ti,palmas"; - reg = <0x58>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - - regulators { - smps12 { - regulator-name = "vdd-ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8: smps3 { - regulator-name = "vdd-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - smps457 { - regulator-name = "vdd-soc"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8 { - regulator-name = "avdd-pll-1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9 { - regulator-name = "vdd-2v85-emmc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - smps10_out1 { - regulator-name = "vdd-fan"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out2 { - regulator-name = "vdd-5v0-sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "vdd-2v8-display"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v2_ap: ldo3 { - regulator-name = "avdd-1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4 { - regulator-name = "vpp-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5 { - regulator-name = "avdd-hdmi-pll"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo6 { - regulator-name = "vdd-sensor-2v8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo8 { - regulator-name = "vdd-rtc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - ti,enable-ldo8-tracking; - }; - - vddio_sdmmc3: ldo9 { - regulator-name = "vddio-sdmmc3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldousb { - regulator-name = "avdd-usb-hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regen1 { - regulator-name = "rail-3v3"; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - regen2 { - regulator-name = "rail-5v0"; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - }; - - /* SD card */ - sdhci@78000400 { - status = "okay"; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - /* External USB port (must be powered) */ - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - interrupts = ; - /* Should be changed to "otg" once we have vbus_supply */ - /* As of now, USB devices need to be powered externally */ - dr_mode = "host"; - }; - - /* SHIELD controller */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 1 40000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <&lcd_bl_en>; - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - back { - label = "Back"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - lcd_bl_en: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "lcd_bl_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vdd_lcd: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_lcd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v8_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_3v3_ts"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_1v8_com"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_3v3_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_sys>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra114-tn7.dts b/software/linux/kernel/arch/arm/boot/dts/tegra114-tn7.dts deleted file mode 100644 index a161fa1df..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra114-tn7.dts +++ /dev/null @@ -1,351 +0,0 @@ -/dts-v1/; - -#include -#include "tegra114.dtsi" - -/ { - model = "Tegra Note 7"; - compatible = "nvidia,tn7", "nvidia,tegra114"; - - chosen { - /* TN7's bootloader's arguments need to be overridden */ - bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; - /* TN7's bootloader will place initrd at this address */ - linux,initrd-start = <0x82000000>; - linux,initrd-end = <0x82800000>; - }; - - aliases { - serial0 = &uartd; - }; - - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - - memory { - /* memory >= 0x37e00000 is reserved for firmware usage */ - reg = <0x80000000 0x37e00000>; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - vdd-supply = <&vdd_1v2_ap>; - - panel@0 { - compatible = "lg,ld070wx3-sl01"; - reg = <0>; - - power-supply = <&vdd_lcd>; - backlight = <&backlight>; - }; - }; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - palmas: pmic@58 { - compatible = "ti,palmas"; - reg = <0x58>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pmic { - compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; - - ldoln-in-supply = <&vdd_smps10_out2>; - - regulators { - smps123 { - regulator-name = "vd-cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45 { - regulator-name = "vd-soc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6 { - regulator-name = "va-lcd-hv"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7 { - regulator-name = "vd-ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8: smps8 { - regulator-name = "vs-pmu-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_2v9_sys: smps9 { - regulator-name = "vs-sys-2v9"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_smps10_out1: smps10_out1 { - regulator-name = "vd-smps10-out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_smps10_out2: smps10_out2 { - regulator-name = "vd-smps10-out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1 { - regulator-name = "va-pllx"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v2_ap: ldo2 { - regulator-name = "va-ap-1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3 { - regulator-name = "vd-fuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4 { - regulator-name = "vd-ts-hv"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo5 { - regulator-name = "va-cam2-hv"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo6 { - regulator-name = "va-sns-hv"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo7 { - regulator-name = "va-cam1-hv"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - ldo8 { - regulator-name = "va-ap-rtc"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - ti,enable-ldo8-tracking; - regulator-always-on; - regulator-boot-on; - }; - - ldo9 { - regulator-name = "vi-sdcard"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - ldousb { - regulator-name = "avdd-usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln { - regulator-name = "va-hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - }; - - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - nvidia,xcvr-setup = <7>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - interrupts = ; - /* Should be changed to "otg" once we have vbus_supply */ - /* As of now, USB devices need to be powered externally */ - dr_mode = "host"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 1 40000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <&lcd_bl_en>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume_down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - /* FIXME: output of BQ24192 */ - vs_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VS_SYS"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - regulator-boot-on; - }; - - lcd_bl_en: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_LCD_BL"; - regulator-min-microvolt = <16500000>; - regulator-max-microvolt = <16500000>; - gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vs_sys>; - regulator-boot-on; - }; - - vdd_lcd: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "VD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_1v8>; - regulator-boot-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra114.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra114.dtsi deleted file mode 100644 index 8932ea3af..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra114.dtsi +++ /dev/null @@ -1,787 +0,0 @@ -#include -#include -#include -#include -#include - -#include "skeleton.dtsi" - -/ { - compatible = "nvidia,tegra114"; - interrupt-parent = <&lic>; - - host1x@50000000 { - compatible = "nvidia,tegra114-host1x", "simple-bus"; - reg = <0x50000000 0x00028000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA114_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x01000000>; - - gr2d@54140000 { - compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; - }; - - dc@54200000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_DISP1>, - <&tegra_car TEGRA114_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_DISP2>, - <&tegra_car TEGRA114_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - - rgb { - status = "disabled"; - }; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra114-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_HDMI>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - dsi@54300000 { - compatible = "nvidia,tegra114-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_DSIA>, - <&tegra_car TEGRA114_CLK_DSIALP>, - <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - dsi@54400000 { - compatible = "nvidia,tegra114-dsi"; - reg = <0x54400000 0x00040000>; - clocks = <&tegra_car TEGRA114_CLK_DSIB>, - <&tegra_car TEGRA114_CLK_DSIBLP>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 82>; - reset-names = "dsi"; - nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x50041000 0x1000>, - <0x50042000 0x1000>, - <0x50044000 0x2000>, - <0x50046000 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>, - <0x60004400 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA114_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra114-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra114-apbdma"; - reg = <0x6000a000 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA114_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb: ahb@6000c000 { - compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; - reg = <0x6000c000 0x150>; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - /* - gpio-ranges = <&pinmux 0 0 246>; - */ - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra114-pinmux"; - reg = <0x70000868 0x148 /* Pad control registers */ - 0x70003000 0x40c>; /* Mux registers */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA114_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c700 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000d000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000dc00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC5>; - clock-names = "spi"; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000de00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA114_CLK_SBC6>; - clock-names = "spi"; - resets = <&tegra_car 105>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_RTC>; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra114-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra114-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra114-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA114_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra114-mc"; - reg = <0x70019000 0x1000>; - clocks = <&tegra_car TEGRA114_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - }; - - ahub@70080000 { - compatible = "nvidia,tegra114-ahub"; - reg = <0x70080000 0x200>, - <0x70080200 0x100>, - <0x70081000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, - <&tegra_car TEGRA114_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>, /* spdif */ - <&tegra_car 153>, /* amx */ - <&tegra_car 154>; /* adx */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif", "amx", "adx"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>, - <&apbdma 6>, <&apbdma 6>, - <&apbdma 7>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 12>, - <&apbdma 13>, <&apbdma 13>, - <&apbdma 14>, <&apbdma 14>, - <&apbdma 29>, <&apbdma 29>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", - "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", - "rx9", "tx9"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - tegra_i2s0: i2s@70080300 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080300 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA114_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70080400 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080400 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA114_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70080500 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080500 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA114_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70080600 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080600 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA114_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70080700 { - compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; - reg = <0x70080700 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA114_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - mipi: mipi@700e3000 { - compatible = "nvidia,tegra114-mipi"; - reg = <0x700e3000 0x100>; - clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; - #nvidia,mipi-calibrate-cells = <1>; - }; - - sdhci@78000000 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000200 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000400 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000600 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - usb@7d000000 { - compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USBD>, - <&tegra_car TEGRA114_CLK_PLL_U>, - <&tegra_car TEGRA114_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA114_CLK_USB3>, - <&tegra_car TEGRA114_CLK_PLL_U>, - <&tegra_car TEGRA114_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - interrupt-parent = <&gic>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis-emc.dtsi deleted file mode 100644 index ca2c3a557..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ /dev/null @@ -1,1502 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-924000000 { - clock-frequency = <924000000>; - nvidia,parent-clock-frequency = <924000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - emc@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 0x00000003 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000060 - 0x00000000 0x00000018 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000007 0x0000000f - 0x00000005 0x00000005 - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x00000064 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000007 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 0x00000005 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x0000009a - 0x00000000 0x00000026 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000007 0x0000000f - 0x00000006 0x00000006 - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x000000a0 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x0000000b 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 0x0000000a - 0x00000000 0x00000001 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000134 - 0x00000000 0x0000004d - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000008 0x0000000f - 0x0000000c 0x0000000c - 0x00000004 0x00000005 - 0x00000004 0x00000000 - 0x00000000 0x00000005 - 0x00000005 0x0000013f - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000015 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 0x00000011 - 0x00000000 0x00000002 - 0x00000000 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000000 - 0x00000000 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000202 - 0x00000000 0x00000080 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x0000000f 0x0000000f - 0x00000013 0x00000013 - 0x00000004 0x00000005 - 0x00000004 0x00000001 - 0x00000000 0x00000005 - 0x00000005 0x00000213 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000022 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 0x0000001a - 0x00000000 0x00000003 - 0x00000001 0x00000004 - 0x0000000a 0x00000005 - 0x0000000b 0x00000001 - 0x00000001 0x00000003 - 0x00000003 0x00000000 - 0x00000006 0x00000006 - 0x00000006 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000004 - 0x0000000c 0x0000000d - 0x0000000f 0x00000304 - 0x00000000 0x000000c1 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000018 0x0000000f - 0x0000001c 0x0000001c - 0x00000004 0x00000005 - 0x00000004 0x00000002 - 0x00000000 0x00000005 - 0x00000005 0x0000031c - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x000fc000 0x000fc000 - 0x000fc000 0x000fc000 - 0x0000fc00 0x0000fc00 - 0x0000fc00 0x0000fc00 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000e0e 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000033 0x00000000 - 0x00000042 0x000e000e - 0x00000000 0x00000003 - 0x0000f2f3 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008cd>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 0x00000035 - 0x00000000 0x00000006 - 0x00000002 0x00000005 - 0x0000000a 0x00000005 - 0x0000000b 0x00000002 - 0x00000002 0x00000003 - 0x00000003 0x00000000 - 0x00000005 0x00000005 - 0x00000006 0x00000002 - 0x00000000 0x00000004 - 0x00000006 0x00010000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000003 - 0x0000000d 0x0000000f - 0x00000011 0x00000607 - 0x00000000 0x00000181 - 0x00000002 0x00000002 - 0x00000001 0x00000000 - 0x00000032 0x0000000f - 0x00000038 0x00000038 - 0x00000004 0x00000005 - 0x00000004 0x00000006 - 0x00000000 0x00000005 - 0x00000005 0x00000638 - 0x00000000 0x00000000 - 0x00000000 0x106aa298 - 0x002c00a0 0x00008000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00080000 0x00080000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00008000 0x00000000 - 0x00000000 0x00008000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00090000 0x00090000 - 0x00090000 0x00090000 - 0x00009000 0x00009000 - 0x00009000 0x00009000 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000707 0x81f1f108 - 0x07070004 0x0000003f - 0x016eeeee 0x51451400 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000066 0x00000000 - 0x00000100 0x000e000e - 0x00000000 0x00000003 - 0x0000d2b3 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0173000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d 0x0000004d - 0x00000000 0x00000009 - 0x00000003 0x00000004 - 0x00000008 0x00000002 - 0x00000009 0x00000003 - 0x00000003 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000005 0x00000002 - 0x00000000 0x00000002 - 0x00000007 0x00020000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x0000000e 0x00000010 - 0x00000012 0x000008e4 - 0x00000000 0x00000239 - 0x00000001 0x00000008 - 0x00000001 0x00000000 - 0x0000004b 0x0000000e - 0x00000052 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000008 - 0x00000000 0x00000005 - 0x00000005 0x00000924 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0x002c00a0 0x00008000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00098000 0x00098000 - 0x00000000 0x00098000 - 0x00098000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00050000 0x00050000 - 0x00050000 0x00050000 - 0x00005000 0x00005000 - 0x00005000 0x00005000 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x00000096 0x00000000 - 0x00000100 0x0173000e - 0x00000000 0x00000003 - 0x000052a3 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 0x00000066 - 0x00000000 0x0000000c - 0x00000004 0x00000004 - 0x00000008 0x00000002 - 0x0000000a 0x00000004 - 0x00000004 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000005 0x00000002 - 0x00000000 0x00000001 - 0x00000008 0x00020000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000f 0x00000010 - 0x00000012 0x00000bd1 - 0x00000000 0x000002f4 - 0x00000001 0x00000008 - 0x00000001 0x00000000 - 0x00000063 0x0000000f - 0x0000006c 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x0000000b - 0x00000000 0x00000005 - 0x00000005 0x00000c11 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0x002c00a0 0x00008000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00030000 0x00030000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00070000 0x00070000 - 0x00000000 0x00070000 - 0x00070000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00038000 0x00038000 - 0x00038000 0x00038000 - 0x00003800 0x00003800 - 0x00003800 0x00003800 - 0x10000280 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc081 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0000003f - 0x000000c6 0x00000000 - 0x00000100 0x015b000e - 0x00000000 0x00000003 - 0x000052a3 0x8000188b - 0x00000009 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x0139000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 0x00000088 - 0x00000000 0x00000010 - 0x00000006 0x00000006 - 0x00000009 0x00000002 - 0x0000000d 0x00000006 - 0x00000006 0x00000002 - 0x00000002 0x00000000 - 0x00000003 0x00000003 - 0x00000006 0x00000002 - 0x00000000 0x00000001 - 0x00000009 0x00030000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000010 0x00000012 - 0x00000014 0x00000fd6 - 0x00000000 0x000003f5 - 0x00000002 0x0000000b - 0x00000001 0x00000000 - 0x00000085 0x00000012 - 0x00000090 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000010 - 0x00000000 0x00000006 - 0x00000006 0x00001017 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe01200b1 0x00008000 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00054000 0x00054000 - 0x00000000 0x00054000 - 0x00054000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x0000000c 0x0000000c - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x0139000e - 0x00000000 0x00000003 - 0x000042a0 0x80002062 - 0x0000000a - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0127000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001b 0x0000009b - 0x00000000 0x00000013 - 0x00000007 0x00000007 - 0x0000000b 0x00000003 - 0x00000010 0x00000007 - 0x00000007 0x00000002 - 0x00000002 0x00000000 - 0x00000005 0x00000005 - 0x0000000a 0x00000002 - 0x00000000 0x00000003 - 0x0000000b 0x00070000 - 0x00000003 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000002 - 0x00000012 0x00000016 - 0x00000018 0x00001208 - 0x00000000 0x00000482 - 0x00000002 0x0000000d - 0x00000001 0x00000000 - 0x00000097 0x00000015 - 0x000000a3 0x00000200 - 0x00000004 0x00000005 - 0x00000004 0x00000013 - 0x00000000 0x00000006 - 0x00000006 0x00001248 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe00e00b1 0x00008000 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00048000 0x00048000 - 0x00000000 0x00048000 - 0x00048000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x0000000d 0x0000000d - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000505 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x51451420 - 0x00514514 0x00514514 - 0x51451400 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x0127000e - 0x00000000 0x00000003 - 0x000040a0 0x800024aa - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f7000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000024 0x000000cd - 0x00000000 0x00000019 - 0x0000000a 0x00000008 - 0x0000000d 0x00000004 - 0x00000013 0x0000000a - 0x0000000a 0x00000004 - 0x00000002 0x00000000 - 0x00000006 0x00000006 - 0x0000000b 0x00000002 - 0x00000000 0x00000002 - 0x0000000d 0x00080000 - 0x00000004 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x00000014 0x00000018 - 0x0000001a 0x000017e2 - 0x00000000 0x000005f8 - 0x00000003 0x00000011 - 0x00000001 0x00000000 - 0x000000c7 0x00000018 - 0x000000d7 0x00000200 - 0x00000005 0x00000006 - 0x00000005 0x00000019 - 0x00000000 0x00000008 - 0x00000008 0x00001822 - 0x00000000 0x00000000 - 0x00000000 0x104ab098 - 0xe00700b1 0x00008000 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x007fc008 0x007fc008 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00034000 0x00034000 - 0x00000000 0x00034000 - 0x00034000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x00000005 0x00000005 - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x0000000a 0x0000000a - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000000 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x61861820 - 0x00514514 0x00514514 - 0x61861800 0x0606003f - 0x00000000 0x00000000 - 0x00000100 0x00f7000e - 0x00000000 0x00000004 - 0x00004080 0x80003012 - 0x0000000f - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emc-auto-cal-config = <0xa1430303>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200020>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000f15>; - nvidia,emc-mrs-wait-cnt = <0x00cd000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x0000004c>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000002b 0x000000f0 - 0x00000000 0x0000001e - 0x0000000b 0x00000009 - 0x0000000f 0x00000005 - 0x00000016 0x0000000b - 0x0000000b 0x00000004 - 0x00000002 0x00000000 - 0x00000007 0x00000007 - 0x0000000d 0x00000002 - 0x00000000 0x00000002 - 0x0000000f 0x000a0000 - 0x00000004 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000001 - 0x00000016 0x0000001a - 0x0000001c 0x00001be7 - 0x00000000 0x000006f9 - 0x00000004 0x00000015 - 0x00000001 0x00000000 - 0x000000e7 0x0000001b - 0x000000fb 0x00000200 - 0x00000006 0x00000007 - 0x00000006 0x0000001e - 0x00000000 0x0000000a - 0x0000000a 0x00001c28 - 0x00000000 0x00000000 - 0x00000000 0x104ab898 - 0xe00400b1 0x00008000 - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x007f800a 0x007f800a - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x0002c000 0x0002c000 - 0x00000000 0x0002c000 - 0x0002c000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000000 0x00000000 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000004 0x00000004 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x00000008 0x00000008 - 0x100002a0 0x00000000 - 0x00111111 0x00000000 - 0x00000000 0x77ffc085 - 0x00000000 0x81f1f108 - 0x07070004 0x00000000 - 0x016eeeee 0x5d75d720 - 0x00514514 0x00514514 - 0x5d75d700 0x0606003f - 0x00000000 0x00000000 - 0x00000128 0x00cd000e - 0x00000000 0x00000004 - 0x00004080 0x800037ea - 0x00000011 - >; - }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 0x8000000a - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x77e30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 0x80000012 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x76230303 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 0x80000017 - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74a30303 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 0x8000001e - 0x00000001 0x00000001 - 0x00000002 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0502 - 0x74230403 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 0x80000026 - 0x00000001 0x00000001 - 0x00000003 0x00000000 - 0x00000002 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000003 0x00000006 - 0x06030203 0x000a0503 - 0x73c30504 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 0x80000040 - 0x00000001 0x00000001 - 0x00000004 0x00000002 - 0x00000003 0x00000001 - 0x00000003 0x00000008 - 0x00000003 0x00000002 - 0x00000004 0x00000006 - 0x06040203 0x000a0504 - 0x73840a05 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 0x80000040 - 0x00000001 0x00000002 - 0x00000007 0x00000004 - 0x00000004 0x00000001 - 0x00000002 0x00000007 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000b0607 - 0x77450e08 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 0x80000040 - 0x00000001 0x00000002 - 0x00000009 0x00000005 - 0x00000006 0x00000001 - 0x00000002 0x00000008 - 0x00000002 0x00000002 - 0x00000004 0x00000006 - 0x06040202 0x000d0709 - 0x7586120a 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 0x80000040 - 0x00000002 0x00000003 - 0x0000000c 0x00000007 - 0x00000008 0x00000001 - 0x00000002 0x00000009 - 0x00000002 0x00000002 - 0x00000005 0x00000006 - 0x06050202 0x0010090c - 0x7428180d 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 0x80000040 - 0x00000003 0x00000004 - 0x0000000e 0x00000009 - 0x0000000a 0x00000001 - 0x00000003 0x0000000b - 0x00000002 0x00000002 - 0x00000005 0x00000007 - 0x07050202 0x00130b0e - 0x73a91b0f 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b 0x80000040 - 0x00000004 0x00000005 - 0x00000013 0x0000000c - 0x0000000d 0x00000002 - 0x00000003 0x0000000c - 0x00000002 0x00000002 - 0x00000006 0x00000008 - 0x08060202 0x00170e13 - 0x736c2414 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d 0x80000040 - 0x00000005 0x00000006 - 0x00000016 0x0000000e - 0x0000000f 0x00000002 - 0x00000004 0x0000000e - 0x00000002 0x00000002 - 0x00000006 0x00000009 - 0x09060202 0x001a1016 - 0x734e2a17 0x70000f02 - 0x001f0000 - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis-eval.dts b/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis-eval.dts deleted file mode 100644 index 653044a44..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include "tegra124-apalis.dtsi" - -/ { - model = "Toradex Apalis TK1 on Apalis Evaluation Board"; - compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1", - "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/pmic@40"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie-controller@01003000 { - pci@1,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - /* Apalis UART1 */ - serial@70006000 { - status = "okay"; - }; - - /* Apalis UART2 */ - serial@70006040 { - status = "okay"; - }; - - /* Apalis UART3 */ - serial@70006200 { - status = "okay"; - }; - - /* Apalis UART4 */ - serial@70006300 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; - }; - - /* - * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) - */ - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* - * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor - * on carrier board) - */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* I2C4 (DDC): unused */ - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <50000000>; - - spidev0: spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - /* SPI4: Apalis SPI2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <50000000>; - - spidev1: spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - /* Apalis Serial ATA */ - sata@70020000 { - status = "okay"; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - status = "okay"; - }; - - /* Apalis MMC1 */ - sdhci@700b0000 { - status = "okay"; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc1>; - }; - - /* Apalis SD1 */ - sdhci@700b0400 { - status = "okay"; - /* - * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it - * features some magic properties even though the external - * loopback is disabled and the internal loopback used as per - * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being - * set to 0xfffd according to the TRM! - * cd-gpios = <&gpio TEGRA_GPIO(EE, 4) GPIO_ACTIVE_LOW>; - */ - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <®_usbo1_vbus>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <®_usbh_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - /* BKL1_PWM */ - pwms = <&pwm 3 5000000>; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* USBO1_EN */ - reg_usbo1_vbus: regulator-usbo1-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBO1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; - - /* USBH_EN */ - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_5v0>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis.dtsi deleted file mode 100644 index e7a73db17..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-apalis.dtsi +++ /dev/null @@ -1,2100 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "tegra124.dtsi" -#include "tegra124-apalis-emc.dtsi" - -/* - * Toradex Apalis TK1 Module Device Tree - * Compatible for Revisions 2GB: V1.0A - */ -/ { - model = "Toradex Apalis TK1"; - compatible = "toradex,apalis-tk1", "nvidia,tegra124"; - - memory { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - pcie-controller@01003000 { - status = "okay"; - - avddio-pex-supply = <&vdd_1v05>; - avdd-pex-pll-supply = <&vdd_1v05>; - avdd-pll-erefe-supply = <&avdd_1v05>; - dvddio-pex-supply = <&vdd_1v05>; - hvdd-pex-pll-e-supply = <®_3v3>; - hvdd-pex-supply = <®_3v3>; - vddio-pex-ctl-supply = <®_3v3>; - - /* Apalis PCIe (additional lane Apalis type specific) */ - pci@1,0 { - /* PCIE1_RX/TX and TS_DIFF1/2 */ - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names = "pcie-0", "pcie-1"; - }; - - /* I210 Gigabit Ethernet Controller (On-module) */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - pll-supply = <®_1v05_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - gpu@0,57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <&vdd_gpu>; - }; - - pinmux: pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Analogue Audio (On-module) */ - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_ON */ - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis BKL1_PWM */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAM1_MCLK */ - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb3 { /* DAP1_RESET */ - nvidia,pins = "pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis GPIO */ - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis HDMI1_CEC */ - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis HDMI1_HPD */ - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - - /* Apalis I2C1 */ - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C2 (DDC) */ - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis I2C3 (CAM) */ - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis MMC1 */ - sdmmc1_cd_n_pv3 { /* CD# GPIO */ - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { /* D5 GPIO */ - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { /* D4 GPIO */ - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it - * features some magic properties even though the - * external loopback is disabled and the internal - * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 - * register's SDMMC_SPARE1 bits being set to 0xfffd - * according to the TRM! - */ - sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { /* D7 GPIO */ - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM */ - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* PWM3 active on pu6 being Apalis BKL1_PWM */ - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SATA1_ACT# */ - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SD1 */ - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - /* - * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it - * features some magic properties even though the - * external loopback is disabled and the internal - * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 - * register's SDMMC_SPARE1 bits being set to 0xfffd - * according to the TRM! - */ - sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */ - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPDIF */ - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI2 */ - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART1 */ - pb1 { /* DCD GPIO */ - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { /* RI GPIO */ - nvidia,pins = "pk7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1_txd_pu0 { - nvidia,pins = "pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1_rxd_pu1 { - nvidia,pins = "pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1_cts_n_pu2 { - nvidia,pins = "pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart1_rts_n_pu3 { - nvidia,pins = "pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { /* DSR GPIO */ - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { /* DTR GPIO */ - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART2 */ - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART3 */ - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis UART4 */ - uart4_rxd_pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart4_txd_pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBH_EN */ - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBH_OC# */ - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis USBO1_EN */ - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* Apalis USBO1_OC# */ - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CORE_PWR_REQ */ - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* CPU_PWR_REQ */ - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* DVFS */ - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC */ - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* JTAG_RTCK */ - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_DEV_OFF# */ - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_RESET# */ - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* LAN_WAKE# */ - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT1# */ - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT2# */ - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT3# */ - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_INT4# */ - pj0 { - nvidia,pins = "pj0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU_RESET */ - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* MCU SPI */ - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { /* MCU_CS */ - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w2_aud_pw2 { /* MCU_CSEZP */ - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CLK_32K */ - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PMIC_CPU_OC_INT */ - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* PWR_I2C */ - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - - /* PWR_INT_N */ - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_MOCI_CTRL */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* RESET_OUT_N */ - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_IN */ - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Configure level-shifter as output for HDA */ - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_DIR_OUT */ - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* SHIFT_CTRL_OE */ - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* GPIO_PI6 aka TEMP_ALERT_L */ - pi6 { - nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_INT */ - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - pc7 { /* NC */ - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { /* NC */ - nvidia,pins = "pg0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { /* NC */ - nvidia,pins = "pg1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { /* NC */ - nvidia,pins = "pg2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { /* NC */ - nvidia,pins = "pg3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { /* NC */ - nvidia,pins = "pg4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { /* NC */ - nvidia,pins = "ph4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { /* NC */ - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { /* NC */ - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { /* NC */ - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { /* NC */ - nvidia,pins = "pi0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { /* NC */ - nvidia,pins = "pi1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { /* NC */ - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { /* NC */ - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { /* NC */ - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { /* NC */ - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { /* NC */ - nvidia,pins = "pk1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { /* NC */ - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { /* NC */ - nvidia,pins = "pk4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { /* NC */ - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { /* NC */ - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { /* NC */ - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data7_po0 { /* NC */ - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { /* NC */ - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { /* NC */ - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { /* NC */ - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { /* NC */ - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { /* NC */ - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { /* NC */ - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { /* NC */ - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { /* NC */ - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { /* NC */ - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { /* NC */ - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { /* NC */ - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { /* NC */ - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { /* NC */ - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { /* NC */ - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { /* NC */ - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { /* NC */ - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { /* NC */ - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { /* NC */ - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { /* NC */ - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { /* NC */ - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { /* NC */ - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { /* NC */ - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { /* NC */ - nvidia,pins = "kb_row17_pt1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { /* NC */ - nvidia,pins = "pu5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { /* NC */ - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { /* NC */ - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { /* NC */ - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { /* NC */ - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { /* NC */ - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { /* NC */ - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { /* NC */ - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { /* NC */ - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { /* NC */ - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { /* NC */ - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006040 { - compatible = "nvidia,tegra124-hsuart"; - }; - - serial@70006200 { - compatible = "nvidia,tegra124-hsuart"; - }; - - serial@70006300 { - compatible = "nvidia,tegra124-hsuart"; - }; - - hdmi_ddc: i2c@7000c400 { - clock-frequency = <100000>; - }; - - /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - /* SGTL5000 audio codec */ - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <&vddio_1v8>; - clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; - }; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio2_7 { - pins = "gpio2", /* PWR_EN_+V3.3 */ - "gpio7"; /* +V1.6_LPO */ - function = "gpio"; - bias-pull-up; - }; - - gpio1_3_4_5_6 { - pins = "gpio1", "gpio3", "gpio4", - "gpio5", "gpio6"; - bias-high-impedance; - }; - }; - - regulators { - vsup-sd2-supply = <®_3v3>; - vsup-sd3-supply = <®_3v3>; - vsup-sd4-supply = <®_3v3>; - vsup-sd5-supply = <®_3v3>; - vin-ldo0-supply = <&vddio_ddr_1v35>; - vin-ldo1-6-supply = <®_3v3>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <®_3v3>; - vin-ldo9-10-supply = <®_3v3>; - vin-ldo11-supply = <®_3v3>; - - vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vddio_ddr_1v35: sd2 { - regulator-name = - "+V1.35_VDDIO_DDR(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = - "+V1.35_VDDIO_DDR(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05: sd4 { - regulator-name = "+V1.05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05: ldo0 { - regulator-name = "+V1.05_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - vddio_sdmmc1: ldo1 { - regulator-name = "VDDIO_SDMMC1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "+V1.2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+V1.05_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - /* 1.8V for LVDS, 3.3V for eDP */ - ldo4 { - regulator-name = "AVDD_LVDS0_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* LDO5 not used */ - - vddio_sdmmc3: ldo6 { - regulator-name = "VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - /* LDO7 not used */ - - ldo9 { - regulator-name = "+V3.3_ETH(ldo9)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo10 { - regulator-name = "+V3.3_ETH(ldo10)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo11 { - regulator-name = "+V1.8_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - /* - * TMP451 temperature sensor - * Note: THERM_N directly connected to AS3722 PMIC THERM - */ - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - /* SPI2: MCU SPI */ - spi@7000d600 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - /* Set power_off bit in ResetControl register of AS3722 PMIC */ - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - - sata@70020000 { - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; - - avdd-supply = <&vdd_1v05>; - hvdd-supply = <®_3v3>; - vddio-supply = <&vdd_1v05>; - }; - - usb@70090000 { - /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; - phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - - avddio-pex-supply = <&vdd_1v05>; - avdd-pll-erefe-supply = <&avdd_1v05>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-usb-ss-pll-supply = <&vdd_1v05>; - avdd-usb-supply = <®_3v3>; - dvddio-pex-supply = <&vdd_1v05>; - hvdd-usb-ss-pll-e-supply = <®_3v3>; - hvdd-usb-ss-supply = <®_3v3>; - }; - - padctl@7009f000 { - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie"; - status = "okay"; - }; - - pcie-3 { - nvidia,function = "pcie"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - /* USBO1 */ - usb2-0 { - status = "okay"; - mode = "otg"; - - vbus-supply = <®_usbo1_vbus>; - }; - - /* USBH2 */ - usb2-1 { - status = "okay"; - mode = "host"; - - vbus-supply = <®_usbh_vbus>; - }; - - /* USBH4 */ - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <®_usbh_vbus>; - }; - - usb3-0 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - }; - }; - - /* eMMC */ - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - vdd-cpu-supply = <&vdd_cpu>; - nvidia,i2c-fs-rate = <400000>; - }; - - ahub@70300000 { - i2s@70301200 { - status = "okay"; - }; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <&vdd_cpu>; - }; - }; - - reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { - compatible = "regulator-fixed"; - regulator-name = "+V1.05_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05>; - }; - - reg_3v3_mxm: regulator-3v3-mxm { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_MXM"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - /* PWR_EN_+V3.3 */ - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_3v3_mxm>; - }; - - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_1v05>; - }; - - sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis TK1"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - cpu { - trips { - trip@0 { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; - }; - - mem { - trips { - trip@0 { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; - }; - - gpu { - trips { - trip@0 { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi deleted file mode 100644 index accb70551..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ /dev/null @@ -1,2421 +0,0 @@ -/ { - clock@60006000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - timing-528000000 { - clock-frequency = <528000000>; - nvidia,parent-clock-frequency = <528000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - timing-924000000 { - clock-frequency = <924000000>; - nvidia,parent-clock-frequency = <924000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - emc@7001b000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 - 0x0000000a - 0x00000000 - 0x00000001 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 - 0x00000011 - 0x00000000 - 0x00000002 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000202 - 0x00000000 - 0x00000080 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000001 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000213 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000022 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 - 0x0000001a - 0x00000000 - 0x00000003 - 0x00000001 - 0x00000004 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000304 - 0x00000000 - 0x000000c1 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000018 - 0x0000000f - 0x0000001c - 0x0000001c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000031c - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000e0e - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000033 - 0x00000000 - 0x00000042 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008cd>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000e000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 - 0x00000035 - 0x00000000 - 0x00000006 - 0x00000002 - 0x00000005 - 0x0000000a - 0x00000005 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000004 - 0x00000006 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000003 - 0x0000000d - 0x0000000f - 0x00000011 - 0x00000607 - 0x00000000 - 0x00000181 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000032 - 0x0000000f - 0x00000038 - 0x00000038 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000006 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000638 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00080000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00008000 - 0x00000000 - 0x00000000 - 0x00008000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000707 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000066 - 0x00000000 - 0x00000100 - 0x000e000e - 0x00000000 - 0x00000003 - 0x0000d2b3 - 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0173000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d - 0x0000004d - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 - 0x00000003 - 0x00000003 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000007 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 - 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x0000004b - 0x0000000e - 0x00000052 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000008 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000924 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00050000 - 0x00005000 - 0x00005000 - 0x00005000 - 0x00005000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000096 - 0x00000000 - 0x00000100 - 0x0173000e - 0x00000000 - 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000011 - 0x00000066 - 0x00000000 - 0x0000000c - 0x00000004 - 0x00000004 - 0x00000008 - 0x00000002 - 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 - 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x00000063 - 0x0000000f - 0x0000006c - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x0000000b - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000c11 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00038000 - 0x00003800 - 0x00003800 - 0x00003800 - 0x00003800 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x000000c6 - 0x00000000 - 0x00000100 - 0x015b000e - 0x00000000 - 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000941>; - nvidia,emc-mrs-wait-cnt = <0x0139000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000018 - 0x00000088 - 0x00000000 - 0x00000010 - 0x00000006 - 0x00000006 - 0x00000009 - 0x00000002 - 0x0000000d - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000009 - 0x00030000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000010 - 0x00000012 - 0x00000014 - 0x00000fd6 - 0x00000000 - 0x000003f5 - 0x00000002 - 0x0000000b - 0x00000001 - 0x00000000 - 0x00000085 - 0x00000012 - 0x00000090 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000010 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001017 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe01200b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00054000 - 0x00054000 - 0x00000000 - 0x00054000 - 0x00054000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x0000000c - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0139000e - 0x00000000 - 0x00000003 - 0x000042a0 - 0x80002062 - 0x0000000a - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0127000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001b - 0x0000009b - 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b - 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000000a - 0x00000002 - 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000002 - 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 - 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d - 0x00000001 - 0x00000000 - 0x00000097 - 0x00000015 - 0x000000a3 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000013 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001248 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00e00b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x0000000d - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0127000e - 0x00000000 - 0x00000003 - 0x000040a0 - 0x800024aa - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f7000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000024 - 0x000000cd - 0x00000000 - 0x00000019 - 0x0000000a - 0x00000008 - 0x0000000d - 0x00000004 - 0x00000013 - 0x0000000a - 0x0000000a - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 - 0x00000003 - 0x00000011 - 0x00000001 - 0x00000000 - 0x000000c7 - 0x00000018 - 0x000000d7 - 0x00000200 - 0x00000005 - 0x00000006 - 0x00000005 - 0x00000019 - 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00700b1 - 0x00008000 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x007fc008 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000000 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x61861820 - 0x00514514 - 0x00514514 - 0x61861800 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x00f7000e - 0x00000000 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emc-auto-cal-config = <0xa1430303>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200020>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000f15>; - nvidia,emc-mrs-wait-cnt = <0x00cd000e>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x0000004c>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000002b - 0x000000f0 - 0x00000000 - 0x0000001e - 0x0000000b - 0x00000009 - 0x0000000f - 0x00000005 - 0x00000016 - 0x0000000b - 0x0000000b - 0x00000004 - 0x00000002 - 0x00000000 - 0x00000007 - 0x00000007 - 0x0000000d - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000f - 0x000a0000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000016 - 0x0000001a - 0x0000001c - 0x00001be7 - 0x00000000 - 0x000006f9 - 0x00000004 - 0x00000015 - 0x00000001 - 0x00000000 - 0x000000e7 - 0x0000001b - 0x000000fb - 0x00000200 - 0x00000006 - 0x00000007 - 0x00000006 - 0x0000001e - 0x00000000 - 0x0000000a - 0x0000000a - 0x00001c28 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab898 - 0xe00400b1 - 0x00008000 - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x007f800a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000004 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000000 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x5d75d720 - 0x00514514 - 0x00514514 - 0x5d75d700 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000128 - 0x00cd000e - 0x00000000 - 0x00000004 - 0x00004080 - 0x800037ea - 0x00000011 - >; - }; - - }; - }; - - memory-controller@70019000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0502 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0503 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000004 - 0x00000002 - 0x00000003 - 0x00000001 - 0x00000003 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0504 - 0x73840a05 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000006 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000007 - 0x00000008 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090c - 0x7428180d - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000a - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000d - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00170e13 - 0x736c2414 - 0x70000f02 - 0x001f0000 - >; - }; - - timing-924000000 { - clock-frequency = <924000000>; - - nvidia,emem-configuration = < - 0x0e00000d - 0x80000040 - 0x00000005 - 0x00000006 - 0x00000016 - 0x0000000e - 0x0000000f - 0x00000002 - 0x00000004 - 0x0000000e - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000009 - 0x09060202 - 0x001a1016 - 0x734e2a17 - 0x70000f02 - 0x001f0000 - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/software/linux/kernel/arch/arm/boot/dts/tegra124-jetson-tk1.dts deleted file mode 100644 index 53994f9fb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ /dev/null @@ -1,2076 +0,0 @@ -/dts-v1/; - -#include -#include "tegra124.dtsi" - -#include "tegra124-jetson-tk1-emc.dtsi" - -/ { - model = "NVIDIA Tegra124 Jetson TK1"; - compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - - /* This order keeps the mapping DB9 connector <-> ttyS0 */ - serial0 = &uartd; - serial1 = &uarta; - serial2 = &uartb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - pcie-controller@01003000 { - status = "okay"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-supply = <&vdd_3v3_lp0>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - vddio-pex-ctl-supply = <&vdd_3v3_lp0>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - - /* Mini PCIe */ - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0"; - status = "okay"; - }; - - /* Gigabit Ethernet */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - vdd-supply = <&vdd_3v3_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - gpu@0,57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <&vdd_gpu>; - }; - - pinmux: pinmux@70000868 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "displaya_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vimclk2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dsi_b { - nvidia,pins = "mipi_pad_ctrl_dsi_b"; - nvidia,function = "dsi_b"; - }; - }; - }; - - /* - * First high speed UART, exposed on the expansion connector J3A2 - * Pin 41: BR_UART1_TXD - * Pin 44: BR_UART1_RXD - */ - serial@70006000 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - /* - * Second high speed UART, exposed on the expansion connector J3A2 - * Pin 65: UART2_RXD - * Pin 68: UART2_TXD - * Pin 71: UART2_CTS_L - * Pin 74: UART2_RTS_L - */ - serial@70006040 { - compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - /* DB9 serial port */ - serial@70006300 { - status = "okay"; - }; - - /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - rt5639: audio-codec@1c { - compatible = "realtek,rt5639"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - eeprom@56 { - compatible = "atmel,24c02"; - reg = <0x56>; - pagesize = <8>; - }; - }; - - /* Expansion GEN2_I2C_* */ - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* Expansion CAM_I2C_* */ - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* HDMI DDC */ - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* Expansion PWR_I2C_*, on-board components */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1_2_4_7 { - pins = "gpio1", "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_5_6 { - pins = "gpio3", "gpio5", "gpio6"; - bias-high-impedance; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.05V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - ldo4 { - regulator-name = "+2.8V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+3.3V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - /* Expansion TS_SPI_* */ - spi@7000d400 { - status = "okay"; - }; - - /* Internal SPI */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@0 { - compatible = "winbond,w25q32dw"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - - /* Serial ATA */ - sata@70020000 { - status = "okay"; - - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; - - hvdd-supply = <&vdd_3v3_lp0>; - vddio-supply = <&vdd_1v05_run>; - avdd-supply = <&vdd_1v05_run>; - - target-5v-supply = <&vdd_5v0_sata>; - target-12v-supply = <&vdd_12v0_sata>; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - /* Micro A/B */ - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - /* Mini PCIe */ - usb2-1 { - status = "okay"; - mode = "host"; - }; - - /* USB3 */ - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - /* SD card */ - sdhci@700b0400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* eMMC */ - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "okay"; - vdd-cpu-supply = <&vdd_cpu>; - nvidia,i2c-fs-rate = <400000>; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - /* mini-PCIe USB */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - }; - - /* USB A connector */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <&vdd_cpu>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+USB0_VBUS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - /* Molex power connector */ - vdd_5v0_sata: regulator@13 { - compatible = "regulator-fixed"; - reg = <13>; - regulator-name = "+5V_SATA"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_12v0_sata: regulator@14 { - compatible = "regulator-fixed"; - reg = <14>; - regulator-name = "+12V_SATA"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Jetson TK1"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5639>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - cpu { - trips { - cpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mem { - trips { - mem-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpu { - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi deleted file mode 100644 index 4458e86b2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ /dev/null @@ -1,2023 +0,0 @@ -/ { - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - /* TODO: Add 528MHz frequency */ - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - emc@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 - 0x0000000a - 0x00000000 - 0x00000001 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 - 0x00000011 - 0x00000000 - 0x00000002 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000202 - 0x00000000 - 0x00000080 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000001 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000213 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000022 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 - 0x0000001a - 0x00000000 - 0x00000003 - 0x00000001 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000304 - 0x00000000 - 0x000000c1 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000018 - 0x0000000f - 0x0000001c - 0x0000001c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000031c - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000033 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 - 0x00000035 - 0x00000000 - 0x00000007 - 0x00000002 - 0x00000005 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000004 - 0x00000006 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000003 - 0x0000000d - 0x0000000f - 0x00000011 - 0x00000607 - 0x00000000 - 0x00000181 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000032 - 0x0000000f - 0x00000038 - 0x00000038 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000007 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000638 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00094000 - 0x00094000 - 0x00009400 - 0x00009000 - 0x00009000 - 0x00009000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000066 - 0x00000000 - 0x00000100 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000d2b3 - 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d - 0x0000004c - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 - 0x00000003 - 0x00000003 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000007 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 - 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x0000004a - 0x0000000e - 0x00000051 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000009 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000924 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000101 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000096 - 0x00000000 - 0x00000100 - 0x0174000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 - 0x00000065 - 0x00000000 - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000008 - 0x00000002 - 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 - 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x00000063 - 0x0000000f - 0x0000006b - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x0000000d - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000c11 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00048000 - 0x00048000 - 0x00004800 - 0x00004800 - 0x00004800 - 0x00004800 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000101 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x000000c6 - 0x00000000 - 0x00000100 - 0x015b000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c - 0x0000009a - 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b - 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000000a - 0x00000002 - 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000002 - 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 - 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d - 0x00000001 - 0x00000000 - 0x00000096 - 0x00000015 - 0x000000a2 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000015 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001249 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00e00b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000005 - 0x00000006 - 0x00000003 - 0x00000006 - 0x00000005 - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000005 - 0x00000006 - 0x00000003 - 0x00000006 - 0x00000005 - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000101 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0128000c - 0x00000000 - 0x00000003 - 0x000040a0 - 0x800024aa - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0080089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200418>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 - 0x000000cc - 0x00000000 - 0x0000001a - 0x00000009 - 0x00000008 - 0x0000000d - 0x00000004 - 0x00000013 - 0x00000009 - 0x00000009 - 0x00000003 - 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 - 0x00000003 - 0x00000011 - 0x00000001 - 0x00000000 - 0x000000c6 - 0x00000018 - 0x000000d6 - 0x00000200 - 0x00000005 - 0x00000006 - 0x00000005 - 0x0000001d - 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 - 0x00000000 - 0x80000005 - 0x00000000 - 0x104ab198 - 0xe00700b1 - 0x00008000 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000009 - 0x00000009 - 0x00000007 - 0x00000009 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000009 - 0x00000009 - 0x00000007 - 0x00000009 - 0x00000008 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000101 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x61861820 - 0x00514514 - 0x00514514 - 0x61861800 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x00f8000c - 0x00000007 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f - >; - }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0403 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000005 - 0x00000002 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0405 - 0x73840a06 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000005 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000007 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000b - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000f - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00160d13 - 0x734c2414 - 0x70000f02 - 0x001f0000 - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-big.dts b/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-big.dts deleted file mode 100644 index 67d7cfb32..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-big.dts +++ /dev/null @@ -1,1338 +0,0 @@ -/dts-v1/; - -#include "tegra124-nyan.dtsi" - -#include "tegra124-nyan-big-emc.dtsi" - -/ { - model = "Acer Chromebook 13 CB5-311"; - compatible = "google,nyan-big", "nvidia,tegra124"; - - panel: panel { - compatible = "auo,b133xtn01"; - - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - sdhci@700b0400 { /* SD Card on this bus */ - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-big", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBig"; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; - - pinmux_default: common { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi deleted file mode 100644 index 4e7b59e25..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ /dev/null @@ -1,2049 +0,0 @@ -/ { - clock@60006000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-40800000 { - clock-frequency = <40800000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-68000000 { - clock-frequency = <68000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-102000000 { - clock-frequency = <102000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-204000000 { - clock-frequency = <204000000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-300000000 { - clock-frequency = <300000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C>; - clock-names = "emc-parent"; - }; - timing-396000000 { - clock-frequency = <396000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M>; - clock-names = "emc-parent"; - }; - /* TODO: Add 528MHz frequency */ - timing-600000000 { - clock-frequency = <600000000>; - nvidia,parent-clock-frequency = <600000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; - clock-names = "emc-parent"; - }; - timing-792000000 { - clock-frequency = <792000000>; - nvidia,parent-clock-frequency = <792000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; - clock-names = "emc-parent"; - }; - }; - }; - - emc@7001b000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000001 - 0x0000000a - 0x00000000 - 0x00000001 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000370 - 0x0000000a - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000003 - 0x00000011 - 0x00000000 - 0x00000002 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000202 - 0x00000000 - 0x00000080 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000001 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000213 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000022 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000050e - 0x0000000a - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000004 - 0x0000001a - 0x00000000 - 0x00000003 - 0x00000001 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000304 - 0x00000000 - 0x000000c1 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000018 - 0x0000000f - 0x0000001c - 0x0000001c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000031c - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000033 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000713 - 0x0000000a - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x0000088d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mrs-wait-cnt = <0x000c000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000009 - 0x00000035 - 0x00000000 - 0x00000007 - 0x00000002 - 0x00000005 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000004 - 0x00000006 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000003 - 0x0000000d - 0x0000000f - 0x00000011 - 0x00000607 - 0x00000000 - 0x00000181 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000032 - 0x0000000f - 0x00000038 - 0x00000038 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000007 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000638 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x0000c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00090000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x00009000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000505 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000066 - 0x00000000 - 0x00000100 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000d2b3 - 0x80000d22 - 0x0000000a - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x000008d5>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000321>; - nvidia,emc-mrs-wait-cnt = <0x0174000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000000d - 0x0000004c - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 - 0x00000003 - 0x00000003 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000007 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 - 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x0000004a - 0x0000000e - 0x00000051 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000009 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000924 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000096 - 0x00000000 - 0x00000100 - 0x0174000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73340000>; - nvidia,emc-cfg-2 = <0x00000895>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200000>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000521>; - nvidia,emc-mrs-wait-cnt = <0x015b000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x01231339>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000012 - 0x00000065 - 0x00000000 - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000008 - 0x00000002 - 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 - 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x00000063 - 0x0000000f - 0x0000006b - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x0000000d - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000c11 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00068000 - 0x00068000 - 0x00000000 - 0x00068000 - 0x00068000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00058000 - 0x00058000 - 0x00058000 - 0x00058000 - 0x00005800 - 0x00005800 - 0x00005800 - 0x00005800 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x000000c6 - 0x00000000 - 0x00000100 - 0x015b000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200010>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000b61>; - nvidia,emc-mrs-wait-cnt = <0x0128000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040008>; - nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x0000001c - 0x0000009a - 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b - 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000000a - 0x00000002 - 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000002 - 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 - 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d - 0x00000001 - 0x00000000 - 0x00000096 - 0x00000015 - 0x000000a2 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000015 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001248 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00e00b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00040000 - 0x00040000 - 0x00000000 - 0x00040000 - 0x00040000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000005 - 0x00000007 - 0x00000004 - 0x00000006 - 0x00000007 - 0x00000004 - 0x00000004 - 0x00000001 - 0x00000005 - 0x00000007 - 0x00000004 - 0x00000006 - 0x00000007 - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0128000c - 0x00000000 - 0x00000003 - 0x000040a0 - 0x800024a9 - 0x0000000e - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-bgbias-ctl0 = <0x00000000>; - nvidia,emc-cfg = <0x73300000>; - nvidia,emc-cfg-2 = <0x0000089d>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-mode-1 = <0x80100002>; - nvidia,emc-mode-2 = <0x80200018>; - nvidia,emc-mode-4 = <0x00000000>; - nvidia,emc-mode-reset = <0x80000d71>; - nvidia,emc-mrs-wait-cnt = <0x00f8000c>; - nvidia,emc-sel-dpd-ctrl = <0x00040000>; - nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-zcal-interval = <0x00020000>; - - nvidia,emc-configuration = < - 0x00000025 - 0x000000cc - 0x00000000 - 0x0000001a - 0x00000009 - 0x00000008 - 0x0000000d - 0x00000004 - 0x00000013 - 0x00000009 - 0x00000009 - 0x00000003 - 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 - 0x00000003 - 0x00000011 - 0x00000001 - 0x00000000 - 0x000000c6 - 0x00000018 - 0x000000d6 - 0x00000200 - 0x00000005 - 0x00000006 - 0x00000005 - 0x0000001d - 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00700b1 - 0x00008000 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x0002c000 - 0x0002c000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000008 - 0x0000000a - 0x00000008 - 0x0000000a - 0x0000000a - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000008 - 0x0000000a - 0x00000008 - 0x0000000a - 0x0000000a - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000202 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x61861820 - 0x00492492 - 0x00492492 - 0x61861800 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x00f8000c - 0x00000000 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f - >; - }; - - }; - }; - - memory-controller@70019000 { - emc-timings-1 { - nvidia,ram-code = <1>; - - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x77e30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-20400000 { - clock-frequency = <20400000>; - - nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x76230303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-40800000 { - clock-frequency = <40800000>; - - nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74a30303 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-68000000 { - clock-frequency = <68000000>; - - nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74230403 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-102000000 { - clock-frequency = <102000000>; - - nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0403 - 0x73c30504 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-204000000 { - clock-frequency = <204000000>; - - nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000005 - 0x00000002 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0405 - 0x73840a06 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-300000000 { - clock-frequency = <300000000>; - - nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000005 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 - >; - }; - - timing-396000000 { - clock-frequency = <396000000>; - - nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000007 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 - >; - }; - - timing-528000000 { - clock-frequency = <528000000>; - - nvidia,emem-configuration = < - 0x0f000007 - 0x80000040 - 0x00000002 - 0x00000003 - 0x0000000d - 0x00000008 - 0x0000000a - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000006 - 0x06050202 - 0x0010090d - 0x7428180e - 0x70000f03 - 0x001f0000 - >; - }; - - timing-600000000 { - clock-frequency = <600000000>; - - nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000b - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 - >; - }; - - timing-792000000 { - clock-frequency = <792000000>; - - nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000f - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00160d13 - 0x734c2414 - 0x70000f02 - 0x001f0000 - >; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-blaze.dts deleted file mode 100644 index c9582361c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ /dev/null @@ -1,1334 +0,0 @@ -/dts-v1/; - -#include "tegra124-nyan.dtsi" - -#include "tegra124-nyan-blaze-emc.dtsi" - -/ { - model = "HP Chromebook 14"; - compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124"; - - panel: panel { - compatible = "samsung,ltn140at29-301"; - - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-blaze", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBlaze"; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; - - pinmux_default: common { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan.dtsi deleted file mode 100644 index 271505e07..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-nyan.dtsi +++ /dev/null @@ -1,778 +0,0 @@ -#include -#include "tegra124.dtsi" - -/ { - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@54540000 { - status = "okay"; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux@545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; - }; - - serial@70006000 { - /* Debug connector on the bottom of the board near SD card. */ - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio>; - interrupts = ; - wakeup-source; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1 { - pins = "gpio1"; - function = "gpio"; - bias-pull-up; - }; - - gpio2_4_7 { - pins = "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - bias-pull-down; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - vdd_cpu: sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+3.3V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - power-supplies = <&charger>; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - flash@0 { - compatible = "winbond,w25q32dw"; - spi-max-frequency = <25000000>; - reg = <0>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - vbus-supply = <&vdd_usb1_vbus>; - status = "okay"; - mode = "otg"; - }; - - usb2-1 { - vbus-supply = <&vdd_run_cam>; - status = "okay"; - mode = "host"; - }; - - usb2-2 { - vbus-supply = <&vdd_usb3_vbus>; - status = "okay"; - mode = "host"; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <1>; - status = "okay"; - }; - }; - }; - - sdhci0_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - - reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - - sdhci@700b0000 { /* WiFi/BT on this bus */ - status = "okay"; - bus-width = <4>; - no-1-8-v; - non-removable; - mmc-pwrseq = <&sdhci0_pwrseq>; - vmmc-supply = <&vdd_3v3_lp0>; - vqmmc-supply = <&vddio_1v8>; - keep-power-in-suspend; - }; - - sdhci@700b0400 { /* SD Card on this bus */ - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - no-1-8-v; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - sdhci@700b0600 { /* eMMC on this bus */ - status = "okay"; - bus-width = <8>; - no-1-8-v; - non-removable; - }; - - /* CPU DFLL clock */ - clock@70110000 { - status = "disabled"; - vdd-cpu-supply = <&vdd_cpu>; - nvidia,i2c-fs-rate = <400000>; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - default-brightness-level = <224>; - brightness-levels = - < 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - 256>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - cpu@0 { - vdd-cpu-supply = <&vdd_cpu>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <5>; - linux,code = ; - debounce-interval = <1>; - wakeup-source; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - wakeup-source; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - - sound { - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "DMICL", "Int Mic", - "DMICR", "Int Mic", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; - nvidia,mic-det-gpios = - <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - priority = <200>; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124-venice2.dts b/software/linux/kernel/arch/arm/boot/dts/tegra124-venice2.dts deleted file mode 100644 index 6e59cec09..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124-venice2.dts +++ /dev/null @@ -1,1270 +0,0 @@ -/dts-v1/; - -#include -#include "tegra124.dtsi" - -/ { - model = "NVIDIA Tegra124 Venice2"; - compatible = "nvidia,venice2", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@54540000 { - status = "okay"; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux@545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; - }; - - gpu@0,57000000 { - /* - * Node left disabled on purpose - the bootloader will enable - * it after having set the VPR up - */ - vdd-supply = <&vdd_gpu>; - }; - - pinmux: pinmux@70000868 { - pinctrl-names = "boot"; - pinctrl-0 = <&pinmux_boot>; - - pinmux_boot: common { - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - pg4 { - nvidia,pins = "pg4", - "pg5", - "pg6", - "pi3"; - nvidia,function = "spi4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pk0 { - nvidia,pins = "pk0", - "kb_row15_ps7", - "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5", - "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - pj7 { - nvidia,pins = "pj7", - "pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pb0 { - nvidia,pins = "pb0", - "pb1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "displaya_alt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <32>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <20>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <1>; - nvidia,pull-up-strength = <2>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; - }; - als_irq_l { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - codec_irq_l { - nvidia,pins = "ph4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_bl_en { - nvidia,pins = "ph2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - touch_irq_l { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - tpm_davint_l { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_irq_l { - nvidia,pins = "pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_reset_l { - nvidia,pins = "pk4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_shdn_l { - nvidia,pins = "pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_ap { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lid_open { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - en_vdd_sd { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ac_ok { - nvidia,pins = "pj0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sensor_irq_l { - nvidia,pins = "pi6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - wifi_en { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - wifi_rst_l { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hp_det_l { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - acodec: audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio>; - interrupts = ; - linux,gpio-keymap = <0 0 0 BTN_LEFT>; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1_2_4_7 { - pins = "gpio1", "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_6 { - pins = "gpio3", "gpio6"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+3.3V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <4000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <1>; - }; - }; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@0 { - compatible = "winbond,w25q32dw"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@70030000 { - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb2-1 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_run_cam>; - }; - - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - sdhci@700b0400 { - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - status = "okay"; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - sdhci@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - ahub@70300000 { - i2s@70301100 { - status = "okay"; - }; - }; - - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <&vdd_run_cam>; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "lg,lp129qe", "simple-panel"; - - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-venice2", - "nvidia,tegra-audio-max98090"; - nvidia,model = "NVIDIA Tegra Venice2"; - - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra124.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra124.dtsi deleted file mode 100644 index 187a36c6d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra124.dtsi +++ /dev/null @@ -1,1277 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include - -#include "skeleton.dtsi" - -/ { - compatible = "nvidia,tegra124"; - interrupt-parent = <&lic>; - #address-cells = <2>; - #size-cells = <2>; - - pcie-controller@01003000 { - compatible = "nvidia,tegra124-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA124_CLK_PCIE>, - <&tegra_car TEGRA124_CLK_AFI>, - <&tegra_car TEGRA124_CLK_PLL_E>, - <&tegra_car TEGRA124_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra124-host1x", "simple-bus"; - reg = <0x0 0x50000000 0x0 0x00034000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA124_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; - - dc@54200000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54200000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP1>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - }; - - dc@54240000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54240000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP2>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra124-hdmi"; - reg = <0x0 0x54280000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDMI>, - <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - sor@54540000 { - compatible = "nvidia,tegra124-sor"; - reg = <0x0 0x54540000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SOR0>, - <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, - <&tegra_car TEGRA124_CLK_PLL_DP>, - <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "parent", "dp", "safe"; - resets = <&tegra_car 182>; - reset-names = "sor"; - status = "disabled"; - }; - - dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; - reg = <0x0 0x545c0000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DPAUX>, - <&tegra_car TEGRA124_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 181>; - reset-names = "dpaux"; - status = "disabled"; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x50041000 0x0 0x1000>, - <0x0 0x50042000 0x0 0x1000>, - <0x0 0x50044000 0x0 0x2000>, - <0x0 0x50046000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - /* - * Please keep the following 0, notation in place as a former mainline - * U-Boot version was looking for that particular notation in order to - * perform required fix-ups on that GPU node. - */ - gpu@0,57000000 { - compatible = "nvidia,gk20a"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - - iommus = <&mc TEGRA_SWGROUP_GPU>; - - status = "disabled"; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; - reg = <0x0 0x60004000 0x0 0x100>, - <0x0 0x60004100 0x0 0x100>, - <0x0 0x60004200 0x0 0x100>, - <0x0 0x60004300 0x0 0x100>, - <0x0 0x60004400 0x0 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra124-car"; - reg = <0x0 0x60006000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra124-flowctrl"; - reg = <0x0 0x60007000 0x0 0x1000>; - }; - - actmon@6000c800 { - compatible = "nvidia,tegra124-actmon"; - reg = <0x0 0x6000c800 0x0 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_ACTMON>, - <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "actmon", "emc"; - resets = <&tegra_car 119>; - reset-names = "actmon"; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; - reg = <0x0 0x6000d000 0x0 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - /* - gpio-ranges = <&pinmux 0 0 251>; - */ - }; - - apbdma: dma@60020000 { - compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x0 0x60020000 0x0 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra124-pinmux"; - reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x434>, /* Mux registers */ - <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006040 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006200 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006300 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; - reg = <0x0 0x7000a000 0x0 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA124_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c400 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c500 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c700 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d100 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&tegra_car 166>; - reset-names = "i2c"; - dmas = <&apbdma 30>, <&apbdma 30>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d400 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d600 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d800 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000da00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000dc00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC5>; - clock-names = "spi"; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000de00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC6>; - clock-names = "spi"; - resets = <&tegra_car 105>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; - reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_RTC>; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra124-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra124-efuse"; - reg = <0x0 0x7000f800 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra124-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - }; - - emc: emc@7001b000 { - compatible = "nvidia,tegra124-emc"; - reg = <0x0 0x7001b000 0x0 0x1000>; - - nvidia,memory-controller = <&mc>; - }; - - sata@70020000 { - compatible = "nvidia,tegra124-ahci"; - reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ - <0x0 0x70020000 0x0 0x7000>; /* SATA */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; - resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; - status = "disabled"; - }; - - hda@70030000 { - compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; - reg = <0x0 0x70030000 0x0 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDA>, - <&tegra_car TEGRA124_CLK_HDA2HDMI>, - <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - usb@70090000 { - compatible = "nvidia,tegra124-xusb"; - reg = <0x0 0x70090000 0x0 0x8000>, - <0x0 0x70098000 0x0 0x1000>, - <0x0 0x70099000 0x0 0x1000>; - reg-names = "hcd", "fpci", "ipfs"; - - interrupts = , - ; - - clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, - <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, - <&tegra_car TEGRA124_CLK_PLL_U_480M>, - <&tegra_car TEGRA124_CLK_CLK_M>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "xusb_host", "xusb_host_src", - "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", - "xusb_hs_src", "xusb_fs_src", - "pll_u_480m", "clk_m", "pll_e"; - resets = <&tegra_car 89>, <&tegra_car 156>, - <&tegra_car 143>; - reset-names = "xusb_host", "xusb_ss", "xusb_src"; - - nvidia,xusb-padctl = <&padctl>; - - status = "disabled"; - }; - - padctl: padctl@7009f000 { - compatible = "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - pads { - usb2 { - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - ulpi { - status = "disabled"; - - lanes { - ulpi-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - ulpi-0 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - }; - }; - - sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0200 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0200 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0400 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0400 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@700b0600 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0600 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ - 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ - reg-names = "soctherm-reg", "car-reg"; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - #thermal-sensor-cells = <1>; - - throttle-cfgs { - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-percent = <85>; - - #cooling-cells = <2>; - }; - }; - }; - - dfll: clock@70110000 { - compatible = "nvidia,tegra124-dfll"; - reg = <0 0x70110000 0 0x100>, /* DFLL control */ - <0 0x70110000 0 0x100>, /* I2C output control */ - <0 0x70110100 0 0x100>, /* Integrated I2C controller */ - <0 0x70110200 0 0x100>; /* Look-up table RAM */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, - <&tegra_car TEGRA124_CLK_DFLL_REF>, - <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; - reset-names = "dvco"; - #clock-cells = <0>; - clock-output-names = "dfllCPU_out"; - nvidia,sample-rate = <12500>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,cf = <10>; - nvidia,ci = <0>; - nvidia,cg = <2>; - status = "disabled"; - }; - - ahub@70300000 { - compatible = "nvidia,tegra124-ahub"; - reg = <0x0 0x70300000 0x0 0x200>, - <0x0 0x70300800 0x0 0x800>, - <0x0 0x70300200 0x0 0x600>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, - <&tegra_car TEGRA124_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>, /* spdif */ - <&tegra_car 153>, /* amx */ - <&tegra_car 185>, /* amx1 */ - <&tegra_car 154>, /* adx */ - <&tegra_car 180>, /* adx1 */ - <&tegra_car 186>, /* afc0 */ - <&tegra_car 187>, /* afc1 */ - <&tegra_car 188>, /* afc2 */ - <&tegra_car 189>, /* afc3 */ - <&tegra_car 190>, /* afc4 */ - <&tegra_car 191>; /* afc5 */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif", "amx", "amx1", "adx", "adx1", - "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>, - <&apbdma 6>, <&apbdma 6>, - <&apbdma 7>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 12>, - <&apbdma 13>, <&apbdma 13>, - <&apbdma 14>, <&apbdma 14>, - <&apbdma 29>, <&apbdma 29>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", - "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", - "rx9", "tx9"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - tegra_i2s0: i2s@70301000 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301000 0x0 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA124_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70301100 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301100 0x0 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA124_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70301200 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301200 0x0 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA124_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70301300 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301300 0x0 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA124_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70301400 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301400 0x0 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA124_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - usb@7d000000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d000000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d004000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d004000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d008000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d008000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, - <&tegra_car TEGRA124_CLK_PLL_X>, - <&tegra_car TEGRA124_CLK_PLL_P>, - <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; - /* FIXME: what's the actual transition time? */ - clock-latency = <300000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&{/cpus/cpu@0}>, - <&{/cpus/cpu@1}>, - <&{/cpus/cpu@2}>, - <&{/cpus/cpu@3}>; - }; - - thermal-zones { - cpu { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - cpu_throttle_trip: throttle-trip { - temperature = <100000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - mem { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - - gpu { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu-shutdown-trip { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - gpu_throttle_trip: throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - pllx { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra20-colibri-512.dtsi deleted file mode 100644 index 1242b841f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -#include "tegra20.dtsi" - -/ { - model = "Toradex Colibri T20 512MB"; - compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&i2c_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - audio_refclk { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - nvidia,pull = ; - nvidia,tristate = ; - }; - crt { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - displaya { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", - "ld4", "ld5", "ld6", "ld7", "ld8", - "ld9", "ld10", "ld11", "ld12", "ld13", - "ld14", "ld15", "ld16", "ld17", - "lhs", "lpw0", "lpw2", "lsc0", - "lsc1", "lsck", "lsda", "lspi", "lvs"; - nvidia,function = "displaya"; - nvidia,tristate = ; - }; - gpio_dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_gmi { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap1", "dap2", "dap4", "gpu", "irrx", - "irtx", "spia", "spib", "spic"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_uac { - nvidia,pins = "uac"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - nvidia,tristate = ; - }; - i2c1 { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2c3 { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2cddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - nvidia,pull = ; - nvidia,tristate = ; - }; - irda { - nvidia,pins = "uad"; - nvidia,function = "irda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - nand { - nvidia,pins = "kbca", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - }; - owc { - nvidia,pins = "owc"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - nvidia,tristate = ; - }; - pwm { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - nvidia,tristate = ; - }; - sdio4 { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - spi1 { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - spi4 { - nvidia,pins = "slxa", "slxc", "slxd", "slxk"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - uarta { - nvidia,pins = "sdio1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - uartd { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - ulpi_refclk { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - usb_gpio { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - nvidia,pull = ; - nvidia,tristate = ; - }; - vi { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - vi_sc { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - ac97: ac97@70002000 { - status = "okay"; - nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_HIGH>; - nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) - GPIO_ACTIVE_HIGH>; - }; - - i2c@7000c000 { - clock-frequency = <400000>; - }; - - i2c_ddc: i2c@7000c400 { - clock-frequency = <100000>; - }; - - i2c@7000c500 { - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_3v3_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&vdd_3v3_reg>; - vinldo4-supply = <&vdd_3v3_reg>; - vinldo678-supply = <&vdd_3v3_reg>; - vinldo9-supply = <&vdd_3v3_reg>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - sys_reg: regulator@0 { - reg = <0>; - regulator-compatible = "sys"; - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - regulator@1 { - reg = <1>; - regulator-compatible = "sm0"; - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - regulator@2 { - reg = <2>; - regulator-compatible = "sm1"; - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: regulator@3 { - reg = <3>; - regulator-compatible = "sm2"; - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - regulator@5 { - reg = <5>; - regulator-compatible = "ldo1"; - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - regulator@6 { - reg = <6>; - regulator-compatible = "ldo2"; - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - /* LDO3 is not connected to anything */ - - regulator@8 { - reg = <8>; - regulator-compatible = "ldo4"; - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: regulator@9 { - reg = <9>; - regulator-compatible = "ldo5"; - regulator-name = "vdd_ldo5,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator@10 { - reg = <10>; - regulator-compatible = "ldo6"; - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - hdmi_vdd_reg: regulator@11 { - reg = <11>; - regulator-compatible = "ldo7"; - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: regulator@12 { - reg = <12>; - regulator-compatible = "ldo8"; - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - regulator@13 { - reg = <13>; - regulator-compatible = "ldo9"; - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - regulator@14 { - reg = <14>; - regulator-compatible = "ldo_rtc"; - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - memory-controller@7000f400 { - emc-table@83250 { - reg = <83250>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <83250>; - nvidia,emc-registers = <0x00000005 0x00000011 - 0x00000004 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000001 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000025f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000005 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00520006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@133200 { - reg = <133200>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <133200>; - nvidia,emc-registers = <0x00000008 0x00000019 - 0x00000006 0x00000002 0x00000004 0x00000004 - 0x00000001 0x0000000a 0x00000002 0x00000002 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x0000039f - 0x00000000 0x00000003 0x00000003 0x00000002 - 0x00000002 0x00000001 0x00000008 0x000000c8 - 0x00000003 0x00000007 0x00000003 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00510006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000021 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000a 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x00000009 0x000000c8 - 0x00000003 0x00000009 0x00000004 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x004f0006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000014 0x00000041 - 0x0000000f 0x00000005 0x00000004 0x00000005 - 0x00000003 0x0000000a 0x00000005 0x00000005 - 0x00000004 0x00000001 0x00000003 0x00000004 - 0x00000003 0x00000009 0x0000000c 0x000009ff - 0x00000000 0x00000003 0x00000003 0x00000005 - 0x00000005 0x00000001 0x0000000e 0x000000c8 - 0x00000003 0x00000011 0x00000006 0x0000000c - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0x00380006 - 0x00000010 0x00000008 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - sdhci@c8000600 { - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_3v3_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "internal_usb"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; - nvidia,model = "Colibri T20 AC97 Audio"; - - nvidia,audio-routing = - "Headphone", "HPOUTL", - "Headphone", "HPOUTR", - "LineIn", "LINEINL", - "LineIn", "LINEINR", - "Mic", "MIC1"; - - nvidia,ac97-controller = <&ac97>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-harmony.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-harmony.dts deleted file mode 100644 index d4fb4d39e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-harmony.dts +++ /dev/null @@ -1,781 +0,0 @@ -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Harmony evaluation board"; - compatible = "nvidia,harmony", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", - "spia", "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtd"; - nvidia,function = "sdio2"; - }; - dtb { - nvidia,pins = "dtb", "dtc", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dtb", "gma", - "gmb", "gmc", "gmd", "gme", "gpu7", - "gpv", "i2cp", "pta", "rm", "slxa", - "slxk", "spia", "spib", "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "dtf", "gpu", "sdio1", - "slxc", "slxd", "spdi", "spdo", "spig", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dta", "dtd", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "sdc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "owc", "sdb"; - nvidia,tristate = ; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "sdd", "spic", - "spie", "spih", "uaa", "uab", "uad", - "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - pci_clk_reg: ldo0 { - regulator-name = "vdd_ldo0,vddio_pex_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <2>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - pcie-controller@80003000 { - status = "okay"; - - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000200 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <8>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel: panel { - compatible = "auo,b101aw03", "simple-panel"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - pci_vdd_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_pnl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_5v0_hdmi: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-harmony", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Harmony"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) - GPIO_ACTIVE_HIGH>; - nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-iris-512.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-iris-512.dts deleted file mode 100644 index bb56dfe9e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-iris-512.dts +++ /dev/null @@ -1,105 +0,0 @@ -/dts-v1/; - -#include "tegra20-colibri-512.dtsi" - -/ { - model = "Toradex Colibri T20 512MB on Iris"; - compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; - - aliases { - serial0 = &uarta; - serial1 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - pinmux@70000014 { - state_default: pinmux { - hdint { - nvidia,tristate = ; - }; - - i2cddc { - nvidia,tristate = ; - }; - - sdio4 { - nvidia,tristate = ; - }; - - uarta { - nvidia,tristate = ; - }; - - uartd { - nvidia,tristate = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - i2c_ddc: i2c@7000c400 { - status = "okay"; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <4>; - vmmc-supply = <&vcc_sd_reg>; - vqmmc-supply = <&vcc_sd_reg>; - }; - - regulators { - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - }; - - vcc_sd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-medcom-wide.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-medcom-wide.dts deleted file mode 100644 index 34c6588e9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ /dev/null @@ -1,134 +0,0 @@ -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Medcom-Wide board"; - compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; - - aliases { - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - panel: panel { - compatible = "innolux,n156bge-l21", "simple-panel"; - - power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - sound { - compatible = "ad,tegra-audio-wm8903-medcom-wide", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design Medcom-Wide"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-paz00.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-paz00.dts deleted file mode 100644 index b4bfa5586..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-paz00.dts +++ /dev/null @@ -1,603 +0,0 @@ -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "Toshiba AC100 / Dynabook AZ"; - compatible = "compal,paz00", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap2", "gmb", "gmc", "gmd", "spia", - "spib", "spic", "spid", "spie"; - nvidia,function = "gmi"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "pllc_out1"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gpu { - nvidia,pins = "gpu", "sdb", "sdd"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - kbcb { - nvidia,pins = "kbcb", "kbcd"; - nvidia,function = "sdio2"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc"; - nvidia,function = "owr"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdc { - nvidia,pins = "sdc"; - nvidia,function = "twc"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spi4"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "rsvd2"; - }; - spif { - nvidia,pins = "spif", "uac"; - nvidia,function = "rsvd4"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "spdif"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dap2", "dtf", - "gma", "gmb", "gmc", "gmd", "gme", - "gpu", "gpu7", "gpv", "i2cp", "pta", - "rm", "sdio1", "slxk", "spdo", "uac", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap3", "dap4", "dtb", - "dtc", "dte", "slxa", "slxc", "slxd", - "spdi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_csus { - nvidia,pins = "csus", "spia", "spib", "spid", - "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "irrx", "irtx", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "spic", "spig", "uaa", "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", - "spie", "spih", "uad", "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhs", "lsc0", "lspi", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_lcsn { - nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", - "lm0", "lm1", "lpp", "lpw0", "lpw1", - "lpw2", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "lvp1", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006200 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - lvds_ddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - alc5632: alc5632@1e { - compatible = "realtek,alc5632"; - reg = <0x1e>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - nvec@7000c500 { - compatible = "nvidia,nvec"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <80000>; - request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - slave-addr = <138>; - clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&p5valw_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "+1.2vs_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "+1.0vs_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "+3.7vs_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "+1.1vs_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "+1.2vs_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "+3.3vs_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "+2.85vs_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - /* - * Research indicates this should be - * 1.8v; other boards that use this - * rail for the same purpose need it - * set to 1.8v. The schematic signal - * name is incorrect; perhaps copied - * from an incorrect NVIDIA reference. - */ - regulator-name = "+2.85vs_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "+3.3vs_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "+3.3vs_rtc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - adt7461@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,sys-clock-req-active-high; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; - default-brightness-level = <10>; - - backlight-boot-off; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wifi { - label = "wifi-led"; - gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - linux,default-trigger = "rfkill0"; - }; - }; - - panel: panel { - compatible = "samsung,ltn101nt05", "simple-panel"; - - ddc-i2c-bus = <&lvds_ddc>; - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - p5valw_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+5valw"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_pnl_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+3VS,vdd_pnl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-alc5632-paz00", - "nvidia,tegra-audio-alc5632"; - - nvidia,model = "Compal PAZ00"; - - nvidia,audio-routing = - "Int Spk", "SPKOUT", - "Int Spk", "SPKOUTN", - "Headset Mic", "MICBIAS1", - "MIC1", "Headset Mic", - "Headset Stereophone", "HPR", - "Headset Stereophone", "HPL", - "DMICDAT", "Digital Mic"; - - nvidia,audio-codec = <&alc5632>; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-plutux.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-plutux.dts deleted file mode 100644 index a10b415bb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-plutux.dts +++ /dev/null @@ -1,102 +0,0 @@ -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Plutux board"; - compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - sound { - compatible = "ad,tegra-audio-plutux", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design Plutux"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-seaboard.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-seaboard.dts deleted file mode 100644 index 2017acacc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-seaboard.dts +++ /dev/null @@ -1,940 +0,0 @@ -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Seaboard"; - compatible = "nvidia,seaboard", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", - "lsck", "lsda"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lsc0", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap2", - "dap4", "ddc", "dtf", "gma", "gmc", "gmd", - "gme", "gpu", "gpu7", "i2cp", "irrx", - "irtx", "pta", "rm", "sdc", "sdd", - "slxd", "slxk", "spdi", "spdo", "uac", - "uad", "uca", "ucb", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ate { - nvidia,pins = "ate", "csus", "dap3", - "gpv", "owc", "slxc", "spib", "spid", - "spie"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spia", - "spig", "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dte { - nvidia,pins = "dte", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0"; - nvidia,tristate = ; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "spic", "uaa", - "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux_i2cmux_ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux_i2cmux_pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - - state_i2cmux_idle: pinmux_i2cmux_idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - /* ALS and proximity sensor */ - isl29018@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - gyrometer@68 { - compatible = "invn,mpu3050"; - reg = <0x68>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - smart-battery@b { - compatible = "ti,bq20z75", "smart-battery-1.1"; - reg = <0xb>; - ti,i2c-retry-count = <2>; - ti,poll-retry-count = <10>; - }; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0xc>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1125000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <32>; - nvidia,repeat-delay-ms = <160>; - nvidia,ghost-filter; - nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - memory-controller@7000f400 { - emc-table@190000 { - reg = <190000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <190000>; - nvidia,emc-registers = <0x0000000c 0x00000026 - 0x00000009 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x0000059f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000b 0x000000c8 - 0x00000003 0x00000007 0x00000004 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xa06204ae - 0x007dc010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@380000 { - reg = <380000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <380000>; - nvidia,emc-registers = <0x00000017 0x0000004b - 0x00000012 0x00000006 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000b5f - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe044048b - 0x007d8010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - usb@c5000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus_reg>; - dr_mode = "otg"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 2 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - ddc-i2c-bus = <&lvds_ddc>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_vbus_wup1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) 0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_pnl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_hdmi: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-seaboard", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Seaboard"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1R", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-tamonten.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra20-tamonten.dtsi deleted file mode 100644 index 27d2bbbf1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -#include "tegra20.dtsi" - -/ { - model = "Avionic Design Tamonten SOM"; - compatible = "ad,tamonten", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", - "spia", "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtd"; - nvidia,function = "sdio2"; - }; - dtb { - nvidia,pins = "dtb", "dtc", "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uarta"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dtb", "gma", - "gmb", "gmc", "gmd", "gme", "gpu7", - "gpv", "i2cp", "pta", "rm", "slxa", - "slxk", "spia", "spib", "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_crtp { - nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "dtf", "gpu", "sdio1", - "slxc", "slxd", "spdi", "spdo", "spig", - "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dta", "dtd", "kbca", - "kbcb", "kbcc", "kbcd", "kbce", "kbcf", - "sdc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "owc", "sdb"; - nvidia,tristate = ; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "sdd", "spic", - "spie", "spih", "uaa", "uab", "uad", - "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "pmc"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - }; - - state_i2cmux_ddc: pinmux_i2cmux_ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux_i2cmux_pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - - state_i2cmux_idle: pinmux_i2cmux_idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - i2c@7000c000 { - clock-frequency = <400000>; - status = "okay"; - }; - - i2c@7000c400 { - clock-frequency = <100000>; - status = "okay"; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2c@7000d000 { - clock-frequency = <400000>; - status = "okay"; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - /* vdd_5v0_reg must be provided by the base board */ - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "vdd_sys_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sys_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sys_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - pci_clk_reg: ldo0 { - regulator-name = "vdd_ldo0,vddio_pex_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - /* - * According to the Tegra 2 Automotive - * DataSheet, a typical value for this - * would be 2.8V, but the PMIC only - * supports 2.85V. - */ - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; - /* - * According to the Tegra 2 Automotive - * DataSheet, a typical value for this - * would be 2.8V, but the PMIC only - * supports 2.85V. - */ - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - pcie-controller@80003000 { - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000600 { - cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - status = "okay"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - - #address-cells = <1>; - #size-cells = <0>; - - pci_vdd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 0>; - enable-active-high; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-tec.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-tec.dts deleted file mode 100644 index c12d8bead..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-tec.dts +++ /dev/null @@ -1,111 +0,0 @@ -/dts-v1/; - -#include "tegra20-tamonten.dtsi" - -/ { - model = "Avionic Design Tamonten Evaluation Carrier"; - compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - }; - }; - - i2c@7000c000 { - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff - 0xffffffff - 0 - 0xffffffff - 0xffffffff>; - }; - }; - - pcie-controller@80003000 { - status = "okay"; - - pci@1,0 { - status = "okay"; - }; - }; - - sound { - compatible = "ad,tegra-audio-wm8903-tec", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Avionic Design TEC"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; - - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-trimslice.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-trimslice.dts deleted file mode 100644 index 381747f11..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-trimslice.dts +++ /dev/null @@ -1,472 +0,0 @@ -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "Compulab TrimSlice board"; - compatible = "compulab,trimslice", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000c500/rtc@56"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc", "gmb"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gme", "pta"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc", "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "uarta"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ld0", "ld1", "ld2", - "ld3", "ld4", "ld5", "ld6", "ld7", - "ld8", "ld9", "ld10", "ld11", "ld12", - "ld13", "ld14", "ld15", "ld16", "ld17", - "ldc", "ldi", "lhp0", "lhp1", "lhp2", - "lhs", "lm0", "lm1", "lpp", "lpw0", - "lpw1", "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lsdi", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxc { - nvidia,pins = "slxc", "slxd"; - nvidia,function = "sdio3"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "spdif"; - }; - spia { - nvidia,pins = "spia", "spib", "spic"; - nvidia,function = "spi2"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "crtp", "dap2", "dap3", "dap4", "dta", - "dtb", "dtc", "dtd", "dte", "gmb", - "gme", "i2cp", "pta", "slxc", "slxd", - "spdi", "spdo", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_atb { - nvidia,pins = "atb", "cdev1", "cdev2", "dap1", - "gma", "gmc", "gmd", "gpu", "gpu7", - "gpv", "sdio1", "slxa", "slxk", "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_csus { - nvidia,pins = "csus", "spia", "spib", - "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ddc { - nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsc1", "lsck", "lsda", "lsdi", - "lvp0", "pmc"; - nvidia,tristate = ; - }; - conf_irrx { - nvidia,pins = "irrx", "irtx", "kbca", "kbcb", - "kbcc", "kbcd", "kbce", "kbcf", "owc", - "spic", "spie", "spig", "spih", "uaa", - "uab", "uad", "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lspi", "lvp1", - "lvs", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - conf_spif { - nvidia,pins = "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006000 { - status = "okay"; - }; - - dvi_ddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - spi@7000c380 { - status = "okay"; - spi-max-frequency = <48000000>; - spi-flash@0 { - compatible = "winbond,w25q80bl"; - reg = <0>; - spi-max-frequency = <48000000>; - }; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - - codec: codec@1a { - compatible = "ti,tlv320aic23"; - reg = <0x1a>; - }; - - rtc@56 { - compatible = "emmicro,em3027"; - reg = <0x56>; - }; - }; - - pmc@7000e400 { - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - pcie-controller@80003000 { - status = "okay"; - - avdd-pex-supply = <&pci_vdd_reg>; - vdd-pex-supply = <&pci_vdd_reg>; - avdd-pex-pll-supply = <&pci_vdd_reg>; - avdd-plle-supply = <&pci_vdd_reg>; - vddio-pex-clk-supply = <&pci_clk_reg>; - - pci@1,0 { - status = "okay"; - }; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus_reg>; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_vdd_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - hdmi_pll_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vbus_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(V, 2) 0>; - regulator-always-on; - regulator-boot-on; - }; - - pci_clk_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "pci_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - pci_vdd_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "pci_vdd"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-trimslice"; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&codec>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-ventana.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-ventana.dts deleted file mode 100644 index 8f0aaabf7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-ventana.dts +++ /dev/null @@ -1,706 +0,0 @@ -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Ventana evaluation board"; - compatible = "nvidia,ventana", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - serial0 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x40000000>; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - crtp { - nvidia,pins = "crtp", "lm1"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv", "slxa", "slxk"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lpw0", - "lpw2", "lsc0", "lsc1", "lsck", "lsda", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxc"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - slxd { - nvidia,pins = "slxd"; - nvidia,function = "spdif"; - }; - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap2", - "dap4", "ddc", "dtf", "gma", "gmc", - "gme", "gpu", "gpu7", "i2cp", "irrx", - "irtx", "pta", "rm", "sdc", "sdd", - "slxc", "slxd", "slxk", "spdi", "spdo", - "uac", "uad", "uca", "ucb", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ate { - nvidia,pins = "ate", "csus", "dap3", "gmd", - "gpv", "owc", "spia", "spib", "spic", - "spid", "spie", "spig"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp", "gmb", "slxa", "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dte { - nvidia,pins = "dte", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = ; - }; - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "uaa", "uab"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lsc1", "lspi", - "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux_i2cmux_ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux_i2cmux_pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - - state_i2cmux_idle: pinmux_i2cmux_idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006300 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - /* ALS and proximity sensor */ - isl29018@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,sys-clock-req-active-high; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 2 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - ddc-i2c-bus = <&lvds_ddc>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_pnl_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_bl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-ventana", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Ventana"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) - GPIO_ACTIVE_HIGH>; - nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20-whistler.dts b/software/linux/kernel/arch/arm/boot/dts/tegra20-whistler.dts deleted file mode 100644 index 1e06f854c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20-whistler.dts +++ /dev/null @@ -1,636 +0,0 @@ -/dts-v1/; - -#include -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Whistler evaluation board"; - compatible = "nvidia,whistler", "nvidia,tegra20"; - - aliases { - rtc0 = "/i2c@7000d000/max8907@3c"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x00000000 0x20000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata", "atb", "ate", "gma", "gmb", - "gmc", "gmd", "gpu"; - nvidia,function = "gmi"; - }; - atc { - nvidia,pins = "atc", "atd"; - nvidia,function = "sdio4"; - }; - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "osc"; - }; - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,function = "vi"; - }; - dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - }; - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - gme { - nvidia,pins = "gme"; - nvidia,function = "dap5"; - }; - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - gpv { - nvidia,pins = "gpv"; - nvidia,function = "pcie"; - }; - hdint { - nvidia,pins = "hdint", "pta"; - nvidia,function = "hdmi"; - }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - kbca { - nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - kbcb { - nvidia,pins = "kbcb", "kbcd"; - nvidia,function = "sdio2"; - }; - lcsn { - nvidia,pins = "lcsn", "lsck", "lsda", "lsdi", - "spia", "spib", "spic"; - nvidia,function = "spi3"; - }; - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldc", "ldi", - "lhp0", "lhp1", "lhp2", "lhs", "lm0", - "lm1", "lpp", "lpw0", "lpw1", "lpw2", - "lsc0", "lsc1", "lspi", "lvp0", "lvp1", - "lvs"; - nvidia,function = "displaya"; - }; - owc { - nvidia,pins = "owc", "uac"; - nvidia,function = "owr"; - }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxa", - "slxc", "slxd", "slxk"; - nvidia,function = "sdio3"; - }; - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - spdi { - nvidia,pins = "spdi", "spdo"; - nvidia,function = "rsvd2"; - }; - spid { - nvidia,pins = "spid", "spie", "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - spif { - nvidia,pins = "spif"; - nvidia,function = "spi2"; - }; - uaa { - nvidia,pins = "uaa", "uab"; - nvidia,function = "uarta"; - }; - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - uda { - nvidia,pins = "uda"; - nvidia,function = "spi1"; - }; - conf_ata { - nvidia,pins = "ata", "atb", "atc", "ddc", "gma", - "gmb", "gmc", "gmd", "irrx", "irtx", - "kbca", "kbcb", "kbcc", "kbcd", "kbce", - "kbcf", "sdc", "sdd", "spie", "spig", - "spih", "uaa", "uab", "uad", "uca", - "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_atd { - nvidia,pins = "atd", "ate", "cdev1", "csus", - "dap1", "dap2", "dap3", "dap4", "dte", - "dtf", "gpu", "gpu7", "gpv", "i2cp", - "rm", "sdio1", "slxa", "slxc", "slxd", - "slxk", "spdi", "spdo", "uac", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_cdev2 { - nvidia,pins = "cdev2", "spia", "spib"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "lc", "pmca", - "pmcb", "pmcc", "pmcd", "xm2c", - "xm2d"; - nvidia,pull = ; - }; - conf_crtp { - nvidia,pins = "crtp"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", - "spid", "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_gme { - nvidia,pins = "gme", "owc", "pta", "spic"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - conf_ls { - nvidia,pins = "ls", "pmce"; - nvidia,pull = ; - }; - drive_dap1 { - nvidia,pins = "drive_dap1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <0>; - nvidia,pull-up-strength = <0>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - }; - - i2s@70002800 { - status = "okay"; - }; - - serial@70006000 { - status = "okay"; - }; - - hdmi_ddc: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - codec: codec@1a { - compatible = "wlf,wm8753"; - reg = <0x1a>; - }; - - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - max8907@3c { - compatible = "maxim,max8907"; - reg = <0x3c>; - interrupts = ; - - maxim,system-power-controller; - - mbatt-supply = <&usb0_vbus_reg>; - in-v1-supply = <&mbatt_reg>; - in-v2-supply = <&mbatt_reg>; - in-v3-supply = <&mbatt_reg>; - in1-supply = <&mbatt_reg>; - in2-supply = <&nvvdd_sv3_reg>; - in3-supply = <&mbatt_reg>; - in4-supply = <&mbatt_reg>; - in5-supply = <&mbatt_reg>; - in6-supply = <&mbatt_reg>; - in7-supply = <&mbatt_reg>; - in8-supply = <&mbatt_reg>; - in9-supply = <&mbatt_reg>; - in10-supply = <&mbatt_reg>; - in11-supply = <&mbatt_reg>; - in12-supply = <&mbatt_reg>; - in13-supply = <&mbatt_reg>; - in14-supply = <&mbatt_reg>; - in15-supply = <&mbatt_reg>; - in16-supply = <&mbatt_reg>; - in17-supply = <&nvvdd_sv3_reg>; - in18-supply = <&nvvdd_sv3_reg>; - in19-supply = <&mbatt_reg>; - in20-supply = <&mbatt_reg>; - - regulators { - mbatt_reg: mbatt { - regulator-name = "vbat_pmu"; - regulator-always-on; - }; - - sd1 { - regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sd2 { - regulator-name = "nvvdd_sv2,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - nvvdd_sv3_reg: sd3 { - regulator-name = "nvvdd_sv3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1 { - regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo2 { - regulator-name = "nvvdd_ldo2,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3 { - regulator-name = "nvvdd_ldo3,vcom_1v8b"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "nvvdd_ldo4,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo5 { - regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - hdmi_pll_reg: ldo6 { - regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo7 { - regulator-name = "nvvdd_ldo7,avddio_audio"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo8 { - regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo9 { - regulator-name = "nvvdd_ldo9,avdd_cam*"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - hdmi_vdd_reg: ldo11 { - regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo12 { - regulator-name = "nvvdd_ldo12,vddio_sdio"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo13 { - regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo14 { - regulator-name = "nvvdd_ldo14,avdd_vdac"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo15 { - regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16 { - regulator-name = "nvvdd_ldo16,vdd_dbrtr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - ldo17 { - regulator-name = "nvvdd_ldo17,vddio_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18 { - regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19 { - regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo20 { - regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - out5v { - regulator-name = "usb0_vbus_reg"; - }; - - out33v { - regulator-name = "pmu_out3v3"; - }; - - bbat { - regulator-name = "pmu_bbat"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2400000>; - regulator-always-on; - }; - - sdby { - regulator-name = "vdd_aon"; - regulator-always-on; - }; - - vrtc { - regulator-name = "vrtc,pmu_vccadc"; - regulator-always-on; - }; - }; - }; - }; - - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <20>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2>; - nvidia,kbc-col-pins = <16 17>; - wakeup-source; - linux,keymap = ; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <1000>; - nvidia,core-pwr-good-time = <0 3845>; - nvidia,core-pwr-off-time = <93727>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,combined-power-req; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus1_reg>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - vbus-supply = <&vbus3_reg>; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - bus-width = <8>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb0_vbus_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vbus1_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ - regulator-always-on; - regulator-boot-on; - }; - - vbus3_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vbus3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ - regulator-always-on; - regulator-boot-on; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8753-whistler", - "nvidia,tegra-audio-wm8753"; - nvidia,model = "NVIDIA Tegra Whistler"; - - nvidia,audio-routing = - "Headphone Jack", "LOUT1", - "Headphone Jack", "ROUT1", - "MIC2", "Mic Jack", - "MIC2N", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&codec>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra20.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra20.dtsi deleted file mode 100644 index 2207c08e3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra20.dtsi +++ /dev/null @@ -1,795 +0,0 @@ -#include -#include -#include -#include - -#include "skeleton.dtsi" - -/ { - compatible = "nvidia,tegra20"; - interrupt-parent = <&lic>; - - host1x@50000000 { - compatible = "nvidia,tegra20-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA20_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe@54040000 { - compatible = "nvidia,tegra20-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&tegra_car 60>; - reset-names = "mpe"; - }; - - vi@54080000 { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_VI>; - resets = <&tegra_car 20>; - reset-names = "vi"; - }; - - epp@540c0000 { - compatible = "nvidia,tegra20-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_EPP>; - resets = <&tegra_car 19>; - reset-names = "epp"; - }; - - isp@54100000 { - compatible = "nvidia,tegra20-isp"; - reg = <0x54100000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_ISP>; - resets = <&tegra_car 23>; - reset-names = "isp"; - }; - - gr2d@54140000 { - compatible = "nvidia,tegra20-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; - }; - - dc@54200000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_DISP1>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - nvidia,head = <0>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_DISP2>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - nvidia,head = <1>; - - rgb { - status = "disabled"; - }; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra20-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_HDMI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - tvo@542c0000 { - compatible = "nvidia,tegra20-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_TVO>; - status = "disabled"; - }; - - dsi@54300000 { - compatible = "nvidia,tegra20-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_DSI>; - resets = <&tegra_car 48>; - reset-names = "dsi"; - status = "disabled"; - }; - }; - - timer@50040600 { - compatible = "arm,cortex-a9-twd-timer"; - interrupt-parent = <&intc>; - reg = <0x50040600 0x20>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_TWD>; - }; - - intc: interrupt-controller@50041000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <5 5 2>; - arm,tag-latency = <4 4 2>; - cache-unified; - cache-level = <2>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra20-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - timer@60005000 { - compatible = "nvidia,tegra20-timer"; - reg = <0x60005000 0x60>; - interrupts = , - , - , - ; - clocks = <&tegra_car TEGRA20_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra20-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1200>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA20_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb@6000c000 { - compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra20-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - /* - gpio-ranges = <&pinmux 0 0 224>; - */ - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000014 { - compatible = "nvidia,tegra20-pinmux"; - reg = <0x70000014 0x10 /* Tri-state registers */ - 0x70000080 0x20 /* Mux registers */ - 0x700000a0 0x14 /* Pull-up/down registers */ - 0x70000868 0xa8>; /* Pad control registers */ - }; - - das@70000c00 { - compatible = "nvidia,tegra20-das"; - reg = <0x70000c00 0x80>; - }; - - tegra_ac97: ac97@70002000 { - compatible = "nvidia,tegra20-ac97"; - reg = <0x70002000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_AC97>; - resets = <&tegra_car 3>; - reset-names = "ac97"; - dmas = <&apbdma 12>, <&apbdma 12>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70002800 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002800 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - dmas = <&apbdma 2>, <&apbdma 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70002a00 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002a00 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - dmas = <&apbdma 1>, <&apbdma 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra20-uart" and to enable the APB DMA based serial - * driver, the compatible is "nvidia,tegra20-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uarte: serial@70006400 { - compatible = "nvidia,tegra20-uart"; - reg = <0x70006400 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_UARTE>; - resets = <&tegra_car 66>; - reset-names = "serial"; - dmas = <&apbdma 20>, <&apbdma 20>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA20_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_RTC>; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C1>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000c380 { - compatible = "nvidia,tegra20-sflash"; - reg = <0x7000c380 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SPI>; - resets = <&tegra_car 43>; - reset-names = "spi"; - dmas = <&apbdma 11>, <&apbdma 11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C2>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra20-i2c-dvc"; - reg = <0x7000d000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_DVC>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC1>; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC2>; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC3>; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA20_CLK_SBC4>; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra20-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc"; - reg = <0x7000f000 0x024 - 0x7000f03c 0x3c4>; - interrupts = ; - }; - - iommu@7000f024 { - compatible = "nvidia,tegra20-gart"; - reg = <0x7000f024 0x00000018 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ - }; - - memory-controller@7000f400 { - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; - #address-cells = <1>; - #size-cells = <0>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - pcie-controller@80003000 { - compatible = "nvidia,tegra20-pcie"; - device_type = "pci"; - reg = <0x80003000 0x00000800 /* PADS registers */ - 0x80003800 0x00000200 /* AFI registers */ - 0x90000000 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ - 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ - 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ - - clocks = <&tegra_car TEGRA20_CLK_PEX>, - <&tegra_car TEGRA20_CLK_AFI>, - <&tegra_car TEGRA20_CLK_PLL_E>; - clock-names = "pex", "afi", "pll_e"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - }; - - usb@c5000000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - nvidia,has-legacy-mode; - clocks = <&tegra_car TEGRA20_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,needs-double-reset; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@c5000000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5000000 0x4000 0xc5000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USBD>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CLK_M>, - <&tegra_car TEGRA20_CLK_USBD>; - clock-names = "reg", "pll_u", "timer", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,has-legacy-mode; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <1>; - nvidia,xcvr-lsrslew = <1>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@c5004000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5004000 0x4000>; - interrupts = ; - phy_type = "ulpi"; - clocks = <&tegra_car TEGRA20_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@c5004000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5004000 0x4000>; - phy_type = "ulpi"; - clocks = <&tegra_car TEGRA20_CLK_USB2>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CDEV2>; - clock-names = "reg", "pll_u", "ulpi-link"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - status = "disabled"; - }; - - usb@c5008000 { - compatible = "nvidia,tegra20-ehci", "usb-ehci"; - reg = <0xc5008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@c5008000 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5008000 0x4000 0xc5000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA20_CLK_USB3>, - <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_CLK_M>, - <&tegra_car TEGRA20_CLK_USBD>; - clock-names = "reg", "pll_u", "timer", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - status = "disabled"; - }; - - sdhci@c8000000 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@c8000200 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@c8000400 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@c8000600 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30-apalis-eval.dts b/software/linux/kernel/arch/arm/boot/dts/tegra30-apalis-eval.dts deleted file mode 100644 index 99a69457d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ /dev/null @@ -1,273 +0,0 @@ -/dts-v1/; - -#include -#include "tegra30-apalis.dtsi" - -/ { - model = "Toradex Apalis T30 on Apalis Evaluation Board"; - compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/tps65911@2d"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - pcie-controller@00003000 { - status = "okay"; - - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - - pci@3,0 { - status = "okay"; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - hdmi@54280000 { - status = "okay"; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; - }; - - /* GEN2_I2C: unused */ - - /* - * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on - * carrier board) - */ - cami2c: i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ - hdmiddc: i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Apalis SPI1 */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - spidev0: spidev@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <25000000>; - }; - }; - - /* SPI5: Apalis SPI2 */ - spi@7000dc00 { - status = "okay"; - spi-max-frequency = <25000000>; - spidev1: spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - }; - }; - - hda@70030000 { - status = "okay"; - }; - - sd1: sdhci@78000000 { - status = "okay"; - bus-width = <4>; - /* SD1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - mmc1: sdhci@78000400 { - status = "okay"; - bus-width = <8>; - /* MMC1_CD# */ - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - dr_mode = "otg"; - vbus-supply = <&usbo1_vbus_reg>; - }; - - /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <&usbh_vbus_reg>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&usbh_vbus_reg>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - /* PWM_BKL1 */ - pwms = <&pwm 0 5000000>; - brightness-levels = <255 231 223 207 191 159 127 0>; - default-brightness-level = <6>; - /* BKL1_ON */ - enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "WAKE1_MICO"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu", "simple-panel"; - - backlight = <&backlight>; - }; - - pwmleds { - compatible = "pwm-leds"; - - pwm1 { - label = "PWM1"; - pwms = <&pwm 3 19600>; - max-brightness = <255>; - }; - - pwm2 { - label = "PWM2"; - pwms = <&pwm 2 19600>; - max-brightness = <255>; - }; - - pwm3 { - label = "PWM3"; - pwms = <&pwm 1 19600>; - max-brightness = <255>; - }; - }; - - regulators { - sys_5v0_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - /* USBO1_EN */ - usbo1_vbus_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usbo1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&sys_5v0_reg>; - }; - - /* USBH_EN */ - usbh_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usbh_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&sys_5v0_reg>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30-apalis.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra30-apalis.dtsi deleted file mode 100644 index 192b95177..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30-apalis.dtsi +++ /dev/null @@ -1,736 +0,0 @@ -#include "tegra30.dtsi" - -/* - * Toradex Apalis T30 Module Device Tree - * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A; - * 2GB: V1.0B, V1.0C, V1.0E, V1.1A - */ -/ { - model = "Toradex Apalis T30"; - compatible = "toradex,apalis_t30", "nvidia,tegra30"; - - pcie-controller@00003000 { - avdd-pexa-supply = <&vdd2_reg>; - vdd-pexa-supply = <&vdd2_reg>; - avdd-pexb-supply = <&vdd2_reg>; - vdd-pexb-supply = <&vdd2_reg>; - avdd-pex-pll-supply = <&vdd2_reg>; - avdd-plle-supply = <&ldo6_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; - hvdd-pex-supply = <&sys_3v3_reg>; - - pci@1,0 { - nvidia,num-lanes = <4>; - }; - - pci@2,0 { - nvidia,num-lanes = <1>; - }; - - pci@3,0 { - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - vdd-supply = <&avdd_hdmi_3v3_reg>; - pll-supply = <&avdd_hdmi_pll_1v8_reg>; - - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmiddc>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Apalis BKL1_ON */ - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis BKL1_PWM */ - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis CAN1 on SPI6 */ - spi2_cs0_n_px3 { - nvidia,pins = "spi2_cs0_n_px3", - "spi2_miso_px1", - "spi2_mosi_px0", - "spi2_sck_px2"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* CAN_INT1 */ - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis CAN2 on SPI4 */ - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* CAN_INT2 */ - spi2_cs2_n_pw3 { - nvidia,pins = "spi2_cs2_n_pw3"; - nvidia,function = "spi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis Digital Audio */ - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0", - "dap1_din_pn1", - "dap1_dout_pn2", - "dap1_sclk_pn3"; - nvidia,function = "hda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis I2C3 */ - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - - /* Apalis MMC1 */ - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6", - "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "sdmmc3_dat4_pd1", - "sdmmc3_dat5_pd0", - "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis MMC1_CD# */ - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis PWM1 */ - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM2 */ - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM3 */ - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis PWM4 */ - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis RESET_MOCI# */ - gmi_rst_n_pi4 { - nvidia,pins = "gmi_rst_n_pi4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SD1 */ - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - /* Apalis SD1_CD# */ - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis SPI1 */ - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5", - "spi1_mosi_px4", - "spi1_miso_px7", - "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis SPI2 */ - lcd_sck_pz4 { - nvidia,pins = "lcd_sck_pz4", - "lcd_sdout_pn5", - "lcd_sdin_pz2", - "lcd_cs0_n_pn4"; - nvidia,function = "spi5"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART1 */ - ulpi_data0 { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART2 */ - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART3 */ - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis UART4 */ - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBO1_EN */ - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Apalis USBO1_OC# */ - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "rsvd4"; - nvidia,open-drain = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Apalis WAKE1_MICO */ - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* eMMC (On-module) */ - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* LVDS Transceiver Configuration */ - pbb0 { - nvidia,pins = "pbb0", - "pbb7", - "pcc1", - "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb4", - "pbb5", - "pbb6"; - nvidia,function = "displayb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - }; - - /* Power I2C (On-module) */ - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - - /* - * THERMD_ALERT#, unlatched I2C address pin of LM95245 - * temperature sensor therefore requires disabling for - * now - */ - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_PEN_INT# */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - hdmiddc: i2c@7000c700 { - clock-frequency = <100000>; - }; - - /* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&sys_3v3_reg>; - vcc2-supply = <&sys_3v3_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&sys_3v3_reg>; - vcc5-supply = <&sys_3v3_reg>; - vcc6-supply = <&vio_reg>; - vcc7-supply = <&charge_pump_5v0_reg>; - vccio-supply = <&sys_3v3_reg>; - - regulators { - /* SW1: +V1.35_VDDIO_DDR */ - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - /* SW2: +V1.05 */ - vdd2_reg: vdd2 { - regulator-name = - "vdd_pexa,vdd_pexb,vdd_sata"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* SW CTRL: +V1.0_VDD_CPU */ - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - /* SWIO: +V1.8 */ - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO1: unused */ - - /* - * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN - * see also v3_3 fixed supply - */ - ldo2_reg: ldo2 { - regulator-name = "en_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* +V1.2_CSI */ - ldo3_reg: ldo3 { - regulator-name = - "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - /* +V1.2_VDD_RTC */ - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* - * +V2.8_AVDD_VDAC: - * only required for analog RGB - */ - ldo5_reg: ldo5 { - regulator-name = "avdd_vdac"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - /* - * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V - * but LDO6 can't set voltage in 50mV - * granularity - */ - ldo6_reg: ldo6 { - regulator-name = "avdd_plle"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - /* +V1.2_AVDD_PLL */ - ldo7_reg: ldo7 { - regulator-name = "avdd_pll"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* +V1.0_VDD_DDR_HS */ - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - /* STMPE811 touch screen controller */ - stmpe811@41 { - compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - interrupts = ; - interrupt-parent = <&gpio>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - - stmpe_touchscreen@0 { - compatible = "st,stmpe-ts"; - reg = <0>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - }; - - /* - * LM95245 temperature sensor - * Note: OVERT_N directly connected to PMIC PWRDN - */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - - /* SW: +V1.2_VDD_CORE */ - tps62362@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - - regulator-name = "tps62362-vout"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; - }; - }; - - /* SPI4: CAN2 */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - /* SPI6: CAN1 */ - spi@7000de00 { - status = "okay"; - spi-max-frequency = <10000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clk@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - clk16m: clk@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "clk16m"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - avdd_hdmi_pll_1v8_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; - - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - avdd_hdmi_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - charge_pump_5v0_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30-beaver.dts b/software/linux/kernel/arch/arm/boot/dts/tegra30-beaver.dts deleted file mode 100644 index 035000284..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30-beaver.dts +++ /dev/null @@ -1,2109 +0,0 @@ -/dts-v1/; - -#include "tegra30.dtsi" - -/ { - model = "NVIDIA Tegra30 Beaver evaluation board"; - compatible = "nvidia,beaver", "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000d000/tps65911@2d"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x80000000 0x7ff00000>; - }; - - pcie-controller@00003000 { - status = "okay"; - - avdd-pexa-supply = <&ldo1_reg>; - vdd-pexa-supply = <&ldo1_reg>; - avdd-pexb-supply = <&ldo1_reg>; - vdd-pexb-supply = <&ldo1_reg>; - avdd-pex-pll-supply = <&ldo1_reg>; - avdd-plle-supply = <&ldo1_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; - hvdd-pex-supply = <&sys_3v3_pexs_reg>; - - pci@1,0 { - status = "okay"; - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - nvidia,num-lanes = <2>; - }; - - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <2>; - }; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - vdd-supply = <&sys_3v3_reg>; - pll-supply = <&vio_reg>; - - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmiddc>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a18_pb1 { - nvidia,pins = "gmi_a18_pb1"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr0_pb2 { - nvidia,pins = "lcd_pwr0_pb2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pclk_pb3 { - nvidia,pins = "lcd_pclk_pb3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_pwr1_pc1 { - nvidia,pins = "lcd_pwr1_pc1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_pwr2_pc6 { - nvidia,pins = "lcd_pwr2_pc6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wp_n_pc7 { - nvidia,pins = "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat5_pd0 { - nvidia,pins = "sdmmc3_dat5_pd0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat4_pd1 { - nvidia,pins = "sdmmc3_dat4_pd1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat6_pd3 { - nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_dat7_pd4 { - nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d1_pd5 { - nvidia,pins = "vi_d1_pd5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_hsync_pd7 { - nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d0_pe0 { - nvidia,pins = "lcd_d0_pe0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d1_pe1 { - nvidia,pins = "lcd_d1_pe1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d2_pe2 { - nvidia,pins = "lcd_d2_pe2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d3_pe3 { - nvidia,pins = "lcd_d3_pe3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d4_pe4 { - nvidia,pins = "lcd_d4_pe4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d5_pe5 { - nvidia,pins = "lcd_d5_pe5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d6_pe6 { - nvidia,pins = "lcd_d6_pe6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d7_pe7 { - nvidia,pins = "lcd_d7_pe7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d8_pf0 { - nvidia,pins = "lcd_d8_pf0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d9_pf1 { - nvidia,pins = "lcd_d9_pf1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d10_pf2 { - nvidia,pins = "lcd_d10_pf2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d11_pf3 { - nvidia,pins = "lcd_d11_pf3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d12_pf4 { - nvidia,pins = "lcd_d12_pf4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d13_pf5 { - nvidia,pins = "lcd_d13_pf5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d14_pf6 { - nvidia,pins = "lcd_d14_pf6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d15_pf7 { - nvidia,pins = "lcd_d15_pf7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad1_pg1 { - nvidia,pins = "gmi_ad1_pg1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad3_pg3 { - nvidia,pins = "gmi_ad3_pg3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad4_pg4 { - nvidia,pins = "gmi_ad4_pg4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad7_pg7 { - nvidia,pins = "gmi_ad7_pg7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad8_ph0 { - nvidia,pins = "gmi_ad8_ph0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad11_ph3 { - nvidia,pins = "gmi_ad11_ph3"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad13_ph5 { - nvidia,pins = "gmi_ad13_ph5"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_ad14_ph6 { - nvidia,pins = "gmi_ad14_ph6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wr_n_pi0 { - nvidia,pins = "gmi_wr_n_pi0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_oe_n_pi1 { - nvidia,pins = "gmi_oe_n_pi1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_dqs_pi2 { - nvidia,pins = "gmi_dqs_pi2"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_iordy_pi5 { - nvidia,pins = "gmi_iordy_pi5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs7_n_pi6 { - nvidia,pins = "gmi_cs7_n_pi6"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_wait_pi7 { - nvidia,pins = "gmi_wait_pi7"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_de_pj1 { - nvidia,pins = "lcd_de_pj1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_hsync_pj3 { - nvidia,pins = "lcd_hsync_pj3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_vsync_pj4 { - nvidia,pins = "lcd_vsync_pj4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_clk_pk1 { - nvidia,pins = "gmi_clk_pk1"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs2_n_pk3 { - nvidia,pins = "gmi_cs2_n_pk3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "nand"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d2_pl0 { - nvidia,pins = "vi_d2_pl0"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d3_pl1 { - nvidia,pins = "vi_d3_pl1"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d5_pl3 { - nvidia,pins = "vi_d5_pl3"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d7_pl5 { - nvidia,pins = "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d9_pl7 { - nvidia,pins = "vi_d9_pl7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d16_pm0 { - nvidia,pins = "lcd_d16_pm0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d17_pm1 { - nvidia,pins = "lcd_d17_pm1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d18_pm2 { - nvidia,pins = "lcd_d18_pm2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d19_pm3 { - nvidia,pins = "lcd_d19_pm3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d20_pm4 { - nvidia,pins = "lcd_d20_pm4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d21_pm5 { - nvidia,pins = "lcd_d21_pm5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d22_pm6 { - nvidia,pins = "lcd_d22_pm6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_d23_pm7 { - nvidia,pins = "lcd_d23_pm7"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs0_n_pn4 { - nvidia,pins = "lcd_cs0_n_pn4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdout_pn5 { - nvidia,pins = "lcd_sdout_pn5"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_dc0_pn6 { - nvidia,pins = "lcd_dc0_pn6"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_pclk_pt0 { - nvidia,pins = "vi_pclk_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_mclk_pt1 { - nvidia,pins = "vi_mclk_pt1"; - nvidia,function = "vi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d11_pt3 { - nvidia,pins = "vi_d11_pt3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - vi_d0_pt4 { - nvidia,pins = "vi_d0_pt4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "pwm2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - jtag_rtck_pu7 { - nvidia,pins = "jtag_rtck_pu7"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pv3 { - nvidia,pins = "pv3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_hsync_pv6 { - nvidia,pins = "crt_hsync_pv6"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - crt_vsync_pv7 { - nvidia,pins = "crt_vsync_pv7"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_cs1_n_pw0 { - nvidia,pins = "lcd_cs1_n_pw0"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_m1_pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_cs1_n_pw2 { - nvidia,pins = "spi2_cs1_n_pw2"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi2_sck_px2 { - nvidia,pins = "spi2_sck_px2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_mosi_px4 { - nvidia,pins = "spi1_mosi_px4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_sck_px5 { - nvidia,pins = "spi1_sck_px5"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_cs0_n_px6 { - nvidia,pins = "spi1_cs0_n_px6"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spi1_miso_px7 { - nvidia,pins = "spi1_miso_px7"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sdin_pz2 { - nvidia,pins = "lcd_sdin_pz2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_wr_n_pz3 { - nvidia,pins = "lcd_wr_n_pz3"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_sck_pz4 { - nvidia,pins = "lcd_sck_pz4"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "vgp5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "vgp6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "i2s4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_rst_n_pcc3 { - nvidia,pins = "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_rst_n_pcc6 { - nvidia,pins = "pex_l2_rst_n_pcc6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_clkreq_n_pcc7 { - nvidia,pins = "pex_l2_clkreq_n_pcc7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_prsnt_n_pdd0 { - nvidia,pins = "pex_l0_prsnt_n_pdd0"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_rst_n_pdd1 { - nvidia,pins = "pex_l0_rst_n_pdd1"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l0_clkreq_n_pdd2 { - nvidia,pins = "pex_l0_clkreq_n_pdd2"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_wake_n_pdd3 { - nvidia,pins = "pex_wake_n_pdd3"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_prsnt_n_pdd4 { - nvidia,pins = "pex_l1_prsnt_n_pdd4"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_rst_n_pdd5 { - nvidia,pins = "pex_l1_rst_n_pdd5"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l1_clkreq_n_pdd6 { - nvidia,pins = "pex_l1_clkreq_n_pdd6"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pex_l2_prsnt_n_pdd7 { - nvidia,pins = "pex_l2_prsnt_n_pdd7"; - nvidia,function = "pcie"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "dev3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2"; - nvidia,function = "dap"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; - }; - gpv { - nvidia,pins = "drive_gpv"; - nvidia,pull-up-strength = <16>; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - hdmiddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; - }; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_5v_in_reg>; - vcc2-supply = <&vdd_5v_in_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&vdd_5v_in_reg>; - vcc5-supply = <&vdd_5v_in_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_5v_in_reg>; - vccio-supply = <&vdd_5v_in_reg>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@1 { - compatible = "winbond,w25q32"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - sdhci@78000000 { - status = "okay"; - vqmmc-supply = <&ldo5_reg>; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d004000 { - status = "okay"; - }; - - phy2: usb-phy@7d004000 { - vbus-supply = <&sys_3v3_reg>; - status = "okay"; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - gpled1 { - label = "LED1"; /* CR5A1 (blue) */ - gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; - }; - gpled2 { - label = "LED2"; /* CR4A2 (green) */ - gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v_in_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v_in"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - chargepump_5v_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "chargepump_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - ddr_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - vdd_5v_sata_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_5v_sata"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - usb1_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; - - usb3_vbus_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; - - sys_3v3_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "sys_3v3,vdd_3v3_alw"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; - - sys_3v3_pexs_reg: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "sys_3v3_pexs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_5v0_hdmi: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+VDD_5V_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&sys_3v3_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-beaver", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Beaver"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu-a02.dts deleted file mode 100644 index c9bfedcca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ /dev/null @@ -1,94 +0,0 @@ -/dts-v1/; - -#include "tegra30-cardhu.dtsi" - -/* This dts file support the cardhu A02 version of board */ - -/ { - model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; - compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - ddr_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; - - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - usb3_vbus_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - vdd_5v0_reg: regulator@104 { - compatible = "regulator-fixed"; - reg = <104>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_bl_reg: regulator@105 { - compatible = "regulator-fixed"; - reg = <105>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; - }; - }; -}; - diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu-a04.dts deleted file mode 100644 index fadf55e46..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ /dev/null @@ -1,105 +0,0 @@ -/dts-v1/; - -#include "tegra30-cardhu.dtsi" - -/* This dts file support the cardhu A04 and later versions of board */ - -/ { - model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; - compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - ddr_reg: regulator@100 { - compatible = "regulator-fixed"; - regulator-name = "ddr"; - reg = <100>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; - - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; - - usb1_vbus_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - usb3_vbus_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - - vdd_5v0_reg: regulator@104 { - compatible = "regulator-fixed"; - reg = <104>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_bl_reg: regulator@105 { - compatible = "regulator-fixed"; - reg = <105>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; - }; - - vdd_bl2_reg: regulator@106 { - compatible = "regulator-fixed"; - reg = <106>; - regulator-name = "vdd_bl2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu.dtsi deleted file mode 100644 index f11012bb5..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ /dev/null @@ -1,650 +0,0 @@ -#include -#include "tegra30.dtsi" - -/** - * This file contains common DT entry for all fab version of Cardhu. - * There is multiple fab version of Cardhu starting from A01 to A07. - * Cardhu fab version A01 and A03 are not supported. Cardhu fab version - * A02 will have different sets of GPIOs for fixed regulator compare to - * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are - * compatible with fab version A04. Based on Cardhu fab version, the - * related dts file need to be chosen like for Cardhu fab version A02, - * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use - * tegra30-cardhu-a04.dts. - * The identification of board is done in two ways, by looking the sticker - * on PCB and by reading board id eeprom. - * The sticker will have number like 600-81291-1000-002 C.3. In this 4th - * number is the fab version like here it is 002 and hence fab version A02. - * The (downstream internal) U-Boot of Cardhu display the board-id as - * follows: - * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 - * In this Fab version is 02 i.e. A02. - * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). - * The location 0x8 of this eeprom contains the Fab version. It is 1 byte - * wide. - */ - -/ { - model = "NVIDIA Tegra30 Cardhu evaluation board"; - compatible = "nvidia,cardhu", "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000d000/tps65911@2d"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x80000000 0x40000000>; - }; - - pcie-controller@00003000 { - status = "okay"; - - /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ - avdd-pexb-supply = <&ldo1_reg>; - vdd-pexb-supply = <&ldo1_reg>; - avdd-pex-pll-supply = <&ldo1_reg>; - hvdd-pex-supply = <&pex_hvdd_3v3_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; - avdd-plle-supply = <&ldo2_reg>; - - pci@1,0 { - nvidia,num-lanes = <4>; - }; - - pci@2,0 { - nvidia,num-lanes = <1>; - }; - - pci@3,0 { - status = "okay"; - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - nvidia,panel = <&panel>; - }; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <46>; - nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6", - "uart3_cts_n_pa1", - "uart3_rts_n_pc0", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - panelddc: i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - - /* ALS and Proximity sensor */ - isl29028@44 { - compatible = "isil,isl29028"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - i2cmux@70 { - compatible = "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - }; - }; - - i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_ac_bat_reg>; - vcc2-supply = <&vdd_ac_bat_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&vdd_5v0_reg>; - vcc5-supply = <&vdd_ac_bat_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_ac_bat_reg>; - vccio-supply = <&vdd_ac_bat_reg>; - - regulators { - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: vdd2 { - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2_reg: ldo2 { - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-name = "vddio_sdmmc,avdd_vdac"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7_reg: ldo7 { - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - - tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - }; - - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@1 { - compatible = "winbond,w25q32"; - reg = <1>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@7000e400 { - status = "okay"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - - sdhci@78000000 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - vbus-supply = <&usb3_vbus_reg>; - status = "okay"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_bl_reg>; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - panel: panel { - compatible = "chunghwa,claa101wb01", "simple-panel"; - ddc-i2c-bus = <&panelddc>; - - power-supply = <&vdd_pnl1_reg>; - enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - cam_1v8_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "cam_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; - - cp_5v_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "cp_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - - emmc_3v3_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "emmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - modem_3v3_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "modem_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - }; - - pex_hvdd_3v3_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "pex_hvdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam1_ldo_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd_cam1_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam2_ldo_reg: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "vdd_cam2_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_cam3_ldo_reg: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "vdd_cam3_ldo"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_com_reg: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "vdd_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_fuse_3v3_reg: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "vdd_fuse_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_pnl1_reg: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "vdd_pnl1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - vdd_vid_reg: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "vddio_vid"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-cardhu", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Cardhu"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - interrupt-parent = <&pmic>; - interrupts = <2 0>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/software/linux/kernel/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts deleted file mode 100644 index a8c031874..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ /dev/null @@ -1,213 +0,0 @@ -/dts-v1/; - -#include "tegra30-colibri.dtsi" - -/ { - model = "Toradex Colibri T30 on Colibri Evaluation Board"; - compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30"; - - aliases { - rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/tps65911@2d"; - rtc2 = "/rtc@7000e000"; - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartd; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - nvidia,panel = <&panel>; - }; - }; - hdmi@54280000 { - status = "okay"; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - /* - * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier - * board) - */ - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - /* M41T0M6 real time clock on carrier board */ - rtc@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; - }; - - /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - hdmiddc: i2c@7000c700 { - status = "okay"; - }; - - /* SPI1: Colibri SSP */ - spi@7000d400 { - status = "okay"; - spi-max-frequency = <25000000>; - can0: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - interrupts = ; - spi-max-frequency = <10000000>; - }; - spidev0: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <25000000>; - }; - }; - - /* SD/MMC */ - sdhci@78000200 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; - no-1-8-v; - }; - - /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - dr_mode = "otg"; - vbus-supply = <&usbc_vbus_reg>; - }; - - /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&usbh_vbus_reg>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - /* PWM */ - pwms = <&pwm 0 5000000>; - brightness-levels = <255 128 64 32 16 8 4 0>; - default-brightness-level = <6>; - /* BL_ON */ - enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; - }; - - clocks { - clk16m: clk@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "clk16m"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wakeup { - label = "SODIMM pin 45 wakeup"; - gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu", "simple-panel"; - - backlight = <&backlight>; - }; - - pwmleds { - compatible = "pwm-leds"; - - pwmb { - label = "PWM"; - pwms = <&pwm 1 19600>; - max-brightness = <255>; - }; - pwmc { - label = "PWM"; - pwms = <&pwm 2 19600>; - max-brightness = <255>; - }; - pwmd { - label = "PWM"; - pwms = <&pwm 3 19600>; - max-brightness = <255>; - }; - }; - - regulators { - sys_5v0_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - usbc_vbus_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usbc_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&sys_5v0_reg>; - }; - - /* USBH_PEN */ - usbh_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usbh_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - vin-supply = <&sys_5v0_reg>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30-colibri.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra30-colibri.dtsi deleted file mode 100644 index a265534cd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30-colibri.dtsi +++ /dev/null @@ -1,474 +0,0 @@ -#include -#include "tegra30.dtsi" - -/* - * Toradex Colibri T30 Module Device Tree - * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A - */ -/ { - model = "Toradex Colibri T30"; - compatible = "toradex,colibri_t30", "nvidia,tegra30"; - - memory { - reg = <0x80000000 0x40000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - vdd-supply = <&avdd_hdmi_3v3_reg>; - pll-supply = <&avdd_hdmi_pll_1v8_reg>; - - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmiddc>; - }; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - /* Colibri BL_ON */ - pv2 { - nvidia,pins = "pv2"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri Backlight PWM */ - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri CAN_INT */ - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* - * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE - * todays display need DE, disable LCD_M1 - */ - lcd_m1_pw1 { - nvidia,pins = "lcd_m1_pw1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* Colibri MMC */ - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3", - "kb_row12_ps4", - "kb_row13_ps5", - "kb_row14_ps6", - "kb_row15_ps7"; - nvidia,function = "sdmmc2"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri SSP */ - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc3_dat6_pd3 { - nvidia,pins = "sdmmc3_dat6_pd3", - "sdmmc3_dat7_pd4"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART_A */ - ulpi_data0 { - nvidia,pins = "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART_B */ - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7", - "gmi_a17_pb0", - "gmi_a18_pb1", - "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Colibri UART_C */ - uart2_rxd { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* eMMC */ - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - /* Power I2C (On-module) */ - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - - /* - * THERMD_ALERT#, unlatched I2C address pin of LM95245 - * temperature sensor therefore requires disabling for - * now - */ - lcd_dc1_pd2 { - nvidia,pins = "lcd_dc1_pd2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - - /* TOUCH_PEN_INT# */ - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - hdmiddc: i2c@7000c700 { - clock-frequency = <100000>; - }; - - /* - * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller - */ - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&sys_3v3_reg>; - vcc2-supply = <&sys_3v3_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&sys_3v3_reg>; - vcc5-supply = <&sys_3v3_reg>; - vcc6-supply = <&vio_reg>; - vcc7-supply = <&charge_pump_5v0_reg>; - vccio-supply = <&sys_3v3_reg>; - - regulators { - /* SW1: +V1.35_VDDIO_DDR */ - vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - /* SW2: unused */ - - /* SW CTRL: +V1.0_VDD_CPU */ - vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - }; - - /* SWIO: +V1.8 */ - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - /* LDO1: unused */ - - /* - * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN - * see also 3v3 fixed supply - */ - ldo2_reg: ldo2 { - regulator-name = "en_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - /* LDO3: unused */ - - /* +V1.2_VDD_RTC */ - ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* - * +V2.8_AVDD_VDAC: - * only required for analog RGB - */ - ldo5_reg: ldo5 { - regulator-name = "avdd_vdac"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - /* - * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V - * but LDO6 can't set voltage in 50mV - * granularity - */ - ldo6_reg: ldo6 { - regulator-name = "avdd_plle"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - /* +V1.2_AVDD_PLL */ - ldo7_reg: ldo7 { - regulator-name = "avdd_pll"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - /* +V1.0_VDD_DDR_HS */ - ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - - /* STMPE811 touch screen controller */ - stmpe811@41 { - compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x41>; - interrupts = ; - interrupt-parent = <&gpio>; - interrupt-controller; - id = <0>; - blocks = <0x5>; - irq-trigger = <0x1>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - reg = <0>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - }; - - /* - * LM95245 temperature sensor - * Note: OVERT_N directly connected to PMIC PWRDN - */ - temp-sensor@4c { - compatible = "national,lm95245"; - reg = <0x4c>; - }; - - /* SW: +V1.2_VDD_CORE */ - tps62362@60 { - compatible = "ti,tps62362"; - reg = <0x60>; - - regulator-name = "tps62362-vout"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-low; - /* VSEL1: EN_CORE_DVFS_N low for DVFS */ - ti,vsel1-state-low; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - /* eMMC */ - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - /* EHCI instance 1: USB2_DP/N -> AX88772B */ - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - nvidia,is-wired = <1>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clk@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - avdd_hdmi_pll_1v8_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; - - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - avdd_hdmi_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; - - charge_pump_5v0_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tegra30.dtsi b/software/linux/kernel/arch/arm/boot/dts/tegra30.dtsi deleted file mode 100644 index 5030065cb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tegra30.dtsi +++ /dev/null @@ -1,944 +0,0 @@ -#include -#include -#include -#include -#include - -#include "skeleton.dtsi" - -/ { - compatible = "nvidia,tegra30"; - interrupt-parent = <&lic>; - - pcie-controller@00003000 { - compatible = "nvidia,tegra30-pcie"; - device_type = "pci"; - reg = <0x00003000 0x00000800 /* PADS registers */ - 0x00003800 0x00000200 /* AFI registers */ - 0x10000000 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ - - clocks = <&tegra_car TEGRA30_CLK_PCIE>, - <&tegra_car TEGRA30_CLK_AFI>, - <&tegra_car TEGRA30_CLK_PLL_E>, - <&tegra_car TEGRA30_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; - reg = <0x001800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra30-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = , /* syncpt */ - ; /* general */ - clocks = <&tegra_car TEGRA30_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe@54040000 { - compatible = "nvidia,tegra30-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_MPE>; - resets = <&tegra_car 60>; - reset-names = "mpe"; - }; - - vi@54080000 { - compatible = "nvidia,tegra30-vi"; - reg = <0x54080000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_VI>; - resets = <&tegra_car 20>; - reset-names = "vi"; - }; - - epp@540c0000 { - compatible = "nvidia,tegra30-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_EPP>; - resets = <&tegra_car 19>; - reset-names = "epp"; - }; - - isp@54100000 { - compatible = "nvidia,tegra30-isp"; - reg = <0x54100000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_ISP>; - resets = <&tegra_car 23>; - reset-names = "isp"; - }; - - gr2d@54140000 { - compatible = "nvidia,tegra30-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; - }; - - gr3d@54180000 { - compatible = "nvidia,tegra30-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_GR3D - &tegra_car TEGRA30_CLK_GR3D2>; - clock-names = "3d", "3d2"; - resets = <&tegra_car 24>, - <&tegra_car 98>; - reset-names = "3d", "3d2"; - }; - - dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_DISP1>, - <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra30-dc"; - reg = <0x54240000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_DISP2>, - <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - - rgb { - status = "disabled"; - }; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra30-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_HDMI>, - <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - tvo@542c0000 { - compatible = "nvidia,tegra30-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_TVO>; - status = "disabled"; - }; - - dsi@54300000 { - compatible = "nvidia,tegra30-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; - resets = <&tegra_car 48>; - reset-names = "dsi"; - status = "disabled"; - }; - }; - - timer@50040600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x50040600 0x20>; - interrupt-parent = <&intc>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_TWD>; - }; - - intc: interrupt-controller@50041000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <6 6 2>; - arm,tag-latency = <5 5 2>; - cache-unified; - cache-level = <2>; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra30-ictlr"; - reg = <0x60004000 0x100>, - <0x60004100 0x50>, - <0x60004200 0x50>, - <0x60004300 0x50>, - <0x60004400 0x50>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; - - timer@60005000 { - compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA30_CLK_TIMER>; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra30-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra30-flowctrl"; - reg = <0x60007000 0x1000>; - }; - - apbdma: dma@6000a000 { - compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA30_CLK_APBDMA>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - ahb: ahb@6000c000 { - compatible = "nvidia,tegra30-ahb"; - reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - /* - gpio-ranges = <&pinmux 0 0 248>; - */ - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra30-pinmux"; - reg = <0x70000868 0xd4 /* Pad control registers */ - 0x70003000 0x3e4>; /* Mux registers */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTA>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTB>; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTC>; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTD>; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uarte: serial@70006400 { - compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; - reg = <0x70006400 0x100>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_UARTE>; - resets = <&tegra_car 66>; - reset-names = "serial"; - dmas = <&apbdma 20>, <&apbdma 20>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA30_CLK_PWM>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_RTC>; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C1>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c400 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C2>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c500 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C3>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000c700 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C4>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - resets = <&tegra_car 103>; - reset-names = "i2c"; - clock-names = "div-clk", "fast-clk"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000d000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_I2C5>, - <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d400 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC1>; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC2>; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC3>; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000da00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC4>; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000dc00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC5>; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000de00 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA30_CLK_SBC6>; - resets = <&tegra_car 106>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - kbc@7000e200 { - compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; - reg = <0x7000e200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_KBC>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - status = "disabled"; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra30-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - }; - - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra30-mc"; - reg = <0x7000f000 0x400>; - clocks = <&tegra_car TEGRA30_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra30-efuse"; - reg = <0x7000f800 0x400>; - clocks = <&tegra_car TEGRA30_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - hda@70030000 { - compatible = "nvidia,tegra30-hda"; - reg = <0x70030000 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_HDA>, - <&tegra_car TEGRA30_CLK_HDA2HDMI>, - <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - ahub@70080000 { - compatible = "nvidia,tegra30-ahub"; - reg = <0x70080000 0x200 - 0x70080200 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, - <&tegra_car TEGRA30_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>; /* spdif */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3"; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - tegra_i2s0: i2s@70080300 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080300 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA30_CLK_I2S0>; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70080400 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080400 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA30_CLK_I2S1>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70080500 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080500 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA30_CLK_I2S2>; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70080600 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080600 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA30_CLK_I2S3>; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70080700 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080700 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA30_CLK_I2S4>; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - sdhci@78000000 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000000 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000200 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000200 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000400 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000400 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - sdhci@78000600 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; - reg = <0x78000600 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - usb@7d000000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d000000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USBD>; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,needs-double-reset; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USBD>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia.xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <1>; - nvidia,xcvr-lsrslew = <1>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d004000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB2>; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB2>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <9>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia.xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d008000 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB3>; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA30_CLK_USB3>, - <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <51>; - nvidia.xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - nvidia,xcvr-hsslew = <32>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = , - , - , - ; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tny_a9260.dts b/software/linux/kernel/arch/arm/boot/dts/tny_a9260.dts deleted file mode 100644 index dabe23221..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tny_a9260.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9260.dtsi" -#include "tny_a9260_common.dtsi" - -/ { - model = "Calao TNY A9260"; - compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tny_a9260_common.dtsi b/software/linux/kernel/arch/arm/boot/dts/tny_a9260_common.dtsi deleted file mode 100644 index f9dc463b9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tny_a9260_common.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* - * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ - -/ { - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tny_a9263.dts b/software/linux/kernel/arch/arm/boot/dts/tny_a9263.dts deleted file mode 100644 index 9161cd988..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tny_a9263.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 only - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Calao TNY A9263"; - compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tny_a9g20.dts b/software/linux/kernel/arch/arm/boot/dts/tny_a9g20.dts deleted file mode 100644 index 8456d70bb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tny_a9g20.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9g20.dtsi" -#include "tny_a9260_common.dtsi" - -/ { - model = "Calao TNY A9G20"; - compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tps6507x.dtsi b/software/linux/kernel/arch/arm/boot/dts/tps6507x.dtsi deleted file mode 100644 index 4c326e591..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tps6507x.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65070.pdf - */ - -&tps { - compatible = "ti,tps6507x"; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vdcdc1_reg: regulator@0 { - reg = <0>; - regulator-compatible = "VDCDC1"; - }; - - vdcdc2_reg: regulator@1 { - reg = <1>; - regulator-compatible = "VDCDC2"; - }; - - vdcdc3_reg: regulator@2 { - reg = <2>; - regulator-compatible = "VDCDC3"; - }; - - ldo1_reg: regulator@3 { - reg = <3>; - regulator-compatible = "LDO1"; - }; - - ldo2_reg: regulator@4 { - reg = <4>; - regulator-compatible = "LDO2"; - }; - - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tps65217.dtsi b/software/linux/kernel/arch/arm/boot/dts/tps65217.dtsi deleted file mode 100644 index a63272422..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tps65217.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65217.pdf - */ - -&tps { - compatible = "ti,tps65217"; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - dcdc1_reg: regulator@0 { - reg = <0>; - regulator-compatible = "dcdc1"; - }; - - dcdc2_reg: regulator@1 { - reg = <1>; - regulator-compatible = "dcdc2"; - }; - - dcdc3_reg: regulator@2 { - reg = <2>; - regulator-compatible = "dcdc3"; - }; - - ldo1_reg: regulator@3 { - reg = <3>; - regulator-compatible = "ldo1"; - }; - - ldo2_reg: regulator@4 { - reg = <4>; - regulator-compatible = "ldo2"; - }; - - ldo3_reg: regulator@5 { - reg = <5>; - regulator-compatible = "ldo3"; - }; - - ldo4_reg: regulator@6 { - reg = <6>; - regulator-compatible = "ldo4"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/tps65910.dtsi b/software/linux/kernel/arch/arm/boot/dts/tps65910.dtsi deleted file mode 100644 index b0ac6657a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/tps65910.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65910.pdf - */ - -&tps { - compatible = "ti,tps65910"; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vrtc_reg: regulator@0 { - reg = <0>; - regulator-compatible = "vrtc"; - }; - - vio_reg: regulator@1 { - reg = <1>; - regulator-compatible = "vio"; - }; - - vdd1_reg: regulator@2 { - reg = <2>; - regulator-compatible = "vdd1"; - }; - - vdd2_reg: regulator@3 { - reg = <3>; - regulator-compatible = "vdd2"; - }; - - vdd3_reg: regulator@4 { - reg = <4>; - regulator-compatible = "vdd3"; - }; - - vdig1_reg: regulator@5 { - reg = <5>; - regulator-compatible = "vdig1"; - }; - - vdig2_reg: regulator@6 { - reg = <6>; - regulator-compatible = "vdig2"; - }; - - vpll_reg: regulator@7 { - reg = <7>; - regulator-compatible = "vpll"; - }; - - vdac_reg: regulator@8 { - reg = <8>; - regulator-compatible = "vdac"; - }; - - vaux1_reg: regulator@9 { - reg = <9>; - regulator-compatible = "vaux1"; - }; - - vaux2_reg: regulator@10 { - reg = <10>; - regulator-compatible = "vaux2"; - }; - - vaux33_reg: regulator@11 { - reg = <11>; - regulator-compatible = "vaux33"; - }; - - vmmc_reg: regulator@12 { - reg = <12>; - regulator-compatible = "vmmc"; - }; - - vbb_reg: regulator@13 { - reg = <13>; - regulator-compatible = "vbb"; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/twl4030.dtsi b/software/linux/kernel/arch/arm/boot/dts/twl4030.dtsi deleted file mode 100644 index 36ae9160b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/twl4030.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Integrated Power Management Chip - */ -&twl { - compatible = "ti,twl4030"; - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - charger: bci { - compatible = "ti,twl4030-bci"; - interrupts = <9>, <2>; - bci3v1-supply = <&vusb3v1>; - }; - - watchdog { - compatible = "ti,twl4030-wdt"; - }; - - vaux1: regulator-vaux1 { - compatible = "ti,twl4030-vaux1"; - }; - - vaux2: regulator-vaux2 { - compatible = "ti,twl4030-vaux2"; - }; - - vaux3: regulator-vaux3 { - compatible = "ti,twl4030-vaux3"; - }; - - vaux4: regulator-vaux4 { - compatible = "ti,twl4030-vaux4"; - }; - - vcc: regulator-vdd1 { - compatible = "ti,twl4030-vdd1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1450000>; - }; - - vdac: regulator-vdac { - compatible = "ti,twl4030-vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vio: regulator-vio { - compatible = "ti,twl4030-vio"; - }; - - vintana1: regulator-vintana1 { - compatible = "ti,twl4030-vintana1"; - }; - - vintana2: regulator-vintana2 { - compatible = "ti,twl4030-vintana2"; - }; - - vintdig: regulator-vintdig { - compatible = "ti,twl4030-vintdig"; - }; - - vmmc1: regulator-vmmc1 { - compatible = "ti,twl4030-vmmc1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - }; - - vmmc2: regulator-vmmc2 { - compatible = "ti,twl4030-vmmc2"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - }; - - vusb1v5: regulator-vusb1v5 { - compatible = "ti,twl4030-vusb1v5"; - }; - - vusb1v8: regulator-vusb1v8 { - compatible = "ti,twl4030-vusb1v8"; - }; - - vusb3v1: regulator-vusb3v1 { - compatible = "ti,twl4030-vusb3v1"; - }; - - vpll1: regulator-vpll1 { - compatible = "ti,twl4030-vpll1"; - }; - - vpll2: regulator-vpll2 { - compatible = "ti,twl4030-vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vsim: regulator-vsim { - compatible = "ti,twl4030-vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - twl_gpio: gpio { - compatible = "ti,twl4030-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - usb2_phy: twl4030-usb { - compatible = "ti,twl4030-usb"; - interrupts = <10>, <4>; - usb1v5-supply = <&vusb1v5>; - usb1v8-supply = <&vusb1v8>; - usb3v1-supply = <&vusb3v1>; - usb_mode = <1>; - #phy-cells = <0>; - }; - - twl_pwm: pwm { - compatible = "ti,twl4030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - compatible = "ti,twl4030-pwmled"; - #pwm-cells = <2>; - }; - - twl_pwrbutton: pwrbutton { - compatible = "ti,twl4030-pwrbutton"; - interrupts = <8>; - }; - - twl_keypad: keypad { - compatible = "ti,twl4030-keypad"; - interrupts = <1>; - keypad,num-rows = <8>; - keypad,num-columns = <8>; - }; - - twl_madc: madc { - compatible = "ti,twl4030-madc"; - interrupts = <3>; - #io-channel-cells = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/twl4030_omap3.dtsi b/software/linux/kernel/arch/arm/boot/dts/twl4030_omap3.dtsi deleted file mode 100644 index 5288e6dff..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/twl4030_omap3.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2013 Linaro, Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -&twl { - pinctrl-names = "default"; - pinctrl-0 = <&twl4030_pins &twl4030_vpins>; -}; - -&omap3_pmx_core { - /* - * On most OMAP3 platforms, the twl4030 IRQ line is connected - * to the SYS_NIRQ line on OMAP. Therefore, configure the - * defaults for the SYS_NIRQ pin here. - */ - twl4030_pins: pinmux_twl4030_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ - >; - }; -}; - -/* - * If your board is not using the I2C4 pins with twl4030, then don't include - * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode - * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and - * sys_nvmode2 signaling. - */ -&omap3_pmx_wkup { - twl4030_vpins: pinmux_twl4030_vpins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ - OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ - OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */ - OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/twl6030.dtsi b/software/linux/kernel/arch/arm/boot/dts/twl6030.dtsi deleted file mode 100644 index c45f97f37..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/twl6030.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf - */ -&twl { - compatible = "ti,twl6030"; - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - vaux1: regulator-vaux1 { - compatible = "ti,twl6030-vaux1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - vaux2: regulator-vaux2 { - compatible = "ti,twl6030-vaux2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - }; - - vaux3: regulator-vaux3 { - compatible = "ti,twl6030-vaux3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - vmmc: regulator-vmmc { - compatible = "ti,twl6030-vmmc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - }; - - vpp: regulator-vpp { - compatible = "ti,twl6030-vpp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - }; - - vusim: regulator-vusim { - compatible = "ti,twl6030-vusim"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2900000>; - }; - - vdac: regulator-vdac { - compatible = "ti,twl6030-vdac"; - }; - - vana: regulator-vana { - compatible = "ti,twl6030-vana"; - }; - - vcxio: regulator-vcxio { - compatible = "ti,twl6030-vcxio"; - regulator-always-on; - }; - - vusb: regulator-vusb { - compatible = "ti,twl6030-vusb"; - }; - - v1v8: regulator-v1v8 { - compatible = "ti,twl6030-v1v8"; - regulator-always-on; - }; - - v2v1: regulator-v2v1 { - compatible = "ti,twl6030-v2v1"; - regulator-always-on; - }; - - twl_usb_comparator: usb-comparator { - compatible = "ti,twl6030-usb"; - interrupts = <4>, <10>; - }; - - twl_pwm: pwm { - /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - /* provides one PWM (id 0 for Charging indicator LED) */ - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; - }; - - gpadc { - compatible = "ti,twl6030-gpadc"; - interrupts = <3>; - #io-channel-cells = <1>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/twl6030_omap4.dtsi b/software/linux/kernel/arch/arm/boot/dts/twl6030_omap4.dtsi deleted file mode 100644 index e373f59ce..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/twl6030_omap4.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -&twl { - /* - * On most OMAP4 platforms, the twl6030 IRQ line is connected - * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is - * connected to the fref_clk0_out.sys_drm_msecure line. - * Therefore, configure the defaults for the SYS_NIRQ1 and - * fref_clk0_out.sys_drm_msecure pins here. - */ - pinctrl-names = "default"; - pinctrl-0 = < - &twl6030_pins - &twl6030_wkup_pins - >; -}; - -&omap4_pmx_wkup { - twl6030_wkup_pins: pinmux_twl6030_wkup_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ - >; - }; -}; - -&omap4_pmx_core { - twl6030_pins: pinmux_twl6030_pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-common32.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-common32.dtsi deleted file mode 100644 index 8c8a85176..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-common32.dtsi +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Device Tree Source commonly used by UniPhier ARM SoCs - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - #clock-cells = <1>; - }; - - mio_rst: reset { - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - #clock-cells = <1>; - }; - - peri_rst: reset { - #reset-cells = <1>; - }; - }; - - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; - - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - /* specify compatible in each SoC DTSI */ - }; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - sys_clk: clock { - #clock-cells = <1>; - }; - - sys_rst: reset { - #reset-cells = <1>; - }; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-ld4-ref.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-ld4-ref.dts deleted file mode 100644 index 110031bc0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Device Tree Source for UniPhier LD4 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ld4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD4 Reference Board"; - compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-ld4.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-ld4.dtsi deleted file mode 100644 index 95f342c9d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-ld4.dtsi +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Device Tree Source for UniPhier LD4 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,uniphier-ld4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; - }; - -}; - -&refclk { - clock-frequency = <24576000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&mio_clk { - compatible = "socionext,uniphier-ld4-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-ld4-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-ld4-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-ld4-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-ld4-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-ld4-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-ld4-reset"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-ld6b-ref.dts deleted file mode 100644 index c05d631dc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Device Tree Source for UniPhier LD6b Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ld6b.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD6b Reference Board"; - compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -ðsc { - interrupts = <0 52 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-ld6b.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-ld6b.dtsi deleted file mode 100644 index 905c77d49..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-ld6b.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Device Tree Source for UniPhier LD6b SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * LD6b consists of two silicon dies: D-chip and A-chip. - * The D-chip (digital chip) is the same as the PXs2 die. - * Reuse the PXs2 device tree with some properties overridden. - */ -/include/ "uniphier-pxs2.dtsi" - -/ { - compatible = "socionext,uniphier-ld6b"; -}; - -/* UART3 unavailable: the pads are not wired to the package balls */ -&serial3 { - status = "disabled"; -}; - -/* - * LD6b and PXs2 have completely different packages, - * which makes the pinctrl driver unshareable. - */ -&pinctrl { - compatible = "socionext,uniphier-ld6b-pinctrl"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-pinctrl.dtsi deleted file mode 100644 index 10a711041..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Device Tree Source for UniPhier SoCs default pinctrl settings - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&pinctrl { - pinctrl_i2c0: i2c0_grp { - groups = "i2c0"; - function = "i2c0"; - }; - - pinctrl_i2c1: i2c1_grp { - groups = "i2c1"; - function = "i2c1"; - }; - - pinctrl_i2c2: i2c2_grp { - groups = "i2c2"; - function = "i2c2"; - }; - - pinctrl_i2c3: i2c3_grp { - groups = "i2c3"; - function = "i2c3"; - }; - - pinctrl_i2c4: i2c4_grp { - groups = "i2c4"; - function = "i2c4"; - }; - - pinctrl_nand: nand_grp { - groups = "nand"; - function = "nand"; - }; - - pinctrl_nand2cs: nand2cs_grp { - groups = "nand", "nand_cs1"; - function = "nand"; - }; - - pinctrl_system_bus: system_bus_grp { - groups = "system_bus", "system_bus_cs1"; - function = "system_bus"; - }; - - pinctrl_uart0: uart0_grp { - groups = "uart0"; - function = "uart0"; - }; - - pinctrl_uart1: uart1_grp { - groups = "uart1"; - function = "uart1"; - }; - - pinctrl_uart2: uart2_grp { - groups = "uart2"; - function = "uart2"; - }; - - pinctrl_uart3: uart3_grp { - groups = "uart3"; - function = "uart3"; - }; - - pinctrl_usb0: usb0_grp { - groups = "usb0"; - function = "usb0"; - }; - - pinctrl_usb1: usb1_grp { - groups = "usb1"; - function = "usb1"; - }; - - pinctrl_usb2: usb2_grp { - groups = "usb2"; - function = "usb2"; - }; - - pinctrl_usb3: usb3_grp { - groups = "usb3"; - function = "usb3"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-ace.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-ace.dts deleted file mode 100644 index 0ab0a40c0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-ace.dts +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Device Tree Source for UniPhier Pro4 Ace Board - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-pro4.dtsi" - -/ { - model = "UniPhier Pro4 Ace Board"; - compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-ref.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-ref.dts deleted file mode 100644 index 9e92e60d2..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Device Tree Source for UniPhier Pro4 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-pro4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier Pro4 Reference Board"; - compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -ðsc { - interrupts = <0 50 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-sanji.dts deleted file mode 100644 index dc4ea8832..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4-sanji.dts +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Device Tree Source for UniPhier Pro4 Sanji Board - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-pro4.dtsi" - -/ { - model = "UniPhier Pro4 Sanji Board"; - compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4.dtsi deleted file mode 100644 index ba700267a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro4.dtsi +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Device Tree Source for UniPhier Pro4 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,uniphier-pro4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; - }; - - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; - - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pro4-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pro4-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-pro4-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pro4-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pro4-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pro4-reset"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro5.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-pro5.dtsi deleted file mode 100644 index 5357ea9c1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pro5.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Device Tree Source for UniPhier Pro5 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,uniphier-pro5"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; - }; -}; - -&refclk { - clock-frequency = <20000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pro5-sd-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pro5-sd-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pro5-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pro5-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro5-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pro5-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pro5-reset"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2-gentil.dts deleted file mode 100644 index 373818ace..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Device Tree Source for UniPhier PXs2 Gentil Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-pxs2.dtsi" - -/ { - model = "UniPhier PXs2 Gentil Board"; - compatible = "socionext,uniphier-pxs2-gentil", - "socionext,uniphier-pxs2"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2-vodka.dts deleted file mode 100644 index 51a3eacdd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Device Tree Source for UniPhier PXs2 Vodka Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-pxs2.dtsi" - -/ { - model = "UniPhier PXs2 Vodka Board"; - compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2.dtsi deleted file mode 100644 index 950f07ba0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Device Tree Source for UniPhier PXs2 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,uniphier-pxs2"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&peri_clk 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&peri_clk 8>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - clock-frequency = <400000>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pxs2-sd-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pxs2-sd-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pxs2-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pxs2-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pxs2-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pxs2-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pxs2-reset"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-ref-daughter.dtsi deleted file mode 100644 index f7df0881c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-ref-daughter.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Device Tree Source for UniPhier Reference Daughter Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&i2c0 { - eeprom@50 { - compatible = "microchip,24lc128"; - reg = <0x50>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-sld3-ref.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-sld3-ref.dts deleted file mode 100644 index ac792ae07..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-sld3-ref.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Device Tree Source for UniPhier sLD3 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-sld3.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier sLD3 Reference Board"; - compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000 - 0xc0000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-sld3.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-sld3.dtsi deleted file mode 100644 index 5fa96c939..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-sld3.dtsi +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Device Tree Source for UniPhier sLD3 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "socionext,uniphier-sld3"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - timer@20000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; - - timer@20000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@20001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x20001000 0x1000>, - <0x20000100 0x100>; - }; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - clocks = <&sys_clk 0>; - fifo-size = <64>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - clocks = <&sys_clk 0>; - fifo-size = <64>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - clocks = <&sys_clk 0>; - fifo-size = <64>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - clocks = <&sys_clk 1>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58600000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58600000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 1>; - clocks = <&sys_clk 1>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - compatible = "socionext,uniphier-sld3-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-sld3-mio-reset"; - #reset-cells = <1>; - }; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - }; - - usb3: usb@5a830100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a830100 0x100>; - interrupts = <0 83 4>; - }; - - sysctrl@f1840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0xf1840000 0x4000>; - - sys_clk: clock { - compatible = "socionext,uniphier-sld3-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-sld3-reset"; - #reset-cells = <1>; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-sld8-ref.dts b/software/linux/kernel/arch/arm/boot/dts/uniphier-sld8-ref.dts deleted file mode 100644 index a8291f988..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Device Tree Source for UniPhier sLD8 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-sld8.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier sLD8 Reference Board"; - compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; -}; - -ðsc { - interrupts = <0 48 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-sld8.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-sld8.dtsi deleted file mode 100644 index d8cf0e7e1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-sld8.dtsi +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Device Tree Source for UniPhier sLD8 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,uniphier-sld8"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - clock-frequency = <100000>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; - resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; - resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; - resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&mio_clk { - compatible = "socionext,uniphier-sld8-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-sld8-mio-reset"; - resets = <&sys_rst 7>; -}; - -&peri_clk { - compatible = "socionext,uniphier-sld8-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-sld8-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-sld8-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-sld8-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-sld8-reset"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/uniphier-support-card.dtsi b/software/linux/kernel/arch/arm/boot/dts/uniphier-support-card.dtsi deleted file mode 100644 index 51ecc9b9c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/uniphier-support-card.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Device Tree Source for UniPhier Support Card (Expansion Board) - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&system_bus { - status = "okay"; - ranges = <1 0x00000000 0x42000000 0x02000000>; - - support_card: support_card { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 1 0x01f00000 0x00100000>; - - ethsc: ethernet@00000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x00000000 0x1000>; - phy-mode = "mii"; - reg-io-width = <4>; - }; - - serialsc: uart@000b0000 { - compatible = "ns16550a"; - reg = <0x000b0000 0x20>; - clock-frequency = <12288000>; - reg-shift = <1>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/usb_a9260.dts b/software/linux/kernel/arch/arm/boot/dts/usb_a9260.dts deleted file mode 100644 index de0c24f52..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/usb_a9260.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * usb_a9260.dts - Device Tree file for Caloa USB A9260 board - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "at91sam9260.dtsi" -#include "usb_a9260_common.dtsi" - -/ { - model = "Calao USB A9260"; - compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - ahb { - apb { - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/usb_a9260_common.dtsi b/software/linux/kernel/arch/arm/boot/dts/usb_a9260_common.dtsi deleted file mode 100644 index 7514b347c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/usb_a9260_common.dtsi +++ /dev/null @@ -1,116 +0,0 @@ -/* - * usb_a926x.dts - Device Tree file for Caloa USB A926x board - * - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 or later. - */ - -/ { - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - - usb0: ohci@500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/usb_a9263.dts b/software/linux/kernel/arch/arm/boot/dts/usb_a9263.dts deleted file mode 100644 index bfc48a272..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/usb_a9263.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board - * - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 only - */ -/dts-v1/; -#include "at91sam9263.dtsi" - -/ { - model = "Calao USB A9263"; - compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; - - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - }; - - ahb { - apb { - dbgu: serial@ffffee00 { - status = "okay"; - }; - - macb0: ethernet@fffbc000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - spi0: spi@fffa4000 { - cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - reg = <0>; - spi-max-frequency = <15000000>; - }; - }; - - shdwc@fffffd10 { - atmel,wakeup-counter = <10>; - atmel,wakeup-rtt-timer; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x20000>; - }; - - barebox@20000 { - label = "barebox"; - reg = <0x20000 0x40000>; - }; - - bareboxenv@60000 { - label = "bareboxenv"; - reg = <0x60000 0x20000>; - }; - - bareboxenv2@80000 { - label = "bareboxenv2"; - reg = <0x80000 0x20000>; - }; - - oftree@80000 { - label = "oftree"; - reg = <0xa0000 0x20000>; - }; - - kernel@a0000 { - label = "kernel"; - reg = <0xc0000 0x400000>; - }; - - rootfs@4a0000 { - label = "rootfs"; - reg = <0x4c0000 0x7800000>; - }; - - data@7ca0000 { - label = "data"; - reg = <0x7cc0000 0x8340000>; - }; - }; - - usb0: ohci@00a00000 { - num-ports = <2>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led { - label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb { - label = "user_pb"; - gpios = <&pioB 10 GPIO_ACTIVE_LOW>; - linux,code = <28>; - wakeup-source; - }; - }; - - i2c-gpio-0 { - status = "okay"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/software/linux/kernel/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi deleted file mode 100644 index 5b0ffc1a0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2. - */ - -/ { - ahb { - apb { - usart1: serial@fffb4000 { - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - }; - }; - - i2c-gpio@0 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "user_led1"; - gpios = <&pioB 20 GPIO_ACTIVE_LOW>; - }; - -/* -* led already used by mother board but active as high -* user_led2 { -* label = "user_led2"; -* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; -* }; -*/ - user_led3 { - label = "user_led3"; - gpios = <&pioB 22 GPIO_ACTIVE_LOW>; - }; - - user_led4 { - label = "user_led4"; - gpios = <&pioB 23 GPIO_ACTIVE_LOW>; - }; - - red { - label = "red"; - gpios = <&pioB 24 GPIO_ACTIVE_LOW>; - }; - - orange { - label = "orange"; - gpios = <&pioB 30 GPIO_ACTIVE_LOW>; - }; - - green { - label = "green"; - gpios = <&pioB 31 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - user_pb1 { - label = "user_pb1"; - gpios = <&pioB 25 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - }; - - user_pb2 { - label = "user_pb2"; - gpios = <&pioB 13 GPIO_ACTIVE_LOW>; - linux,code = <0x101>; - }; - - user_pb3 { - label = "user_pb3"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - }; - - user_pb4 { - label = "user_pb4"; - gpios = <&pioC 9 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/usb_a9g20.dts b/software/linux/kernel/arch/arm/boot/dts/usb_a9g20.dts deleted file mode 100644 index ec77cf8f9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/usb_a9g20.dts +++ /dev/null @@ -1,14 +0,0 @@ -/* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "usb_a9g20_common.dtsi" - -/ { - model = "Calao USB A9G20"; - compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/usb_a9g20_common.dtsi b/software/linux/kernel/arch/arm/boot/dts/usb_a9g20_common.dtsi deleted file mode 100644 index 088c2c368..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/usb_a9g20_common.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 or later. - */ - -#include "at91sam9g20.dtsi" -#include "usb_a9260_common.dtsi" - -/ { - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x20000000 0x4000000>; - }; - - i2c-gpio-0 { - rv3029c2@56 { - compatible = "rv3029c2"; - reg = <0x56>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/usb_a9g20_lpw.dts b/software/linux/kernel/arch/arm/boot/dts/usb_a9g20_lpw.dts deleted file mode 100644 index f8cb1b9a0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/usb_a9g20_lpw.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board - * - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD - * - * Licensed under GPLv2 or later. - */ -/dts-v1/; -#include "usb_a9g20_common.dtsi" - -/ { - model = "Calao USB A9G20 Low Power"; - compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; - - ahb { - apb { - spi1: spi@fffcc000 { - cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - mmc-slot@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - voltage-ranges = <3200 3400>; - spi-max-frequency = <25000000>; - interrupt-parent = <&pioC>; - interrupts = <4 IRQ_TYPE_EDGE_BOTH>; - }; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/versatile-ab.dts b/software/linux/kernel/arch/arm/boot/dts/versatile-ab.dts deleted file mode 100644 index 409e069b3..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/versatile-ab.dts +++ /dev/null @@ -1,357 +0,0 @@ -/dts-v1/; -/include/ "skeleton.dtsi" - -/ { - model = "ARM Versatile AB"; - compatible = "arm,versatile-ab"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&vic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - }; - - chosen { - stdout-path = &uart0; - }; - - memory { - reg = <0x0 0x08000000>; - }; - - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - core-module@10000000 { - compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; - reg = <0x10000000 0x200>; - - led@08.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@08.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@08.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@08.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@08.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@08.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@08.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@08.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; - - /* OSC1 on AB, OSC4 on PB */ - osc1: cm_aux_osc@24M { - #clock-cells = <0>; - compatible = "arm,versatile-cm-auxosc"; - clocks = <&xtal24mhz>; - }; - - /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - pclk: pclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - }; - - flash@34000000 { - /* 64 MiB NOR flash in non-interleaved chips */ - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x34000000 0x04000000>; - bank-width = <4>; - }; - - i2c0: i2c@10002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x10002000 0x1000>; - - rtc@68 { - compatible = "dallas,ds1338"; - reg = <0x68>; - }; - }; - - net@10010000 { - compatible = "smsc,lan91c111"; - reg = <0x10010000 0x10000>; - interrupts = <25>; - }; - - lcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic: intc@10140000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140000 0x1000>; - clear-mask = <0xffffffff>; - valid-mask = <0xffffffff>; - }; - - sic: intc@10003000 { - compatible = "arm,versatile-sic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10003000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <31>; /* Cascaded to vic */ - clear-mask = <0xffffffff>; - /* - * Valid interrupt lines mask according to - * table 4-36 page 4-50 of ARM DUI 0225D - */ - valid-mask = <0x0760031b>; - }; - - dma@10130000 { - compatible = "arm,pl081", "arm,primecell"; - reg = <0x10130000 0x1000>; - interrupts = <17>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - uart0: uart@101f1000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f1000 0x1000>; - interrupts = <12>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart1: uart@101f2000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f2000 0x1000>; - interrupts = <13>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart2: uart@101f3000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x101f3000 0x1000>; - interrupts = <14>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - smc@10100000 { - compatible = "arm,primecell"; - reg = <0x10100000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - mpmc@10110000 { - compatible = "arm,primecell"; - reg = <0x10110000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - display@10120000 { - compatible = "arm,pl110", "arm,primecell"; - reg = <0x10120000 0x1000>; - interrupts = <16>; - clocks = <&osc1>, <&pclk>; - clock-names = "clcd", "apb_pclk"; - }; - - sctl@101e0000 { - compatible = "arm,primecell"; - reg = <0x101e0000 0x1000>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - watchdog@101e1000 { - compatible = "arm,primecell"; - reg = <0x101e1000 0x1000>; - interrupts = <0>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - timer@101e2000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x101e2000 0x1000>; - interrupts = <4>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer0", "timer1", "apb_pclk"; - }; - - timer@101e3000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x101e3000 0x1000>; - interrupts = <5>; - clocks = <&timclk>, <&timclk>, <&pclk>; - clock-names = "timer0", "timer1", "apb_pclk"; - }; - - gpio0: gpio@101e4000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e4000 0x1000>; - gpio-controller; - interrupts = <6>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@101e5000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e5000 0x1000>; - interrupts = <7>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - rtc@101e8000 { - compatible = "arm,pl030", "arm,primecell"; - reg = <0x101e8000 0x1000>; - interrupts = <10>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - sci@101f0000 { - compatible = "arm,primecell"; - reg = <0x101f0000 0x1000>; - interrupts = <15>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - ssp@101f4000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x101f4000 0x1000>; - interrupts = <11>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; - }; - - fpga { - compatible = "arm,versatile-fpga", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10000000 0x10000>; - - sysreg@0 { - compatible = "arm,versatile-sysreg", "syscon"; - reg = <0x00000 0x1000>; - }; - - aaci@4000 { - compatible = "arm,primecell"; - reg = <0x4000 0x1000>; - interrupts = <24>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - mmc@5000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x5000 0x1000>; - interrupts-extended = <&vic 22 &sic 1>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - kmi@6000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x6000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <3>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - kmi@7000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x7000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <4>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/versatile-pb.dts b/software/linux/kernel/arch/arm/boot/dts/versatile-pb.dts deleted file mode 100644 index 33a8eb283..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/versatile-pb.dts +++ /dev/null @@ -1,113 +0,0 @@ -#include - -/ { - model = "ARM Versatile PB"; - compatible = "arm,versatile-pb"; - - amba { - /* The Versatile PB is using more SIC IRQ lines than the AB */ - sic: intc@10003000 { - clear-mask = <0xffffffff>; - /* - * Valid interrupt lines mask according to - * figure 3-30 page 3-74 of ARM DUI 0224B - */ - valid-mask = <0x7fe003ff>; - }; - - gpio2: gpio@101e6000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e6000 0x1000>; - interrupts = <8>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@101e7000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x101e7000 0x1000>; - interrupts = <9>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pclk>; - clock-names = "apb_pclk"; - }; - - pci-controller@10001000 { - compatible = "arm,versatile-pci"; - device_type = "pci"; - reg = <0x10001000 0x1000 - 0x41000000 0x10000 - 0x42000000 0x100000>; - bus-range = <0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ - 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ - 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ - - interrupt-map-mask = <0x1800 0 0 7>; - interrupt-map = <0x1800 0 0 1 &sic 28 - 0x1800 0 0 2 &sic 29 - 0x1800 0 0 3 &sic 30 - 0x1800 0 0 4 &sic 27 - - 0x1000 0 0 1 &sic 27 - 0x1000 0 0 2 &sic 28 - 0x1000 0 0 3 &sic 29 - 0x1000 0 0 4 &sic 30 - - 0x0800 0 0 1 &sic 30 - 0x0800 0 0 2 &sic 27 - 0x0800 0 0 3 &sic 28 - 0x0800 0 0 4 &sic 29 - - 0x0000 0 0 1 &sic 29 - 0x0000 0 0 2 &sic 30 - 0x0000 0 0 3 &sic 27 - 0x0000 0 0 4 &sic 28>; - }; - - fpga { - mmc@5000 { - /* - * Overrides the interrupt assignment from - * the Versatile AB board file. - */ - interrupts-extended = <&sic 22 &sic 23>; - }; - uart@9000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x9000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <6>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "uartclk", "apb_pclk"; - }; - sci@a000 { - compatible = "arm,primecell"; - reg = <0xa000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <5>; - clocks = <&xtal24mhz>; - clock-names = "apb_pclk"; - }; - mmc@b000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0xb000 0x1000>; - interrupt-parent = <&sic>; - interrupts = <1>, <2>; - clocks = <&xtal24mhz>, <&pclk>; - clock-names = "mclk", "apb_pclk"; - }; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/software/linux/kernel/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi deleted file mode 100644 index 3086efacd..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,442 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ - - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@1,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - v2m_video_ram: vram@2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@2,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@3,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@010000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - - v2m_led_gpios: sys_led { - compatible = "arm,vexpress-sysreg,sys_led"; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: sys_mci { - compatible = "arm,vexpress-sysreg,sys_mci"; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: sys_flash { - compatible = "arm,vexpress-sysreg,sys_flash"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@020000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@030000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@040000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@050000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9 10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@060000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@070000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@090000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@0a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@0b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@0c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@0f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - memory-region = <&v2m_video_ram>; - max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ - - port { - v2m_clcd_pads: endpoint { - remote-endpoint = <&v2m_clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - v2m_clcd_panel: endpoint { - remote-endpoint = <&v2m_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <40>; - hfront-porch = <24>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <2>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; diff --git a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2m.dtsi b/software/linux/kernel/arch/arm/boot/dts/vexpress-v2m.dtsi deleted file mode 100644 index c6393d3f1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2m.dtsi +++ /dev/null @@ -1,441 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * Original memory map ("Legacy memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m-rs1.dtsi! - */ - - motherboard { - model = "V2M-P1"; - arm,hbi = <0x190>; - arm,vexpress,site = <0>; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <1 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@2,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <2 0x00000000 0x02000000>; - bank-width = <4>; - }; - - v2m_video_ram: vram@3,00000000 { - compatible = "arm,vexpress-vram"; - reg = <3 0x00000000 0x00800000>; - }; - - ethernet@3,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <3 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&v2m_fixed_3v3>; - vddvario-supply = <&v2m_fixed_3v3>; - }; - - usb@3,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <3 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@7,00000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 7 0 0x20000>; - - v2m_sysreg: sysreg@00000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x00000 0x1000>; - - v2m_led_gpios: sys_led { - compatible = "arm,vexpress-sysreg,sys_led"; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: sys_mci { - compatible = "arm,vexpress-sysreg,sys_mci"; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: sys_flash { - compatible = "arm,vexpress-sysreg,sys_flash"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - v2m_sysctl: sysctl@01000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x01000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@02000 { - compatible = "arm,versatile-i2c"; - reg = <0x02000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@04000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x04000 0x1000>; - interrupts = <11>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - mmci@05000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x05000 0x1000>; - interrupts = <9 10>; - cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@06000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x06000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@07000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x07000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&smbclk>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@09000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x09000 0x1000>; - interrupts = <5>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@0a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a000 0x1000>; - interrupts = <6>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@0b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b000 0x1000>; - interrupts = <7>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@0c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c000 0x1000>; - interrupts = <8>; - clocks = <&v2m_oscclk2>, <&smbclk>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@0f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@11000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x11000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@12000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@16000 { - compatible = "arm,versatile-i2c"; - reg = <0x16000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@17000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x17000 0x1000>; - interrupts = <4>; - clocks = <&smbclk>; - clock-names = "apb_pclk"; - }; - - compact-flash@1a000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a000 0x100 - 0x1a100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&smbclk>; - clock-names = "clcdclk", "apb_pclk"; - memory-region = <&v2m_video_ram>; - max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ - - port { - v2m_clcd_pads: endpoint { - remote-endpoint = <&v2m_clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - v2m_clcd_panel: endpoint { - remote-endpoint = <&v2m_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <40>; - hfront-porch = <24>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <2>; - }; - }; - }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; diff --git a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts deleted file mode 100644 index 102838fcc..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ /dev/null @@ -1,296 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 (version with Test Chip 1) - * Cortex-A15 MPCore (V2P-CA15) - * - * HBI-0237A - */ - -/dts-v1/; - -/ { - model = "V2P-CA15"; - arm,hbi = <0x237>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - wdt@2b060000 { - compatible = "arm,sp805", "arm,primecell"; - status = "disabled"; - reg = <0 0x2b060000 0 0x1000>; - interrupts = <0 98 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x1000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - dma@7ffb0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0 0x7ffb0000 0 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* CPU PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <50000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - oscclk4 { - /* Multiplexed AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - hdlcd_clk: oscclk5 { - /* HDLCD PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - smbclk: oscclk6 { - /* SMB clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 6>; - freq-range = <20000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk6"; - }; - - sys_pll: oscclk7 { - /* SYS PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 7>; - freq-range = <20000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk7"; - }; - - oscclk8 { - /* DDR2 PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 8>; - freq-range = <40000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk8"; - }; - - volt-cores { - /* CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "Cores"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "Cores"; - }; - - amp-cores { - /* Total current for the two cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "Cores"; - }; - - temp-dcc { - /* DCC internal temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - - power-cores { - /* Total power */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "Cores"; - }; - - energy { - /* Total energy */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>; - label = "Cores"; - }; - }; - - smb@08000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - - /include/ "vexpress-v2m-rs1.dtsi" - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x3fef0000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts deleted file mode 100644 index 0205c97ef..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ /dev/null @@ -1,654 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 A7x3 - * Cortex-A15_A7 MPCore (V2P-CA15_A7) - * - * HBI-0249A - */ - -/dts-v1/; - -/ { - model = "V2P-CA15_CA7"; - arm,hbi = <0x249>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - cci-control-port = <&cci_control1>; - cpu-idle-states = <&CLUSTER_SLEEP_BIG>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - }; - - cpu4: cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cci-control-port = <&cci_control2>; - cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; - }; - - idle-states { - CLUSTER_SLEEP_BIG: cluster-sleep-big { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_LITTLE: cluster-sleep-little { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <500>; - min-residency-us = <2500>; - }; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - wdt@2a490000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0 0x2a490000 0 0x1000>; - interrupts = <0 98 4>; - clocks = <&oscclk6a>, <&oscclk6a>; - clock-names = "wdogclk", "apb_pclk"; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x1000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - cci@2c090000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x2c090000 0 0x1000>; - ranges = <0x0 0x0 0x2c090000 0x10000>; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r0"; - reg = <0x9000 0x5000>; - interrupts = <0 105 4>, - <0 101 4>, - <0 102 4>, - <0 103 4>, - <0 104 4>; - }; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - dma@7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0 0x7ff00000 0 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - }; - - scc@7fff0000 { - compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; - reg = <0 0x7fff0000 0 0x1000>; - interrupts = <0 95 4>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - pmu_a15 { - compatible = "arm,cortex-a15-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>; - }; - - pmu_a7 { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 128 4>, - <0 129 4>, - <0 130 4>; - interrupt-affinity = <&cpu2>, - <&cpu3>, - <&cpu4>; - }; - - oscclk6a: oscclk6a { - /* Reference 24MHz clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "oscclk6a"; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* A15 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - oscclk1 { - /* A15 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* A7 PLL 0 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - oscclk3 { - /* A7 PLL 1 reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* External AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - hdlcd_clk: oscclk5 { - /* HDLCD PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - smbclk: oscclk6 { - /* Static memory controller clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 6>; - freq-range = <20000000 40000000>; - #clock-cells = <0>; - clock-output-names = "oscclk6"; - }; - - oscclk7 { - /* SYS PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 7>; - freq-range = <17000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk7"; - }; - - oscclk8 { - /* DDR2 PLL reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 8>; - freq-range = <20000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk8"; - }; - - volt-a15 { - /* A15 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "A15 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A15 Vcore"; - }; - - volt-a7 { - /* A7 CPU core voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "A7 Vcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - label = "A7 Vcore"; - }; - - amp-a15 { - /* Total current for the two A15 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "A15 Icore"; - }; - - amp-a7 { - /* Total current for the three A7 cores */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "A7 Icore"; - }; - - temp-dcc { - /* DCC internal temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - - power-a15 { - /* Total power for the two A15 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "A15 Pcore"; - }; - - power-a7 { - /* Total power for the three A7 cores */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "A7 Pcore"; - }; - - energy-a15 { - /* Total energy for the two A15 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>, <13 1>; - label = "A15 Jcore"; - }; - - energy-a7 { - /* Total energy for the three A7 cores */ - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 2>, <13 3>; - label = "A7 Jcore"; - }; - }; - - etb@0,20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - etb_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - - tpiu@0,20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel@0,20040000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output port */ - port@0 { - reg = <0>; - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - - /* funnel input ports */ - port@1 { - reg = <0>; - funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@2 { - reg = <1>; - funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@3 { - reg = <2>; - funnel_in_port2: endpoint { - slave-mode; - remote-endpoint = <&etm0_out_port>; - }; - }; - - /* Input port #3 is for ITM, not supported here */ - - port@4 { - reg = <4>; - funnel_in_port4: endpoint { - slave-mode; - remote-endpoint = <&etm1_out_port>; - }; - }; - - port@5 { - reg = <5>; - funnel_in_port5: endpoint { - slave-mode; - remote-endpoint = <&etm2_out_port>; - }; - }; - }; - }; - - ptm@0,2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - - ptm@0,2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - - etm@0,2203c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203c000 0 0x1000>; - - cpu = <&cpu2>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - etm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port2>; - }; - }; - }; - - etm@0,2203d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203d000 0 0x1000>; - - cpu = <&cpu3>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - etm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port4>; - }; - }; - }; - - etm@0,2203e000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2203e000 0 0x1000>; - - cpu = <&cpu4>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - etm2_out_port: endpoint { - remote-endpoint = <&funnel_in_port5>; - }; - }; - }; - - smb@08000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - - /include/ "vexpress-v2m-rs1.dtsi" - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x3fef0000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca5s.dts deleted file mode 100644 index 1acecaf4b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ /dev/null @@ -1,266 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A5x2 - * Cortex-A5 MPCore (V2P-CA5s) - * - * HBI-0225B - */ - -/dts-v1/; - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - hdlcd@2a110000 { - compatible = "arm,hdlcd"; - reg = <0x2a110000 0x1000>; - interrupts = <0 85 4>; - clocks = <&hdlcd_clk>; - clock-names = "pxlclk"; - }; - - memory-controller@2a150000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2a150000 0x1000>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - memory-controller@2a190000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x2a190000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&axi_clk>; - clock-names = "apb_pclk"; - }; - - scu@2c000000 { - compatible = "arm,cortex-a5-scu"; - reg = <0x2c000000 0x58>; - }; - - timer@2c000600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0x304>; - }; - - timer@2c000200 { - compatible = "arm,cortex-a5-global-timer", - "arm,cortex-a9-global-timer"; - reg = <0x2c000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&cpu_clk>; - }; - - watchdog@2c000620 { - compatible = "arm,cortex-a5-twd-wdt"; - reg = <0x2c000620 0x20>; - interrupts = <1 14 0x304>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - L2: cache-controller@2c0f0000 { - compatible = "arm,pl310-cache"; - reg = <0x2c0f0000 0x1000>; - interrupts = <0 84 4>; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a5-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - cpu_clk: oscclk0 { - /* CPU and internal AXI reference clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <50000000 100000000>; - #clock-cells = <0>; - clock-output-names = "oscclk0"; - }; - - axi_clk: oscclk1 { - /* Multiplexed AXI master clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <5000000 50000000>; - #clock-cells = <0>; - clock-output-names = "oscclk1"; - }; - - oscclk2 { - /* DDR2 */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <80000000 120000000>; - #clock-cells = <0>; - clock-output-names = "oscclk2"; - }; - - hdlcd_clk: oscclk3 { - /* HDLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 3>; - freq-range = <23750000 165000000>; - #clock-cells = <0>; - clock-output-names = "oscclk3"; - }; - - oscclk4 { - /* Test chip gate configuration */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <80000000 80000000>; - #clock-cells = <0>; - clock-output-names = "oscclk4"; - }; - - smbclk: oscclk5 { - /* SMB clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 5>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "oscclk5"; - }; - - temp-dcc { - /* DCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "DCC"; - }; - }; - - smb@08000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - - /include/ "vexpress-v2m-rs1.dtsi" - }; - - site2: hsb@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000000 0x40000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca9.dts deleted file mode 100644 index b608a03ee..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ /dev/null @@ -1,375 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A9x4 - * Cortex-A9 MPCore (V2P-CA9) - * - * HBI-0191B - */ - -/dts-v1/; - -/ { - model = "V2P-CA9"; - arm,hbi = <0x191>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A9_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - A9_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - A9_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - A9_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - interrupts = <0 44 4>; - clocks = <&oscclk1>, <&oscclk2>; - clock-names = "clcdclk", "apb_pclk"; - max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ - - port { - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <63500127>; - hactive = <1024>; - hback-porch = <152>; - hfront-porch = <48>; - hsync-len = <104>; - vactive = <768>; - vback-porch = <23>; - vfront-porch = <3>; - vsync-len = <4>; - }; - }; - }; - - memory-controller@100e0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x100e0000 0x1000>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - memory-controller@100e1000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x100e1000 0x1000>; - interrupts = <0 45 4>, - <0 46 4>; - clocks = <&oscclk2>; - clock-names = "apb_pclk"; - }; - - timer@100e4000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x100e4000 0x1000>; - interrupts = <0 48 4>, - <0 49 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "timclk", "apb_pclk"; - status = "disabled"; - }; - - watchdog@100e5000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x100e5000 0x1000>; - interrupts = <0 51 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "wdogclk", "apb_pclk"; - }; - - scu@1e000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000000 0x58>; - }; - - timer@1e000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e000600 0x20>; - interrupts = <1 13 0xf04>; - }; - - watchdog@1e000620 { - compatible = "arm,cortex-a9-twd-wdt"; - reg = <0x1e000620 0x20>; - interrupts = <1 14 0xf04>; - }; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000100 0x100>; - }; - - L2: cache-controller@1e00a000 { - compatible = "arm,pl310-cache"; - reg = <0x1e00a000 0x1000>; - interrupts = <0 43 4>; - cache-unified; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; - - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0: extsaxiclk { - /* ACLK clock to the AXI master port on the test chip */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <30000000 50000000>; - #clock-cells = <0>; - clock-output-names = "extsaxiclk"; - }; - - oscclk1: clcdclk { - /* Reference clock for the CLCD */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <10000000 80000000>; - #clock-cells = <0>; - clock-output-names = "clcdclk"; - }; - - smbclk: oscclk2: tcrefclk { - /* Reference clock for the test chip internal PLLs */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <33000000 100000000>; - #clock-cells = <0>; - clock-output-names = "tcrefclk"; - }; - - volt-vd10 { - /* Test Chip internal logic voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VD10"; - regulator-always-on; - label = "VD10"; - }; - - volt-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "VD10_S2"; - regulator-always-on; - label = "VD10_S2"; - }; - - volt-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 2>; - regulator-name = "VD10_S3"; - regulator-always-on; - label = "VD10_S3"; - }; - - volt-vcc1v8 { - /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 3>; - regulator-name = "VCC1V8"; - regulator-always-on; - label = "VCC1V8"; - }; - - volt-ddr2vtt { - /* DDR2 SDRAM VTT termination voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 4>; - regulator-name = "DDR2VTT"; - regulator-always-on; - label = "DDR2VTT"; - }; - - volt-vcc3v3 { - /* Local board supply for miscellaneous logic external to the Test Chip */ - arm,vexpress-sysreg,func = <2 5>; - compatible = "arm,vexpress-volt"; - regulator-name = "VCC3V3"; - regulator-always-on; - label = "VCC3V3"; - }; - - amp-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 0>; - label = "VD10_S2"; - }; - - amp-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-amp"; - arm,vexpress-sysreg,func = <3 1>; - label = "VD10_S3"; - }; - - power-vd10-s2 { - /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 0>; - label = "PVD10_S2"; - }; - - power-vd10-s3 { - /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ - compatible = "arm,vexpress-power"; - arm,vexpress-sysreg,func = <12 1>; - label = "PVD10_S3"; - }; - }; - - smb@04000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x40000000 0x04000000>, - <1 0 0x44000000 0x04000000>, - <2 0 0x48000000 0x04000000>, - <3 0 0x4c000000 0x04000000>, - <7 0 0x10000000 0x00020000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - - /include/ "vexpress-v2m.dtsi" - }; - - site2: hsb@e0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe0000000 0x20000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 3>; - interrupt-map = <0 0 &gic 0 36 4>, - <0 1 &gic 0 37 4>, - <0 2 &gic 0 38 4>, - <0 3 &gic 0 39 4>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/software/linux/kernel/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi deleted file mode 100644 index 1e0b823f7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk16m: clk16m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - - port { - panel_in: endpoint { - remote-endpoint = <&dcu_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */ - vin-supply = <®_5v0>; - }; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - status = "okay"; -}; - -&dcu0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dcu0_1>; - status = "okay"; - - port { - dcu_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&dspi1 { - status = "okay"; - - mcp2515can: can@0 { - compatible = "microchip,mcp2515"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - clocks = <&clk16m>; - spi-max-frequency = <10000000>; - interrupt-parent = <&gpio1>; - interrupts = <11 GPIO_ACTIVE_LOW>; - }; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -®_module_3v3 { - vin-supply = <®_3v3>; -}; - -&tcon0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh_vbus>; -}; - -&iomuxc { - vf610-colibri { - pinctrl_can_int: can_int { - fsl,pins = < - VF610_PAD_PTB21__GPIO_43 0x22ed - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf-colibri.dtsi b/software/linux/kernel/arch/arm/boot/dts/vf-colibri.dtsi deleted file mode 100644 index b7417094d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf-colibri.dtsi +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - aliases { - ethernet0 = &fec1; - ethernet1 = &fec0; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm0 0 5000000 0>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc0 { - status = "okay"; - vref-supply = <®_module_3v3_avdd>; -}; - -&adc1 { - status = "okay"; - vref-supply = <®_module_3v3_avdd>; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan0>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&clks { - assigned-clocks = <&clks VF610_CLK_ENET_SEL>, - <&clks VF610_CLK_ENET_TS_SEL>; - assigned-clock-parents = <&clks VF610_CLK_ENET_50M>, - <&clks VF610_CLK_ENET_50M>; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; -}; - -&edma0 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - disable-wp; -}; - -&fec1 { - phy-mode = "rmii"; - phy-supply = <®_module_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; -}; - -&i2c0 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - status = "okay"; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <32>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; - -&usbdev0 { - disable-over-current; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; - -&iomuxc { - vf610-colibri { - pinctrl_flexcan0: can0grp { - fsl,pins = < - VF610_PAD_PTB14__CAN0_RX 0x31F1 - VF610_PAD_PTB15__CAN0_TX 0x31F2 - >; - }; - - pinctrl_flexcan1: can1grp { - fsl,pins = < - VF610_PAD_PTB16__CAN1_RX 0x31F1 - VF610_PAD_PTB17__CAN1_TX 0x31F2 - >; - }; - - pinctrl_gpio_ext: gpio_ext { - fsl,pins = < - VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */ - VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */ - VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */ - >; - }; - - pinctrl_dcu0_1: dcu0grp_1 { - fsl,pins = < - VF610_PAD_PTE0__DCU0_HSYNC 0x1902 - VF610_PAD_PTE1__DCU0_VSYNC 0x1902 - VF610_PAD_PTE2__DCU0_PCLK 0x1902 - VF610_PAD_PTE4__DCU0_DE 0x1902 - VF610_PAD_PTE5__DCU0_R0 0x1902 - VF610_PAD_PTE6__DCU0_R1 0x1902 - VF610_PAD_PTE7__DCU0_R2 0x1902 - VF610_PAD_PTE8__DCU0_R3 0x1902 - VF610_PAD_PTE9__DCU0_R4 0x1902 - VF610_PAD_PTE10__DCU0_R5 0x1902 - VF610_PAD_PTE11__DCU0_R6 0x1902 - VF610_PAD_PTE12__DCU0_R7 0x1902 - VF610_PAD_PTE13__DCU0_G0 0x1902 - VF610_PAD_PTE14__DCU0_G1 0x1902 - VF610_PAD_PTE15__DCU0_G2 0x1902 - VF610_PAD_PTE16__DCU0_G3 0x1902 - VF610_PAD_PTE17__DCU0_G4 0x1902 - VF610_PAD_PTE18__DCU0_G5 0x1902 - VF610_PAD_PTE19__DCU0_G6 0x1902 - VF610_PAD_PTE20__DCU0_G7 0x1902 - VF610_PAD_PTE21__DCU0_B0 0x1902 - VF610_PAD_PTE22__DCU0_B1 0x1902 - VF610_PAD_PTE23__DCU0_B2 0x1902 - VF610_PAD_PTE24__DCU0_B3 0x1902 - VF610_PAD_PTE25__DCU0_B4 0x1902 - VF610_PAD_PTE26__DCU0_B5 0x1902 - VF610_PAD_PTE27__DCU0_B6 0x1902 - VF610_PAD_PTE28__DCU0_B7 0x1902 - >; - }; - - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x33e2 - VF610_PAD_PTD6__DSPI1_SIN 0x33e1 - VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 - VF610_PAD_PTD8__DSPI1_SCK 0x33e2 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB20__GPIO_42 0x219d - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKOUT 0x30d2 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_bl_on: gpio_bl_on { - fsl,pins = < - VF610_PAD_PTC0__GPIO_45 0x22ef - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - VF610_PAD_PTB0__FTM0_CH0 0x1182 - VF610_PAD_PTB1__FTM0_CH1 0x1182 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - VF610_PAD_PTB8__FTM1_CH0 0x1182 - VF610_PAD_PTB9__FTM1_CH1 0x1182 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - VF610_PAD_PTB12__UART0_RTS 0x21a2 - VF610_PAD_PTB13__UART0_CTS 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 - VF610_PAD_PTD3__UART2_CTS 0x21a1 - >; - }; - - pinctrl_usbh1_reg: gpio_usb_vbus { - fsl,pins = < - VF610_PAD_PTD4__GPIO_83 0x22ed - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/software/linux/kernel/arch/arm/boot/dts/vf500-colibri-eval-v3.dts deleted file mode 100644 index b3aeab58f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf500-colibri-eval-v3.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf500-colibri.dtsi" -#include "vf-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri VF50 on Colibri Evaluation Board"; - compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500"; -}; - -&touchscreen { - vf50-ts-min-pressure = <200>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf500-colibri.dtsi b/software/linux/kernel/arch/arm/boot/dts/vf500-colibri.dtsi deleted file mode 100644 index 1a8a0efa1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf500-colibri.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "vf500.dtsi" -#include "vf-colibri.dtsi" - -/ { - model = "Toradex Colibri VF50 COM"; - compatible = "toradex,vf610-colibri_vf50", "fsl,vf500"; - - memory { - reg = <0x80000000 0x8000000>; - }; - - touchscreen: vf50-touchscreen { - compatible = "toradex,vf50-touchscreen"; - io-channels = <&adc1 0>,<&adc0 0>, - <&adc0 1>,<&adc1 2>; - xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "idle","default","gpios"; - pinctrl-0 = <&pinctrl_touchctrl_idle>; - pinctrl-1 = <&pinctrl_touchctrl_default>; - pinctrl-2 = <&pinctrl_touchctrl_gpios>; - vf50-ts-min-pressure = <200>; - status = "disabled"; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; -}; - -&iomuxc { - vf610-colibri { - pinctrl_touchctrl_idle: touchctrl_idle { - fsl,pins = < - VF610_PAD_PTA18__GPIO_8 0x006d - VF610_PAD_PTA19__GPIO_9 0x006c - >; - }; - - pinctrl_touchctrl_default: touchctrl_default { - fsl,pins = < - VF610_PAD_PTA18__ADC0_SE0 0x0040 - VF610_PAD_PTA19__ADC0_SE1 0x0040 - VF610_PAD_PTA16__ADC1_SE0 0x0040 - VF610_PAD_PTB2__ADC1_SE2 0x0040 - >; - }; - - pinctrl_touchctrl_gpios: touchctrl_gpios { - fsl,pins = < - VF610_PAD_PTA23__GPIO_13 0x22e9 - VF610_PAD_PTB23__GPIO_93 0x22e9 - VF610_PAD_PTA22__GPIO_12 0x22e9 - VF610_PAD_PTA11__GPIO_4 0x22e9 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf500.dtsi b/software/linux/kernel/arch/arm/boot/dts/vf500.dtsi deleted file mode 100644 index d7fdb2a7d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf500.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include "vfxxx.dtsi" -#include - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a5_cpu: cpu@0 { - compatible = "arm,cortex-a5"; - device_type = "cpu"; - reg = <0x0>; - }; - }; - - soc { - aips-bus@40000000 { - - intc: interrupt-controller@40002000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupt-parent = <&intc>; - reg = <0x40003000 0x1000>, - <0x40002100 0x100>; - }; - - global_timer: timer@40002200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x40002200 0x20>; - interrupts = ; - interrupt-parent = <&intc>; - clocks = <&clks VF610_CLK_PLATFORM_BUS>; - }; - }; - - aips-bus@40080000 { - pmu@40089000 { - compatible = "arm,cortex-a5-pmu"; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a5_cpu>; - reg = <0x40089000 0x1000>; - }; - }; - - }; -}; - -&mscm_ir { - interrupt-parent = <&intc>; -}; - -&wdoga5 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/software/linux/kernel/arch/arm/boot/dts/vf610-colibri-eval-v3.dts deleted file mode 100644 index dbca4f86f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610-colibri-eval-v3.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610-colibri.dtsi" -#include "vf-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri VF61 on Colibri Evaluation Board"; - compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610-colibri.dtsi b/software/linux/kernel/arch/arm/boot/dts/vf610-colibri.dtsi deleted file mode 100644 index 9ec9e337f..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610-colibri.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "vf610.dtsi" -#include "vf-colibri.dtsi" - -/ { - model = "Toradex Colibri VF61 COM"; - compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; - - memory { - reg = <0x80000000 0x10000000>; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <50000000>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610-cosmic.dts b/software/linux/kernel/arch/arm/boot/dts/vf610-cosmic.dts deleted file mode 100644 index 5447f2594..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610-cosmic.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "PHYTEC Cosmic/Cosmic+ Board"; - compatible = "phytec,vf610-cosmic", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP1,115200"; - }; - - memory { - reg = <0x80000000 0x10000000>; - }; - - enet_ext: enet_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; -}; - -&clks { - clocks = <&sxosc>, <&fxosc>, <&enet_ext>; - clock-names = "sxosc", "fxosc", "enet_ext"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&iomuxc { - vf610-cosmic { - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610-pinfunc.h b/software/linux/kernel/arch/arm/boot/dts/vf610-pinfunc.h deleted file mode 100644 index fcad7132c..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610-pinfunc.h +++ /dev/null @@ -1,810 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_VF610_PINFUNC_H -#define __DTS_VF610_PINFUNC_H - -/* - * The pin function ID for VF610 is a tuple of: - * - */ - -#define ALT0 0x0 -#define ALT1 0x1 -#define ALT2 0x2 -#define ALT3 0x3 -#define ALT4 0x4 -#define ALT5 0x5 -#define ALT6 0x6 -#define ALT7 0x7 - - -#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 -#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 -#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 -#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 -#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 -#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 -#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 -#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 -#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 -#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 -#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 -#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 -#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 -#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 -#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 -#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 -#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 -#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 -#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 -#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 -#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 -#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 -#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 -#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 -#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 -#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 -#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 -#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 -#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 -#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 -#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 -#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 -#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 -#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 -#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 -#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 -#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 -#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 -#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 -#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 -#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 -#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 -#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 -#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 -#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 -#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 -#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 -#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 -#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 -#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 -#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 -#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 -#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 -#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 -#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 -#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 -#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 -#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 -#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 -#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 -#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 -#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 -#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 -#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 -#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 -#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 -#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 -#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 -#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 -#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 -#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 -#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 -#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 -#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 -#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 -#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 -#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 -#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 -#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 -#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 -#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 -#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 -#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 -#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 -#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 -#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 -#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 -#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 -#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 -#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 -#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 -#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 -#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 -#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 -#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 -#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 -#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 -#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 -#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 -#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 -#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 -#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 -#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 -#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 -#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 -#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 -#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 -#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 -#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 -#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 -#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 -#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 -#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 -#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 -#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 -#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 -#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 -#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 -#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 -#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 -#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 -#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 -#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 -#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 -#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 -#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 -#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 -#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 -#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 -#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 -#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 -#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 -#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 -#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 -#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 -#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 -#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 -#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 -#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 -#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 -#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 -#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 -#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 -#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 -#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 -#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 -#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 -#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 -#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 -#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 -#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 -#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 -#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 -#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 -#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 -#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 -#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 -#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 -#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 -#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 -#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 -#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 -#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 -#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 -#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 -#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 -#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 -#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 -#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 -#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 -#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 -#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 -#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 -#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 -#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 -#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 -#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 -#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 -#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 -#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 -#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 -#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 -#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 -#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 -#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 -#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 -#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 -#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 -#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 -#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 -#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 -#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 -#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 -#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 -#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 -#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 -#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 -#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 -#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 -#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 -#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 -#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 -#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 -#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 -#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 -#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 -#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 -#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 -#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 -#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 -#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 -#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 -#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 -#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 -#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 -#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 -#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 -#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 -#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 -#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 -#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 -#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 -#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 -#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 -#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 -#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 -#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 -#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 -#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 -#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 -#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 -#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 -#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 -#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 -#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 -#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 -#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 -#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 -#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 -#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 -#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 -#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 -#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 -#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 -#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 -#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 -#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 -#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 -#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 -#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 -#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 -#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 -#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 -#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 -#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 -#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 -#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 -#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 -#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 -#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 -#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 -#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 -#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 -#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 -#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 -#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 -#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 -#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 -#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 -#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 -#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 -#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 -#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 -#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 -#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 -#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 -#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 -#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 -#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 -#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 -#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 -#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 -#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 -#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 -#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 -#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 -#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 -#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 -#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 -#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 -#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 -#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 -#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 -#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 -#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 -#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 -#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 -#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 -#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 -#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 -#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 -#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 -#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 -#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 -#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 -#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 -#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 -#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 -#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 -#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 -#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 -#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 -#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 -#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 -#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 -#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 -#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 -#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 -#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 -#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 -#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 -#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 -#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 -#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 -#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 -#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 -#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 -#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 -#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 -#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 -#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 -#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 -#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 -#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 -#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 -#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 -#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 -#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 -#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 -#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 -#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 -#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 -#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 -#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 -#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0 -#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 -#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 -#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 -#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 -#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 -#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 -#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 -#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 -#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 -#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 -#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 -#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 -#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 -#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 -#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 -#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 -#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 -#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 -#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 -#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 -#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 -#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 -#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 -#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 -#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 -#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 -#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 -#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 -#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 -#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 -#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 -#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 -#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 -#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 -#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 -#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 -#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 -#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 -#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 -#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 -#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 -#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 -#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 -#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 -#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 -#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 -#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 -#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 -#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 -#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 -#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 -#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 -#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 -#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 -#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 -#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 -#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 -#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 -#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 -#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 -#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 -#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 -#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 -#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 -#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 -#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 -#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 -#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 -#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 -#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 -#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 -#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 -#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 -#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 -#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 -#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 -#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 -#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 -#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 -#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 -#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 -#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 -#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 -#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 -#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 -#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 -#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 -#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 -#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 -#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 -#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 -#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 -#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 -#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 -#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 -#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 -#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 -#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 -#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 -#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 -#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 -#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 -#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 -#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 -#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 -#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 -#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 -#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 -#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 -#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 -#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 -#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 -#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 -#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 -#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 -#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 -#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 -#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 -#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 -#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 -#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 -#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 -#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 -#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 -#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 -#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 -#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 -#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 -#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 -#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 -#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 -#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 -#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 -#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 -#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 -#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 -#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 -#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 -#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 -#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 -#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 -#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 -#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 -#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 -#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 -#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 -#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 -#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 -#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 -#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 -#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 -#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 -#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 -#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 -#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 -#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 -#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 -#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 -#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 -#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 -#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 -#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 -#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 -#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 -#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 -#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 -#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 -#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 -#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 -#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 -#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 -#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 -#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 -#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 -#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 -#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 -#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 -#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 -#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 -#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 -#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 -#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 -#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 -#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 -#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 -#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 -#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 -#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 -#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 -#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 -#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 -#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 -#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 -#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 -#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 -#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 -#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 -#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 -#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 -#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 -#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 -#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 -#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 -#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 -#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 -#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 -#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 -#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 -#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 -#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 -#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 -#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 -#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 -#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 -#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 -#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 -#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 -#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 -#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 -#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 -#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 -#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 -#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 -#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 -#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 -#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 -#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 -#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 -#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 -#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 -#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 -#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 -#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 -#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 -#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 -#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 -#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 -#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 -#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 -#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 -#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 -#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 -#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 -#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 -#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 -#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 -#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 -#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 -#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 -#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 -#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 -#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 -#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 -#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 -#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 -#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 -#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 -#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 -#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 -#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 -#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 -#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 -#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 -#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 -#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 -#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 -#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 -#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 -#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 -#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 -#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 -#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 -#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 -#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 -#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 -#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 -#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 -#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 -#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 -#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 -#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 -#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 -#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 -#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 -#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 -#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 -#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 -#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 -#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 -#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 -#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 -#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 -#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 -#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 -#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 -#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 -#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 -#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 -#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 -#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 -#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 -#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 -#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 -#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 -#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 -#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 -#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 -#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 -#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 -#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 -#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 -#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 -#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 -#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 -#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 -#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 -#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 -#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 -#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 -#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 -#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 -#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 -#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 -#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 -#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 -#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 -#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 -#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 -#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 -#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 -#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 -#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 -#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 -#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 -#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 -#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 -#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 -#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 -#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 -#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 -#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 -#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 -#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 -#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 -#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 -#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 -#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 -#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 -#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 -#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 -#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 -#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 -#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 -#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 -#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 -#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 -#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 -#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 -#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 -#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 -#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 -#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 -#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 -#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 -#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 -#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 -#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 -#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 -#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 -#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 -#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 -#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 -#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 -#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 -#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 -#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 -#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 -#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 -#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 -#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 -#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 -#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 -#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 -#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 -#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 -#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 -#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 -#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 -#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 -#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 -#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 -#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 -#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 -#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 -#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 -#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 -#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 -#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 -#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 -#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 -#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 -#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 -#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 -#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 -#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 -#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 -#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 -#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 -#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 -#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 -#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 -#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 -#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 -#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 -#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 -#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 -#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 -#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 -#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 -#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 -#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 -#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 -#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 -#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 -#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 -#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 -#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 -#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 -#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 -#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 -#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 -#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 -#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 -#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 -#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 -#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 - -#endif diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610-twr.dts b/software/linux/kernel/arch/arm/boot/dts/vf610-twr.dts deleted file mode 100644 index cdc100732..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610-twr.dts +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "VF610 Tower Board"; - compatible = "fsl,vf610-twr", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP1,115200"; - }; - - memory { - reg = <0x80000000 0x8000000>; - }; - - audio_ext: mclk_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - enet_ext: eth_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vcc_3v3_mcu: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - }; - }; -}; - -&adc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_ad5>; - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&clks { - clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; - clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; - assigned-clocks = <&clks VF610_CLK_ENET_SEL>, - <&clks VF610_CLK_ENET_TS_SEL>; - assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>, - <&clks VF610_CLK_ENET_EXT>; -}; - -&dspi0 { - bus-num = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0>; - status = "okay"; - - sflash: at26df081a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at26df081a"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&edma0 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec0 { - phy-mode = "rmii"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&fec1 { - phy-mode = "rmii"; - phy-handle = <ðphy1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - codec: sgtl5000@0a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&clks VF610_CLK_SAI2>; - }; -}; - -&iomuxc { - vf610-twr { - pinctrl_adc0_ad5: adc0ad5grp { - fsl,pins = < - VF610_PAD_PTC30__ADC0_SE5 0xa1 - >; - }; - - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTA7__GPIO_134 0x219d - >; - }; - - pinctrl_fec0: fec0grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x30d3 - VF610_PAD_PTB15__I2C0_SDA 0x30d3 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - VF610_PAD_PTD31__NF_IO15 0x28df - VF610_PAD_PTD30__NF_IO14 0x28df - VF610_PAD_PTD29__NF_IO13 0x28df - VF610_PAD_PTD28__NF_IO12 0x28df - VF610_PAD_PTD27__NF_IO11 0x28df - VF610_PAD_PTD26__NF_IO10 0x28df - VF610_PAD_PTD25__NF_IO9 0x28df - VF610_PAD_PTD24__NF_IO8 0x28df - VF610_PAD_PTD23__NF_IO7 0x28df - VF610_PAD_PTD22__NF_IO6 0x28df - VF610_PAD_PTD21__NF_IO5 0x28df - VF610_PAD_PTD20__NF_IO4 0x28df - VF610_PAD_PTD19__NF_IO3 0x28df - VF610_PAD_PTD18__NF_IO2 0x28df - VF610_PAD_PTD17__NF_IO1 0x28df - VF610_PAD_PTD16__NF_IO0 0x28df - VF610_PAD_PTB24__NF_WE_B 0x28c2 - VF610_PAD_PTB25__NF_CE0_B 0x28c2 - VF610_PAD_PTB27__NF_RE_B 0x28c2 - VF610_PAD_PTC26__NF_RB_B 0x283d - VF610_PAD_PTC27__NF_ALE 0x28c2 - VF610_PAD_PTC28__NF_CLE 0x28c2 - >; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - VF610_PAD_PTB0__FTM0_CH0 0x1582 - VF610_PAD_PTB1__FTM0_CH1 0x1582 - VF610_PAD_PTB2__FTM0_CH2 0x1582 - VF610_PAD_PTB3__FTM0_CH3 0x1582 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed - VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee - VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed - VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed - VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed - VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed - VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB4__UART1_TX 0x21a2 - VF610_PAD_PTB5__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTB6__UART2_TX 0x21a2 - VF610_PAD_PTB7__UART2_RX 0x21a1 - >; - }; - }; -}; - -&nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - status = "okay"; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <16>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <24>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; - status = "okay"; -}; - -&sai2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbdev0 { - disable-over-current; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/software/linux/kernel/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts deleted file mode 100644 index 5c1fcab4a..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "ZII VF610 Development Board, Rev B"; - compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0x80000000 0x20000000>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pinctrl_leds_debug>; - pinctrl-names = "default"; - - debug { - label = "zii:green:debug1"; - gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - mdio-mux { - compatible = "mdio-mux-gpio"; - pinctrl-0 = <&pinctrl_mdio_mux>; - pinctrl-names = "default"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH - &gpio0 9 GPIO_ACTIVE_HIGH - &gpio0 24 GPIO_ACTIVE_HIGH - &gpio0 25 GPIO_ACTIVE_HIGH>; - mdio-parent-bus = <&mdio1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio_mux_1: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch0@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - switch0port5: port@5 { - reg = <5>; - label = "dsa"; - phy-mode = "rgmii-txid"; - link = <&switch1port6 - &switch2port9>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&fec1>; - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; - }; - - mdio_mux_2: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - switch1: switch1@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - dsa,member = <0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan3"; - phy-handle = <&switch1phy0>; - }; - - port@1 { - reg = <1>; - label = "lan4"; - phy-handle = <&switch1phy1>; - }; - - port@2 { - reg = <2>; - label = "lan5"; - phy-handle = <&switch1phy2>; - }; - - switch1port5: port@5 { - reg = <5>; - label = "dsa"; - link = <&switch2port9>; - phy-mode = "rgmii-txid"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch1port6: port@6 { - reg = <6>; - label = "dsa"; - phy-mode = "rgmii-txid"; - link = <&switch0port5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - switch1phy0: switch1phy0@0 { - reg = <0>; - }; - switch1phy1: switch1phy0@1 { - reg = <1>; - }; - switch1phy2: switch1phy0@2 { - reg = <2>; - }; - }; - }; - }; - - mdio_mux_4: mdio@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - switch2: switch2@0 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - dsa,member = <0 2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan6"; - }; - - port@1 { - reg = <1>; - label = "lan7"; - }; - - port@2 { - reg = <2>; - label = "lan8"; - }; - - port@3 { - reg = <3>; - label = "optical3"; - fixed-link { - speed = <1000>; - full-duplex; - link-gpios = <&gpio6 2 - GPIO_ACTIVE_HIGH>; - }; - }; - - port@4 { - reg = <4>; - label = "optical4"; - fixed-link { - speed = <1000>; - full-duplex; - link-gpios = <&gpio6 3 - GPIO_ACTIVE_HIGH>; - }; - }; - - switch2port9: port@9 { - reg = <9>; - label = "dsa"; - phy-mode = "rgmii-txid"; - link = <&switch1port5 - &switch0port5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; - - mdio_mux_8: mdio@8 { - reg = <8>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - pinctrl-0 = <&pinctrl_usb_vbus>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 6 0>; - }; - - spi0 { - compatible = "spi-gpio"; - pinctrl-0 = <&pinctrl_gpio_spi0>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH - &gpio1 8 GPIO_ACTIVE_HIGH>; - num-chipselects = <2>; - - m25p128@0 { - compatible = "m25p128", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - at93c46d@1 { - compatible = "atmel,at93c46d"; - pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>; - pinctrl-names = "default"; - #address-cells = <0>; - #size-cells = <0>; - reg = <1>; - spi-max-frequency = <500000>; - spi-cs-high; - data-size = <16>; - select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_ad5>; - vref-supply = <®_vcc_3v3_mcu>; - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - bus-width = <4>; - status = "okay"; -}; - -&fec0 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0>; - status = "okay"; -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - fixed-link { - speed = <100>; - full-duplex; - }; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - status = "okay"; - - gpio5: pca9554@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - - }; - - gpio6: pca9554@22 { - compatible = "nxp,pca9554"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9554_22>; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - }; - - lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - at24c04@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - }; - - at24c04@52 { - compatible = "atmel,24c04"; - reg = <0x52>; - }; - - ds1682@6b { - compatible = "dallas,ds1682"; - reg = <0x6b>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - tca9548@70 { - compatible = "nxp,pca9548"; - pinctrl-0 = <&pinctrl_i2c_mux_reset>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - sfp1: at24c04@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - sfp2: at24c04@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - sfp3: at24c04@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - sfp4: at24c04@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbdev0 { - disable-over-current; - vbus-supply = <&usb0_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbmisc0 { - status = "okay"; -}; - -&usbmisc1 { - status = "okay"; -}; - -&usbphy0 { - status = "okay"; -}; - -&usbphy1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_adc0_ad5: adc0ad5grp { - fsl,pins = < - VF610_PAD_PTC30__ADC0_SE5 0x00a1 - >; - }; - - pinctrl_dspi0: dspi0grp { - fsl,pins = < - VF610_PAD_PTB18__DSPI0_CS1 0x1182 - VF610_PAD_PTB19__DSPI0_CS0 0x1182 - VF610_PAD_PTB20__DSPI0_SIN 0x1181 - VF610_PAD_PTB21__DSPI0_SOUT 0x1182 - VF610_PAD_PTB22__DSPI0_SCK 0x1182 - >; - }; - - pinctrl_dspi2: dspi2grp { - fsl,pins = < - VF610_PAD_PTD31__DSPI2_CS1 0x1182 - VF610_PAD_PTD30__DSPI2_CS0 0x1182 - VF610_PAD_PTD29__DSPI2_SIN 0x1181 - VF610_PAD_PTD28__DSPI2_SOUT 0x1182 - VF610_PAD_PTD27__DSPI2_SCK 0x1182 - >; - }; - - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - VF610_PAD_PTA24__ESDHC1_CLK 0x31ef - VF610_PAD_PTA25__ESDHC1_CMD 0x31ef - VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef - VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef - VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef - VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef - VF610_PAD_PTA7__GPIO_134 0x219d - >; - }; - - pinctrl_fec0: fec0grp { - fsl,pins = < - VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2 - VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3 - VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 - VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 - VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 - VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 - VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 - VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 - VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - VF610_PAD_PTA6__RMII_CLKIN 0x30d1 - VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 - VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 - VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 - VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 - VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 - VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 - VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 - VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 - >; - }; - - pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { - fsl,pins = < - VF610_PAD_PTE27__GPIO_132 0x33e2 - >; - }; - - pinctrl_gpio_spi0: pinctrl-gpio-spi0 { - fsl,pins = < - VF610_PAD_PTB22__GPIO_44 0x33e2 - VF610_PAD_PTB21__GPIO_43 0x33e2 - VF610_PAD_PTB20__GPIO_42 0x33e1 - VF610_PAD_PTB19__GPIO_41 0x33e2 - VF610_PAD_PTB18__GPIO_40 0x33e2 - >; - }; - - pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset { - fsl,pins = < - VF610_PAD_PTE14__GPIO_119 0x31c2 - >; - }; - - pinctrl_i2c0: i2c0grp { - fsl,pins = < - VF610_PAD_PTB14__I2C0_SCL 0x37ff - VF610_PAD_PTB15__I2C0_SDA 0x37ff - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - VF610_PAD_PTB16__I2C1_SCL 0x37ff - VF610_PAD_PTB17__I2C1_SDA 0x37ff - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - VF610_PAD_PTA22__I2C2_SCL 0x37ff - VF610_PAD_PTA23__I2C2_SDA 0x37ff - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - VF610_PAD_PTA30__I2C3_SCL 0x37ff - VF610_PAD_PTA31__I2C3_SDA 0x37ff - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD20__GPIO_74 0x31c2 - >; - }; - - pinctrl_mdio_mux: pinctrl-mdio-mux { - fsl,pins = < - VF610_PAD_PTA18__GPIO_8 0x31c2 - VF610_PAD_PTA19__GPIO_9 0x31c2 - VF610_PAD_PTB2__GPIO_24 0x31c2 - VF610_PAD_PTB3__GPIO_25 0x31c2 - >; - }; - - pinctrl_pca9554_22: pinctrl-pca95540-22 { - fsl,pins = < - VF610_PAD_PTB28__GPIO_98 0x219d - >; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - VF610_PAD_PTB0__FTM0_CH0 0x1582 - VF610_PAD_PTB1__FTM0_CH1 0x1582 - VF610_PAD_PTB2__FTM0_CH2 0x1582 - VF610_PAD_PTB3__FTM0_CH3 0x1582 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 - VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff - VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 - >; - }; - - pinctrl_uart0: uart0grp { - fsl,pins = < - VF610_PAD_PTB10__UART0_TX 0x21a2 - VF610_PAD_PTB11__UART0_RX 0x21a1 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - VF610_PAD_PTB23__UART1_TX 0x21a2 - VF610_PAD_PTB24__UART1_RX 0x21a1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - >; - }; - - pinctrl_usb_vbus: pinctrl-usb-vbus { - fsl,pins = < - VF610_PAD_PTA16__GPIO_6 0x31c2 - >; - }; - - pinctrl_usb0_host: usb0-host-grp { - fsl,pins = < - VF610_PAD_PTD6__GPIO_85 0x0062 - >; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610.dtsi b/software/linux/kernel/arch/arm/boot/dts/vf610.dtsi deleted file mode 100644 index 0cfc060f9..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "vf500.dtsi" - -&a5_cpu { - next-level-cache = <&L2>; -}; - -&aips0 { - L2: l2-cache@40006000 { - compatible = "arm,pl310-cache"; - reg = <0x40006000 0x1000>; - cache-unified; - cache-level = <2>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610m4-colibri.dts b/software/linux/kernel/arch/arm/boot/dts/vf610m4-colibri.dts deleted file mode 100644 index 2931a80ca..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610m4-colibri.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Device tree for Colibri VF61 Cortex-M4 support - * - * Copyright (C) 2015 Stefan Agner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610m4.dtsi" - -/ { - model = "VF610 Cortex-M4"; - compatible = "fsl,vf610m4"; - - chosen { - bootargs = "console=ttyLP2,115200 clk_ignore_unused init=/linuxrc rw"; - linux,stdout-path = "&uart2"; - }; - - memory { - reg = <0x8c000000 0x3000000>; - }; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&gpio3 { - status = "disabled"; -}; - -&gpio4 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&iomuxc { - vf610-colibri { - pinctrl_uart2: uart2grp { - fsl,pins = < - VF610_PAD_PTD0__UART2_TX 0x21a2 - VF610_PAD_PTD1__UART2_RX 0x21a1 - VF610_PAD_PTD2__UART2_RTS 0x21a2 - VF610_PAD_PTD3__UART2_CTS 0x21a1 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610m4-cosmic.dts b/software/linux/kernel/arch/arm/boot/dts/vf610m4-cosmic.dts deleted file mode 100644 index 8944a2d20..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610m4-cosmic.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Device tree for Cosmic+ VF6xx Cortex-M4 support - * - * Copyright (C) 2015 - * - * Based on vf610m4 Colibri - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "vf610m4.dtsi" - -/ { - model = "VF610 Cortex-M4"; - compatible = "fsl,vf610m4"; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&gpio3 { - status = "disabled"; -}; - -&gpio4 { - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&iomuxc { - vf610-cosmic { - pinctrl_uart3: uart3grp { - fsl,pins = < - VF610_PAD_PTA20__UART3_TX 0x21a2 - VF610_PAD_PTA21__UART3_RX 0x21a1 - >; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vf610m4.dtsi b/software/linux/kernel/arch/arm/boot/dts/vf610m4.dtsi deleted file mode 100644 index 9f2c73183..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vf610m4.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Device tree for VF6xx Cortex-M4 support - * - * Copyright (C) 2015 Stefan Agner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "skeleton.dtsi" -#include "armv7-m.dtsi" -#include "vfxxx.dtsi" - -&mscm_ir { - interrupt-parent = <&nvic>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vfxxx.dtsi b/software/linux/kernel/arch/arm/boot/dts/vfxxx.dtsi deleted file mode 100644 index 2c13ec696..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vfxxx.dtsi +++ /dev/null @@ -1,753 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "vf610-pinfunc.h" -#include -#include -#include - -/ { - aliases { - can0 = &can0; - can1 = &can1; - ethernet0 = &fec0; - ethernet1 = &fec1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - usbphy0 = &usbphy0; - usbphy1 = &usbphy1; - }; - - fxosc: fxosc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - sxosc: sxosc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&src>; - offset = <0x0>; - mask = <0x1000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&mscm_ir>; - ranges; - - aips0: aips-bus@40000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x00070000>; - ranges; - - mscm_cpucfg: cpucfg@40001000 { - compatible = "fsl,vf610-mscm-cpucfg", "syscon"; - reg = <0x40001000 0x800>; - }; - - mscm_ir: interrupt-controller@40001800 { - compatible = "fsl,vf610-mscm-ir"; - reg = <0x40001800 0x400>; - fsl,cpucfg = <&mscm_cpucfg>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - edma0: dma-controller@40018000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40018000 0x2000>, - <0x40024000 0x1000>, - <0x40025000 0x1000>; - dma-channels = <32>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, - <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX0>, - <&clks VF610_CLK_DMAMUX1>; - status = "disabled"; - }; - - can0: flexcan@40020000 { - compatible = "fsl,vf610-flexcan"; - reg = <0x40020000 0x4000>; - interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_FLEXCAN0>, - <&clks VF610_CLK_FLEXCAN0>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart0: serial@40027000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40027000 0x1000>; - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART0>; - clock-names = "ipg"; - dmas = <&edma0 0 2>, - <&edma0 0 3>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart1: serial@40028000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40028000 0x1000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART1>; - clock-names = "ipg"; - dmas = <&edma0 0 4>, - <&edma0 0 5>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart2: serial@40029000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40029000 0x1000>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART2>; - clock-names = "ipg"; - dmas = <&edma0 0 6>, - <&edma0 0 7>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart3: serial@4002a000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x4002a000 0x1000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART3>; - clock-names = "ipg"; - dmas = <&edma0 0 8>, - <&edma0 0 9>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - dspi0: dspi0@4002c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002c000 0x1000>; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI0>; - clock-names = "dspi"; - spi-num-chipselects = <6>; - status = "disabled"; - }; - - dspi1: dspi1@4002d000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002d000 0x1000>; - interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI1>; - clock-names = "dspi"; - spi-num-chipselects = <4>; - status = "disabled"; - }; - - sai0: sai@4002f000 { - compatible = "fsl,vf610-sai"; - reg = <0x4002f000 0x1000>; - interrupts = <84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI0>, - <&clks VF610_CLK_SAI0_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 17>, - <&edma0 0 16>; - status = "disabled"; - }; - - sai1: sai@40030000 { - compatible = "fsl,vf610-sai"; - reg = <0x40030000 0x1000>; - interrupts = <85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI1>, - <&clks VF610_CLK_SAI1_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 19>, - <&edma0 0 18>; - status = "disabled"; - }; - - sai2: sai@40031000 { - compatible = "fsl,vf610-sai"; - reg = <0x40031000 0x1000>; - interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI2>, - <&clks VF610_CLK_SAI2_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 21>, - <&edma0 0 20>; - status = "disabled"; - }; - - sai3: sai@40032000 { - compatible = "fsl,vf610-sai"; - reg = <0x40032000 0x1000>; - interrupts = <87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI3>, - <&clks VF610_CLK_SAI3_DIV>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 9>, - <&edma0 1 8>; - status = "disabled"; - }; - - pit: pit@40037000 { - compatible = "fsl,vf610-pit"; - reg = <0x40037000 0x1000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_PIT>; - clock-names = "pit"; - }; - - pwm0: pwm@40038000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x40038000 0x1000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM0>, - <&clks VF610_CLK_FTM0_EXT_SEL>, - <&clks VF610_CLK_FTM0_FIX_SEL>, - <&clks VF610_CLK_FTM0_EXT_FIX_EN>; - status = "disabled"; - }; - - pwm1: pwm@40039000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x40039000 0x1000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM1>, - <&clks VF610_CLK_FTM1_EXT_SEL>, - <&clks VF610_CLK_FTM1_FIX_SEL>, - <&clks VF610_CLK_FTM1_EXT_FIX_EN>; - status = "disabled"; - }; - - adc0: adc@4003b000 { - compatible = "fsl,vf610-adc"; - reg = <0x4003b000 0x1000>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ADC0>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - }; - - tcon0: timing-controller@4003d000 { - compatible = "fsl,vf610-tcon"; - reg = <0x4003d000 0x1000>; - clocks = <&clks VF610_CLK_TCON0>; - clock-names = "ipg"; - status = "disabled"; - }; - - wdoga5: wdog@4003e000 { - compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; - reg = <0x4003e000 0x1000>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_WDT>; - clock-names = "wdog"; - status = "disabled"; - }; - - qspi0: quadspi@40044000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI0_EN>, - <&clks VF610_CLK_QSPI0>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - iomuxc: iomuxc@40048000 { - compatible = "fsl,vf610-iomuxc"; - reg = <0x40048000 0x1000>; - }; - - gpio0: gpio@40049000 { - compatible = "fsl,vf610-gpio"; - reg = <0x40049000 0x1000 0x400ff000 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 0 32>; - }; - - gpio1: gpio@4004a000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004a000 0x1000 0x400ff040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 32 32>; - }; - - gpio2: gpio@4004b000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004b000 0x1000 0x400ff080 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 64 32>; - }; - - gpio3: gpio@4004c000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 96 32>; - }; - - gpio4: gpio@4004d000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004d000 0x1000 0x400ff100 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 128 7>; - }; - - anatop: anatop@40050000 { - compatible = "fsl,vf610-anatop", "syscon"; - reg = <0x40050000 0x400>; - }; - - usbphy0: usbphy@40050800 { - compatible = "fsl,vf610-usbphy"; - reg = <0x40050800 0x400>; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBPHY0>; - fsl,anatop = <&anatop>; - status = "disabled"; - }; - - usbphy1: usbphy@40050c00 { - compatible = "fsl,vf610-usbphy"; - reg = <0x40050c00 0x400>; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - status = "disabled"; - }; - - dcu0: dcu@40058000 { - compatible = "fsl,vf610-dcu"; - reg = <0x40058000 0x1200>; - interrupts = <30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DCU0>, - <&clks VF610_CLK_DCU0_DIV>; - clock-names = "dcu", "pix"; - fsl,tcon = <&tcon0>; - status = "disabled"; - }; - - i2c0: i2c@40066000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x40066000 0x1000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C0>; - clock-names = "ipg"; - dmas = <&edma0 0 50>, - <&edma0 0 51>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - i2c1: i2c@40067000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x40067000 0x1000>; - interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C1>; - clock-names = "ipg"; - dmas = <&edma0 0 52>, - <&edma0 0 53>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - clks: ccm@4006b000 { - compatible = "fsl,vf610-ccm"; - reg = <0x4006b000 0x1000>; - clocks = <&sxosc>, <&fxosc>; - clock-names = "sxosc", "fxosc"; - #clock-cells = <1>; - }; - - usbdev0: usb@40034000 { - compatible = "fsl,vf610-usb", "fsl,imx27-usb"; - reg = <0x40034000 0x800>; - interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBC0>; - fsl,usbphy = <&usbphy0>; - fsl,usbmisc = <&usbmisc0 0>; - dr_mode = "peripheral"; - status = "disabled"; - }; - - usbmisc0: usb@40034800 { - #index-cells = <1>; - compatible = "fsl,vf610-usbmisc"; - reg = <0x40034800 0x200>; - clocks = <&clks VF610_CLK_USBC0>; - status = "disabled"; - }; - - src: src@4006e000 { - compatible = "fsl,vf610-src", "syscon"; - reg = <0x4006e000 0x1000>; - interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips1: aips-bus@40080000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40080000 0x0007f000>; - ranges; - - edma1: dma-controller@40098000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40098000 0x2000>, - <0x400a1000 0x1000>, - <0x400a2000 0x1000>; - dma-channels = <32>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX2>, - <&clks VF610_CLK_DMAMUX3>; - status = "disabled"; - }; - - snvs0: snvs@400a7000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x400a7000 0x2000>; - - snvsrtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs0>; - offset = <0x34>; - interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SNVS>; - clock-names = "snvs-rtc"; - }; - }; - - uart4: serial@400a9000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x400a9000 0x1000>; - interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART4>; - clock-names = "ipg"; - status = "disabled"; - }; - - uart5: serial@400aa000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x400aa000 0x1000>; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART5>; - clock-names = "ipg"; - status = "disabled"; - }; - - dspi2: dspi2@400ac000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x400ac000 0x1000>; - interrupts = <69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI2>; - clock-names = "dspi"; - spi-num-chipselects = <2>; - status = "disabled"; - }; - - dspi3: dspi3@400ad000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x400ad000 0x1000>; - interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI3>; - clock-names = "dspi"; - spi-num-chipselects = <2>; - status = "disabled"; - }; - - adc1: adc@400bb000 { - compatible = "fsl,vf610-adc"; - reg = <0x400bb000 0x1000>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ADC1>; - clock-names = "adc"; - #io-channel-cells = <1>; - status = "disabled"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - }; - - esdhc0: esdhc@400b1000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x400b1000 0x1000>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_IPG_BUS>, - <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_ESDHC0>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - esdhc1: esdhc@400b2000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x400b2000 0x1000>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_IPG_BUS>, - <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_ESDHC1>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - usbh1: usb@400b4000 { - compatible = "fsl,vf610-usb", "fsl,imx27-usb"; - reg = <0x400b4000 0x800>; - interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_USBC1>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc1 0>; - dr_mode = "host"; - status = "disabled"; - }; - - usbmisc1: usb@400b4800 { - #index-cells = <1>; - compatible = "fsl,vf610-usbmisc"; - reg = <0x400b4800 0x200>; - clocks = <&clks VF610_CLK_USBC1>; - status = "disabled"; - }; - - ftm: ftm@400b8000 { - compatible = "fsl,ftm-timer"; - reg = <0x400b8000 0x1000 0x400b9000 0x1000>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "ftm-evt", "ftm-src", - "ftm-evt-counter-en", "ftm-src-counter-en"; - clocks = <&clks VF610_CLK_FTM2>, - <&clks VF610_CLK_FTM3>, - <&clks VF610_CLK_FTM2_EXT_FIX_EN>, - <&clks VF610_CLK_FTM3_EXT_FIX_EN>; - status = "disabled"; - }; - - qspi1: quadspi@400c4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-qspi"; - reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI1_EN>, - <&clks VF610_CLK_QSPI1>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - dac0: dac@400cc000 { - compatible = "fsl,vf610-dac"; - reg = <0x400cc000 1000>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dac"; - clocks = <&clks VF610_CLK_DAC0>; - status = "disabled"; - }; - - dac1: dac@400cd000 { - compatible = "fsl,vf610-dac"; - reg = <0x400cd000 1000>; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dac"; - clocks = <&clks VF610_CLK_DAC1>; - status = "disabled"; - }; - - fec0: ethernet@400d0000 { - compatible = "fsl,mvf600-fec"; - reg = <0x400d0000 0x1000>; - interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ENET0>, - <&clks VF610_CLK_ENET0>, - <&clks VF610_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - fec1: ethernet@400d1000 { - compatible = "fsl,mvf600-fec"; - reg = <0x400d1000 0x1000>; - interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ENET1>, - <&clks VF610_CLK_ENET1>, - <&clks VF610_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - can1: flexcan@400d4000 { - compatible = "fsl,vf610-flexcan"; - reg = <0x400d4000 0x4000>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_FLEXCAN1>, - <&clks VF610_CLK_FLEXCAN1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - nfc: nand@400e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-nfc"; - reg = <0x400e0000 0x4000>; - interrupts = <83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_NFC>; - clock-names = "nfc"; - status = "disabled"; - }; - - i2c2: i2c@400e6000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x400e6000 0x1000>; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C2>; - clock-names = "ipg"; - dmas = <&edma0 1 36>, - <&edma0 1 37>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - i2c3: i2c@400e7000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x400e7000 0x1000>; - interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C3>; - clock-names = "ipg"; - dmas = <&edma0 1 38>, - <&edma0 1 39>; - dma-names = "rx","tx"; - status = "disabled"; - }; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 16>, <&adc1 16>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vt8500-bv07.dts b/software/linux/kernel/arch/arm/boot/dts/vt8500-bv07.dts deleted file mode 100644 index 87f33310e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vt8500-bv07.dts +++ /dev/null @@ -1,36 +0,0 @@ -/* - * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/dts-v1/; -/include/ "vt8500.dtsi" - -/ { - model = "Benign BV07 Netbook"; -}; - -&fb { - bits-per-pixel = <16>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/vt8500.dtsi b/software/linux/kernel/arch/arm/boot/dts/vt8500.dtsi deleted file mode 100644 index 1929ad390..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/vt8500.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -/* - * vt8500.dtsi - Device tree file for VIA VT8500 SoC - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "via,vt8500"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc>; - - intc: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "via,vt8500-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <3>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <4>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <43>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <43>; - }; - - fb: fb@d8050800 { - compatible = "via,vt8500-fb"; - reg = <0xd800e400 0x400>; - interrupts = <12>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wd-mbwe.dts b/software/linux/kernel/arch/arm/boot/dts/wd-mbwe.dts deleted file mode 100644 index ac3250ae8..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wd-mbwe.dts +++ /dev/null @@ -1,112 +0,0 @@ -/* - * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition - * - * Copyright (C) 2016 Neil Armstrong - * - * Licensed under GPLv2 or later - */ - -/dts-v1/; -#include "ox810se.dtsi" - -/ { - model = "Western Digital My Book World Edition"; - - compatible = "wd,mbwe", "oxsemi,ox810se"; - - chosen { - bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; - }; - - memory { - /* 128Mbytes DDR */ - reg = <0x48000000 0x8000000>; - }; - - aliases { - serial1 = &uart1; - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power { - label = "power"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - recovery { - label = "recovery"; - gpios = <&gpio0 4 1>; - linux,code = <0xab>; - }; - }; - - leds { - compatible = "gpio-leds"; - - a0 { - label = "activity0"; - gpios = <&gpio0 25 0>; - default-state = "keep"; - }; - - a1 { - label = "activity1"; - gpios = <&gpio0 26 0>; - default-state = "keep"; - }; - - a2 { - label = "activity2"; - gpios = <&gpio0 5 0>; - default-state = "keep"; - }; - - a3 { - label = "activity3"; - gpios = <&gpio0 6 0>; - default-state = "keep"; - }; - - a4 { - label = "activity4"; - gpios = <&gpio0 7 0>; - default-state = "keep"; - }; - - a5 { - label = "activity5"; - gpios = <&gpio1 2 0>; - default-state = "keep"; - }; - }; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&gpio0 3 0 /* sda */ - &gpio0 2 0 /* scl */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - rtc0: rtc@48 { - compatible = "st,m41t00"; - reg = <0x68>; - }; - }; -}; - -&uart1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wm8505-ref.dts b/software/linux/kernel/arch/arm/boot/dts/wm8505-ref.dts deleted file mode 100644 index e3e6b9eb0..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wm8505-ref.dts +++ /dev/null @@ -1,36 +0,0 @@ -/* - * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/dts-v1/; -/include/ "wm8505.dtsi" - -/ { - model = "Wondermedia WM8505 Netbook"; -}; - -&fb { - bits-per-pixel = <32>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wm8505.dtsi b/software/linux/kernel/arch/arm/boot/dts/wm8505.dtsi deleted file mode 100644 index e9ef539e1..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wm8505.dtsi +++ /dev/null @@ -1,290 +0,0 @@ -/* - * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "wm,wm8505"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8505-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "via,vt8500-pll-clock"; - clocks = <&ref25>; - reg = <0x20c>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <3>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <4>; - }; - - clkuart4: uart4 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <22>; - }; - - clkuart5: uart5 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <23>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x328>; - divisor-mask = <0x3f>; - enable-reg = <0x254>; - enable-bit = <18>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007100 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007100 0x200>; - interrupts = <1>; - }; - - uhci@d8007300 { - compatible = "platform-uhci"; - reg = <0xd8007300 0x200>; - interrupts = <0>; - }; - - fb: fb@d8050800 { - compatible = "wm,wm8505-fb"; - reg = <0xd8050800 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - uart4: serial@d8370000 { - compatible = "via,vt8500-uart"; - reg = <0xd8370000 0x1040>; - interrupts = <31>; - clocks = <&clkuart4>; - status = "disabled"; - }; - - uart5: serial@d8380000 { - compatible = "via,vt8500-uart"; - reg = <0xd8380000 0x1040>; - interrupts = <30>; - clocks = <&clkuart5>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x400>; - interrupts = <20>, <21>; - clocks = <&clksdhc>; - bus-width = <4>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wm8650-mid.dts b/software/linux/kernel/arch/arm/boot/dts/wm8650-mid.dts deleted file mode 100644 index dd0d1b602..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wm8650-mid.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/dts-v1/; -/include/ "wm8650.dtsi" - -/ { - model = "Wondermedia WM8650-MID Tablet"; -}; - -&fb { - bits-per-pixel = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wm8650.dtsi b/software/linux/kernel/arch/arm/boot/dts/wm8650.dtsi deleted file mode 100644 index e12213d16..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wm8650.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -/* - * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "wm,wm8650"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - }; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8650-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x20c>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x210>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <1>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x250>; - enable-bit = <2>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x328>; - divisor-mask = <0x3f>; - enable-reg = <0x254>; - enable-bit = <18>; - }; - }; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <43>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <43>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x400>; - interrupts = <20>, <21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - fb: fb@d8050800 { - compatible = "wm,wm8505-fb"; - reg = <0xd8050800 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wm8750-apc8750.dts b/software/linux/kernel/arch/arm/boot/dts/wm8750-apc8750.dts deleted file mode 100644 index 37e4a408b..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wm8750-apc8750.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * wm8750-apc8750.dts - * - Device tree file for VIA APC8750 - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/dts-v1/; -/include/ "wm8750.dtsi" - -/ { - model = "VIA APC8750"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&i2c>; - - i2c: i2c { - wm,pins = <168 169 170 171>; - wm,function = <2>; /* alt */ - wm,pull = <2>; /* pull-up */ - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wm8750.dtsi b/software/linux/kernel/arch/arm/boot/dts/wm8750.dtsi deleted file mode 100644 index 46d076d73..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wm8750.dtsi +++ /dev/null @@ -1,347 +0,0 @@ -/* - * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "wm,wm8750"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm1176jzf"; - }; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8750-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x20C>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8750-pll-clock"; - clocks = <&ref25>; - reg = <0x210>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <24>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <25>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <26>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <27>; - }; - - clkuart4: uart4 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <28>; - }; - - clkuart5: uart5 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <29>; - }; - - clkpwm: pwm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - enable-reg = <0x250>; - enable-bit = <17>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x330>; - divisor-mask = <0x3f>; - enable-reg = <0x250>; - enable-bit = <0>; - }; - - clki2c0: i2c0clk { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x3A0>; - enable-reg = <0x250>; - enable-bit = <8>; - }; - - clki2c1: i2c1clk { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x3A4>; - enable-reg = <0x250>; - enable-bit = <9>; - }; - }; - }; - - pwm: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x100>; - clocks = <&clkpwm>; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <26>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <26>; - }; - - uhci@d8008d00 { - compatible = "platform-uhci"; - reg = <0xd8008d00 0x200>; - interrupts = <26>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - uart4: serial@d8370000 { - compatible = "via,vt8500-uart"; - reg = <0xd8370000 0x1040>; - interrupts = <30>; - clocks = <&clkuart4>; - status = "disabled"; - }; - - uart5: serial@d8380000 { - compatible = "via,vt8500-uart"; - reg = <0xd8380000 0x1040>; - interrupts = <43>; - clocks = <&clkuart5>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - i2c_0: i2c@d8280000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8280000 0x1000>; - interrupts = <19>; - clocks = <&clki2c0>; - clock-frequency = <400000>; - }; - - i2c_1: i2c@d8320000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8320000 0x1000>; - interrupts = <18>; - clocks = <&clki2c1>; - clock-frequency = <400000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wm8850-w70v2.dts b/software/linux/kernel/arch/arm/boot/dts/wm8850-w70v2.dts deleted file mode 100644 index 7a563d252..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wm8850-w70v2.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * wm8850-w70v2.dts - * - Device tree file for Wondermedia WM8850 Tablet - * - 'W70-V2' mainboard - * - HongLianYing 'HLY070ML268-21A' 7" LCD panel - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/dts-v1/; -/include/ "wm8850.dtsi" -#include - -/ { - model = "Wondermedia WM8850-W70v2 Tablet"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - - brightness-levels = <0 40 60 80 100 130 190 255>; - default-brightness-level = <5>; - }; -}; - -&fb { - bits-per-pixel = <16>; - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/wm8850.dtsi b/software/linux/kernel/arch/arm/boot/dts/wm8850.dtsi deleted file mode 100644 index 8fbccfbe7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/wm8850.dtsi +++ /dev/null @@ -1,308 +0,0 @@ -/* - * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC - * - * Copyright (C) 2012 Tony Prisk - * - * Licensed under GPLv2 or later - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "wm,wm8850"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - }; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc0>; - - intc0: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; - - /* Secondary IC cascaded to intc0 */ - intc1: interrupt-controller@d8150000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xD8150000 0x10000>; - interrupts = <56 57 58 59 60 61 62 63>; - }; - - pinctrl: pinctrl@d8110000 { - compatible = "wm,wm8850-pinctrl"; - reg = <0xd8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - ref24: ref24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x200>; - }; - - pllb: pllb { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x204>; - }; - - pllc: pllc { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x208>; - }; - - plld: plld { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x20c>; - }; - - plle: plle { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x210>; - }; - - pllf: pllf { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x214>; - }; - - pllg: pllg { - #clock-cells = <0>; - compatible = "wm,wm8850-pll-clock"; - clocks = <&ref24>; - reg = <0x218>; - }; - - clkarm: arm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plla>; - divisor-reg = <0x300>; - }; - - clkahb: ahb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x304>; - }; - - clkapb: apb { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x320>; - }; - - clkddr: ddr { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&plld>; - divisor-reg = <0x310>; - }; - - clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <24>; - }; - - clkuart1: uart1 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <25>; - }; - - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <26>; - }; - - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <27>; - }; - - clkpwm: pwm { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x350>; - enable-reg = <0x250>; - enable-bit = <17>; - }; - - clksdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x330>; - divisor-mask = <0x3f>; - enable-reg = <0x250>; - enable-bit = <0>; - }; - }; - }; - - fb: fb@d8051700 { - compatible = "wm,wm8505-fb"; - reg = <0xd8051700 0x200>; - }; - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; - - pwm: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x100>; - clocks = <&clkpwm>; - }; - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; - - ehci@d8007900 { - compatible = "via,vt8500-ehci"; - reg = <0xd8007900 0x200>; - interrupts = <26>; - }; - - uhci@d8007b00 { - compatible = "platform-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <26>; - }; - - uhci@d8008d00 { - compatible = "platform-uhci"; - reg = <0xd8008d00 0x200>; - interrupts = <26>; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - status = "disabled"; - }; - - uart1: serial@d82b0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82b0000 0x1040>; - interrupts = <33>; - clocks = <&clkuart1>; - status = "disabled"; - }; - - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; - status = "disabled"; - }; - - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; - status = "disabled"; - }; - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; - - sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&clksdhc>; - bus-width = <4>; - sdon-inverted; - }; - - ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/xenvm-4.2.dts b/software/linux/kernel/arch/arm/boot/dts/xenvm-4.2.dts deleted file mode 100644 index 336915151..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/xenvm-4.2.dts +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Xen Virtual Machine for unprivileged guests - * - * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) - * Cortex-A15 MPCore (V2P-CA15) - * - */ - -/dts-v1/; - -/ { - model = "XENVM-4.2"; - compatible = "xen,xenvm-4.2", "xen,xenvm"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - /* this field is going to be adjusted by the hypervisor */ - bootargs = "console=hvc0 root=/dev/xvda"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - psci { - compatible = "arm,psci"; - method = "hvc"; - cpu_off = <1>; - cpu_on = <2>; - }; - - memory@80000000 { - device_type = "memory"; - /* this field is going to be adjusted by the hypervisor */ - reg = <0 0x80000000 0 0x08000000>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x100>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - hypervisor { - compatible = "xen,xen-4.2", "xen,xen"; - /* this field is going to be adjusted by the hypervisor */ - reg = <0 0xb0000000 0 0x20000>; - /* this field is going to be adjusted by the hypervisor */ - interrupts = <1 15 0xf08>; - }; - - motherboard { - arm,v2m-memory-map = "rs1"; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/zx296702-ad1.dts b/software/linux/kernel/arch/arm/boot/dts/zx296702-ad1.dts deleted file mode 100644 index 081f980cf..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/zx296702-ad1.dts +++ /dev/null @@ -1,48 +0,0 @@ - -/dts-v1/; - -#include "zx296702.dtsi" - -/ { - model = "ZTE ZX296702 AD1 Board"; - compatible = "zte,zx296702-ad1", "zte,zx296702"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - memory { - reg = <0x50000000 0x20000000>; - }; -}; - -&mmc0 { - num-slots = <1>; - supports-highspeed; - non-removable; - disable-wp; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; -}; - -&mmc1 { - num-slots = <1>; - supports-highspeed; - non-removable; - disable-wp; - status = "okay"; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/zx296702.dtsi b/software/linux/kernel/arch/arm/boot/dts/zx296702.dtsi deleted file mode 100644 index d45c8fcd7..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/zx296702.dtsi +++ /dev/null @@ -1,139 +0,0 @@ - -#include "skeleton.dtsi" -#include -#include - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "zte,zx296702-smp"; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2cc>; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - next-level-cache = <&l2cc>; - reg = <1>; - }; - }; - - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - matrix: bus-matrix@400000 { - compatible = "zte,zx-bus-matrix"; - reg = <0x00400000 0x1000>; - }; - - intc: interrupt-controller@00801000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - reg = <0x00801000 0x1000>, - <0x00800100 0x100>; - }; - - global_timer: timer@008000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x00800200 0x20>; - interrupts = ; - interrupt-parent = <&intc>; - clocks = <&topclk ZX296702_A9_PERIPHCLK>; - }; - - l2cc: l2-cache-controller@0x00c00000 { - compatible = "arm,pl310-cache"; - reg = <0x00c00000 0x1000>; - cache-unified; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - }; - - pcu: pcu@0xa0008000 { - compatible = "zte,zx296702-pcu"; - reg = <0xa0008000 0x1000>; - }; - - topclk: topclk@0x09800000 { - compatible = "zte,zx296702-topcrm-clk"; - reg = <0x09800000 0x1000>; - #clock-cells = <1>; - }; - - lsp1clk: lsp1clk@0x09400000 { - compatible = "zte,zx296702-lsp1crpm-clk"; - reg = <0x09400000 0x1000>; - #clock-cells = <1>; - }; - - lsp0clk: lsp0clk@0x0b000000 { - compatible = "zte,zx296702-lsp0crpm-clk"; - reg = <0x0b000000 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@0x09405000 { - compatible = "zte,zx296702-uart"; - reg = <0x09405000 0x1000>; - interrupts = ; - clocks = <&lsp1clk ZX296702_UART0_WCLK>; - status = "disabled"; - }; - - uart1: serial@0x09406000 { - compatible = "zte,zx296702-uart"; - reg = <0x09406000 0x1000>; - interrupts = ; - clocks = <&lsp1clk ZX296702_UART1_WCLK>; - status = "disabled"; - }; - - mmc0: mmc@0x09408000 { - compatible = "snps,dw-mshc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x09408000 0x1000>; - interrupts = ; - fifo-depth = <32>; - clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>, - <&lsp1clk ZX296702_SDMMC0_WCLK>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - mmc1: mmc@0x0b003000 { - compatible = "snps,dw-mshc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0b003000 0x1000>; - interrupts = ; - fifo-depth = <32>; - clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>, - <&lsp0clk ZX296702_SDMMC1_WCLK>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysctrl: sysctrl@0xa0007000 { - compatible = "zte,sysctrl", "syscon"; - reg = <0xa0007000 0x1000>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/zynq-7000.dtsi b/software/linux/kernel/arch/arm/boot/dts/zynq-7000.dtsi deleted file mode 100644 index f283ff083..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/zynq-7000.dtsi +++ /dev/null @@ -1,367 +0,0 @@ -/* - * Copyright (C) 2011 - 2014 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/include/ "skeleton.dtsi" - -/ { - compatible = "xlnx,zynq-7000"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - clocks = <&clkc 3>; - clock-latency = <1000>; - cpu0-supply = <®ulator_vccpint>; - operating-points = < - /* kHz uV */ - 666667 1000000 - 333334 1000000 - >; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - clocks = <&clkc 3>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 5 4>, <0 6 4>; - interrupt-parent = <&intc>; - reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; - }; - - regulator_vccpint: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "VCCPINT"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - amba: amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - - adc: adc@f8007100 { - compatible = "xlnx,zynq-xadc-1.00.a"; - reg = <0xf8007100 0x20>; - interrupts = <0 7 4>; - interrupt-parent = <&intc>; - clocks = <&clkc 12>; - }; - - can0: can@e0008000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clocks = <&clkc 19>, <&clkc 36>; - clock-names = "can_clk", "pclk"; - reg = <0xe0008000 0x1000>; - interrupts = <0 28 4>; - interrupt-parent = <&intc>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - }; - - can1: can@e0009000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clocks = <&clkc 20>, <&clkc 37>; - clock-names = "can_clk", "pclk"; - reg = <0xe0009000 0x1000>; - interrupts = <0 51 4>; - interrupt-parent = <&intc>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - }; - - gpio0: gpio@e000a000 { - compatible = "xlnx,zynq-gpio-1.0"; - #gpio-cells = <2>; - clocks = <&clkc 42>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <0 20 4>; - reg = <0xe000a000 0x1000>; - }; - - i2c0: i2c@e0004000 { - compatible = "cdns,i2c-r1p10"; - status = "disabled"; - clocks = <&clkc 38>; - interrupt-parent = <&intc>; - interrupts = <0 25 4>; - reg = <0xe0004000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@e0005000 { - compatible = "cdns,i2c-r1p10"; - status = "disabled"; - clocks = <&clkc 39>; - interrupt-parent = <&intc>; - interrupts = <0 48 4>; - reg = <0xe0005000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@f8f01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xF8F01000 0x1000>, - <0xF8F00100 0x100>; - }; - - L2: cache-controller@f8f02000 { - compatible = "arm,pl310-cache"; - reg = <0xF8F02000 0x1000>; - interrupts = <0 2 4>; - arm,data-latency = <3 2 2>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - mc: memory-controller@f8006000 { - compatible = "xlnx,zynq-ddrc-a05"; - reg = <0xf8006000 0x1000>; - }; - - uart0: serial@e0000000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - status = "disabled"; - clocks = <&clkc 23>, <&clkc 40>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0000000 0x1000>; - interrupts = <0 27 4>; - }; - - uart1: serial@e0001000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - status = "disabled"; - clocks = <&clkc 24>, <&clkc 41>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0001000 0x1000>; - interrupts = <0 50 4>; - }; - - spi0: spi@e0006000 { - compatible = "xlnx,zynq-spi-r1p6"; - reg = <0xe0006000 0x1000>; - status = "disabled"; - interrupt-parent = <&intc>; - interrupts = <0 26 4>; - clocks = <&clkc 25>, <&clkc 34>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@e0007000 { - compatible = "xlnx,zynq-spi-r1p6"; - reg = <0xe0007000 0x1000>; - status = "disabled"; - interrupt-parent = <&intc>; - interrupts = <0 49 4>; - clocks = <&clkc 26>, <&clkc 35>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gem0: ethernet@e000b000 { - compatible = "cdns,zynq-gem", "cdns,gem"; - reg = <0xe000b000 0x1000>; - status = "disabled"; - interrupts = <0 22 4>; - clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gem1: ethernet@e000c000 { - compatible = "cdns,zynq-gem", "cdns,gem"; - reg = <0xe000c000 0x1000>; - status = "disabled"; - interrupts = <0 45 4>; - clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - sdhci0: sdhci@e0100000 { - compatible = "arasan,sdhci-8.9a"; - status = "disabled"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkc 21>, <&clkc 32>; - interrupt-parent = <&intc>; - interrupts = <0 24 4>; - reg = <0xe0100000 0x1000>; - }; - - sdhci1: sdhci@e0101000 { - compatible = "arasan,sdhci-8.9a"; - status = "disabled"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkc 22>, <&clkc 33>; - interrupt-parent = <&intc>; - interrupts = <0 47 4>; - reg = <0xe0101000 0x1000>; - }; - - slcr: slcr@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; - reg = <0xF8000000 0x1000>; - ranges; - clkc: clkc@100 { - #clock-cells = <1>; - compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; - clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", - "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", - "dci", "lqspi", "smc", "pcap", "gem0", "gem1", - "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", - "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", - "dma", "usb0_aper", "usb1_aper", "gem0_aper", - "gem1_aper", "sdio0_aper", "sdio1_aper", - "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", - "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", - "gpio_aper", "lqspi_aper", "smc_aper", "swdt", - "dbg_trc", "dbg_apb"; - reg = <0x100 0x100>; - }; - - rstc: rstc@200 { - compatible = "xlnx,zynq-reset"; - reg = <0x200 0x48>; - #reset-cells = <1>; - syscon = <&slcr>; - }; - - pinctrl0: pinctrl@700 { - compatible = "xlnx,pinctrl-zynq"; - reg = <0x700 0x200>; - syscon = <&slcr>; - }; - }; - - dmac_s: dmac@f8003000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xf8003000 0x1000>; - interrupt-parent = <&intc>; - interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", - "dma4", "dma5", "dma6", "dma7"; - interrupts = <0 13 4>, - <0 14 4>, <0 15 4>, - <0 16 4>, <0 17 4>, - <0 40 4>, <0 41 4>, - <0 42 4>, <0 43 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <4>; - clocks = <&clkc 27>; - clock-names = "apb_pclk"; - }; - - devcfg: devcfg@f8007000 { - compatible = "xlnx,zynq-devcfg-1.0"; - reg = <0xf8007000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 8 4>; - clocks = <&clkc 12>; - clock-names = "ref_clk"; - syscon = <&slcr>; - }; - - global_timer: timer@f8f00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xf8f00200 0x20>; - interrupts = <1 11 0x301>; - interrupt-parent = <&intc>; - clocks = <&clkc 4>; - }; - - ttc0: timer@f8001000 { - interrupt-parent = <&intc>; - interrupts = <0 10 4>, <0 11 4>, <0 12 4>; - compatible = "cdns,ttc"; - clocks = <&clkc 6>; - reg = <0xF8001000 0x1000>; - }; - - ttc1: timer@f8002000 { - interrupt-parent = <&intc>; - interrupts = <0 37 4>, <0 38 4>, <0 39 4>; - compatible = "cdns,ttc"; - clocks = <&clkc 6>; - reg = <0xF8002000 0x1000>; - }; - - scutimer: timer@f8f00600 { - interrupt-parent = <&intc>; - interrupts = <1 13 0x301>; - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xf8f00600 0x20>; - clocks = <&clkc 4>; - }; - - usb0: usb@e0002000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; - status = "disabled"; - clocks = <&clkc 28>; - interrupt-parent = <&intc>; - interrupts = <0 21 4>; - reg = <0xe0002000 0x1000>; - phy_type = "ulpi"; - }; - - usb1: usb@e0003000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; - status = "disabled"; - clocks = <&clkc 29>; - interrupt-parent = <&intc>; - interrupts = <0 44 4>; - reg = <0xe0003000 0x1000>; - phy_type = "ulpi"; - }; - - watchdog0: watchdog@f8005000 { - clocks = <&clkc 45>; - compatible = "cdns,wdt-r1p2"; - interrupt-parent = <&intc>; - interrupts = <0 9 1>; - reg = <0xf8005000 0x1000>; - timeout-sec = <10>; - }; - }; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/zynq-parallella.dts b/software/linux/kernel/arch/arm/boot/dts/zynq-parallella.dts deleted file mode 100644 index 307ed201d..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/zynq-parallella.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2014 SUSE LINUX Products GmbH - * - * Derived from zynq-zed.dts: - * - * Copyright (C) 2011 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Adapteva Parallella Board"; - compatible = "adapteva,parallella", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlycon root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; - stdout-path = "serial0:115200n8"; - }; -}; - -&clkc { - fclk-enable = <0xf>; - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - /* Marvell 88E1318 */ - compatible = "ethernet-phy-id0141.0e90", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - marvell,reg-init = <0x3 0x10 0xff00 0x1e>, - <0x3 0x11 0xfff0 0xa>; - }; -}; - -&i2c0 { - status = "okay"; - - isl9305: isl9305@68 { - compatible = "isil,isl9305"; - reg = <0x68>; - - regulators { - dcd1 { - regulator-name = "VDD_DSP"; - regulator-always-on; - }; - dcd2 { - regulator-name = "1P35V"; - regulator-always-on; - }; - ldo1 { - regulator-name = "VDD_ADJ"; - }; - ldo2 { - regulator-name = "VDD_GPIO"; - regulator-always-on; - }; - }; - }; -}; - -&sdhci1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/zynq-zc702.dts b/software/linux/kernel/arch/arm/boot/dts/zynq-zc702.dts deleted file mode 100644 index e96959b2e..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/zynq-zc702.dts +++ /dev/null @@ -1,394 +0,0 @@ -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Zynq ZC702 Development Board"; - compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - sw14 { - label = "sw14"; - gpios = <&gpio0 12 0>; - linux,code = <108>; /* down */ - wakeup-source; - autorepeat; - }; - sw13 { - label = "sw13"; - gpios = <&gpio0 14 0>; - linux,code = <103>; /* up */ - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - - ds23 { - label = "ds23"; - gpios = <&gpio0 10 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&amba { - ocm: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0xfffc0000 0x10000>; - }; -}; - -&can0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_default>; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem0_default>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - i2cswitch@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@54 { - compatible = "at,24c08"; - reg = <0x54>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - hwmon@52 { - compatible = "ti,ucd9248"; - reg = <52>; - }; - hwmon@53 { - compatible = "ti,ucd9248"; - reg = <53>; - }; - hwmon@54 { - compatible = "ti,ucd9248"; - reg = <54>; - }; - }; - }; -}; - -&pinctrl0 { - pinctrl_can0_default: can0-default { - mux { - function = "can0"; - groups = "can0_9_grp"; - }; - - conf { - groups = "can0_9_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO46"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO47"; - bias-disable; - }; - }; - - pinctrl_gem0_default: gem0-default { - mux { - function = "ethernet0"; - groups = "ethernet0_0_grp"; - }; - - conf { - groups = "ethernet0_0_grp"; - slew-rate = <0>; - io-standard = <4>; - }; - - conf-rx { - pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; - bias-disable; - low-power-enable; - }; - - mux-mdio { - function = "mdio0"; - groups = "mdio0_0_grp"; - }; - - conf-mdio { - groups = "mdio0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - }; - - pinctrl_gpio0_default: gpio0-default { - mux { - function = "gpio0"; - groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", - "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", - "gpio0_13_grp", "gpio0_14_grp"; - }; - - conf { - groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", - "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", - "gpio0_13_grp", "gpio0_14_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-pull-up { - pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO7", "MIO8"; - bias-disable; - }; - }; - - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_10_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_10_grp"; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_sdhci0_default: sdhci0-default { - mux { - groups = "sdio0_2_grp"; - function = "sdio0"; - }; - - conf { - groups = "sdio0_2_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - - mux-cd { - groups = "gpio0_0_grp"; - function = "sdio0_cd"; - }; - - conf-cd { - groups = "gpio0_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - - mux-wp { - groups = "gpio0_15_grp"; - function = "sdio0_wp"; - }; - - conf-wp { - groups = "gpio0_15_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_10_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_10_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO49"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO48"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO29", "MIO31", "MIO36"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", - "MIO35", "MIO37", "MIO38", "MIO39"; - bias-disable; - }; - }; -}; - -&sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/zynq-zc706.dts b/software/linux/kernel/arch/arm/boot/dts/zynq-zc706.dts deleted file mode 100644 index be6a986bb..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/zynq-zc706.dts +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Zynq ZC706 Development Board"; - compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem0_default>; - - ethernet_phy: ethernet-phy@7 { - reg = <7>; - }; -}; - -&gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - - i2cswitch@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@54 { - compatible = "at,24c08"; - reg = <0x54>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - ucd90120@65 { - compatible = "ti,ucd90120"; - reg = <0x65>; - }; - }; - }; -}; - -&pinctrl0 { - pinctrl_gem0_default: gem0-default { - mux { - function = "ethernet0"; - groups = "ethernet0_0_grp"; - }; - - conf { - groups = "ethernet0_0_grp"; - slew-rate = <0>; - io-standard = <4>; - }; - - conf-rx { - pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; - low-power-enable; - bias-disable; - }; - - mux-mdio { - function = "mdio0"; - groups = "mdio0_0_grp"; - }; - - conf-mdio { - groups = "mdio0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - }; - - pinctrl_gpio0_default: gpio0-default { - mux { - function = "gpio0"; - groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; - }; - - conf { - groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-pull-up { - pins = "MIO46", "MIO47"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO7"; - bias-disable; - }; - }; - - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_10_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_10_grp"; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_sdhci0_default: sdhci0-default { - mux { - groups = "sdio0_2_grp"; - function = "sdio0"; - }; - - conf { - groups = "sdio0_2_grp"; - slew-rate = <0>; - io-standard = <1>; - bias-disable; - }; - - mux-cd { - groups = "gpio0_14_grp"; - function = "sdio0_cd"; - }; - - conf-cd { - groups = "gpio0_14_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - - mux-wp { - groups = "gpio0_15_grp"; - function = "sdio0_wp"; - }; - - conf-wp { - groups = "gpio0_15_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0>; - io-standard = <1>; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_10_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_10_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO49"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO48"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO29", "MIO31", "MIO36"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", - "MIO35", "MIO37", "MIO38", "MIO39"; - bias-disable; - }; - }; -}; - -&sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/zynq-zed.dts b/software/linux/kernel/arch/arm/boot/dts/zynq-zed.dts deleted file mode 100644 index 7250c1eac..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/zynq-zed.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Zynq Zed Development Board"; - compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/software/linux/kernel/arch/arm/boot/dts/zynq-zybo.dts b/software/linux/kernel/arch/arm/boot/dts/zynq-zybo.dts deleted file mode 100644 index d9e0f3e70..000000000 --- a/software/linux/kernel/arch/arm/boot/dts/zynq-zybo.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Zynq ZYBO Development Board"; - compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio0 46 1>; - }; -}; - -&clkc { - ps-clk-frequency = <50000000>; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&sdhci0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; diff --git a/software/linux/kernel/arch/arm/configs/infinity2m_spinand_fusionx_defconfig b/software/linux/kernel/arch/arm/configs/infinity2m_spinand_fusionx_defconfig index 5273e0175..9d9281126 100755 --- a/software/linux/kernel/arch/arm/configs/infinity2m_spinand_fusionx_defconfig +++ b/software/linux/kernel/arch/arm/configs/infinity2m_spinand_fusionx_defconfig @@ -43,7 +43,7 @@ CONFIG_KERNEL_XZ=y # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y +# CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y @@ -79,18 +79,16 @@ CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set -# CONFIG_NO_HZ_IDLE is not set -CONFIG_NO_HZ_FULL=y -# CONFIG_NO_HZ_FULL_ALL is not set -# CONFIG_NO_HZ_FULL_SYSIDLE is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # # CPU/Task time and stats accounting # -CONFIG_VIRT_CPU_ACCOUNTING=y -CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set @@ -103,13 +101,7 @@ CONFIG_PREEMPT_RCU=y CONFIG_SRCU=y # CONFIG_TASKS_RCU is not set CONFIG_RCU_STALL_COMMON=y -CONFIG_CONTEXT_TRACKING=y -# CONFIG_CONTEXT_TRACKING_FORCE is not set # CONFIG_TREE_RCU_TRACE is not set -CONFIG_RCU_NOCB_CPU=y -CONFIG_RCU_NOCB_CPU_NONE=y -# CONFIG_RCU_NOCB_CPU_ZERO is not set -# CONFIG_RCU_NOCB_CPU_ALL is not set # CONFIG_RCU_EXPEDITE_BOOT is not set # CONFIG_BUILD_BIN2C is not set # CONFIG_IKCONFIG is not set @@ -123,8 +115,7 @@ CONFIG_CGROUPS=y # CONFIG_CGROUP_SCHED is not set # CONFIG_CGROUP_PIDS is not set # CONFIG_CGROUP_FREEZER is not set -CONFIG_CPUSETS=y -CONFIG_PROC_PID_CPUSET=y +# CONFIG_CPUSETS is not set # CONFIG_CGROUP_DEVICE is not set # CONFIG_CGROUP_CPUACCT is not set # CONFIG_CGROUP_PERF is not set @@ -343,7 +334,7 @@ CONFIG_ARCH_SSTAR=y # # Options # -CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc011a-s01a-fusionx" +CONFIG_SS_DTB_NAME="infinity2m-spinand-ssc011a-s01a-rgb565-rmii-doublenet" CONFIG_SS_BUILTIN_DTB=y CONFIG_MS_KERNEL_TYPE="" CONFIG_SSTAR_CHIP_NAME="infinity2m" @@ -526,16 +517,13 @@ CONFIG_MIGRATION=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set CONFIG_CMA=y CONFIG_CMA_DEBUG=y CONFIG_CMA_DEBUGFS=y CONFIG_CMA_AREAS=1 # CONFIG_ZPOOL is not set # CONFIG_ZBUD is not set -CONFIG_ZSMALLOC=y -# CONFIG_PGTABLE_MAPPING is not set -# CONFIG_ZSMALLOC_STAT is not set +# CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_FRAME_VECTOR=y @@ -633,7 +621,6 @@ CONFIG_COREDUMP=y # Power management options # # CONFIG_SUSPEND is not set -# CONFIG_HIBERNATION is not set # CONFIG_PM is not set # CONFIG_APM_EMULATION is not set CONFIG_PM_OPP=y @@ -707,14 +694,11 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_L2TP is not set -CONFIG_STP=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE is not set CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set -CONFIG_LLC=m # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set @@ -759,7 +743,6 @@ CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y CONFIG_WEXT_PRIV=y CONFIG_CFG80211=y # CONFIG_NL80211_TESTMODE is not set @@ -770,11 +753,7 @@ CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y -CONFIG_LIB80211=y -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -CONFIG_LIB80211_CRYPT_TKIP=m -# CONFIG_LIB80211_DEBUG is not set +# CONFIG_LIB80211 is not set # CONFIG_MAC80211 is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 # CONFIG_WIMAX is not set @@ -860,7 +839,6 @@ CONFIG_MTD_BLOCK=y # CONFIG_SSFDC is not set # CONFIG_SM_FTL is not set # CONFIG_MTD_OOPS is not set -# CONFIG_MTD_SWAP is not set # CONFIG_MTD_PARTITIONED_MASTER is not set # @@ -946,20 +924,7 @@ CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y # CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_NULL_BLK is not set -CONFIG_ZRAM=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_LOOP_MIN_COUNT=2 -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV is not set # CONFIG_NVME_TARGET is not set # @@ -1059,7 +1024,7 @@ CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set -CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -1077,14 +1042,9 @@ CONFIG_CHR_DEV_SG=y CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_ISCSI_BOOT_SYSFS is not set -CONFIG_SCSI_UFSHCD=y -# CONFIG_SCSI_UFSHCD_PLATFORM is not set +# CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_DEBUG is not set -CONFIG_SCSI_DH=y -# CONFIG_SCSI_DH_RDAC is not set -# CONFIG_SCSI_DH_HP_SW is not set -# CONFIG_SCSI_DH_EMC is not set -# CONFIG_SCSI_DH_ALUA is not set +# CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set @@ -1123,6 +1083,7 @@ CONFIG_ATA_BMDMA=y # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set CONFIG_NETDEVICES=y +CONFIG_MII=y # CONFIG_NET_CORE is not set # @@ -1176,17 +1137,8 @@ CONFIG_FIXED_PHY=y # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set -CONFIG_PPP=y -# CONFIG_PPP_BSDCOMP is not set -# CONFIG_PPP_DEFLATE is not set -# CONFIG_PPP_FILTER is not set -# CONFIG_PPP_MPPE is not set -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPPOE is not set -# CONFIG_PPP_ASYNC is not set -# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP is not set # CONFIG_SLIP is not set -CONFIG_SLHC=y # CONFIG_USB_NET_DRIVERS is not set CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y @@ -1199,15 +1151,9 @@ CONFIG_WLAN_VENDOR_BROADCOM=y CONFIG_WLAN_VENDOR_CISCO=y CONFIG_WLAN_VENDOR_INTEL=y CONFIG_WLAN_VENDOR_INTERSIL=y -CONFIG_HOSTAP=m -# CONFIG_HOSTAP_FIRMWARE is not set +# CONFIG_HOSTAP is not set CONFIG_WLAN_VENDOR_MARVELL=y -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_LIBERTAS_SPI=m -CONFIG_LIBERTAS_DEBUG=y -CONFIG_LIBERTAS_MESH=y +# CONFIG_LIBERTAS is not set # CONFIG_MWIFIEX is not set CONFIG_WLAN_VENDOR_MEDIATEK=y CONFIG_WLAN_VENDOR_RALINK=y @@ -1216,7 +1162,7 @@ CONFIG_WLAN_VENDOR_RSI=y CONFIG_WLAN_VENDOR_ST=y CONFIG_WLAN_VENDOR_TI=y CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_USB_ZD1201=m +# CONFIG_USB_ZD1201 is not set # CONFIG_USB_NET_RNDIS_WLAN is not set # @@ -1385,7 +1331,7 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_SERIAL_NONSTANDARD is not set @@ -1752,9 +1698,9 @@ CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEOBUF2_CORE=m -CONFIG_VIDEOBUF2_MEMOPS=m -CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_VMALLOC=y # CONFIG_TTPCI_EEPROM is not set # @@ -1765,8 +1711,8 @@ CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # -CONFIG_SS_HOST_UVC=m -CONFIG_USB_VIDEO_CLASS=m +CONFIG_SS_HOST_UVC=y +CONFIG_USB_VIDEO_CLASS=y CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y # CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set @@ -1896,9 +1842,7 @@ CONFIG_FB_NOTIFY=y # Console display driver support # CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=m -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE is not set # CONFIG_LOGO is not set # CONFIG_SOUND is not set @@ -2035,10 +1979,10 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y # # USB Device Class drivers # -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may @@ -2420,21 +2364,7 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # CONFIG_SOC_BRCMSTB is not set # CONFIG_SUNXI_SRAM is not set # CONFIG_SOC_TI is not set -CONFIG_PM_DEVFREQ=y - -# -# DEVFREQ Governors -# -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_GOV_PASSIVE is not set - -# -# DEVFREQ Drivers -# -# CONFIG_PM_DEVFREQ_EVENT is not set +# CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set # CONFIG_IIO is not set @@ -2507,7 +2437,14 @@ CONFIG_MS_SPI_INFINITY=y CONFIG_MS_EMMC=y CONFIG_MS_EMMC_UNIFY_DRIVER=y CONFIG_MS_SDMMC=y -# CONFIG_MS_EMAC is not set +CONFIG_MS_EMAC=y +# CONFIG_EMAC_SUPPLY_RNG is not set +# CONFIG_MSTAR_HW_TX_CHECKSUM is not set +# CONFIG_K3_RX_SWPATCH is not set +CONFIG_DISCONNECT_DELAY_S=1 +# CONFIG_MSTAR_EEE is not set +CONFIG_EMAC_PHY_RESTART_AN=y +# CONFIG_EMAC_SPEED10_HALF_PATCH is not set CONFIG_MS_CRYPTO=m # CONFIG_SS_AESDMA_INTR is not set CONFIG_CRYPTODEV=m @@ -2541,7 +2478,7 @@ CONFIG_RTCPWC_INNER=y # CONFIG_MS_WATCHDOG is not set # CONFIG_MS_SAR is not set CONFIG_MSTAR_MMAHEAP=y -# CONFIG_SSTAR_NETPHY is not set +CONFIG_SSTAR_NETPHY=y CONFIG_SS_VOLTAGE_CTRL=y # @@ -2820,7 +2757,7 @@ CONFIG_PANIC_TIMEOUT=0 # CONFIG_SCHED_STACK_END_CHECK is not set # CONFIG_DEBUG_TIMEKEEPING is not set # CONFIG_TIMER_STATS is not set -CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_PREEMPT is not set # # Lock Debugging (spinlocks, mutexes, etc...) @@ -2998,7 +2935,7 @@ CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_POLY1305 is not set CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set @@ -3114,10 +3051,6 @@ CONFIG_NLATTR=y # CONFIG_DDR is not set # CONFIG_IRQ_POLL is not set CONFIG_LIBFDT=y -CONFIG_FONT_SUPPORT=m -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y # CONFIG_SG_SPLIT is not set CONFIG_SG_POOL=y CONFIG_ARCH_HAS_SG_CHAIN=y diff --git a/software/linux/project/kbuild/4.9.84/i2m/configs/nvr/011A/glibc/8.2.1/spinand/include/generated/compile.h b/software/linux/project/kbuild/4.9.84/i2m/configs/nvr/011A/glibc/8.2.1/spinand/include/generated/compile.h index 674e191dc..2c88d1417 100644 --- a/software/linux/project/kbuild/4.9.84/i2m/configs/nvr/011A/glibc/8.2.1/spinand/include/generated/compile.h +++ b/software/linux/project/kbuild/4.9.84/i2m/configs/nvr/011A/glibc/8.2.1/spinand/include/generated/compile.h @@ -1,7 +1,7 @@ -/* This file is auto generated, version 2 */ +/* This file is auto generated, version 22 */ /* SMP PREEMPT */ #define UTS_MACHINE "arm" -#define UTS_VERSION "#2 SMP PREEMPT Sat Dec 3 15:06:29 GMT 2022" +#define UTS_VERSION "#22 SMP PREEMPT Sun Feb 12 22:10:10 GMT 2023" #define LINUX_COMPILE_BY "psmart" #define LINUX_COMPILE_HOST "gull" #define LINUX_COMPILER "gcc version 8.2.1 20180802 (GNU Toolchain for the A-profile Architecture 8.2-2018-08 (arm-rel-8.23)) " diff --git a/software/linux/project/kbuild/4.9.84/i2m/drivers/sstar/include/ms_version.h b/software/linux/project/kbuild/4.9.84/i2m/drivers/sstar/include/ms_version.h index fa200c3a4..484ff9651 100644 --- a/software/linux/project/kbuild/4.9.84/i2m/drivers/sstar/include/ms_version.h +++ b/software/linux/project/kbuild/4.9.84/i2m/drivers/sstar/include/ms_version.h @@ -5,6 +5,6 @@ #define MVXV_HEAD_VER "4" #define MVXV_LIB_TYPE "##" #define MVXV_CHIP_ID "I2M#" -#define MVXV_CHANGELIST "g6322424ba" +#define MVXV_CHANGELIST "gef9980d8e" #define MVXV_COMP_ID "KL_LX409##" #define MVXV_EXT "[BR:master]"